SU1118990A1 - Random signal generator - Google Patents

Abstract

A GENERATOR OF RANDOM SIGNALS containing a register whose input is an input of a random signal generator, the first register output is connected to the first input of the first switch, the first and second memory blocks, the second switch, the white noise generator, the clock generator and the digital-to-analog converter whose output is The output of the random signal generator, characterized in that, in order to expand the scope of application by introducing a software reorganization, a third memory block, counters and a trigger are inserted into it. The second register output is connected to the first input of the third memory block, the first input of the first counter and the second input of the first switch, the output of the third memory block is connected to the first inputs of the first and second memory blocks, the outputs of which are connected to the first and second inputs of the second the switch, the output of which is connected to the first input of the digital-to-analog converter, the third output of the register is connected via a clock generator to the first input of the second counter, the input of the white noise generator, the second the input of the first counter, the first input of the third counter and the first input of the fourth counter; the first outputs of the second and third counters are connected respectively to the second inputs of the first and second memory blocks; the second outputs of the second and third counters are connected respectively to the first inputs of the first and second triggers, the output of the first the trigger is connected to the third input of the second switch, the second input of the second counter, the third input of the first i memory unit and the second input of the first trigger; the output of the second trigger is connected to the fourth input of the second switch, the second input of the third counter, the third input of the second memory block and the second input of the first trigger; the fourth output of the register is connected to the second input of the third memory block and the second input of the fourth counter, the output of which is connected to the third inputs of the third and second counters and to the second input of the D / A converter, the output of the white noise generator is connected to the third input of the first 00 switch, the output of which is connected to; o; the third input of the first counter, the output of which connected to the third input of the third memory block.

Description

The invention relates to computing, namely, devices for controlling testing of objects.

Pseudo-random signal generators are known that contain a control unit, shift registers, AND elements, OR element, NOT element, and decoder 1.

The main disadvantage of the known generators is the complexity of the rearrangement, since this generator operates with only one type of spectrum.

Closest to the proposed is a digital random process generator containing a clock frequency (pulse) generator, the outputs of which are connected to the inputs of a multiplexer (switch), the output of which is connected to the input of the white noise generator, the synchronization unit and the block of registers whose output is connected to the input of the first multiplier, the first input of the first element OR and the first input of the second element OR, the output of the first element OR is connected to the first input of the switch, the outputs of which are connected to the second inputs of the unit Registers, the output of the second element OR is connected to the first input of the second multiplier, the output of which is connected through a accumulating adder to the first input of the second element AND, the output of the element AND is connected through serially connected digital-analog converter and a filter to the output of the device, the first and second outputs of the control panel (performed on registers) are connected via the third and fourth elements, respectively, to the first inputs of the first and second memory blocks, the outputs of which are connected respectively to the second inputs of the first first and second multiplier, the output of the first multiplier is connected to the first input of the second accumulating adder, the output of which is connected through the AND element to the second inputs of the first and second element OR, the output of the white noise generator is connected through the fourth element AND to the second input of the second accumulating adder, the second inputs of the first and the second memory unit is connected respectively to the first and second outputs of the synchronization unit, the third output of the control panel (made on the registers) is connected to the input of the multiplexer (switch a) fourth output remote control (performed on registers) is connected to the second input of the synchronization unit, a fifth remote control output connected to a third input of the block synchronization and through the decoder to the second input of the switch 2.

The main disadvantage of the prototype is the complexity of generator tuning.

The purpose of the invention is to expand the scope of application by introducing software restructuring.

The goal is achieved by the fact that 5 into a random signal generator, containing a register whose input is an input of a random signal generator, the first register output is connected to the first input of the first switch, the first and second memory blocks, the second switch, the white noise generator, generator clock pulses and a digital-to-analog converter, the output of which is the output of a random signal generator, a third memory block, counters and triggers are inserted,

5, the second output of the register is connected to the first input of the third memory block, the first input of the first counter and the second input of the first switch, the output of the third memory block is connected to the first inputs of the first and second memory blocks, whose outputs

0 are connected respectively to the first and second inputs of the second switch, the output of which is connected to the first input of the D / A converter; the third output of the register is connected via the clock to the first input of the second counter, the input of the white noise generator, the second input of the first counter, the first input of the third counter and the first the input of the fourth counter, the first outputs of the second and third counters are connected

Q, respectively, to the second inputs of the first and second memory blocks, second outputs of the second and third counters are connected respectively to the first inputs of the first and second triggers, the output of the first trigger is connected to the third input of the second switch, the second input of the second counter, and the third input of the first memory block and the second input of the first trigger, the output of the second trigger is connected to the fourth input of the second switch, the second input of the third counter, the third input of the second

 the memory block and the second input of the first trigger; the fourth output of the register is connected to the second input of the third memory block and the second input of the fourth counter, the output of which is connected to the third inputs of the third 5 of its and second counters and the second input of the digital-analog converter; the output of the white noise generator is connected to the third the input of the first switch, the output of which is connected to the third input of the first counter, the output of which is connected to

0 to the third input of the third memory block.

The drawing shows a structural diagram of a generator of random signals.

Random signal generator contains register 1, memory blocks 2-4, counters 5-8, switches 9 and 10, generator 11

white noise generator, 12 clock pulse generator, triggers 13 and 14, digital-to-analog converter 15, control input 16, generator output 17.

The introduction of new blocks and elements made it possible to eliminate the lengthy process of calculating the required spectrum of random signals, which led to an increase in speed and the selection of the required spectrum of random signals (corresponding codes) at control input 16 by the software and allowed to implement a software reorganization of the random signal generator.

The operation of the random signal generator is based on the generation of digital codes for the digital-to-analog converter 15, which are selected from memory blocks 3 and 4 via switch 9, which selects memory blocks 3 and 4 as they are filled from memory block 2.

The control codes for the random generator come from control input 16 to register 1, which stores the control signals for the generator.

12-stroke pulses, switch 10, counter 5 and memory block 2.

Preparing the generator for operation consists in entering into memory block 2 a set of pseudo-random numbers with a given power spectral density through register 1. In this device operation mode, recording in memory block 2 is performed by control signals from the fourth output register I, the address for the memory device is determined The state of the counter 5, the initial code in which is entered from the switch 10. After entering the initial code, the counter 5 counts the recording control pulses in the memory block 2 and, thus, interrupts p all addresses of memory block 2. After filling in memory block 2, the generator of 12 clock pulses is enabled and the coefficient of recalculation is entered into counter 8, which determines, by its state, the speed of reading information from memory blocks 3 and 4.

In the initial state, one of the triggers 13 and 14 is set to one, the other to zero. State distribution between triggers

13 and 14 occurs randomly, since the outputs of the triggers 13 and 14 are connected in pairs with the reset inputs. The single state of the flip-flops 13 and 14 determines the read mode for the respective blocks 3 and 4 of the memory, the addresses of which are edited by the counters 6 and 7 by counting the number of pulses from the output of the counter 8.

The zero state of the flip-flops 13 and 14 indicates the write mode in the corresponding block (3 or 4) of the memory from block 2 of the memory.

Addresses for reading memory block 2 are generated by counter 5, which in this mode counts pulses from the generator output 12 clocks, and the conversion factor of counter 5 is set by white noise generator 11 through switch 10. Thus, the information input of digital-to-analog converter 15 is obtained codes, which is represented by numbers from memory block 2 (samples of pseudo-random length). The resulting sequence is fully consistent with the spectral probability density of the numbers stored in memory block 2. The contents of memory block 2 are determined by the codes supplied to the input 16 of the control of the generator of random signals through register 1. These

C codes may be generated (e.g., in microcomputers) by the algorithms of the corresponding transformations. Thus, the generator is rearranged by adding new numbers to memory block 2.

The required rate of formation of the signals is determined by the recalculation coefficient of the counter 8, and the speed of reading data from the memory block 2 by the memory blocks 3 and 4 is the clock frequency from the generator output 12 clock pulses. The switching of blocks 3 and 4 of the memory from the write mode to the read mode is carried out by the overflow signal of the corresponding counters 6 and 7. The overflow signals are fixed in the triggers 13 and 14. Such formation of pseudo-random signals eliminates the periodicity in replications of a sample of pseudo-random numbers of finite length and bursts of signals and distortions (resulting from periodicity in the sequence of pseudo-random numbers).

In addition, the operation speed of the device is limited from above by the speed of the memory blocks 3 and 4, the switch 9 and the digital-analog converter 15 and does not depend on the speed of generating pseudo random numbers for the memory block 2.

Compared with the basic oscillator (low-frequency noise generator, which allows to obtain random processes in the frequency range 0.25–20 kHz with a given spectrum), the proposed generator makes it possible: to extend the frequency range of the generated signals 10 times (from 0.001 to 50 kHz) the quality and accuracy of testing of objects, the accuracy of the generation of the spectrum by the proposed generator is 7-10 ° / o, the base 20%); generate signals with different power spectral densities; to automate the testing process, which reduces the time of simple equipment and increases productivity; carry out a wide range of complex tests, such as vibration-climatic, etc.

Claims (1)

A RANDOM SIGNAL GENERATOR containing a register, the input of which is an input of a random signal generator, the first output of the register is connected to the first input of the first switch, the first and second memory blocks, the second switch, a white noise generator, a clock generator and a digital-to-analog converter, the output of which is the output of the generator random signals, characterized in that, in order to expand the scope by introducing software adjustment, a third memory block, counters and triggers are introduced into it, the second A swarm register output is connected to the first input of the third memory block, the first input of the first counter and the second input of the first switch, the output of the third memory block is connected to the first inputs of the first and second memory blocks, the outputs of which are connected respectively to the first and second inputs of the second switch, the output which is connected to the first input of the digital-to-analog converter, the third register output is connected through a clock generator to the first input of the second counter, the input of the white noise generator, the second input of the first about the counter, the first input of the third counter and the first input of the fourth counter, the first outputs of the second and third counters are connected respectively to the second inputs of the first and second memory blocks, the second outputs of the second and third counter are connected respectively to the first inputs of the first and second triggers, the output of the first trigger is connected to the third input of the second switch, the second input of the second counter, the third input of the first p of the memory block and the second input of the first trigger ® ger, the output of the second trigger is connected to I # fourth input ode of the second switch, IV to the second input of the third counter, the third | L input of the second memory unit and the second | the input of the first trigger, the fourth output of the g register is connected to the second input of the third- ~ its memory block and the second input of the fourth counter, the output of which is connected to the third inputs of the third and second counters and the second input of the digital-to-analog converter, the output of the white noise generator is connected to the third input of the first switch whose output is connected to the third input of the first counter, the output of which is connected to the third input of the third memory block.