JP2909218B2 - Period generator for semiconductor test equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a cycle generator that is used in a semiconductor test apparatus and generates a pulse of a set test cycle, that is, a test pattern generation cycle. The present invention relates to a period generator that generates a pulse by using the delay circuit and delays the pulse by a fractional part (fractional part) of a set period by a delay circuit.

BACKGROUND ART FIG. 1 shows a conventional period generator of this kind. The address from the pattern generator 11 is applied to the period value memory 12,
At each enable cycle of the pattern generator 11, the set cycle value is read from the cycle value memory 12 specified by the address, an integer part I in units of clock cycle is set in the match detection counter 13, and the set cycle value is set. Is applied to one input side of the adder 14. The coincidence detection counter 13 counts the clock from the clock generator 15 and supplies an output to the delay circuit 16 when the counted value coincides with the set integer I. Period value memory 12
Is added to the output of the flip-flop 17 by the adder 14, and the addition result is latched in the flip-flop 17 by the clock of the clock generator 15 and the enable signal. The carry output of the adder 14 is latched in the flip-flop 18 by the clock and the enable signal. The fraction F read from the cycle value memory 12 is a value equal to or less than the cycle T of the clock. If the addition result of the adder 14 exceeds the cycle T, a carry output is generated. When the carry occurs, the output of the match detection counter 13 is delayed by one clock cycle T in the delay circuit 16 and supplied to the variable delay element 19; The output passes through the delay circuit 16 without being delayed and is supplied to the variable delay element 19. The output of the delay circuit 16 is also supplied to the pattern generator 11 as a generation trigger of the next cycle. The output of the flip-flop 17 is set in the delay element 19 as a delay amount.

The output of the delay element 19 is supplied to the delay waveform generator 22 as the output of the cycle generator 21. The delay waveform generator 22 generates a pattern of a set waveform that is delayed by the delay amount (phase) set by the pattern generator 11 with reference to the pulse from the cycle generator 21, and is generated through the driver 23. It is applied to one pin terminal of the test IC 24. Note that, for example, as shown in the figure, the output of the coincidence detection counter 13 is supplied to the gates 16a and 16b, the output of the flip-flop 18 is supplied to the gate 16b, and the inverted output thereof is supplied to the gate 16a, The output of 16b is supplied to a flip-flop 16c, and the output of the flip-flop 16c and the output of the gate 16a are supplied to an OR gate 16d. The pattern generator 11 is operated by the clock of the clock generator 15, the output data changes, that is, the address of the cycle generator changes for each enable, and the delay waveform generator 22 also operates with the clock of the clock generator 15. Period value memory
The readout timing of 12 is determined by the clock of the clock generator 15, and the flip-flops 17, 18, and 16c receive the output pulse RA of the delay circuit 16 at their enable terminals E,
The input is taken in by the clock of the clock generator 15 during that time.

When the set period T _S is, for example, 2.25T, an integer I = 2 is set in the match detection counter 13 from the period value memory 12 and
= 0.25 is supplied to the adder 14, and as shown in FIG. 2, an output is generated from the coincidence detection counter 13 every time two clocks CK (FIG. 2A) are counted. The flip-flops 17 and 18 are latched by the clock CK, and the output value RMD of the flip-flop 17 to which a small number (fraction) F = 0.25 is cumulatively added is initially 0, and a carry is generated from the adder 14. During this time, an output RA is generated from the delay circuit 16 as shown in FIG. 2B. This output RA is delayed by the output value RMD of the flip-flop 17 by the delay element 19, but the amount of delay is shown in FIG. As shown in the figure, the initial value is 0, and then increases by 0.25T every time an output from the match detection counter 13 becomes 0.25T, 0.5T, 0.75T, 0.0T, 0.25T,.
When the carry becomes 1.0T and the carry is generated from the adder 14, it becomes 0.0T. At this time, the output of the match detection counter 13 is delayed by one clock cycle T by the delay circuit 16. By operating in this manner, a pulse every 2.25T is output from the delay element 19 as shown in FIG. 2D.

In order to shorten the test period T _S and generate a high-speed test pattern, it is necessary to increase the operation speed of the function blocks of each unit.However, if you want to generate a high-speed test pattern with a cheap and low-speed function block, A so-called interleave method is used. For example, in order to operate the delay waveform generator 22 at a high speed by a two-way interleave method with a low-speed function block, the delay section in the delay waveform generator 22 is composed of two series of delay elements 25 and 26 as shown in FIG. And pattern generator 11
, The delay amounts D _P1 and D _P2 are respectively set, and the delay elements 25 and 2
The outputs of 6 are combined in a series by an OR circuit 27, and the waveform
Supplied to 8. At this time, the delay elements 25 and 26 need only operate at half the speed of the test period T _S.

In this example, the fractional delay by the delay element 19 in the period generator 21 is also performed by the delay elements 25 and 26, and the delay circuit 1
The output of 6 is supplied to the delay element 25 at the odd-numbered test period T _S by the switch 29, and is supplied to the delay element 26 at the even-numbered test cycle T _S.
The delay amount D _P1 of the delay element 25 at the odd-numbered test period T _S
The delay amount of the delay element 26 is added to the even-numbered
It is added to D _P2 by the adder 33. In this way, there is no need to provide the delay element 19 that requires high-speed operation in the period generator 21, and the delay elements 25 and 26 in the delay waveform generator 22 may have low-speed operation.

When the operation of the example shown in FIG. 2 is performed by the configuration shown in FIG. 3, the output RA (FIG. 4B) of the delay circuit 16 becomes as shown in FIGS. 4C and 4D as shown in FIG. And delay elements 25 and 26 alternately
The output value RMD (FIG. 4E) of the flip-flop 17 is also alternately supplied to the delay elements 25 and 26 as shown in FIGS.
Are distributed so as to be added to the delay amounts D _P1 and D _P2 .

In the configuration shown in FIG. 3, it is necessary that the adder 14 in the cycle generator 21 completes the arithmetic operation every test cycle T _S , that is, it needs to operate at high speed.

DISCLOSURE OF THE INVENTION According to the first aspect of the present invention, fractions during a set period are supplied to first to n-th fractional first-stage flip-flops (n is an integer of 2 or more), and the second to n-th terminals are used. The outputs of the first-stage flip-flops are respectively supplied to the second to n-th fraction next-stage flip-flops, and the outputs of the first to n-th fraction first-stage flip-flops are cumulatively added by a first accumulator. The output of the first-stage flip-flop for the n-th fraction is added last, and a value equal to or less than the clock cycle in the cumulative addition result is output as the cumulative addition result, and the carry of the last addition is output, and the first to i-th bits are output. The outputs of the first-stage flip-flops for one fraction (i = 2, 3,..., N) and the outputs of the next-stage flip-flops for the i-th to n-th fractions are added by an i-th cumulative adder. -1 First stage flip-flop output The force is added last, a value less than or equal to the clock cycle in the result of the cumulative addition is output as the cumulative addition value of the i-th cumulative adder, and the carry of the last addition is output from the i-th cumulative adder. . The cumulative addition result of the first cumulative adder is supplied to the third-stage flip-flop, and the integer during the set period is supplied to the first to n-th integer first-stage flip-flops. Are respectively supplied to the first to n-th integer next-stage flip-flops. The outputs of the first to n-th integer next-stage flip-flops are supplied to first to n-th match detection counters. The n-th match detection counter counts a clock from an initial value by a start command, and outputs an output when the count value matches an input integer value, and outputs the first to n-th clocks.
The outputs of the coincidence detection counters are supplied to first to n-th delay circuits, respectively, and the first to n-th delay circuits output the second to n-th +
Controlled by the carry output of a 1 (n + 1 = 1) accumulator, the input is delayed by one clock cycle in the presence of a carry output, and the input is delayed in the absence of a carry output. And the outputs of the first to n-th match detection counters are respectively the second to n + 1-th match detection counters.
It is supplied to the start terminal of the coincidence detection counter. The outputs of the first to n-th delay circuits are respectively supplied to the first to n-th delay elements, and the delay amounts of the first to n-th delay elements are respectively the outputs of the second to n-th accumulators, The outputs are set by the outputs of the stage flip-flops, and the outputs of the first to n-th delay elements are combined by an OR circuit. Each flip-flop is enabled by the output of the p-th delay circuit (p is any one of 1 to n), and each q-th delay circuit (q is other than p in 1 to n). ) Is provided with q-th delay adjusting means for delaying the control by the carry output of the accumulator by one enable delay when the output of the next-stage flip-flop for the q-th integer is not zero.

According to a second aspect of the present invention, in the first aspect of the present invention, the address sequence of the enable cycle from the pattern generator is converted into the first to n-th address sequences of the n-times enable cycle by the address sequence conversion means. The period value memory is read by the first to n-th address strings, and the read first to n-th fractions are stored in the first to n-th fraction first-stage flip-flops, and the read first to n-th fractions are read out. n
The integers are stored in the first to n-th integer first-stage flip-flops, and the delay data sequence of the enable period from the pattern generator is converted into the first to n-th delay data sequences of the n-th enable period by the delay data sequence conversion means. The first to n-th delay data strings are respectively added to the outputs of the first to n-th accumulators by first to n-th adders, and set as delay amounts in the first to n-th delay elements. You.

According to the third aspect of the present invention, an output is obtained from the first to n-th delay circuits in the same manner as in the second aspect of the invention, but the cumulative addition value (fraction) from the first to n-th cumulative adders is obtained. )
Is not sent to the delay waveform generator, the delay waveform generator is provided with a memory similar to the periodic value memory, and the periodic value memory is read out in the first to n-th address strings, and the first to n-th fractions are read out as described above. Similarly to the above, the cumulative addition is performed by n cumulative adders. In this case, it is not necessary to specify the order of addition since carry output is not required. The n cumulative addition results are added to the n delayed data strings by the first to n-th adders, and the first to n-th adders are added.
The delay amount of the delay element is set.

According to a fifth aspect of the present invention, substantially the same as the second aspect of the present invention, the periodic value memory is read by the first to n-th address strings from the pattern generator, and the first to the nth address strings are read out. The first to n-th delayed data strings supplied to the n adders are directly supplied from the pattern generator.

The sixth aspect of the present invention is substantially the same as the third aspect of the present invention, except that the first and second period value memories are read by the first to n-th address strings from the pattern generator. The supply of the first to n-th delay data strings to the first to n-th adders is performed directly from the pattern generator.

In any of claims 2, 3, 5 and 6, the first to n-th waveform generating means are respectively provided between the output side of the first to n-th delay elements and the OR circuit. Inserted,
Each of the first to n-th waveform generating means generates a waveform by using the first to n-th pattern data strings of the n-th enable cycle obtained by converting the pattern data string for each enable cycle from the pattern generator.

In the accumulator according to any one of the claimed inventions, the accumulative addition of the lower digit portion of the input is performed by the lower digit adder, and each carry and the upper digit portion of the input are accumulated in the upper digit adder. The cumulative addition value is added side by side to the upper side of the cumulative addition value of the lower digit adding section. That is, the cumulative addition is processed in a pipeline manner in the lower digit portion and the upper digit portion.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a periodic generator used in a conventional semiconductor test apparatus and its periphery.

FIG. 2 is a time chart for explaining the operation of the period generator in FIG.

FIG. 3 is a block diagram showing the relationship between the delay unit of the delay waveform generator and the cycle generator when interleaving is performed in two streams.

FIG. 4 is a time chart for explaining the operation of FIG.

 FIG. 5 is a block diagram showing an embodiment of the present invention.

FIG. 6 and FIG. 7 are time charts showing the state of each part of the operation example of the embodiment shown in FIG.

FIG. 8 shows an example in which the present invention is applied to a four-sequence interleave system, wherein A is a block diagram of a fractional example, and B is a block diagram of an integer example.

FIG. 9 is a time chart showing the state of each part of the operation example in the embodiment of FIG.

FIG. 10 is a block diagram showing an embodiment to which the present invention is applied when the delay waveform generator has two systems.

FIG. 11 is a block diagram showing an embodiment of the present invention in which the generation of fractions in the embodiment of FIG. 10 is performed by a delay waveform generator.

FIG. 12 is a block diagram showing an embodiment in which the addition in the tracking adder is performed by a pipeline system.

Figure 13 A is a logic circuit diagram showing a specific example of the delay circuit 64 ₁ in Fig. 5, B is a block diagram showing another example of a delayed waveform generator 22 in FIG. 11.

FIG. 14 is a block diagram showing an example of a pattern generator 11 for generating two-series data.

BEST MODE FOR CARRYING OUT THE INVENTION FIG. 5 shows an embodiment of the present invention, in which parts corresponding to those in FIGS. 1 and 3 are denoted by the same reference numerals. In this embodiment, when a periodic signal is generated as two series (n = 2), the address sequence from the pattern generator 11 is converted by the address sequence conversion means 40 into two series of addresses having a cycle twice as long as the clock cycle T. The distribution is converted to a column. For example, a clock generator
The clock CK from 15 is frequency-divided by a frequency divider circuit 40a to one half, and its output controls two gates of the distribution circuit 40b. The addresses of the enable period from the pattern generator 11 are taken into the flip-flops 40c and 40d, respectively, and distributed to the odd-numbered and even-numbered address strings by the two series of clocks.
The outputs of c and 40d are taken into the flip-flops 40e and 40f by one output clock of the distribution circuit 40b, respectively, to form two series of address strings having the same phase. The cycle value memory 12 is read at the timing of taking in the flip-flops 40e and 40f in these two address strings. The cycle value memory 12 is designed so that odd-numbered data and even-numbered data having the same contents as the cycle value memory 12 in FIG. 1 are simultaneously read for each of the two series of addresses. The data is stored in the.

Fractions (values equal to or less than the cycle T) F ₁ and F ₂ in the cycle value read from the cycle value memory 12 are input to flip-flops (first-stage and second-fraction first-stage flip-flops) 41 ₁ and 41 ₂ , respectively. integer I _1, I _2, which is read in the flip-flop is supplied to the (first, initial stage flip-flop for the second integer) 43 _1, 43 _2. Each output of the flip-flop 41 _1, 41 ₂ is supplied to the first cumulative adder 45 _1, flip-flop 41 output of ₂ flip-flop 41 ₁ is supplied to the flip-flop (the next-stage flip-flop fraction) 46 _2, 46 each output of the _two is supplied to the second cumulative adder 45 _1. First cumulative adder 45 ₁ adds the outputs of the flip-flop 48 ₁ of the flip-flop 41 ₁ in the adder 49, and added by the adder 51 the output of the flip-flop 41 ₂ to the added value, the added and stores the result in the flip-flop 48 ₁ stores the carry output of the adder 51 to the flip-flop 52 _1. Second cumulative adder 45 ₂ adds the output of the flip-flop 46 ₂ and the output of the flip-flop 48 ₂ in the adder 54, flip-flops are added by the adder 55 the output of the flip-flop 41 ₁ to the addition result stored in 48 _2, stores the carry output of the adder 55 to the flip-flop 52 _2. The output of the cumulative adder 45 ₁ is supplied to the flip-flop 57. Any cumulative adder 45 _1, 45 ₂ is intended to neither the clock period T as a unit, that is longer than the clock period T during accumulation result is more than the period T at fraction is an integer.

While the output of flip-flop 43 _1, 43 ₂ is supplied to the coincidence detection counter 62 _1, 62 ₂ via a flip-flop (first, next-stage flip-flop for the second integer) 58 _1, 58 _2, respectively, match detection counter The outputs of 62 ₁ and 62 ₂ are supplied to delay circuits 64 ₁ and 64 ₂ respectively. The delay circuit 64 ₂ shows a configuration similar to that of the delay circuit 16 in FIG. 1, is controlled by the output of the flip-flop 52 _2, in the state in which a carry occurs one clock period T by the delay circuit 64 ₂ The input is delayed, and in the absence of a carry, the input passes without delay. But the delay circuit 64 ₂ other than the delay circuit 64 delays the adjustment means ₁ for sending an enable output E of from the OR circuit 66
63 ₁ is provided. Due to the next enabled period that is, when the set cycle to be generated is longer than the period of the reference clock CK is to enable each unit by the output pulse of the delay circuit 64 _2, the delay circuit 64 by the output state of the preceding flip-flop 52 _{2 2} is controlled, but other delay circuits 6
4 ₁ is a flip-flop 52 ₁
Output state changes, and correct control cannot be performed. The delay adjusting unit 63 ₁ is provided to solve this problem.

That output of the flip-flop 58 ₁ as shown in FIG. 13 A is also supplied to the zero detection circuit 64a delays adjusting means 63 _1,
When the output value of the flip-flop 58 ₁ is 0, the 0 detection circuit 64a
Output goes high. The output of the flip-flop 52 ₁ is supplied forbidden gate 64b, to the gate 64c, these gates
Control of 64b and 64c is performed by the output of the 0 detection circuit 64a.
The output of the inhibit gate 64b is supplied to the data terminal of the flip-flop 64d, and the output of the flip-flop 64d and the gate 64c.
Is supplied to the OR gate 64e. Or gate 64e
Output of the circuit 64f having the same configuration as the delay circuit 16 in FIG.
Is supplied as a control signal to the output of the coincidence detection counter 62 ₁ in the circuit 64f is supplied. Gate 64b, 64c, flip-flop 64d, the OR gate 64e constitutes the carry holding circuit 64 g, 0 output of the detection circuit 64a is supplied for high level immediately to circuit 64f a control signal of the flip-flop 52 _1,
That the delay circuit 64 ₁ is the same operation as the delay circuit 64 _2, 0 control signal output from the flip-flop 52 ₁ in the case of low-level detection circuit 64a is (described later) 1 enable period delay circuit 64f. The output of the delay circuit 64 ₂ is supplied to the start terminal S of the coincidence detection counter 62 ₁ is supplied to the delay element 25 _2. Delay circuit 64 ₁
The output is supplied to the start terminal S of the coincidence detection counter 62 ₂ is supplied to the delay element 25 ₁ via the OR circuit 65. The output of the delay circuit 64 ₂ is also supplied to the OR circuit 66, the OR circuit 66 is also input initialization signal IN, OR circuit
The output of 66 is supplied to the enable terminals E of all the flip-flops, not shown, but shown in FIG. 5, and also enables the loading of the match detection counter. Generator
The clock CK from 15 is supplied. Match detection counter 62
_1, 62 ₂ is reset given the start signal to the start terminal S starts counting from the initial value of the clock, when its count value matches the input value, and generates an output. Adders 49,51,
When the added value exceeds the period T of the clock CK, the outputs 54 and 55 output the excess as a result of addition and also carry.

Clock CK period T is 8ns (125MHz) and generation period is 7ns
The operation of the embodiment shown in FIG. 5 for the case (1) will be described with reference to FIG. In this case, the fraction from the periodic memory 12
In the state where 7 is read out as F ₁ and F _{2 and} 0 is read out as integers I ₁ and I ₂ , respectively, and the address is given to the input of the period value memory 12 from the pattern generator as shown in FIG. 2 When the initialization signal iN clock cycle length is input in, the immediately following clock CK ₁ flip-flop 41 _1, 41 ₂ in as shown in FIG. 6 B 7 at the rising of the (Fig. 6 a) is taken And
0 as shown in FIG. 6 I is taking the flip-flop 43 _1, 43 _2. In this state, the adder 49 sets the flip-flop 41 ₁
An output 7 of the flip-flops 48 ₁ output 0 and the adder 4
9 is added and 7 is output.
The output 7 of 1 ₂ is added by the adder 51 to obtain (7 + 7) −8 =
6 is output as an addition result and carry is output. The adder 54 receives 0 and 0 as input, and outputs 0 as the addition result.
The output 7 of the flip-flop 41 ₁ is outputting the addition result 7 are added by the adder 55 and.

Thus the rising of the next clock CK _2, 6 are output as shown from the flip-flop 48 ₁ in FIG. 6 C, the carry output is generated as shown from the flip-flop 52 ₁ in FIG. 6 D, flip-flop 46 the output of the ₂ becomes 7 as shown in FIG. 6 E, with output 7 is shown from the flip-flop 48 ₂ in FIG. 6 G, the output of the flip-flop 52 ₂ low as shown in FIG. 6 H Remains at the level. The 0 from the output of the flip-flop 58 _1, 58 ₂ is output, which is input to the counter 62 _1, 62 _2. In this state, the adder 49 receives 7 and 6 and outputs 5, and the adder 51 receives 5 and 7 and outputs 4, and outputs a carry. The adder 54 outputs 7 and 7 Is input, 6 is output, and 7 is added by the adder 55 to output 5 and output carry.

Each of these accumulators 45 ₁ and 45 ₂ uses a fraction 7 for each clock.
Cumulative addition is performed for each CK, and the cumulative adder 45 ₁ is the cumulative adder 4
It is understood that from 5 ₂ have gone progressing 1 enable period. Here, one enable cycle is a cycle for enabling each flip-flop, that is, the OR circuit 66.
Is the cycle of the output E. In this state, the initialization signal IN
After the run out, started when the signal STT is input in synchronization with for example the clock CK ₃ as shown in FIG. 6 O, first, as the start signal STT rises shown in FIG. 6 Q delay elements 25 ₁ Output as is (with Ons delay). At the same time, coincidence detection counter 62 ₂ is started, the input is 0
Matching the output of the detection counter 62 ₂ goes high, as shown in FIG. 6 J since it is, at this time the flip-flop 52 ₂
Immediately pass to the sixth output of the delay circuit 64 _2, as shown in Figure L is high level output from the delay circuit 64 ₂ of from not outputting a carry counter 62 _2, as is shown in FIG. 6 H from to become, thus matching detection counter 62 ₁ is also activated, the coincidence detection counter 62 ₁ from the input of the coincidence detection counter 62 ₁ is also zero
Also goes high as shown in FIG. 6K. However, the output of the next delay circuit 64 ₁ becomes high level delayed by one clock period T the output R of and zero detection circuit 64a outputs of the flip-flop 52 ₁ at a high level is at a high level.
Therefore the delay circuit 64 ₁ at the time of the clock CK ₃ remain low, as shown in Figure 6 N. The output of the delay circuit 64 ₂ became high by the STT, since the output of the flip-flop 48 ₂ is 7, the rise of the output of the delay circuit 64 ₂ in the delay element 25 _2, as shown in FIG. 6 P Delayed 7ns. Further, since the output of the delay circuit 64 ₂ becomes high level, the flip-flop is enabled, next 4 so that the output of the flip-flop 48 ₁ at the rising of the next clock CK ₄ is shown in Figure 6 C, flip-flop 52 ₁ becomes a carry output state from the output of the flip-flop 57 becomes 6 as shown in FIG. 6 F, the output of the flip-flop 48 ₂ becomes 5 as shown in FIG. 6 G, flip-flop 52 ₂ the output of becomes carry state as shown in FIG. 6 H, thereby, the coincidence detection counter by the delay circuit 64 ₁ as previously described 6
Sixth output of the delay circuit 64 _1, as shown in FIG N high level output of 2 ₁ is delayed by one clock period T goes high,
Output by the coincidence detection counter 62 ₂ is activated, the output is the the output of the flip-flop 58 ₂ is 0 6
It goes high immediately as shown in FIG. J, delay circuit 64 ₂
1 clock period T the output of the flip-flop 52 ₂
Because there is a delay, the output of the delay circuit 64 ₂ 6
Becomes low level as shown in FIG. L, Thus coincidence detecting counter 62 ₁ is in a stopped state, the output is a low level as shown in FIG. 6 K, a high level output which is delayed one clock period T The output of a delay circuit 64 ₁ is
Since 5 ₁ output of flip-flop 57 is 6 FIG. 6 Q
6 ns delay as shown in After a lapse of one clock period T from the rise of the clock CK _4, Figure 6 a high-level output of the coincidence detection counter 62 ₂ from the delay circuit 64 ₂ is output L
The output goes high as shown in
Is 5ns delay as shown by the output value 5 of the flip-flop 48 ₂ in FIG. 6 P _2. In this state, the addition result of the adder 51 is 2 and the addition result of the adder 55 is 3. Also,
When the output of the delay circuit 64 ₂ becomes high level, and loading each match detection counter Again, each flip-flop is enabled.

Therefore, the flip-flop 4 at the rising edge of the next clock CK ₅
The output of the 8 ₁ equals 2, the output of the flip-flop 57 is 4, the output 3 next to the flip-flop 48 ₂ operates Similarly, pulses 7ns period from the OR circuit 27 is obtained. As is apparent from the time chart of Figure 6, the cumulative adder 45 _1, 45 ₂ may be an operation during a two clock cycle both, may be more even operation element 2 times slower conventional.
In addition, although an example in which the cycle is constant has been given for the sake of simplicity, by writing various cycle values in the cycle value memory,
Naturally, the period can be changed in real time according to the address from the pattern generator.

FIG. 7 shows a time chart of the operation of each unit in FIG. 5 when the generation cycle is 13 ns. In this case, the cycle value memory 12
From the above, the fractions F ₁ and F ₂ are read out as 5 each, and the integers I ₁ and I ₂ are read out as 1 each.
The output of the flip-flop 48 ₁ in the initialization signal IN 2 (7
Figure C), the flip-flop 52 ₁ outputs the high level (7
Figure D), the output is 5 (Fig. 7 G of the flip-flop 48 _2), flip-flop 52 ₂ outputs a low level (Fig. 7 H), the output of the flip-flop 58 _2, 58 ₁ 1 (Fig. 7 I). Activation when the signal STT (Fig. 7 O) is given, as in the case of 7ns, at the rising edge of the STT delay elements 25 _1, as shown in FIG. 7 Q and the output of the flip-flop 57 is 0 Is output as is. The coincidence detection counter 62 ₂ starts operating, the next clock CK ₁
1 is counted at the rising edge of the output, and the output is high level (Fig. 7J).
Next, which is fed passed to the delay element 25 ₂ without being delayed a delay circuit 64 ₂ are set the output 5 of the flip-flop 48 ₂ to the delay element 25 _2, the delay element 2
5 ₂ As shown in FIG. 7 P, outputs a delay 5ns from the rising of the high-level output of the delay circuit 64 ₂ is out, and it will be an out output delayed 13ns from the rise of the start signal STT.

Also the output of the delay circuit 64 _2, coincidence detection counter 62 ₁ is started, and also enables further loading of coincidence detection counter becomes each flip-flop is enabled, the flip-flop 4 on the next rising clock CK ₂
8 ₁ The output of the 4 (FIG. 7 C), the flip-flop 52 ₁ outputs the high level (Fig. 7 D), the output of the flip-flop 48 ₂ 7 (FIG. 7 G), the flip-flop 52 and _second output the low level (Fig. 7 H), and the coincidence detection counter 62 ₁ 1
Counting the output is a high level (Fig. 7 K) next to, the output of the output by the delay circuit 64 ₁ 0 detection circuit 64a is low level, before 1 enabled period in the carry holding circuit 64f flip-flop 52 ₁ Is selected, and since this output is at the high level at that time, it is delayed by one clock cycle (7th output).
Figure N), is supplied to the delay element 25 _1, which is 2 ns (FIG. 7 F) delays the output of the flip-flop 57 in the delay element 25 _1, the delay element 25 ₂ of the previous, as shown in FIG. 7 Q A pulse which rises with a delay of 13 ns from the rising of the output (FIG. 7P) is output. The output of the delay circuit 64 _1, the coincidence detection counter 62 ₂ is started, which output counts the next clock goes high (FIG. 7 J), this rising of the flip-flop 48 ₂ by the delay element 25 ₂ The output delays 7 ns as shown in FIG. 7L. Hereinafter, the same operation is performed.

In the above description, the two-sequence interleave method is used, but the number of streams can be processed with a larger number of streams. For example, FIG. 8 shows an example of a four-sequence interleave method. FIG. 8A shows a configuration example of a fractional part, and FIG. 8B shows a configuration of an integer part, which are connected to each other. The case of n series (n is an integer of 2 or more) will be described with this example. The address sequence of the enable period from the pattern generator 11 is sequentially distributed into 4 (n) columns by one enable period by the address sequence conversion means 40, and the period is converted into an address sequence of 4 (n) enable periods. The first to fourth (n) address strings are used to store the cycle value memory 12.
Is read out every 4 (n) enable cycles. Since the shortest of one enable cycle is one clock cycle, the shortest of a 4 (n) enable cycle is 4 (n) clock cycles. Fractions F _{1 to} F ₄ (F _n ) read from cycle value memory 12 _First to _fourth ( _n- th) fraction first-stage flip-flops 41 _{1 to} 41 ₄ (41
_n ), and the outputs of the second to _fourth ( _n -th) fractional first stage flip-flops 41 _{2 to} 41 ₄ (41 _n ) are the second to fourth (n-th) fraction next-stage flip-flops, respectively. Step 46 ₂ -4
6 ₄ (46 _n ). The outputs of the first to _fourth ( _n -th) fractional first stage flip-flops 41 _{1 to} 41 ₄ (41 _n ) are the first
Is supplied to the accumulator 45 ₁ is cumulatively added, the fraction for the first-stage flip-flop 41 of that time the last addition the fourth (No. n)
The output of ₄ (41 _n), is stored in the flip-flop 48 _1, the carry output is stored in the flip-flop 52 ₁ for carry. The i-th cumulative adder 45 _i (i = 2,3,4 (n)) is
To the next-stage flip-flops 46 _{2 to} 46 ₄ for the (n) th fraction
(46 _n ) and the outputs of the first-stage flip-flops 41 _{1 to} 41 _i-1 for the first to the (i−1) _-th fractions are cumulatively added. 41
Finally, adding the output of the _i-1, the addition result is stored to the i-th flip-flop 48 _i, the carry is stored in the flip-flop 52 _i for carry.

On the other hand, in FIG. 8B, the first to fourth (n-th) integers I _{1 to} I ₄ (I _n ) read from the cycle value memory 12 are the first to the first stages for the second to first (n + 1 = 1) integers, respectively. The outputs of the flip-flops 43 ₁ to 43 ₄ (43 _n ) are stored in the flip-flops 43 ₂ to 43 ₁ (43 _{n + 1} ), respectively.
(N) Next-stage flip-flops for integers 58 _{1 to} 58 ₄ (58 _n )
Stored in these flip-flops 58 _{1 to} 58 ₄ (58 _n )
Are the first to fourth (n-th) match detection counters 62 ₁
62 62 ₄ (62 _n ) is input. 1st to 4th (nth)
Each output of the coincidence detection counters 62 _{1 to} 62 ₄ (62 _n ) is supplied to _first to _fourth ( _n- th) delay circuits 64 ₁ to 64 ₄ (64 _n ).
These _first to _fourth ( _n- th) delay circuits 64 ₁ to 64 ₄ (64 _n )
Are the first to fourth (n-th) accumulators 45 _{1 to} 45 _{4, respectively.}
These are controlled by the outputs of the carry flip-flops 52 _{1 to} 52 ₄ (52 _n ) of (45 _n ). The second delay circuit 64 of ₂ than the first delay circuit and the third to fourth (No. n) delay circuit 64 _1, 6
4 ₃ to 64 ₄ (64 _n) has the same structure as the delay circuit 64 ₁ shown in FIG. 13 A, respectively delay adjusting unit 63 _1, 63 ₃ to 63 ₄ (6
3 _n ), and the first, third, and fourth (n-th) integer next-stage flip-flops 58 ₁ , 58 _{3 to} 58 ₄ (58 _n ) are also input,
The output of the carry flip-flops 52 ₁ , 52 _{3 to} 52 ₄ (52 _n ) depends on whether the output of the 0 detection circuit 64a is at a high level or not.
It is used to control whether or not each output of the coincidence detection counters 62 ₁ , 62 _{3 to} 62 ₄ (62 _n ) is delayed, respectively, with or without the enable period. First delay circuit 64
The output of ₁ is the logical sum of the start signal STT at the OR circuit 65 is taken, the output of the second coincidence detection counter 62 ₂ start terminal S
And the second to fourth (n-th) delay circuits 64 ₂ to 64 _2
4 (64 _n ) are supplied to the start terminals S of the third to first (n + 1) -th match detection counters 62 _{2 to} 62 ₄ (62 _n ), respectively. First to fourth (n-th) delay circuits 64 ₁ to 64 ₄ (64 _n )
Are the first to fourth (n-th) delay elements 25 ₁ to 25 2, respectively.
5 ₄ (25 _n ), and the first to fourth (n-th) delay elements 2
5 _{1 to} 25 ₄ (25 _n ) have first to fourth (n) accumulators 45 ₁
The output of 45 ₄ flip-flops 48 ₁ to 48 ₄ (45 _n) (48 _n) is supplied as the set amount of delay. 1st cumulative adder 45 ₁
The output is supplied to the first delay element 25 ₁ flip-flop 57 is one step interposed for adjusting the timing. The output of the second delay circuit 64 ₂ and the initialization signal IN is ORed with the OR circuit 66, supply the output of the enable terminal E of the flip-flop in FIG. 8, the coincidence detection counter load enable terminal Each of these flip-flops is triggered by the clock of the clock generator 15, and the first to fourth (n-th) coincidence detection counters 62 _{1 to} 62 ₄ (62 _n ) count the clock of the clock generator 15. .

FIG. 9 shows a time chart in the case where the cycle generation when the clock cycle T is 8 ns and the set cycle T _S is 3 ns is performed by the four-sequence interleave method shown in FIG. In this case, all the fractions F _{1 to} F ₄ read from the cycle value memory 12 are 3,
I _{1 to} I ₄ are all 0, and the clock is supplied by the initialization signal IN.
During two cycles of CK, the fraction processing side (FIG. 8A) is operated,
In the first clock, the output of the flip-flop 41 _{1-41 4} 3, the output of flip-flop 46 _{2-46 4} 0,
In the next clock, the output of the first flip-flop 48 ₁ of the cumulative adder 45 ₁ is 4 (= 3 + 3 + 3 + 3 = (8 + 1) +
3), the output is low the flip-flops 52 _1, a second output of the accumulator 45 _{and second} flip-flop 48 ₂ 3 (= 0 +
0 + 0 + 3), the output is low the flip-flop 52, _second and third output of the flip-flop 48 ₃ cumulative adder 45 ₃ 6 (= 0 + 0 + 3 + 3), the output is low the flip-flop 52 _3, a fourth accumulator 45 ₄ flip flops 48 ₄
Output 1 (= 0 + 3 + 3 + 3 = 8 + 1), the output is high the flip-flop 52 _4, the output of flip-flop 57 is zero.

When the start signal STT is input in this state, the OR circuit 65
Output is generated from, which is supplied to the delay element 25 _1, the delay (output of flip-flop 57) it is output immediately from the OR circuit 27 at 0. Output of OR circuit 27 to ninth
This is indicated by an arrow in the figure. Start signal output of the OR circuit 65 of the STT output immediately because the input is supplied to the coincidence detection counter 62 ₂ is 0 has occurred, consistent with the same detection counter 6
2 _3, 62 ₄ is also activated sequentially immediately, that each input 0 So immediately output occurs, the control input of the delay circuit 64 _2, 64 ₃ from a low level, the start signal STT at the same time as the output from these results. But the control input of the delay circuit 64 ₄ is for a high level is delayed by one clock period T. Delay element 2
Since the set delay amounts of 5 ₂ and 25 ₃ are 3 and 6, respectively,
The signals are output from the OR circuit 27 after being delayed by 3 ns and 6 ns, respectively. Delayed output from circuit 64 ₄ is output from the OR circuit 27 is 1ns delayed by a delay element 25 ₄ and the coincidence detection circuit 62 ₁ at the output of the delay circuit 64 ₄ is activated, since the input is zero, the aforementioned Match detection counters 62 ₁ , 62 ₂ , 62 ₃
, And outputs immediately and sequentially, and each of the accumulators 45 _{1 to} 45 ₄
There performed accumulating once, flip-flop 48 _{1-48 4} the outputs of the next respective 0,7,2,5, flip-flops 52 ₁ to
Each output of 52 ₄ becomes high level, low level, high level and low level, the output of flip-flop 57 becomes 4, each output of OR circuit 65 and delay circuit 64 ₂ is delayed by 4 ns and 7 ns, respectively, and delay circuit 64 the output of ₃ further 2n is one clock period T delay the output of the flip-flop 52 ₃ is a high level
The signal is output from the OR circuit 27 after being delayed by s. Hereinafter, the same operation is performed.

FIG. 10 shows an example in which the present invention is applied to the case where the delay waveform generator 22 in FIG. 1 is also composed of two streams, and the parts corresponding to those in FIG. In this case, the pattern generator 11
The delayed data sequence for each clock cycle from is divided into two series by the delayed data sequence converting means 42 and the cycle is 2
Doubled. This conversion may be performed by a method similar to that of the address string conversion means 40. Similarly, the pattern data sequence from the pattern generator 11 is divided by the pattern data sequence conversion means 44 into two series having a double cycle. Delay data sequence delay data string of two series from the conversion means 42 output from the adder 32 _1, 32 ₂ respectively a flip-flop 57, are respectively added and a fractional output of the cumulative adder 45 _2, the adder 32 _1, 32 ₂ is set as the delay amount for the delay elements 25 ₁ and 25 ₂ . Delay element
The waveforms of the outputs 25 ₁ and 25 ₂ are respectively generated by the waveform generators 28 ₁ and 28 ₂ in accordance with the two series of pattern data sequences from the pattern data sequence converter 44, and these generated waveform sequences are ORed. The signal is synthesized by the circuit 27 and output.

May the period generator 21 and the delayed waveform generator 22 is far away compared liquid, respectively generally cumulative adder 45 _1, 4
The output fraction from 5 ₂ ,... Has a relatively large number of digits, whereas the number of bits of the address from which the cycle value memory 12 is read may be smaller than the fraction. In such a case, the cycle generator 21 In order to further reduce the number of cores of the signal transmission cable to the delay waveform generator 22, the arrangement shown in FIG. 11 may be used. No.
11, parts corresponding to those in FIG. 10 are denoted by the same reference numerals. A cycle value memory 47 is provided on the side of the delay waveform generator 22. The cycle value memory 47 is read out by the two series of address strings from the address string conversion means 40, and the read fraction thereof is provided.
F _1, F ₂ is the stored contents of the cycle value memory 47 is chosen to be equal to the fractional F _1, F _2, which is read from the period value memory 12. Fraction F ₁ from these periodic value memory 47 is read, F ₂ is flip-flops is stored (first for fractional detection, the second fraction for the first stage flip-flop) 59 _1, 59 _2, respectively, the flip-flop 59 _{and second} output It is stored in the flip-flop (the next-stage flip-flop for the second fraction for fractional detection) 61 _2. The outputs of the flip-flops 59 ₁ and 59 ₂ are the cumulative adder 93 ₁
In the cumulative addition, output of the flip-flop 59 _1, 61 ₁ are cumulatively added by the cumulative adder 93 _2. These cumulative adders 93 ₁ ,
Fractional value of 93 _second accumulated result may be any identical to the end value of the accumulator 45 _1, 45 ₂ of the accumulation result, a carry is not necessary to output, that is, the order in each of the cumulative addition Irrelevant. Accumulated sum of the cumulative adder 93 ₁ is supplied to the flip-flop 71, the timing of the output of the cumulative adder 93 ₂ is fitted. In this way, the tenth
Cumulative adder 45 ₁ in FIG. 45 of the same obtained sum output ₂ ones are obtained, they are supplied to the adder 32 _1, 32 _2, are added delay data sequence two series respectively You.

On the other hand, the fraction of the cumulative adder 45 _1, 45 _2, the cumulative addition result of the period generator 21 does not output, is outputted only its carry output is supplied to the delay circuit 64 _1, 64 _2. The output of the OR circuit 65, delay circuit 64 respectively ₂ of the output at the timing aligning means 72, the period value memory 47, is timed to fractional accumulated value of the two series are obtained by the delay element 2
5 _1, 25 ₂ to be supplied. That is, the timing matching means 72 reads, for example, the period value memory 47, and the flip-flops 73 ₁ , 73 ₂ , 74 corresponding to the respective timings of the flip-flops 59 ₁ , 59 ₂ , 61 ₁ , 61 ₂ , 71 ₁ , 71 _{2. 1,} 7
4 ₂ , 76 ₁ , and 76 _{2 in two} cascaded stages. Each output of flip-flops 73 ₁ and 74 _{1 has} a flip-flop 59 1
_1, and 59 _2, the cumulative adder 93 _1, flip-flop 61 _2, flip-flop 71, and respectively the cumulative adder 93 ₂ enabled. Eleventh delay waveform generating cumulative adder in 22 93 _1, 93 ₂ in the figure may be configured similarly to the cumulative adder 45 _1, 45 ₂ in FIG. 5, or shown in Fig. 13 B As described above, the outputs of the flip-flops 59 ₁ and 59 ₂ are added by the adder 81 ₁ , and the output is added through the flip-flop 61 ₁ to the adder 82 ₁
Is supplied to and added to the output of the flip-flop 71 _1, and supplies the addition result to the flip-flop 71 _1, constitutes a cumulative adder 93 ₁ and the output F ₁ and flip-flop 59 _second periodic memory 47 adds the output adder 81 ₂ is supplied to the adder 82 ₂ and the sum output through the flip-flop 61 _2,
It adds the output of flip-flop ₇₁₂ may be configured to cumulative adder 93 ₂ is supplied to the addition result and the flip-flop _712. In this case, the flip-flop 73 ₁ in the timing aligning means 72, 73 ₂ and the flip-flop 76 _1, 76 ₂ and insert the flip-flop 75 _1, 75 _2, respectively between the flip-flops 73 ₁ of the output flip-flop 59 _1, not only supplied to the 59 _second enable terminal E, also supplied to the flip-flop 61 _1, 61 ₂ of the enable terminal E, the output of flip-flop 75 ₁ to the flip-flop 71 _1, 71 ₂ of the enable terminal E Supply. Between flip-flops 59 ₁ and 61 ₁ ,
Addition operation between flip-flops 61 ₁ and 71 ₁ are each one, adder design than performing two addition operations between the flip-flops 59 ₁ and 61 ₁ becomes easy in Figure 11.

In FIG. 10, the address data sequence, the delay data sequence, and the pattern data sequence from the pattern generator 11 are respectively converted into two-sequence data. However, there are also cases where the pattern generator 11 itself generates two-sequence data. FIG. 14 shows an outline of the configuration example. That is, the first from the address counter 85 _1, 85 _2, the instruction memory ₈₆₁ by the second address, 86 ₂ is read, the instruction memory 86 _1, 86 ₂ instructions read from by the decoder 87 _1, 87 ₂ is decrypted respectively, by result of decoding, the address counter 85 _1, 85 ₂ of the stepping and jumping, stopping, a loop is controlled. Address counter 8
5 _1, 85 first than _2, each cycle control memory 88 ₁ by the second address, 88 ₂ and delayed waveform generation control memory 89 _1, 89 ₂
Is read. The cycle value memory 47 in FIG. 10 is read by the first and second cycle value memory addresses read from the cycle control memories 88 ₁ and 88 ₂ . Although not shown above, the delay waveform generator 22 is provided with a delay data memory and a pattern data memory in the same manner as the cycle value memory 12 in the cycle generator 21. The respective delay data memory addresses and the respective pattern data memory addresses read from the waveform generation control memories 89 ₁ and 89 ₂ are respectively read, and the delay data read from the respective delay data memories is added to the adder 32 in FIG.
_1, 32 is supplied to the _2, read pattern data from the pattern data memory is supplied to the waveform generator 28 _1, 28 _2. Each section shown in FIG. 14 is enabled by an enable output E in the cycle generator.

Figure 10, in FIG. 11, and supplies the output of the delay element 25 _1, 25 ₂ directly to the OR circuit 27, to the output of the OR circuit 27, the waveform generated by the pattern data at the clock period from the pattern generator 11 May be. Further, the method shown in FIG. 10 and FIG. 11 may be processed not only in two series but also in three or more series.

If the number of fractional digits is large, it cannot be used by a general-purpose adder. In such a case, the lower-order digit and the upper-order digit are separated, and these may be subjected to a pipeline operation. This example is shown in FIG. That is, the lower-order portion F ₁ a fraction F ₁ of from flip-flop 41 _1, are cumulatively added by the lower digit addition section 45 ₁ a and the lower-order portion F ₂ a fraction F ₂ of from flip-flop 41 _2, the lower digit adder unit 45 ₁ a of the adder 49a, the carry of 51a are respectively stored in the flip-flop 78 _1, 79 _1. After the upper-order portion F ₂ b of the order portion of the fractional F ₁ F ₁ b and fraction F ₂ is taken timing flip-flop 81 _1, 81 _2, respectively, are cumulatively added in the upper digit adder unit 45 ₁ b . At that time the adder
The carry of each of the flip-flops 78 ₁ and 79 ₁ is also added to 49b and 51b. The fraction of the cumulative addition result from the flip-flop 77 _{1 of the} lower digit adder 45 ₁ a is the flip-flop 48 ₁
timing a is taken to the upper side of the output, the digit adder unit 45 ₁ b by fractional accumulation result is added from the flip-flop 48 ₁ b of, i.e. bits combined cumulative adder 45 ₁ Output, and the adder 51b of the upper digit adder 45 ₁ b
Carry a is stored as a raised flip-flop 52 ₁ double-digit output.

Similarly, in the cumulative adder 45 _2, flip-flop 4
1 ₂ low-order portion of the fractional F ₂ than F ₂ a, the upper-order portion F ₂ b are timing taken respectively by the flip-flop 46a, 81 _2, the flip-flop 46a outputs F ₂ a and from flip-flops 41 ₁ and lower-order portion F ₁ a is cumulatively added by the lower digit addition unit 45 ₂ a, and the upper order portion F ₁ b from the flip-flop 81 _1, the upper-order portion of from flip-flop 81 ₂ F ₂ b a flip-flop
To that timed at 46b are cumulatively added by the digit adder unit 45 ₂ b. Carry the lower digit addition unit 45 ₂ a when this is also added. The fractional part of the cumulative addition result of the lower digit adder 45 ₂ a is timed by the flip-flop 48 ₂ a, and the fractional part of the cumulative addition result of the upper digit adder 45 ₂ b is added to the upper part of the output, It is the output of the cumulative adder 45 _2.
In this case, the operation bit width of the adders can be reduced to half compared with the case of FIG. 5, it is possible that much faster operation, operation stages of the flip-flop 57 from the flip-flop 41 ₁ than the case of FIG. 5 Although it is doubled, since the pipeline operation is performed as described above, the flip-flop 57
The speed obtained one after another is faster than in the case of FIG.

As described above, according to the present invention, the cumulative addition of fractions,
Since the generation of integer cycles is performed separately for each n series, the processing of each series can take n times longer than before, and a high-speed periodic signal can be generated using inexpensive components. Can occur.

The examples up to FIG. 10 are configured on the assumption that the depth of the cycle value memory 12 is large (the number of cycles that can be changed is large), but the depth of the cycle value memory 12 is small and the fraction of the cycle value is small. When the number of bits of F is large (eg, the depth is 2, the fraction is 10 bits), that is, when the depth is smaller than the fraction, the period generator 21
Cycle value memory 12 and cumulative adder 45 _1, 45 ₂ same as FIG. 11, 13 also have ask if period generator 21 and the delay waveform generator to the delay waveform generator 22 as shown in Figure B in There is an effect that the number of core wires of the connection cable between the cable 22 and the cable 22 can be reduced. In this case, if the address of the cycle value memory 12 received by the cycle generator 21 is also given to the delay waveform generator 22, the delay waveform generator 22 can generate the fractional data by itself, so that the same effect as described above is obtained. Obtainable.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28

Claims (8)

(57) [Claims] 1. A cycle generator for generating an integer value having a clock cycle as a unit and a cycle set by a fractional value thereof, wherein the first to n-th fractional first-stage flip-flops to which the fractions are supplied are provided. An integer of 2 or more), the second to n-th fractional next-stage flip-flops to which the outputs of the second to n-th fractional first-stage flip-flops are respectively supplied, and the outputs of the first to n-th fractional first-stage flip-flops At that time, the output of the first-stage flip-flop for the n-th fraction is the last addition, the clock cycle or less in the addition result is output as the cumulative addition result, and the carry of the last addition is output. And a first-stage flip-flop (i) for the first through (i−1) -th fractions.
= 2,3,... N) and the outputs of the i-th to n-th fraction next-stage flip-flops are cumulatively added. An i-th accumulator which outputs the clock cycle or less of the addition result as a cumulative addition result, and outputs the carry of the last addition; and a cumulative addition result of the first accumulator. A first-stage flip-flop to which the integer value is supplied, and a first-to-n-th integer flip-flop to which the output of the first to n-th integer first-stage flip-flop is respectively supplied. The output integer values of the next-stage flip-flop for the n-th integer and the next-stage flip-flops for the first to n-th integers are respectively supplied, and counting of the clock is started from an initial value by a start command, and the count value is input. The first to n-th match detection counters that generate an output when they match the given integer, and the outputs of the first to n-th match detection counters are supplied, respectively, and the carry outputs of the first to n-th accumulators are used. Controlled, the input is delayed by one clock period in the state where the carry output is present, the input is output without delay in the state where the carry output is not present, and the output is the second, third,. , N-th, and n-th delay circuits to be supplied to the start terminals of the match detection counters; an output of the first delay circuit; and an output of the third-stage flip-flop as a set delay amount. A first delay element, and outputs of the second to n-th delay circuits, respectively,
Second to n-th delay elements to which outputs of the second to n-th accumulators are respectively given as set delay amounts; an OR circuit for combining outputs of the first to n-th delay elements; and each of the coincidence detection counters Means for loading data into the memory, enabling each of the flip-flops and the first to n-th accumulators at the output of the p-th delay circuit (p: any of 1 to n); and the q-th delay circuit (Q ≠ p 1, 2,..., N), and when the output of the next-stage flip-flop for the q-th integer is not zero, control by the carry output of the accumulator is delayed by one enable period. And a q-th delay adjusting means. 2. An address string having the same cycle as the enable cycle from the pattern generator is taken out every nth row and converted into first to n-th address strings whose cycle is n times the enable cycle. The first to n-th fractions and the first to n-th integers are read out from the cycle value memory every n enable cycles by the converted first to n-th address strings, and the first to n-th integers are read.
The delay data strings stored in the first to n-th fractional first-stage flip-flops and the first to n-th integer first-stage flip-flops and determining the phase of the generated pattern for each of the enable cycles from the pattern generator are represented by the n The first one in which every cycle is taken out and the cycle is n times the enable cycle
To the n-th delayed data sequence by the delayed data sequence converting means, and the converted first to n-th delayed data sequences are output from the first to n-th cumulative adders by the first to n-th adders, respectively. 2. The period generator according to claim 1, wherein the delay is set for the first to n-th delay elements by adding. 3. A cycle generator for generating a cycle set by an integer value and a fractional value in units of a clock cycle, wherein n address strings having the same cycle as an enable cycle from the pattern generator (where n is 2) Address string conversion means for taking out every other (the above integer) and converting it into first to n-th address strings whose cycle is n times the enable cycle; and using the converted first to n-th address strings for each enable cycle. A first cycle value memory to be read, a first to n-th fractional flip-flop for carry detection for storing first to n-th fractions respectively read from the first cycle value memory; First to n-th integer first-stage flip-flops for storing first to n-th integers read from the cycle value memory, respectively, and the second to n-th fraction first-stage flip-flops for carry detection The outputs of the carry detection second to n-th fraction next-stage flip-flops to which outputs of the carry are supplied, respectively, and the outputs of the carry detection first to n-th fraction first-stage flip-flops are cumulatively added. The output of the first-stage flip-flop for the n-th fraction for carry detection is the last addition, and the first accumulator for carry detection for outputting the carry of the last addition; The output of the first-stage flip-flop for a -1 fraction (i = 2, 3,..., N) and the output of the next-stage flip-flop for the ith to n-th fractions for carry detection are cumulatively added. The output of the first-stage flip-flop for the (i-1) -th fraction for carry detection is the last addition, and the i-th accumulator for carry detection for outputting the carry of the last addition; The output of the first stage flip-flop is supplied The first to n-th integer next-stage flip-flops and the first to n-th integer next-stage flip-flops are supplied with output integer values, respectively, and the count of the clock is started from an initial value by a start command. , A first to an n-th coincidence detection counter that generates an output when the first and the n-th coincidence detection counters are respectively supplied, and the first to the n-th cumulative additions for the carry detection are supplied. The input is delayed by one clock cycle in the state where the carry output is present, the input is output without delay in the state where the carry output does not exist, and the output is output in each case. 2, 3rd,..., Nth, 1st to nth delay circuits to be supplied to the start terminals of the match detection counters, and read out at every n enable period by the converted first to nth address strings. A two-period value memory, a first to n-th fractional flip-flop for fraction detection in which the first to n-th fractions read from the second periodic value memory are stored, respectively; Fraction detection second to n-th to which outputs of the first-stage flip-flop for n-fraction are respectively supplied.
A fraction next stage flip-flop; a fraction detection first cumulative adder that cumulatively adds the outputs of the fraction detection first to n-th fraction first stage flip-flops and outputs a result of the addition equal to or less than the clock cycle; The outputs of the first through i-th fractional flip-flops for fraction detection and the outputs of the i-th through n-th fractional flip-flops for fraction detection are cumulatively added, and the clock cycle of the addition result is obtained. An i-th accumulator for detecting a fraction, a third-stage flip-flop to which the addition result of the first accumulator for detecting a fraction is supplied, and a flip-flop having the same cycle as the enable cycle from the pattern generator. Delay data string conversion means for taking out every nth delayed data string and converting the data into first to n-th delayed data strings whose cycle is n times the enable cycle; A first adder that adds the output of the third-stage flip-flop; and a second to an adder that add the second to the n-th delayed data strings and the outputs of the fraction detection second to the n-th cumulative adders, respectively. An n-th adder, corresponding to a delay from the reading of the second period value memory to the output of the fraction detecting second to n-th accumulator for the output of the first to n-th delay circuits, First to n-th timing means for providing a predetermined delay, and outputs of the first to n-th timing means are supplied, and outputs of the first to n-th adders are respectively provided as set delay amounts. an n-delay element, an OR circuit for synthesizing the outputs of the first to n-th delay elements, loading of the coincidence detection counters, the flip-flops, the carry detection first to n-th accumulators, Fractional inspection Means for enabling the output first to n-th accumulators with the output of the p-th delay circuit (p: any one of 1 to n); and the q-th delay circuit (q ≠ p 1, 2,...) , n), and q-th delay adjusting means for delaying the control by the carry output of the accumulator by one enable cycle when the output of the next-stage flip-flop for the q-th integer is not zero. A periodic generator, characterized in that: 4. A first to n-th pattern data sequence having the same cycle as the enable cycle from the pattern generator is taken out every nth row, and the cycle is made n times the enable cycle.
Pattern data string conversion means for converting the data into a pattern data string, and each of the first to n-th pattern data strings are set between the output examples of the first to n-th delay elements and the OR circuit, respectively. 4. The period generator according to claim 2, further comprising first to n-th waveform generating means for transforming an input pulse into a waveform corresponding to each set pattern data. 5. A cycle generator for generating an integer value in units of a clock cycle and a cycle set by a fractional value thereof, wherein the cycle number is n times (n is an integer of 2 or more) the enable cycle from the pattern generator. A cycle value memory which is read every n enable cycles by the 1st to nth address strings, and a first to nth fractional first stage flip-flop to which the first to nth fractions read from the cycle value memory are respectively supplied; Cumulatively adding the outputs of the second to n-th fractional first-stage flip-flops to which the outputs of the second to n-th fractional first-stage flip-flops are respectively supplied, and the outputs of the first to n-th fractional first-stage flip-flops; At that time, the output of the first-stage flip-flop for the n-th fraction is the last addition, and the clock cycle or less in the addition result is output as the cumulative addition result. A first accumulator that outputs a carry; and a first-stage flip-flop (i)
= 2,3,... N) and the outputs of the i-th to n-th fraction next-stage flip-flops are cumulatively added. An ith accumulation adder that outputs the accumulation below the clock cycle in the addition result as an addition result and outputs the carry of the last addition, and an addition result of the first accumulation adder are supplied. A third stage flip-flop, a first adder for adding a first delay data string whose period from the pattern generator is n enable periods, and an output of the third stage flip-flop; A second to an n-th adder for respectively adding a second to an n-th delay data string having a cycle of an n enable cycle and the outputs of the second to the n-th accumulators; 1 to n-th integer value First to n-th integer first-stage flip-flops respectively supplied; first to n-th integer first-stage flip-flops to which outputs of the first to n-th integer first-stage flip-flops are respectively supplied; The output integer value of the next-stage flip-flop for the n-th integer is supplied, the count of the clock is started from the initial value by the start command, and the output is generated when the count value matches the input integer. The outputs of the n-th match detection counter and the first to n-th match detection counters are supplied, respectively, and controlled by the carry output of the first to n-th accumulators. .., N, and first coincidence detection counts, respectively, with the input delayed by the clock period, without the input being delayed in the absence of a carry output. A first to an n-th delay circuit to be supplied to a start terminal of the first delay circuit;
First to n-th delay elements to which outputs of the first to n-th adders are respectively given as set delay amounts; an OR circuit for synthesizing the outputs of these first to n-th delay elements; Means for loading data, enabling each of the flip-flops and the first to n-th accumulators with the output of the p-th delay circuit (p: any one of 1 to n), and the q-th delay circuit ( .., n) of q ≠ p, and delays the control by the carry output of the accumulator by one enable period when the output of the next-stage flip-flop for the q-th integer is not zero. and q delay adjusting means. 6. A cycle generator for generating a cycle set by an integer value and a fractional value in units of a clock cycle, wherein a cycle from the pattern generator is n times (n times) an enable cycle.
Is an integer of 2 or more), the first cycle value memory read out at every n enable cycle by the first to nth address strings, and the first to nth fractions read from the first cycle value memory are stored respectively. A first-stage flip-flop for first to n-th fraction for carry detection; a first-stage flip-flop for first to n-th integer in which first to n-th integers read from the first period value memory are stored, respectively; The second through n-th flip-flops for carry detection to which the outputs of the first through second flip-flops for carry detection are supplied, respectively, and the first through n-th fractions for carry detection The output of the first-stage flip-flop for n-th fraction is cumulatively added at this time, and the output of the first-stage flip-flop for the n-th fraction for carry detection is the last addition, and the first for carry detection for outputting the carry of the last addition. An accumulative addition device, outputs of the first to ith fraction carry first-stage flip-flops (i = 2,3,..., N) for carry detection, and outputs of the ith to n-th fractions for carry detection. The output of the first stage flip-flop for the (i-1) -th fraction for carry detection is the last addition, and the carry of the last addition is output for carry detection. An i-th accumulative adder; first to n-th integer next-stage flip-flops to which outputs of the first to n-th integer first-stage flip-flops are supplied, respectively; and first to n-th integer next-stage flip-flops. The first to n-th match detection counters each of which starts counting the clock from an initial value in response to a start command and generates an output when the counted value matches the input integer. 1st to n-th match detection counts The carry output of each of the first through n-th accumulators is controlled by the carry output, and the input is delayed by one clock cycle in the presence of the carry output. .., N-th and n-th delay circuits for outputting inputs to the start terminals of the second, third,... A second cycle value memory which is read every n enable cycles by the first to nth address strings, and a first for fraction detection which stores the first to nth fractions read from the second cycle value memory, respectively First to n-th fraction flip-flops; second-to-n-th fraction flip-flops to which outputs of the second to n-th fraction first-stage flip-flops are respectively supplied; and first to n-th fractions for the fraction detection. for A first accumulator for detecting a fraction, which accumulatively adds the outputs of the first-stage flip-flops, and outputs a result of the addition that is equal to or less than the clock cycle; An i-th cumulative adder for detecting a fraction, which cumulatively adds the outputs of the next-stage flip-flops for the i-th to n-th fractions for detecting a fraction and outputs a result of the addition which is equal to or less than the clock cycle; A third-stage flip-flop to which the addition result of the 1-cumulative adder is supplied; a first delay-data column having a period of n enable periods from the pattern generator and an output of the third-stage flip-flop An adder; second to n-th delayed data strings whose cycle from the pattern generator is n enable cycles; and second to n-th fraction detecting cycles.
A second to an n-th adder for adding the output of the accumulator respectively; and an output of the first to the n-th delay circuits, the reading of the second period value memory from the second to the n-th for detecting a fraction. First to n-th timing means for providing a delay corresponding to the delay until an output is obtained from the accumulator; and outputs of the first to n-th timing means are supplied, respectively. First to n-th delay elements each having an output given as a set delay amount; an OR circuit for synthesizing the outputs of the first to n-th delay elements; loading of each of the coincidence detection counters; each of the flip-flops; Means for enabling the first to n-th accumulators for raising detection, the first to n-th accumulators for fraction detection, at the output of the p-th delay circuit (any of p: 1 to n); Q-th delay circuit ( 1, p, 1, 2,..., N), and when the output of the next-stage flip-flop for the q-th integer is other than zero, the control by the carry output of the accumulator is delayed by one enable period. A cycle generator, comprising: delay adjusting means. 7. A first to n-th pattern data string, which is inserted between the output side of each of the first to n-th delay elements and the OR circuit, and whose cycle from the pattern generator is n times the enable cycle. A first for converting the input pulse into a waveform corresponding to each of the set pattern data and the set pattern data;
7. The period generator according to claim 5, further comprising: nth to nth waveform generation means. 8. Each of the accumulators receives a lower digit portion of each input, accumulates the lower digit portion of each input, a carry of the lower digit adder, An upper digit adder for inputting an upper digit portion with respect to the lower digit portion, and accumulating them, an accumulated value of one clock cycle or less of the lower digit adder, and an upper digit adder on the digit side. 7. The period generator according to claim 1, further comprising means for bit-combining the accumulated addition value of one clock cycle or less and outputting the result as an accumulated addition result.