JP2704203B2 - Timing generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator for generating a variable period timing signal suitable for multi-phase, which is effective when applied to an LSI test apparatus or the like. is there.

[Conventional technology]

FIG. 1 shows a block diagram of a conventional timing generator for achieving multi-phase. A conventional timing generator includes a periodic signal generator 11 that repeatedly generates a periodic signal having a period corresponding to periodic data input from the outside and a delay clock signal having a fixed period in synchronization with the periodic signal; Each of the delay clock signals receives a delay clock signal, and delay signals (1 to
It was constituted by a signal delay unit 12 ₁ to 12 repeatedly generates n) _n. The operation of the conventional example will be described in detail with reference to the operation timing chart of FIG. First, the cycle of the delay signal (cycle data) x and the delay time of the delay signal (delay data)
2 is set in the periodic signal generator and each signal delay unit, respectively. Next, by starting the periodic signal generator, the periodic signal generator 11 continuously generates a periodic signal and a delay clock signal. Each signal delay unit 12 ₁ to 12 _n receives the periodic signal and the delayed clock signal from the periodic signal generator 11 in the phase difference allowable respectively, the number of clocks coefficient operation of the delay clock signal on the basis of the periodic signal I do. When the count value matches the respective delay data, a delay signal is generated. By repeating such an operation for each periodic signal, a delay signal is continuously generated. FIG. 2 shows an example in which the delay data is set to 2, and the delay signal is generated by the second delay clock signal based on the periodic signal.

[Problems to be solved by the invention]

Above conventional timing generator as described, but a delay clock signal and the periodic signal generated by the periodic signal generator 11 it is necessary to distribute to each signal delay unit 12 ₁ to 12 _n, the distribution In some cases, there is a restriction that the phase relationship between the periodic signal and the delay clock signal must be adjusted within an allowable range. The allowable range of this phase difference is
It depends on the setup time Ts and the hold time Th of the counter constituting the signal delay unit. If the phase difference between the periodic signal and the delay clock signal exceeds the allowable range as shown in FIG. 3, a desired delay signal cannot be obtained due to malfunction of the signal delay unit. For example, when the delay clock signal has a faster phase relationship than the periodic signal as shown in FIG.
Th is insufficient and malfunction occurs. Further, when the delay clock signal has a late phase relationship with the periodic signal as shown in FIG. 2B), Ts becomes insufficient and malfunction occurs.

Therefore, in the conventional timing generator, it is necessary to adjust the phase relationship between the synchronization signal and the delay clock signal within the allowable phase difference at the input stage of the signal delay unit. Therefore, when actually implementing a device, a means for adjusting the phase relationship between the two signals is required, and there are problems such as an increase in the amount of hardware and limitations on the accuracy of phase adjustment. There was a limit to the polymorphism of. The conventional problem will be described in more detail by taking a timing generator in an LSI test apparatus as an example.
In the pin test device, the number of signal delay device phases is 1280.
In order to supply the periodic signal generated by the periodic signal generator and the clock signal for delay to all of the signal delay units, there are multiple stages between the periodic signal generator and the signal delay unit due to the limitation of the driving capability of the periodic signal generator. However, the phase difference between the periodic signal and the clock signal for delay is greatly different for each distribution circuit because the distribution circuits have individual performance differences and variations in the wiring length in the circuit. . For example, assuming a relatively fast value of 2 ns as the cycle of the delay clock signal, the allowable range of the phase in the normal signal delay unit is about 100 to 200 PS. This tolerance is 2 to 2 even if we consider only the wiring length.
This corresponds to an extremely short wiring length variation of about 3 cm. Actually, there is not only a fixed variation in time such as a wiring length but also a dynamic variation due to a temperature variation or a voltage variation of the distribution circuit as described above, so that an allowable value of the variation due to the wiring length is more severe. This makes it difficult to implement in a large system such as an LSI test device. Therefore, when speeding up or increasing the number of phases is to be achieved in the past, as shown in FIG.
4 was added, but the phase adjustment circuit 13,
There is a problem that there is a limit to the high precision of 14, the difficulty in responding to dynamic variations of the distribution circuit 15, etc., and the addition of a phase adjustment circuit increases the overall hardware There were restrictions on polymorphism.

An object of the present invention is to be used for an LSI test device or the like,
It is an object of the present invention to provide a timing generator capable of easily realizing high speed and multi-phase delay signals, and further reducing the total hardware amount.

[Means for solving the problem]

According to the present invention, the basic clock signal having a period determined by the content of the periodic clock data input from the outside is repeatedly generated by the periodic clock generator, and the basic clock signal is supplied to the delay generator. The delay generator includes a series connection of a coarse delay generator and a minute delay generator, and the coarse delay generator counts down the delay data register storing delay data from the outside and the basic period clock signal, A counter that loads the delay data stored in the delay data register and outputs a coarse delay clock each time a borrow occurs, stores initial delay data in the delay data register, and stores initial delay data in the delay data register. And a means for storing the cycle delay data in the delay data register, and the small delay generator includes a plurality of signal paths provided with a predetermined delay time difference smaller than the basic cycle clock signal. , A plurality of units each including a selection circuit for selecting one of the plurality of signal paths are cascade-connected. Selection of each selection circuit knit made in accordance with the data set in the small delay data register,
A delay equal to or less than the cycle of the basic cycle clock signal is given to the input clock according to this data.

〔Example〕

Prior to the description of the embodiments of the present invention, the principle of the present invention will be described.

FIG. 5 shows the relationship between the delay time of the delay signal and its period. The delay time is defined by a delay time with respect to a reference timing (timing of S: delay time D in the figure). Therefore, a delay signal having a delay time D means a signal having a delay time of D with respect to S in each cycle as shown in the figure. On the other hand, since the cycle of the delay signal has the same value of T as the cycle of S, the delay signal having the delay time D has a delay time of D with respect to S only in the first cycle, On the other hand, it can be rephrased as a signal repeatedly generated with the delay time T. In this sense, a signal having the same cycle and a different delay time is a signal that differs only in the delay time of the first cycle, and thereafter repeatedly generates a delay with the delay time T with respect to the immediately preceding delay signal. it can. According to such a concept, the occurrence of the period and the occurrence of the delay can be basically handled in the same manner. Therefore, unlike the conventional case, it is not necessary to generate the former by sharing the former with a periodic signal generator and the latter with a signal delay, respectively.If a different delay time is generated between the first cycle and the subsequent cycle, only the signal delay is required. Thus, a periodic signal and a delay clock signal can be generated. More specifically, a signal delay unit that has received a basic clock signal having a predetermined cycle generates a delay signal with a delay time D in the first cycle, and then generates a delay signal with a delay time T, thereby obtaining a desired delay signal. Can be obtained. According to this, since only one kind of signal distribution of the basic clock signal is required between the periodic signal generator and the signal delay device, the conventional problem can be solved.

FIG. 6 shows an embodiment of the present invention. The figure shows an example in which the generation timing is multi-phased. The timing generator according to the present invention includes a periodic clock generator 21 that repeatedly outputs a basic periodic clock signal (RCLK signal) corresponding to an externally input periodic clock data, a delayed clock that receives the basic periodic clock signal, and receives an externally input delayed data. Delay generator 22 that repeatedly generates a delay signal having a cycle and delay time corresponding to
_{1 to} 22 _n .

Its operation, first sets the periodic clock data period clock generator 21 sets each of the period delay data of the initial delay data and subsequent cycles of the first cycle to the delay generator 22 ₁ through 22 _n. By starting the periodic clock generator 21, a basic periodic clock signal is generated from the periodic clock generator 21, and each of the delay generators 22 _{1 to} 22 _n
Distribute to Each delay generator 22 ₁ through 22 _n receives the basic period clock signal to generate a delayed signal performs a predetermined operation corresponding to the delay data.

FIG. 7 shows an example of the coarse delay generator in the delay generator. The coarse delay generator includes a delay data register 23 for storing delay data given from the outside, and an initial value load signal (ILD signal).
Alternatively, the content of the delay data register 23 is fetched by its own carry signal (BORROW signal), a subtraction operation is performed from its own set value in synchronization with the basic period clock (RCLK) signal, and at the time when the content becomes 0, The counter 24 generates a carry signal.

The operation of the delay generator will be described in more detail with reference to the operation timing chart of FIG. 8. First, the initial delay data (3) of the first cycle is set in the delay data register 23, and the contents are loaded into the initial value (ILD). ) Set the counter 24 with the signal. At this time, the contents of the delay data register 23 and the counter 24 are both 3 values. Next, the cycle delay data (5) of the subsequent cycle is set in the delay data register 23. Thereafter, the periodic clock generator 21 is activated to generate a basic periodic clock (RCLK) signal corresponding to the periodic data. The counter 24 receives the basic period clock signal,
The counter 24 performs a predetermined counting (subtraction) operation and outputs a carry signal as a delay signal each time the content of the counter 24 becomes zero. Therefore, in the first cycle, a borrow signal is generated by the RCLK signal of the third clock, and thereafter, an operation is performed to generate a borrow signal every five clocks of the RCLK signal. The counter 24 operates to take in the contents (5) of the delay data register 23 for the next counting operation based on the carry signal generated by itself, so that the delay signal can be continuously generated thereafter. According to such a method, since only the signal between the basic clock generator 21 and the delay generator 22 needs to be a basic period clock (RCLK) signal, the phase distribution with high accuracy in the signal distribution between circuits which is a conventional problem. There is no need to perform control, so that high-speed and multi-phase devices can be easily achieved.

However, since the period of the generated delay signal and the delay time are integral multiples of the period of the basic period clock signal, each set resolution is determined by the period of the basic period clock signal. Therefore, unless the cycle of the basic cycle clock signal is generated in accordance with the cycle of the delay signal, for example, unless the cycle of the basic cycle clock signal is an extremely small value with respect to the setting resolution of the cycle of the delay signal and the delay time, As a result, the setting of the delay time of the signal is restricted.

In order to avoid this problem, the present invention employs an embodiment as shown in FIG. 9 so that the period and the delay time can be set flexibly. The embodiment of FIG. 9 has a circuit configuration in which a minute delay generator 26 for generating a delay time shorter than the basic cycle clock cycle time is added to the coarse delay generator 25 shown in FIG. The minute delay generator 26 has a plurality of signal paths (two signal paths 27 ₁ and 27 _{2 in the} figure) provided with a predetermined delay time difference.
And a selection circuit 28 for cascade-connecting a selection circuit 28 for selecting whether to pass a signal through any of the signal paths, and a small delay for storing delay data set externally and transmitting the data to the selection circuit 28. The data register 29 selects an arbitrary signal path according to the delay data and obtains a desired delay time. In the example of FIG. 9, an arbitrary delay can be set with a time resolution of 1/8 of the basic period clock signal. The signal path 27 ₂ is inserted delay elements, 4 / 8T denotes the amount of delay. Using the operation timing chart of FIG.
The operation of the figure will be described in detail. Since the operation of the coarse delay generator 25 is the same as that of the delay generator described in FIG. 7, only the minute delay generator 26 will be described here. By setting desired data to the delay data and inputting a minute delay data load signal (LDF signal), the minute delay data is set in the minute delay data register 29. The selection circuit 28 selects a predetermined signal path according to the data set in the minute delay data register 29. In the example of FIG. 10, since 5 is set, a 4 / 8T signal path and a 1 / 8T signal path are selected.
As a result, the carry signal generated by the coarse delay generator 25 is output with a delay time of 5 / 8T given while passing through the minute delay generator 26. Here, T represents the minimum period of the basic period clock signal. If a delay generator is realized by such a configuration, the period and the delay time can be set flexibly. In FIG. 9, the minute delay generator 26 is arranged at the subsequent stage of the coarse delay generator 25. However, in the present invention, the arrangement can be reversed.

The period of the delay signal generated according to the present invention has a relationship of an integral multiple of the basic period clock signal. In other words, the range in which the period of the basic period clock signal is generated is only an integer fraction of the range in which the desired period is generated. That is, in order to generate a period of, for example, 1 ms to 2 ns, the conventional method needs to have a period generation range of about 6 digits. However, according to the present invention, the period generation range of the basic period clock signal need only be up to twice the minimum period. Therefore, the minimum period 2n
In the case of s, the cycle generation range from 4 ns to 2 ns is sufficient, and the hardware of the periodic clock generator can be simplified.

Therefore, it is possible to realize a periodic clock generator with a simple circuit configuration as shown in FIG. The periodic clock generator of FIG. 11 receives a common input signal at one input terminal, sets the other input terminal as a selection terminal, gives a predetermined delay time to the input signal applied to the input terminal for the common signal, and provides an output terminal. And a delay unit 34 composed of a two-input NOR circuit 31 and a delay unit (delay circuit, delay element, delay line, etc.) 32 which are connected in parallel in the row direction so as to obtain different delay times. The delay block 34 is cascade-connected in the column direction, and the output signal of the last stage delay block is a common input signal of the first stage delay block. It has a function to occur. This periodic clock generator is configured so that the number of inverting circuits in the ring is an odd number even if any delay unit in each column in the ring is selected. The period of the basic period clock signal generated by this period clock generator is two times the total delay time in the ring.
Double. Accordingly, in the cycle of the periodic clock generator shown in FIG. 11, the delay time when the delay unit 33 of the delay time O of all the delay blocks 34 is selected is set to half of the minimum cycle to be generated. Is set to 1/2 of the difference between the generated maximum period and the minimum period, the interval between the maximum period and the minimum period can be set with a resolution of 1/256.

In such a periodic clock generator, a desired period is realized by a combination of the delay unit 33.
In order to obtain a desired period, the individual delay units 33
It is necessary to know the absolute value of the delay time.
FIG. 12 shows the RC of FIG. 11 provided with a function of measuring the delay time of the delay path for that purpose. As described above, the cycle of the basic cycle clock signal is twice as long as the total delay time in the ring. Therefore, if at least the delay time of the variable section is known, the total delay time can be calculated by adding other fixed delay amounts. , The period of the basic period clock signal can be obtained. The periodic clock generator of FIG. 12 operates as follows. First, when measuring the delay time, 0 is added to the gate terminal 35 to cut off the ring-shaped path. Next, a pulse signal is input to the test signal terminal 36, and the test pulse signal passed through the NOR circuit 37 is connected to the input terminal B of the comparator 38. On the other hand, the test pulse signal passed through the delay block 34 is connected to the input terminal A of the comparator 38. Therefore, the delay time can be obtained by measuring the phase difference between the input signals of A and B by the comparator 38. It is also possible to obtain a delay time for generating a desired period by changing the period clock data so as to obtain a desired phase difference between A and B and changing the selection of the delay path.

〔The invention's effect〕

As described above, the present invention has the following features. First, since the signal generated by the periodic clock generator is only one signal of the basic periodic clock signal, there is no need to adjust the phase between signals at the time of signal distribution, which limits the speeding up of the timing generator and the polyphase. The hardware can be simplified, and a high-speed and multi-phase timing generator can be realized very easily. Also, according to the present invention, the period of the basic periodic clock signal generated by the periodic clock generator is an integer fraction of the desired delay signal period, so that the generation range of the basic periodic clock signal period can be limited, and the amount of hardware can be reduced. Can be reduced. Further, the delay signal can be generated with a resolution equal to or less than the cycle of the basic cycle clock signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional timing generator for achieving multi-phase, FIG. 2 is an operation timing diagram of the conventional timing generator, and FIG. 3 explains a problem of the conventional timing generator. FIG. 4 is a diagram showing a permissible phase margin between a periodic signal and a delay clock signal, FIG. 4 is a block diagram showing a conventional timing generator for speeding up and increasing the number of phases, and FIG. 5 explains the concept of the present invention. FIG. 6 is a block diagram showing an embodiment of the present invention, FIG. 7 is a block diagram showing a specific example of a coarse delay generator in a delay generator, and FIG. FIG. 9 is an operation timing diagram of the coarse delay generator of FIG. 7, FIG. 9 is a block diagram showing an example of the delay generator, FIG. 10 is an operation timing diagram of the delay generator of FIG.
FIG. 11 is a block diagram showing a specific example of the periodic clock generator, and FIG. 12 is a block diagram showing another example of the periodic clock generator.

Claims (1)

(57) [Claims] A period clock generator for repeatedly generating a basic period clock signal having a period determined by the content of the period clock data input from the outside; a delay data register storing delay data from the outside; And a counter that loads the delay data stored in the delay data register and outputs a coarse delay clock each time a carry-down occurs, stores the initial delay data in the delay data register, and stores the delay data. Means for loading initial delay data of a register into the counter, and thereafter storing the periodic delay data in the delay data register; and a plurality of signal paths provided with a predetermined delay time difference smaller than the cycle of the basic periodic clock signal. And a selection circuit for selecting one of the plurality of signal paths. A plurality of units are connected in cascade, and selection in each selection circuit of these units is made according to data set in the minute delay data register. In accordance with this data, a delay equal to or less than the cycle of the basic cycle clock signal is input clock. The coarse delay generator and the minute delay generator are connected in series to form a delay generator, and a plurality of the delay generators are provided. A timing generator wherein the basic period clock signal is input in parallel to each clock input terminal of the device.