JP2543514B2 - Timing signal generator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a timing signal generator used in a test apparatus for ICs and LSIs and general measuring instruments, and particularly to a high speed and The present invention relates to a timing signal generator suitable for a test device or the like that performs an accurate timing test.

[Conventional technology]

Regarding timing signal generators used in conventional IC and LSI test equipment, for example, Digest of Papers, Semiconductor Test Symposium (1977), pages 152 to 157 (Digest of papers S
emiconductor test symposium (1977) pp152-157).

FIG. 3 is a block diagram illustrating this conventional timing signal generator. The timing signal generator includes a basic clock generator CG that generates a basic clock 114 corresponding to the basic clock setting signal 211, a rate generator RG that generates a test cycle signal 116 corresponding to the test cycle setting signal 217, and
The phase generator PG is configured by three parts, which output the phase signal 122 corresponding to the phase setting signal 219 and the phase fine adjustment signal 222.

The basic clock generator CG consists of a reference oscillator 10 and a so-called PL.
It consists of an L synthesizer. That is, the PLL synthesizer divides the reference oscillation signal 110 of its output by V by the value V given by the basic clock setting signal 211, and a V frequency divider 11.
The voltage controlled oscillator 14 whose oscillation frequency is controlled by the control voltage 113, the F divider 15 that divides the output basic clock 114 by F, and the phases of the F divided output 115 and the V divided output 111 are The phase comparator 12 to be compared and the error signal 11 of its output
It is composed of a low-pass filter 13 that smoothes 2 and outputs a control voltage 113.

The rate generator RG counts the basic clock 114 and generates a count output 101, and a rate synchronization counter 1 and a count output 1
Comparing 01 and the test cycle setting signal 217, and if they match, a rate comparator 3 that outputs a rate match output 103
And a reset gate 2.

The phase generator PG compares the count output 101 and the phase setting signal 219, and generates a phase coincidence output 104 when the two coincide with each other, and a phase comparator 4 that varies the delay time in response to the phase fine adjustment signal 222. It comprises a delay circuit 22 and a pulse gate 5.

FIG. 4 is an operation waveform diagram of the timing signal generator of FIG. Next, the operation of FIG. 3 will be described with reference to FIG.
First, in the basic clock generator CG, the phase comparator 12 compares the phases of the V-divided output 111 and the F-divided output 115, and outputs the output error signal 112 via the low-pass filter 13 to the control voltage 113. Is applied to the voltage controlled oscillator 14. As a result, V division output 11
PLL so that the oscillation period T _F of one of the oscillation period T _V and F divider output 115 is equal (Phase Locked Loop) control is performed.
Therefore, if the period of the basic clock 114 is T _C and the reference oscillation signal 110 period is T _S , then T _V = V · T _S …… (1) _TF = F ・ T _C …… (2) T _V = T _F …… (3) From the formulas (1) to (3), T _C = (V / F) · T _S …… (4), and the cycle of the basic clock 114 according to the value V given by the basic clock setting signal 211. T _C can be changed.

In the rate generator RG, the late synchronization counter 1 counts the basic clock 114 and outputs a count output 101. Then, when the test cycle setting signal 217 and the count output 101 match, a rate match output 103 is generated, the rate synchronous counter 1 is reset via the reset gate 2, and the counting operation is repeated again. Therefore, the period of the test period signal 116 is T
_{If RATE} and the set value of the test cycle setting signal 217 are N _R , then T _RATE = N _R · T _C = N _R (V / F) · T _S (5).

Phase setting signal 219 and count output 1 in phase generator PG
When 01 matches, a phase matching output 104 is generated, and a phase pulse 105 having the same pulse width as the basic clock 114 is obtained via the pulse gate 5. Further, according to the phase fine adjustment signal 222, the variable delay circuit 22 having a variable width of one cycle or less of the basic clock 114 can obtain the high resolution phase signal 122. Therefore, the delay time of the phase signal 122 is T _phase , and the phase setting signal 219
_Let P be the set value of T and the delay time of the variable delay circuit 22 be T _d , then T _phase = P · T _C + T _d (6).

By the way, in the above timing signal generator,
If the variable width of the variable delay circuit 22 is large, the precision is deteriorated due to the increase in the number of delay element passage stages as the resolution is increased. Therefore, in order to obtain the phase signal 122 with high resolution and high accuracy, it is possible to increase the frequency of the basic clock 114, sufficiently reduce one cycle of the basic clock 114, and obtain a sufficient variable range with a variable delay circuit having a small variable width. Mandatory. Similarly, in order to obtain the high-speed test period signal 116, it is necessary to increase the frequency of the basic clock 114. However, since the basic clock 114 has to be counted by the synchronous counter, it is disadvantageous for speeding up, high accuracy, and high resolution of the timing signal. This is because, in the synchronous counter, generally, the carry operation of the most significant bit needs to be performed within the time period within the basic clock cycle, which is not suitable for the high speed operation.

[Problems to be solved by the invention]

The above-mentioned conventional technique is disadvantageous in increasing the reference oscillation frequency because it is necessary to count the basic clock with the synchronous counter. Further, since the variable range of the variable delay circuit is required up to the basic clock cycle, if the reference oscillation frequency cannot be increased, it becomes necessary to expand the variable range of the variable delay circuit.
The accuracy of the delay time in the variable delay circuit deteriorates, and the time accuracy of the phase signal deteriorates. Further, when the count output of the synchronous counter is distributed to a plurality of phase generating units, there is a problem that adjustment is necessary to minimize the time difference between the signals.

The object of the present invention is to solve the above problems, and
(EN) Provided is a timing signal generator which can obtain a highly accurate timing signal.

[Means for solving problems]

The above-mentioned object is to generate a timing signal generator by a PLL synthesizer from a reference oscillation signal by a basic clock generating means for generating a basic clock having a variable period T _C , and divide the basic clock from the basic clock generating means by a variable frequency division number. By configuring the periodic signal generating means for generating a periodic signal of a variable cycle by one round and one or more phase signal generating means, each phase signal generating means is provided with the basic clock from the basic clock generating means. A frequency divider that divides by a desired frequency division number in a state asynchronous with the basic clock, and in a state where a frequency division output is obtained from the frequency divider, using the periodic signal from the periodic signal generation means as a trigger, A synchronous counter that divides the frequency-divided output by a variable frequency division number in a state of being synchronized with the frequency-divided output, and a delay cycle as the frequency-divided output from the synchronous counter. No. of the basic clock from the basic clock generating means as a shift clock, T _C × variable integral multiple time duration of the first variable delay circuit for shifting a delay, from the variable delay circuit of the first shift delay This is achieved by delaying the delayed period signal thus generated by a desired time within T _C and by configuring the second delay circuit that generates a phase signal having a desired phase.

[Work]

In the above timing signal generator, the rate divider divides the basic clock by G, and then the rate synchronization counter G
The divided basic clock is counted to generate a counting end pulse, the phase divider divides the basic clock by M, and then the phase synchronization counter counts the M divided basic clock to determine the basic clock period. Since the phase signal is obtained with a resolution of M times, the rate synchronization counter and the phase synchronization counter do not need to operate at high speed, and the basic clock can be increased in frequency up to the operating frequency of each frequency divider. A variable delay circuit using a phase shift register changes the delay time with the same resolution as the cycle of the basic clock by switching the number of register stages through which the phase signal passes, and the variable width in the variable delay circuit for fine adjustment is basically Since there is one cycle of the clock, the variable width becomes smaller due to the higher frequency of the basic clock, and therefore the ratio of the minimum resolution to the variable width in the variable delay circuit also becomes smaller.
The number of delay signal passage stages is small, and high resolution and high precision phase signals can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing an embodiment of a timing signal generator according to the present invention. The same reference numerals or symbols throughout the drawings indicate the same or corresponding parts. First
In the figure, the timing signal generator includes a basic clock generation unit CG that generates a basic clock 114 corresponding to the basic clock setting signal 211, a frequency division number setting signal 216 and a test cycle signal corresponding to the test cycle setting signal 217. The phase signal corresponding to the rate generator RG that generates 116, the phase setting signal 219, the shift register delay circuit setting signal 220, and the phase fine adjustment signal 222.
It is composed of three parts of a phase generator PG that outputs 122.

The basic clock generation unit CG has a reference oscillator 10, a V frequency divider 11 that divides the output reference oscillation signal 110 by the value V given by the basic clock setting signal 211, and a control voltage 113 to change the oscillation frequency. A controlled voltage controlled oscillator 14, an F divider 15 that divides the output basic clock 114 by F, a phase comparator 12 that compares the phases of the F divided output 115 and the V divided output 111, It is composed of a low-pass filter 13 which smoothes the output error signal 112 and outputs a control voltage 113.

The rate generator RG changes the frequency division number G from G _{0 to} G ₁ (G ₀ <G ₁ <2G ₀ −
Rate divider 16 that can be changed up to 1) and its output G
Counting the divided clock 126 and counting end pulse for rate 117
Is output to the frequency divider 16 for rate synchronization counter 17 for rate
Consists of Incidentally, the frequency divider 16 and the counter 17 constitute a so-called conventional pulse swallow frequency divider which operates as a variable frequency divider as a whole.

The phase generator PG includes a phase divider 18 that divides the basic clock 114 by M, a phase synchronization counter 19 that counts the output M divided clock 118 and outputs a phase count end pulse 119, and The basic clock 114 corresponding to the pulse selector 20 and the shift register 21 that configure the shift register variable delay circuit SRD that varies the delay time in units of one cycle of the clock 114, and the phase fine adjustment signal 222.
It is composed of a variable delay circuit 22 which varies the delay time within one cycle.

FIG. 2 is an operation waveform diagram of the timing signal generator of FIG. The operation of FIG. 1 will be described with reference to FIG.
First, in the basic clock generator CG, the phase comparator 12 compares the phases of the V-divided output 111 and the F-divided output 115, and outputs the output error signal 112 via the low-pass filter 13 to the control voltage 113. Is applied to the voltage controlled oscillator 14. PLL control so that the oscillation period T _F is equal to the oscillation period T _V and F division output 115 of the V divided output 111 is performed by the PLL configuration. Therefore, if the period of the basic clock 114 is T _C and the period of the reference oscillation signal 110 is T _S , then T _V = V · T _S …… (1) _TF = F ・ T _C …… (2) T _V = T _F …… (3) From equations (1) to (3), T _C = (V / F) · T _S …… (4), and the value V given by the basic clock setting signal 211 causes the cycle T of the basic clock 114 to change. _C can be changed.

Then, in the rate generator RG, the rate synchronization counter 17
Outputs the count end pulse 117 for rate by counting the number of times of the value C given by the test period setting signal 217, the G divided clock 126 obtained by dividing the basic clock 114 by G ₀ . Then, the rate divider 16 switches the frequency division number to the value G ₁ given by the frequency division number setting signal 216, and outputs the test period signal 116 obtained by dividing the basic clock 114 by G ₁ . At the same time, the rate synchronization counter 17 repeats the above counting operation again. Therefore, if the test period of the test period signal 116 is T _RATE and the basic clock period is T _C , then T _RATE = (C · G ₀ + G ₁ ) · T _C (7), which is given by the frequency division number setting signal 216. A test period T _{RATE that} is an integral multiple of the basic clock period T _C can be obtained by the set values G ₀ and G _{1 of the} frequency division number G. Figure 2 shows values G ₀ = 3, G ₁ = 5, C = 2
This is an example of when. At this time, since the rate synchronization counter 17 operates at a speed equal to or lower than G _0/1 of the frequency of the basic clock 114, it is possible to increase the frequency of the basic clock 114 up to the limit determined by the frequency divider 16.

Next, in the phase generator PG, the phase synchronization counter 19 and the phase divider 18 start operating by the test cycle signal 116, and the phase synchronization counter 19 divides the basic clock 114 by the phase divider 18 into M parts. When the divided M divided clock 118 is counted and the number of times of the value P given by the phase setting signal 219 is counted, the phase counting end pulse
Generates 119. Therefore, the delay time of the phase counting end pulse 119 output from the phase synchronization counter 19 can be controlled by the phase setting signal 219 in units of M times the cycle T _C of the basic clock. The next shift register variable delay circuit SRD changes the delay time with one cycle T _C of the basic clock 114 as the resolution by switching the number of stages of the registers through which the phase counting end pulse 119 passes in the shift register 21. Counting end pulse 11
9 is supplied to the shift register 21 via the pulse selector 20. At this time, the shift register delay circuit setting signal 220
The input to the shift register 21 is switched according to the set value S, and the operation of varying the delay time is performed. The phase pulse 121 output from the shift register 21 can be set in units of one cycle T _C of the basic clock 114, and the variable delay circuit 22 having a variable width within one cycle of the basic clock 114 according to the phase fine adjustment signal 222. To obtain a high resolution phase signal 122. Therefore, from the test period signal 116 to the time T _phase
When the phase signal 122 delayed by only
_Let T _{C be} the period of M, the period of the M divided clock 118 be T _MC , and the delay time in the variable delay circuit 22 be T _d , then T _phase = P · T _MC + S · T _C + T _d (8) . FIG. 2 shows an example when the values M = 4, P = 2, and S = 1.

As described above, according to this embodiment, the phase synchronization counter 19 operates at the frequency of 1 / M of the basic clock 114, while the flip-flops forming the phase divider 18 are synchronized. Because it doesn't have to work
Since there is no speed limitation due to the carry operation in the synchronous counter, and therefore the phase divider 18 is capable of high-speed operation, it is possible to operate the phase divider 18 and the shift register 21 at the basic operating frequency. Since the frequency of the clock 114 can be increased, a high-speed timing signal can be obtained.

Since the phase pulse 121 is set with one cycle of the basic clock 114 as a unit, the variable width of the variable delay circuit 22 is up to one cycle of the basic clock 114.
If this variable can be made smaller by increasing the frequency of, the ratio to the minimum resolution in the variable delay circuit 22 can also be made small, so that the number of delay signal passage stages can be made small, and accordingly, the phase signal 122 with high accuracy and high resolution can be obtained. You can

Further, when a plurality of phase generators PG are provided, the test cycle signal 116 and the basic clock 114 are supplied to the phase generators PG.
Since only two signals are supplied, it is possible to reduce the number of signal propagation time adjustment points during signal distribution as compared with the conventional method.

Although the above embodiment is an example of a timing signal generator such as a test device for performing a timing test on an IC or LSI, it can be widely used for a timing signal generator such as a general measuring instrument.

〔The invention's effect〕

According to the present invention, since the phase synchronous counter constituting the timing signal generator counts the output obtained by dividing the basic clock, the basic frequency up to the operating frequency of the divider or shift register, which is more suitable for high-speed operation than the synchronous counter, can be used. Since the clock frequency can be improved, a high-speed timing signal can be obtained. In addition, since the variable width of the variable delay circuit for fine adjustment can be reduced by increasing the frequency of the basic clock, the ratio of the minimum resolution to the variable width is reduced, and a highly accurate phase signal can be obtained.

[Brief description of drawings]

FIG. 1 is a component showing an embodiment of a timing signal generator according to the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, and FIG. 3 is a configuration diagram illustrating a conventional timing signal generator. The figure is an operation waveform diagram of FIG. 10 …… Reference oscillator, 11 …… V frequency divider, 12 …… Phase comparator, 13 …… Low-pass filter, 14 …… Voltage controlled oscillator, 15 ……
F divider, 16 …… Late divider, 17 …… Late synchronization counter, 18 …… Phase divider, 19 …… Phase synchronization counter, 20 …… Pulse selector, 21 …… Shift Register, 22 ... Variable delay circuit, CG ... Basic clock generator, RG ... Rate generator, PG ... Phase generator.

Claims (1)

(57) [Claims] 1. A phase signal generating means corresponding to each of the phase signal generating means provided by one or more with a periodic signal generated from the periodic signal generating means as a trigger based on the basic clock from the basic clock generating means. Is a timing signal generator that generates a phase signal of a desired phase by the next period signal,
A PLL synthesizer generates a basic clock having a variable cycle T _C , and a cycle for generating a cyclic signal having a variable cycle by dividing the basic clock from the basic clock generating means by a variable frequency division number. The signal generating means and one or more phase signal generating means are provided, and each of the phase signal generating means divides the basic clock from the basic clock generating means into a desired frequency division in a state asynchronous with the basic clock. With a frequency divider that divides by a number and a frequency-divided output from the frequency divider,
Using the periodic signal from the periodic signal generation means as a trigger,
A synchronous counter that divides the divided output with a variable dividing number in a state of being synchronized with the divided output, and a delay period signal as the divided output from the synchronous counter are provided as a basic clock from the basic clock generation means. As the shift clock, T _C ×
A first variable delay circuit that shift-delays by a time that is a variable integer multiple, and a shift-delayed delay period signal from the first variable delay circuit that is delayed by a desired time within T _C , A timing signal generator including a second delay circuit that generates a phase signal of a desired phase.