KR100266742B1 - Programmable frequency divider - Google Patents

Abstract

PURPOSE: A frequency divider with a possible program is provided to prevent reduction of speed according to the extension of bit and to make a circuit simple and to reduce electric power. CONSTITUTION: The frequency divider with the possible program includes a two-frequency divider(200), a detecting circuit(201), a program transposition circuit block(300), the first inverter(302), the second inverter(308), the third and fourth D-flip flops(304, 306), a T-flip flop(310) and clock control transistors(312). The program transposition circuit block(300) is connected to the two-frequency divider(200) and the detecting circuit(201). The third and fourth D-flip flops(304, 306) input the output of the detecting circuit(201) through the first inverter(302) and input the clock through the second inverter(308). The clock control transistors(312) control the clock according to the output value of the fourth D flip flop(306) and the programed value. The T-flip flop(310) divides the clock into two by receiving the output of the clock control transistors(312). The program transposition circuit block(300) controls the size of the input frequency input to the two-frequency divider(200).

Description

Programmable Frequency Divider

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable frequency divider and, more particularly, to a high speed program capable of dividing various high frequencies by a program set in a phase locked loop (PLL) frequency synthesizer. It relates to possible frequency dividers.

In general, the programmable frequency divider, together with a voltage controlled oscillator (VCO), a phase detector (PD), and a low pass filter (LPF), forms the basic structure of a phase-locked loop frequency synthesizer. come. In response to the trend of increasing the speed of the phase-locked-loop frequency synthesizer system, high frequency generation has been required. In this trend, various attempts have been made in the part of a programmable frequency divider together with a voltage controlled oscillator.

As one of these attempts, a high speed programmable frequency has been developed using the new structure.

Conventional Asynchronous Programmable Divide-by-N Ripple Counters 100 of two-division with Load or Reset, as shown in FIG. And the detection circuit 101.

In a down-counter circuit where the value of the ripple count 100 decreases, a state in which all the bits become “0” is detected and a division value is loaded into the counter 100. The delay caused by the circuit 101 can be reduced. That is, in the counter 100, the higher order bits are in the "0" state before the lower order bits, so that the values of the higher order bits are detected in advance and the values of the lowest order bits are detected later or all the bits. Delays can be reduced by detecting in advance one to two clocks before the bites become "0". Therefore, the asynchronous ripple counter 100 may be configured as a programmable two-divider (Programmable Divide-by-2) connected in series, and may avoid a delay due to carry transfer that limits the speed of the synchronous counter. .

In the up-counter type circuit in which the value of the ripple count 100 is increased, all bits Bit are detected as "1" and the complement of the divided value is loaded into the counter.

However, the problem of the conventional Asynchronous Divide-by-N as described above is the load of the divided value. For example, when a two-divider is loaded with "1" s in a down-counter scheme consisting of positive edge-triggered flip-flops that change at positive edges, they load simultaneously. If does not occur, the value loaded in the i th bit can change the i + 1 th loaded value, and some bits may have wrong division values. Therefore, to load all the bits simultaneously, there is a wide and large fanout, which limits the counter speed.

In addition, the detection circuit 101 receives a value of the current state for each counter bit, and avoids a delay due to carry transfer while detecting a state in which all bits Bit become "0" or "1". There is a problem that the circuit for the divider is required to increase the structure of the divider.

The present invention has been invented to solve the above problems, and it is possible to simply disperse large fanouts, which have been limited in the frequency divider speed, and to use a structure of a detection circuit without carry transfer. The purpose is to provide a divider.

1 is a block diagram showing the structure of a general asynchronous programmable N-divider.

2 is a circuit diagram showing the structure of a programmable N-divider according to the present invention.

3 is a waveform diagram of a simulation for showing the operation of a programmable divider according to the invention shown in FIG. 2.

4 is a circuit diagram illustrating a structure of a D flip-flop (TSPC-DFF) using a single phase clock in general.

5 is a circuit diagram showing the structure of a T flip-flop (TSPC-TFF) using a single phase clock in general.

Figure 6 is a circuit diagram for showing the structure of the programmable two-divider PDIV2 according to an embodiment of the present invention and a waveform diagram showing the operation according to the program data. FIG. 7 is a circuit diagram showing the structure of a programmable N-divider with a pre-circuit added in the circuit diagram of FIG. 2 according to the present invention.

8 is a waveform diagram simulated to show the operation of FIG. 7 according to the present invention.

<Description of the code | symbol about the principal part of drawing>

20a to 20n: program 2-divider 21: first D flip-flop

21 ': 2nd D flip-flop 22: P-Tr

23: NAND gate 24: NAND gate

26: SR-Latch 201: detection circuit

300: program pre-circuit block 302: first inverter

304: third D-flip flop 306: fourth D-flip flop

308: second inverter 312: clock adjustment transistor

The present invention for performing such an object,

If each bit is programmed as "1", only two divisions are performed without invert operation. If each bit is programmed as "0", only one invert operation is performed after the load signal is generated. A plurality of program two-dividers connected by a ripple method to divide two; And

A negative edge output from a program 2-divider that outputs the highest order bit, and outputs the highest order bit, among the multiple program 2-dividers. ( Detection circuitry for synchronizing the &lt; RTI ID = 0.0 &gt;&lt; / RTI &gt;

According to a preferred embodiment of the present invention, a detection circuit comprises: a first D flip-flop connected to an output of a program two-divider for outputting the highest order bit of the plurality of program two-dividers; A second D flip-flop that receives an output of the first D flip-flop and receives a clock opposite to the first flip-flop; A NAND gate and an inverter connected to an output terminal of the NAND gate for NAND operation of the output values of the first D flip-flop and the second D flip-flop.

According to a preferred embodiment of the present invention, the program two-divider and the detection circuit receive the output of the detection circuit through the first inverter and the third and fourth D-flop connected in series to receive the clock through the second inverter. And a clock adjusting transistor for adjusting the clock according to the output value and the programmed value of the fourth D flip-flop, and a T-flip flop for dividing the clock into two by receiving the output of the clock adjusting transistor. The program pre-circuit block that controls the magnitude of the input frequency input to the divider is connected.

The programmable frequency divider according to the present invention prevents the speed reduction due to bit expansion, simplifies the circuit and reduces power.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention;

The programmable N-divider according to the present invention does not use a general method of counting, but uses a new method of two-division / invert according to a program such as the waveform diagram in FIG. Doing. When each bit is programmed as "1", the program 2-divider (hereinafter referred to as PDIV2) performs only two divisions without invert operation, and when each bit is programmed as "0", the load signal is Once generated, only one invert operation is performed and two minutes are dispensed for the rest of the time. As a result, the higher order bit output has a large period, which is greatly reduced, and the lower order has a smaller period, which is less than the total, resulting in a total program-wide division.

Therefore, the value loaded in the i-th bit does not change the value of the i + 1 th load, which is caused by not loading all the bits presented as a problem in the prior art. You can improve speed by distributing fanouts by loading the lower order bits first, and then loading the bits after the higher ones without having to load fanouts at the same time. Also, the maximum divisional input clock is determined by the lowest possible division / invertability of the order, rather than being affected by the number of bits in the counter.

In addition, the detection circuit 201 does not need to receive the output of the current state for each counter bit, and also eliminates the need for a circuit for avoiding a delay due to carry transfer. The detection circuit 201 only needs to detect an edge generated at the highest order bit and generate a load signal from the lowest order bit in synchronization with an input clock. Therefore, the detection circuit 201 can be simply configured.

FIG. 2 shows a circuit diagram in which an n-bit program two-divider is connected in a ripple manner and a detection circuit diagram for loading, and shows a Divide-by-N, and FIG. 3 shows a spice simulation. 0.8 as the test result μm The results show that the 750 MHz maximum input frequency is divided in the CMOS process.

2, the detection circuit 201 is simply composed of two D flip-flops 21 and 22, a NAND2 23 and an inverter I1. This circuit uses the falling edge of the output of the Most Significient Bit (MSB) 20n among the PDIV2s 20a-20n connected in a ripple manner. Is synchronized to the input clock of the lowest order bit (LSB) 20a. This motivated Will remain in the state of "0" only for half a period when the input clock is "1" and at this moment the programmed divided value is reloaded.

The signal is input to the SR-Latch 26 of Fig. 6 (a) so that the programmed division value is stored in the SR-Latch. At this time The signal can effectively distribute fan-out by storing the programmed values in all PDIV2's SR-Latch (26), as explained earlier. this is The programmed value is stored as soon as possible in the low order bits PDIV2 and buffered in the high order bits PDIV2, so that the number of bits in the divider increases. Minimize the operation speed restriction by the signal. therefore Using high buffers in the memory solved the high fanout problem.

The operation of the n-bit divider 200 implemented by connecting n program two-dividers 20a to 20n in a ripple method is performed with each PDIV2 20a to 20n at reset. D-Flip-Flop (hereinafter referred to as DFF) has a clock and output of "1" Is in the "0" state. When the reset is released, the divider approaches the programmed divider value for several cycles according to the initial state of PDIV2 (20a to 20n), and then divides according to the dispensed value.

That is, as shown in FIG. 6 (a), the n-bit divider uses a falling edge of the PDIV2 20 output. Generates. This indicates the end of dispensing and causes the programmed dispensing value to be reloaded into SR-Latch 26 of PDIV2 20. Then dispense begins again.

When the value stored in SR-Latch 26 is " 1 &quot;, each PDIV2 20 is It is operated by two dividers at Rising Edge of input clock without being influenced by Invert. Even if the frequency of the input clock changes in accordance with the programmed value, it outputs a value of two divisions with different frequencies. This is the same operation as a two-divider using a typical single phase clock.

When the value stored in SR-Latch (26) is "0" Each PDIV2 inverts only during the time between the first and second rising edges of the input clock and changes the SR-Latch (26) value to '1'. Do Before the second Rising Edge Is generated, PDIV2 loads "0" and continues Invert operation without dividing. That is, Invert operation is performed only for one period of the input clock, and the remaining time is continuously divided by two minutes.

The output of this n-bit divider is output with various duty and constant period according to the programmed value.

Truth Table for TSPC-DFF reset Clock in a b out 0 z 0 One One 0 One One One 0 0 z One 0 One z z when a = 0 1 when b = 0 One 0 One z 0 when a = 1 0 when b = 1 One One 0 One 0 z One 0 0 One z 1 when b = 0 One 0 0 0 z 0 when b = 1

Since the single phase clock D-type flip-flop (TSPC-DFF) circuit of FIG. 4 is dynamic and has a single phase clock, the load on the clock is low and power consumption is low. Is small and there is no clock skew. As a positive edge-triggered flip-flop that changes at a positive edge, it has a truth table as shown in <Table 1>. That is, when the clock is "1", the output (out) has a value of high impedance (referred to as "z") to maintain the previous value, and when "0", according to the nodes in, a, b " It has values of 0 "and" 1 ".

FIG. 5 shows the structure of a single-phase clock T-type flip-flop (weak TSPC-TFF) that has a two-dividing function by connecting an input and an output in the TSPC-DFF. .

Program operation process for two-division and invert function reset Clock in a b c One 0z One 0 0 One 0 0 One 0 One 1z 0 One One 0 1z 0 0 One 0 0z 1z 0 0 0 0 One One 0z 0 One 0 1z 0 One 0 One One 0 0z One 0 0 One 0 One 1z 0 One One 0 1z 0 0 One 0 0z 1z 0 0 0 0 One One 0z = ＞ 1 0 0 One 0 One 1z 0 One One 0 1z 0 0 One 0 0z 1z 0 0 0 0 One One 0z 0 One 0 1z 0 One 0 One One 0 0z One 0 0 One 0 One 1z 0 One One 0 1z 0 0 One 0 0z 1z 0 0 0 0 One One 0z

FIG. 6 (a) shows the P-Tr 22, the NAND gate 24 and the SR- in the programmable True Single Phase Clock T-type Flip-flop (hereinafter referred to as PDIV2) circuit of FIG. 4. The addition of a latch 26 shows the circuit of a programmable two-divider (hereinafter referred to as PDIV2) 20 having a Reset. The added P-Tr 22 enables invert operation by making node c "1" when the program value is "0", and SR-Latch 26 It stores the programmed value at the time of reset and has the value "1" when reset or when the programmed value is "1" and "0" value when the programmed value is "0". The NAND gate 24 outputs "0" when the node a and the node b are "1" and the programmed value stored in the SR-Latch 26 is "0" so that the added P-Tr 22 operates. Let Node c be "1". The circuit also features positive edge-triggered dispensing.

The operation table of <Table 2> shows the operation procedure after reset using the PDIV2 circuit 20 of Fig. 6A. Here, "0z" indicates that the previous state is "0" and maintains "0" as the high impedance state, and "1z" also indicates that the previous state is "1" and keeps "1" as the high impedance state. In Table 2, when the clock is "0", the node c always divides into two with "0z" or "1z" depending on the previous value. Program value ( ) Is 0 and node c is "0z", the added P-Tr 22 converts node c to "1", causing PDIV2 (20) to change from 2 divisions to Invert for 1 clock. After changing the value stored in SR-Latch (26) from "0" to "1", it is returned to 2 minutes from the next clock. FIG. 6 (b) shows an operation waveform in which <Table 2> described above is easily seen.

Here, when reset, the output of PDIV2 20 has "1" and stores "1" in SR-Latch 26.

The limit of the maximum input frequency that can be divided in the program N-divider of FIG. 2 depends on whether the lowest order bit PDIV2 20a can be inverted. Therefore, increasing the time for only one invert during the N-dividing cycle will result in a higher maximum divider input frequency. As a method of enabling this, as shown in FIG. 7, there is a method of connecting the program pre-circuit block 300 to the program 2-divider 200 and the detection circuit 201. The program pre-block 300 receives the output of the detection circuit 201 through the first inverter 302 and the third and fourth D-flop connected in series to receive the clock through the second inverter 308. The clock is controlled by receiving the outputs of the clock adjustment transistors 312 and the clock adjustment transistors 312 that adjust the clock according to the output values and the programmed values of the 304 and 306 and fourth D flip-flop 306. The T-flip flop 310 is divided. Program pre-circuit block 300 makes the lowest order bit one more bit. When the program value of 0 is 0, the inverter 308 operates as a general inverter, and the clock is divided into two divisions in the T-flip flop 310 and input to the program two-divider 200.

Also, If the program value of is "1" Only during one period when the signal goes to "0", the output of the inverter 308 becomes High Impedence state so that the existing output does not go to "0" and maintains "1" and then the next stage T- Two minutes are divided in the flip-flop 310 to increase the time to invert in the program 2-divider 200. In this state, the input frequency of the program 2-divider 200 is increased by three times or more. As a result, in the H-spice simulation, as shown in FIG. 8, the 2.5 GHz maximum input frequency was divided in the 0.8um CMOS process.

The effects of applying the programmable frequency divider according to the present invention to a PLL frequency synthesizer are described as follows. First, the structure of the detection circuit for loading a program value is composed of a detection circuit of only the output of the highest order bit in the 'high' or 'low' detection for the output of all the bits. In addition, since a reload signal distributed to each bit can be given, there is almost no effect of speed reduction due to bit expansion. In addition, the circuit is simpler than the existing divider, has a power reduction effect, and restricts the use of a complex structure such as a two-valued dual modulus prescaler.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be improved or modified by those skilled in the art within the scope of the technical idea of the present invention.

Claims (3)

If each bit is programmed as "1", only two divisions are performed without invert operation. If each bit is programmed as "0", only one invert operation is performed after the load signal is generated. A plurality of program two-dividers 200 connected by a ripple method to divide two; And The program 2-divider 20n, which outputs the highest order bits of the plurality of program 2-dividers 200, is output from the program 2-divider 20n, which outputs the highest order bits. Using the negative edges ( And a detection circuit 201 for synchronizing the &lt; RTI ID = 0.0 &gt;)&lt; / RTI &gt; with the input clock of the program two-divider 20a outputting the lowest order bits. 2. The first circuit of claim 1, wherein the detection circuit 201 is connected to an output terminal of the program 2-divider 20n for outputting the highest order bit among the plurality of program 2-dividers 20a to 20n. D flip-flop 21; A second D flip-flop 22 which receives an output of the first D flip-flop 21 and receives a clock opposite to the first flip-flop 21; NAND gate 23 for NAND operation of the output values of the first D flip-flop 21 and the second D flip-flop 22 and the inverter I1 connected to the output terminal of the NAND gate 23 Programmable frequency divider, characterized in that. The method of claim 1, wherein the output of the detection circuit 201 is input to the program two-divider 200 and the detection circuit 201 through the first inverter 302, and the clock is supplied to the second inverter 308. Clock adjustment transistors 312 that adjust the clock according to the output and programmed values of the third and fourth D-flip flops 304 and 306 and the fourth D-flip flop 306 connected in series. And a T-flip flop 310 which divides the clock into two by receiving the output of the clock adjusting transistors 312 to adjust the magnitude of the input frequency input to the program two-divider 200 according to a program value. Programmable frequency divider, characterized in that the program pre-circuit block 300 is connected and configured.