KR102338377B1 - A programmable High-Speed Digital Clock Frequency Divider and method for controlling thereof - Google Patents

Abstract

The present invention relates to a variably programmable high-speed digital clock frequency divider and a control method thereof. The variably programmable high-speed digital clock frequency divider comprises: a synchronous counter which increase and counts the number whenever a pulse signal of an input clock (CLK_IN) occurs, and generates a count code (C) as an output signal; a count detector which compares the count code (C), which is the output signal of the synchronous counter, with a programmable variable divisor (N) applied from the outside, and generates an output clock (CLK_OUT) divided by a frequency 1/N lower than the frequency of the input clock (CLK_IN) under the control of a reset logic unit; and the reset logic unit which detects a change in the output clock (CLK_OUT) of the count detector and generates a reset signal (Reset) for controlling the state of the synchronous counter. The present invention can greatly improve the operating speed of the frequency divider to 10 GHz or more.

Description

A variably programmable High-Speed Digital Clock Frequency Divider and method for controlling thereof

The present invention relates to a clock frequency divider circuit for a semiconductor circuit, and more particularly, to a low output clock frequency of 1/N by dividing a high-speed input clock frequency by a variably programmable integer divisor value N. A high-speed CMOS-based variably programmable high-speed digital clock frequency divider for generating

The frequency divider divides the input signal to generate an output signal having a lower frequency than the input signal. The frequency divider may be applied to a clock generation circuit such as a phase-locked loop (PLL), a frequency synthesizer, and the like, and various integrated circuits including the same.

On-Chip Clock Frequency Divider is a common phase-locked loop (PLL) or Multiplying Delay-Locked Loop (MDLL) based frequency synthesizer/multiplier architecture. It is one of the most essential circuits required for multiplication.

Most integrated circuits (ICs) operating at high speed are PLL (phase-locked loop) or Multiplying Delay-Locked Loop (MDLL)-based frequency synthesizers/ It contains a frequency synthesizer/multiplier circuit, and one of the most essential components of this frequency synthesizer/multiplier structure is a programmable clock frequency divider. In order to generate the output frequency of a wide variety of PLL/MDLL-based frequency multipliers/synthesizers, the variable divisor N value of the clock frequency divider must be variably programmable over a wide range, requiring high-speed operation, small area, and low power consumption. do.

A clock frequency divider is a circuit that divides the frequency of the input clock (fclk) by a specific divisor value N to produce an output frequency fout (= fclk/N) lower than the input.

A typical clock frequency divider may include, for example, a cascaded divide-by-2 counter method and a dual-modulus prescalar method. The divide-by-2 counter type clock divider ^{can only divide the output frequency by 2 M} , so its use is limited.

where M is the number of D flip-flop stages connected in series. Dual-modulus prescalar-based dividers are primarily suitable for wireless RF applications that produce high-frequency resolution in a narrow frequency range.

The divide-by-N clock frequency dividers according to the prior art are not suitable for selectively programming the divisor N in a wide range (eg, 1 to 1024) with a small area.

In addition, the divide-by-N clock frequency dividers of the conventional structure are not suitable for high-speed operation of 10 GHz or more, or have problems with a large silicon area and large power consumption. It has a structure that is difficult to apply to applications such as PLL/MDLL-based frequency synthesizers/multipliers.

Therefore, a variably programmable frequency with ultra-high speed, low power and small area with a divide-by-N counter structure required for the ability to variably change the frequency multiplication factor N programmably in a high-speed PLL or MDLL-based frequency multiplier/synthesizer. There is a need to develop a dispenser.

Korean Patent No. 10-0266742

The present invention is to overcome the above-mentioned conventional problems, and the problem to be solved by the present invention is to freely change the value of a high-speed input clock frequency and divide it by a programmable integer divisor (= Divisor or Division Factor) N to 1 An object of the present invention is to provide a variably programmable high-speed digital clock frequency divider having a high speed, low power, and small area for generating a low output clock frequency of /N, and a method for controlling the same.

According to an exemplary embodiment of the present invention, each time the pulse signal of the input clock (CLK_IN) is generated, counting by increasing the number, a synchronous counter to generate a count code (C) as an output signal; By comparing the counter code (C), which is the output signal of the synchronous counter, and a programmable variable divisor (N) applied from the outside, the frequency of 1/N lower than the frequency of the input clock (CLK_IN) is set according to the control of the reset logic unit. a count detector for generating a divided output clock CLK_OUT; and a reset logic unit that detects a change in the output clock (CLK_OUT) of the count detector and generates a reset signal (Reset) for controlling the state of the synchronous counter. provided

The synchronous counter is composed of a plurality of flip-flops and has multiple outputs of K-bit.

Outputs of the plurality of flip-flops may be synchronized with an input clock (CLK_IN) pulse signal to output a K-bit counter code C, which is a binary output signal.

The synchronous counter performs a counting operation only when the reset signal Reset, which is the output of the reset logic unit, maintains a logic '1'. When the reset signal Reset is a logic '0', the counter code is set to '0'. ' to reset it.

The count detector is a pseudo-NMOS (Pseudo-NMOS) based count detector.

The pseudo-NMOS based count detector converts the output clock CLK_OUT from an initial logic '1' state to a logic '0' when the counter code (C) and the variable divisor (N) value are equal to each other, , when the counter code C increases at the rising edge of the next input clock CLK_IN cycle and the counter code C and the variable divisor N are different from each other, the output clock CLK_OUT is set to a logic '1' return to state

The pseudo-NMOS based count detector may include a PMOS device; a plurality of comparison units connected to the PMOS; and a first CMOS inverter coupled to the plurality of comparison units.

The PMOS is configured such that a gate terminal is connected to a logic '0' value, a source terminal is connected to a power voltage, and a drain terminal is connected to node X so that it is always turned on. and each of the plurality of comparison units is connected to the node X, receives a counter code (C) and a variable divisor (N) as two input signals to perform an Exclusive-OR (XOR) logic function, and the first The CMOS inverter receives the node X as an input and generates an output clock CLK_OUT.

Each of the complement comparison units has a pseudo-NMOS comparator structure together with the PMOS device, and when the counter code (C) and the variable divisor (N) are different, the signal of the X node is maintained at a logic '0' and, when the counter code (C) and the variable divisor (N) are the same, an operation of converting the X node to a logic '1' is performed.

Each of the complement comparison units includes two input terminals having a counter code (C) and a variable divisor (N) as inputs; first to fourth NMOS devices; and a second CMOS inverter and a third CMOS inverter;

Depending on the counter code (C) and the value of the variable divisor (N), activation or blocking of the first current path and the second current path capable of conducting the X node with a logic '0' is determined.

The first NMOS device receives the variable divisor (N) as a gate input, and a drain node is connected to the X node;

The second NMOS device receives the count code (C) as a gate input and a drain node is connected to the X node,

The second CMOS inverter receives the variable divisor (N) as an input and generates a CMOS output,

The third COMS inverter receives the count code (C) as an input and generates a CMOS output,

The third NMOS device receives the output node of the third CMOS inverter as a gate input, receives the source node of the first NMOS device as a drain, and the source node is connected to a ground;

The fourth NMOS device receives the output node of the second CMOS inverter as a gate input, receives the source node of the second NMOS device as a drain, and the source node is connected to a ground.

The reset logic unit receives the output clock (CLK_OUT) signal to generate a reset signal (Reset), and the reset signal (Reset) generates a logic '0' synchronized with a rising edge of the output clock (CLK_OUT) signal. and resetting all output counter codes (C) of the synchronous counter to logic '0'.

According to another aspect of the present invention, there is provided a method comprising: applying a variable divisor (N) value to a pseudo-NMOS based count detector; determining whether an output of the reset signal Reset of the reset logic unit is logic '1'; When the output of the reset signal Reset is logic '1', the synchronous counter receives the input clock CLK_IN and increases the count by '1' for each pulse signal of the input clock, and counts the count code (C) value resetting all counter code (C) values to 0 when the output of the reset signal (Reset) is logic 'O'; comparing the count code (C) value and the variable divisor (N) value to see if they are the same; As a result of the determination, when the count code (C) value and the variable divisor (N) value are the same, generating the output clock (CLK_OUT) divided by a frequency 1/N lower than the frequency of the input clock (CLK_IN); A variably programmable high-speed digital clock frequency divider control method is provided.

The step of generating the output clock CLK_OUT divided by a frequency 1/N lower than the frequency of the input clock CLK_IN includes:

converting an output clock (CLK_OUT) signal from an initial logic '1' state to a logic '0' when the count code (C) value and the variable divisor (N) value are the same; after the counter code C is increased by 1 on the rising edge of the next input clock (CLK_IN) cycle, comparing the count code (C) value and the variable divisor (N) value to see if they are the same; and returning the output clock signal CLK_OUT to a logic '1' state when the count code (C) value and the variable divisor (N) value are different from each other as a result of the determination.

According to the present invention, the operation speed of the frequency divider is greatly improved to 10 GHz or more by using a pseudo-NMOS-based count detector that operates at a high speed of 10 GHz or more while having a small area and low power consumption with a simple structure, and at the same time It has an area and power consumption, and has the effect of dividing by digitally programming the output frequency to 1/N of the input in a wide frequency range.

In addition, the variably programmable high-speed digital clock frequency divider according to the present invention can be applied to a high-speed frequency multiplier/synthesizer of 10 GHz or higher, and can increase the multiplication factor of the CMOS frequency multiplier/synthesizer in a wide and diverse range with a small area and power. It has the effect of variably multiplying / synthesizing.

1 is a conceptual diagram for explaining the operation of a variably programmable high-speed digital clock frequency divider according to the present invention.
2 is a block diagram of a variably programmable high-speed digital clock frequency divider according to an embodiment of the present invention.
3 is a timing diagram for explaining the operation of a variably programmable high-speed digital clock frequency divider according to the present invention.
4 is a circuit diagram showing the configuration of a pseudo-NMOS based count detector.
5 is a flowchart illustrating a control method of a variably programmable high-speed digital clock frequency divider according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram for explaining the operation of a variably programmable high-speed digital clock frequency divider according to the present invention.

1, a variably programmable high-speed digital clock frequency divider according to the present invention divides an input clock frequency fclk by 1/N according to a variable divisor (= divisor) N value programmable from the outside. It performs a function of generating an output clock fout (= (1/N)*fclk) having a low frequency. That is, it is a circuit capable of generating an output frequency fout (= fclk/N) lower than the input by dividing the frequency of the input clock fclk by a programmable variable divisor (=divisor) value N.

2 is a block diagram of a variably programmable high-speed digital clock frequency divider according to an embodiment of the present invention.

Referring to FIG. 2 , a variably programmable high-speed digital clock frequency divider according to an embodiment of the present invention includes a pseudo-NMOS based count detector 200 and a synchronous counter. 300 and a reset logic unit 400 .

The synchronous counter 300 counts by increasing the number by 1 whenever a pulse signal of the high-speed input clock signal CLK_IN having a frequency of fclk occurs, and a multi-bit count code (C) as an output signal causes In this embodiment, the synchronous counter 300 may use a multi-bit synchronous binary counter.

The pseudo-NMOS-based count detector 200 compares the counter code (C) value, which is the output signal of the synchronous counter 300, and the externally applied programmable variable divisor N value with each other, to control the reset logic unit. Accordingly, an output clock signal CLK_OUT divided by a frequency of 1/N lower than the frequency of the input clock CLK_IN is generated.

The reset logic unit 400 detects a change in the output signal CLK_OUT of the pseudo-NMOS based count detector 200 to generate a reset signal Reset for controlling the state of the synchronous counter 300 .

If each configuration is described in more detail,

The synchronous counter 300 is composed of a K-bit synchronous binary counter that counts by increasing the number by 1 in the UP counter method whenever a clock pulse of the periodic input clock (CLK_IN) occurs. do.

The synchronous counter 300 is composed of a plurality of flip-flops and may have multiple K-bit outputs, and the outputs of all flip-flops are synchronized with the input signal (CLK_IN) clock pulse to generate a binary ( Binary) It is a synchronous K-bit binary counter that outputs the K-bit counter code (C), which is an output signal. If you want to increase the range of numbers you want to count, you can change it by increasing the number of K. For example, when K=10 is used in the configuration of the K-bit synchronous counter 300, the countable range corresponds to an integer value of ^{1 to 1024 (=2 K} = 2 ^{10 ) in decimal.}

The synchronous counter 300 performs a counting operation only when the reset signal Reset, which is the output of the reset logic unit 400, maintains a logic “1”, and when the reset signal Reset is a logic “0”, Performs an operation to reset all counter output values to 0. after

When the reset signal is changed back to logic “1”, the counting operation is performed again from the initial value 0.

Each time the input clock (CLK_IN) pulse occurs, the output counter code signal (C) of the synchronous counter increases by 1 until the counter code C value becomes the trigger value N from the initial value 0 by performing a counting operation. do. Here, the trigger value means a divisor value N, and can be freely programmed using multi-bit.

If the counter code C value starts from the initial value and increases by 1 for every input clock (CLK_IN) cycle and becomes the trigger value N at the Nth rising edge, the counter code C value and the variable divisor N value are the same will lose

The pseudo-NMOS based count detector 200 detects the moment when C = N, that is, the moment when the value of the counter code C and the variable divisor N become equal to each other, and a variably programmable high-speed digital clock The output clock signal (CLK_OUT) of the frequency divider is quickly converted from an initial logic “1” state to a logic “0”.

Then, on the rising edge of the next input clock (CLK_IN) cycle, when the counter code C is incremented by 1 and the counter code C value and the variable divisor N value are different from each other, the pseudo-NMOS based count detector 200 quickly detects this moment again. Thus, the output clock signal (CLK_OUT) of the variably programmable high-speed digital clock frequency divider returns to the logic “1” state.

The reset logic unit 400 receives the output clock CLK_OUT signal and generates a reset signal Reset, and the reset signal Reset signal is a logic “0” synchronized with the rising edge of the CLK_OUT signal. A pulse signal is generated and used to reset all output counter code C values of the synchronous counter 300 to logic “0”.

By periodically repeating the above-described operation, the programmable clock frequency divider divides the input clock frequency fclk by 1/N to perform the operation of the frequency divider having an output frequency of fout = (1/N)*fclk. will perform

The maximum operating speed of the frequency divider is limited by the propagation delay time of the count detector, the propagation delay time of the synchronous counter, and the delay time of the reset logic. Among them, the delay component of the count detector occupies the largest portion. In the present invention, the operation speed of the frequency divider is greatly improved to 10 GHz or more by using a pseudo-NMOS based count detector, and at the same time, a small area and power consumption are reduced. It is characterized in that the output frequency is divided by 1/N of the input in a freely programmable manner.

3 is a timing diagram for explaining the operation of a variably programmable high-speed digital clock frequency divider according to the present invention.

3 shows the operation of the variably programmable high-speed digital clock frequency divider 100 when the variable divisor value N = 4 (corresponding to N[4:0] = [00011] in the case of using a 5-bit program code) Explain with an example.

The output counter code (C) signal of the synchronous counter 300 performs a counting operation every time an input clock (CLK_IN) pulse occurs, so that the counter code (C) value changes from the initial value 0 to the trigger value N by 1 increases Here, the trigger value means a divisor value N, and it can be freely programmed using multi-bit (eg N[4:0]).

3 shows a case in which 5-bit N[4:0] = [00011] is allocated for the variable divisor N = 4 and the output frequency is divided by 1/4 of the input frequency for programming.

When the frequency of the input clock CLK_IN is fclk, the frequency of the output clock CLK_OUT of the variably programmable high-speed digital clock frequency divider 100 is 1/N = 1/4*fclk. for example.

The counter code C[4:0] value starts from the initial value [00000] and increases by 1 every input clock (CLK_IN) cycle to become the trigger value [00011] at the 4th rising edge, at this time the counter code The value of C[4:0] and the value of the variable divisor (= N[4:0]) become equal to each other.

The pseudo-NMOS based count detector 200 quickly detects this moment (that is, the moment when the value of the counter code C[4:0] and the value of the variable divisor (= N[4:0]) become equal to each other), The output clock (CLK_OUT) signal of the variably programmable high-speed digital clock frequency divider 100 is converted from a logic “1” state maintained by waiting to a logic “0”.

And, when the counter code C[4:0] increases by 1 on the rising edge of the next input clock (CLK_IN) cycle, the counter code C[4:0] value and the variable divisor N[4:0] value become different from each other, The pseudo-NMOS-based count detector 200 quickly detects this moment again and returns the output clock signal CLK_OUT of the variably programmable high-speed digital clock frequency divider 100 to a logic “1” state.

Subsequently, the reset signal Reset, which is the output of the reset logic unit 400, generates a logic “0” pulse signal synchronized with the rising edge of the output clock (CLK_OUT) signal, and receives this, the synchronous counter 300 outputs all outputs Counter code (C) values are initialized to 0.

By periodically repeating the above-described operation, the variably programmable high-speed digital clock frequency divider 100 divides the input clock frequency fclk by 1/N to obtain a frequency having an output frequency of (1/N)*fclk. It is possible to perform the operation of the divider.

4 is a circuit diagram showing the configuration of a pseudo-NMOS based count detector.

4 illustrates a configuration of a 5-bit pseudo-NMOS (Pseudo-NMOS) based count detector 200 used in the variably programmable high-speed digital clock frequency divider 100 of the present invention as an example.

As can be seen from the descriptions of FIGS. 2 and 3 showing the operation of the variably programmable high-speed digital clock frequency divider 100 , a variable divisor N value and a counter code C value in order for the frequency divider to operate at high speed and high speed It is essential to use a 'Comparator' or 'Count Detector' capable of high-speed operation that can quickly change the phase of the output clock (CLK_OUT) of the frequency divider by comparing .

The 5-bit pseudo-NMOS based count detector 200 of the present invention shown in FIG. 4 includes a PMOS (M0) 310, a plurality of comparison units (Comparator Units) 400, 400a, 400b, 400c, 400d, and and a first CMOS inverter (INV0) 320 .

In FIG. 4 , the PMOS (M0) 310 and the plurality of comparison units 400, 400a, 400b, 400c, and 400d operate as a pseudo-NMOS logic-based comparator.

The gate of the PMOS(M0) 310 is always ON with logic “0”, and the drain node X of the PMOS(M0) 310 has five comparison units, that is, the first comparison unit to the second comparison unit. 5 of the comparison units 400 to 400d are connected to drain nodes of the first NMOS (M1) and the second NMOS (M2).

The first comparison unit 400 includes four NMOS (ie, first NMOS (M1), second NMOS (M2), third NMOS (M3), fourth NMOS (M4)) and two CMOS inverters (ie, It consists of a second CMOS inverter INV1 and a third CMOS inverter INV2), and has a variable divisor N[0] and a counter code C[0] as two input terminals.

According to the values of the two variable divisors N[0] and the counter code C[0], activation or blocking of the first current path and the second current path capable of conducting the X node to logic “0” is determined.

For simple explanation, a case of using the 1-bit count detector using only the first comparison unit 400 will be described as an example.

If the variable divisor N[0] and the counter code C[0] have different values,

One of the first current path and the second current path is activated, so that the node X does not maintain the initial value of logic “1” and is converted to a logic “0” value. In this case, the output clock signal CLK_OUT of the first CMOS inverter (INV0) 320 is switched to a logic “1” value, exhibiting fast rising edge characteristics, and is maintained.

When the variable divisor N[0] and the counter code C[0] have the same value,

Both the first current path and the second current path are deactivated, so that node X is charged to a logic “1” value through the current path of the PMOS(M0) 310, and thus the first CMOS inverter (INV0) 320 The output clock (CLK_OUT) signal of can be quickly converted to a logic “0” value. In a similar way, the configuration of the N-bit count detector can be configured by connecting N comparison units to node X.

In the pseudo-NMOS-based count detector presented in the present invention, when a programmable divisor N value expansion is required, simply add the number of comparison units in parallel to a total of N, and accordingly, a low-power/small-area, high-speed count detector It has the advantage of being able to design

For example, when using an 8-bit pseudo-NMOS count detector, the frequency division coefficient N of the frequency divider of the present invention is 2 ⁸ = 256, and the output frequency is divided by 1/256 with a small area/low power can do it

As a result, the variably programmable high-speed digital clock frequency divider of the present invention can have characteristics suitable for the design of high-speed/low-power/small-area PLL and MDLL-based frequency synthesizers and multipliers operating from several GHz to 10 GHz or higher. .

5 is a flowchart illustrating a control method of a variably programmable high-speed digital clock frequency divider according to the present invention.

Referring to FIG. 5 , first, a variable divisor N is applied to a pseudo-NMOS based count detector ( S110 ).

Next, a process of determining whether the output of the reset signal Reset of the reset logic unit is logic '1' is performed (S120).

When the output of the reset signal Reset is logic '1', the synchronous counter receives the input clock (CLK_IN) and counts by incrementing by '1' for each pulse signal of the input clock, and counts the count code (C) value. The process of generating is performed (S140)

On the other hand, when the output of the reset signal Reset is not a logic '1', that is, when the output of the reset signal Reset is a logic 'O', an operation of resetting all counter code C values to 0 is performed. (S130).

That is, the synchronous counter performs a counting operation only when the reset signal Reset, which is the output of the reset logic unit, maintains a logic “1”, and when the reset signal Reset is a logic “0”, all counter output values are An operation to reset to 0 is performed.

Then, a process of comparing the count code (C) value and the variable divisor (N) value is performed (S150).

As a result of the determination, if the count code C value and the variable divisor N value are different, that is, when the count code C value is smaller than the variable divisor N value, the process returns to step S120.

When the count code (C) value and the variable divisor (N) value are the same, a process of converting the output clock signal CLK_OUT from an initial logic '1' state to a logic '0' is performed (S160).

Then, after the counter code C is increased by 1 at the rising edge of the next input clock (CLK_IN) cycle, a process of comparing whether the count code C value and the variable divisor N value are the same is performed (S170).

As a result of the determination, when the count code (C) value and the variable divisor (N) value are different from each other, a process of returning the output clock signal CLK_OUT to a logic “1” state is performed ( S180 ).

What has been described above is merely an exemplary embodiment of a variably programmable high-speed digital clock frequency divider and a control method thereof according to the present invention, and the present invention is not limited to the above-described embodiment, and is claimed in the following claims. As described above, without departing from the gist of the present invention, it will be said that the technical spirit of the present invention exists to the extent that various modifications can be made by anyone with ordinary knowledge in the field to which the invention pertains.

200: pseudo-NMOS based count detector
300: synchronous counter
400: reset logic unit

Claims (10)

A variably programmable high-speed digital clock frequency divider comprising:
a synchronous counter that counts by increasing a number whenever a pulse signal of the input clock (CLK_IN) is generated, and generates a count code (C) as an output signal;
By comparing the counter code (C), which is the output signal of the synchronous counter, and a programmable variable divisor (N) applied from the outside, the frequency of 1/N lower than the frequency of the input clock (CLK_IN) is set according to the control of the reset logic unit. a count detector for generating a divided output clock CLK_OUT; and
and a reset logic unit that detects a change in the output clock (CLK_OUT) of the count detector and generates a reset signal (Reset) for controlling the state of the synchronous counter. dispenser.
According to claim 1,
The synchronous counter is
A variably programmable high-speed digital clock frequency divider that is composed of a plurality of flip-flops and has multiple K-bit outputs.
3. The method of claim 2,
The output of the plurality of flip-flops is synchronized with the input clock (CLK_IN) pulse signal to output a K-bit counter code (C) that is a binary output signal. Variably programmable high-speed digital clock frequency division Cycle.

3. The method of claim 2,
The synchronous counter performs a counting operation only when a reset signal (Reset), which is an output of the reset logic unit, maintains a logic '1',
A variably programmable high-speed digital clock frequency divider that resets a counter code to '0' when the reset signal (Reset) is logic '0'.
According to claim 1,
The count detector is a variably programmable high-speed digital clock frequency divider, characterized in that the pseudo-NMOS (Pseudo-NMOS) based count detector.
6. The method of claim 5,
The pseudo-NMOS based count detector,
When the counter code (C) and the variable divisor (N) are equal to each other, the output clock (CLK_OUT) is converted from an initial logic '1' state to a logic '0',
When the counter code C increases on the rising edge of the next input clock CLK_IN cycle and the counter code C and the variable divisor N are different from each other, the output clock CLK_OUT is set to a logic '1' state. A variably programmable high-speed digital clock frequency divider that returns to
7. The method of claim 6,
The pseudo-NMOS based count detector,
PMOS devices;
a plurality of comparison units connected to the PMOS; and
and a first CMOS inverter coupled to the plurality of comparison units.
According to claim 1,
The reset logic unit,
A reset signal Reset is generated by receiving the output clock signal CLK_OUT, and the reset signal Reset generates a logic '0' synchronized with a rising edge of the output clock signal CLK_OUT, and the synchronous counter A variably programmable high-speed digital clock frequency divider that resets all output counter codes (C) to logic '0'.
A variably programmable high-speed digital clock frequency divider control method comprising:
applying a variable divisor (N) value to a pseudo-NMOS based count detector;
determining whether an output of the reset signal Reset of the reset logic unit is logic '1';
When the output of the reset signal Reset is logic '1', the synchronous counter receives the input clock CLK_IN and increases the count by '1' for each pulse signal of the input clock, and counts the count code (C) value resetting all counter code (C) values to 0 when the output of the reset signal (Reset) is logic 'O';
comparing the count code (C) value and the variable divisor (N) value to see if they are the same;
As a result of the determination, when the count code (C) value and the variable divisor (N) value are the same, generating the output clock (CLK_OUT) divided by a frequency 1/N lower than the frequency of the input clock (CLK_IN); A variably programmable high-speed digital clock frequency divider control method.
10. The method of claim 9,
The step of generating the output clock CLK_OUT divided by a frequency that is 1/N lower than the frequency of the input clock CLK_IN includes:
converting an output clock signal CLK_OUT from an initial logic '1' state to a logic '0' when the count code (C) value and the variable divisor (N) value are the same;
after the counter code C is increased by 1 at the rising edge of the next input clock (CLK_IN) cycle, comparing the count code (C) value and the variable divisor (N) value to see if they are the same;
As a result of the determination, if the count code (C) value and the variable divisor (N) value are different from each other, returning the output clock (CLK_OUT) signal to a logic '1'state; High-speed digital clock frequency divider control method.

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