KR20090036446A - Programmable divider and method of controlling the same - Google Patents

Abstract

A programmable divider and a control method thereof are provided to perform a high speed operation by reducing a fanout of a DMP(Dual Modulus Prescaler) without a swallow counter. A programmable divider(10) includes a DMP(20), a down counter(30), and a coarse detector(40). The DMP divides an input signal and outputs a clock signal. The down counter down-counts the clock signal from a predetermined reference counting value and outputs the counting signal. The down counter outputs the divider output signal according to the counting result. If the counting signal coincides with the predetermined division ratio change value, the coarse detector outputs the DMP control signal for controlling the division ratio of the DMP.

Description

Programmable Divider and method of controlling the same

The present invention relates to a programmable divider and a control method thereof, and more particularly, to divide a high frequency signal with various division ratios in a phase locked loop (PLL) frequency synthesizer that generates a high frequency. The present invention relates to a programmable divider and a method of controlling the same, which reduce power consumption and enable high speed operation by simplifying a circuit configuration of a cycle.

Typically, there is a phase locked loop frequency synthesizer in a system for processing or transmitting or receiving digital data. A phase-locked loop frequency synthesizer is a device that generates various frequency signals from a single reference frequency.The phase-locked-loop frequency synthesizer compares the phase of the oscillation frequency of the predetermined frequency and the phase of the reference frequency that the voltage-controlled oscillator outputs to convert the phase of the oscillation frequency to the reference clock. It synchronizes and fixes the oscillation frequency.

The phase-locked loop frequency synthesizer divides a voltage controlled oscillator (VCO), a phase detector (PD), a low pass filter (LPF), and a high frequency at which the output frequency is controlled at a predetermined division ratio. It consists of a divider.

Here, the divider divides the high output frequency of the voltage controlled oscillator at the same level as the reference clock to enable phase comparison, and the configuration thereof is shown in FIG. 1.

1 is a control block diagram of a conventional frequency divider and illustrates a configuration of a programmable divider-by-M. As shown in FIG. 1, the frequency divider 1 includes a dual modulus prescaler (DMP) 3 for high-speed division, a program counter for counting the total number of divisions; And a swallow counter 7 for selecting a dividing value of the DMP 3.

The DMP 3 divides the input signal Fin from the voltage controlled oscillator (not shown) at a division ratio of 1 / N and 1 / (N + 1) in accordance with the value of the control signal MC to program counter 5 ) And the swallow counter 7.

The program counter 5 counts the pulses output from the DMP 3 with the 1 / P division ratio to count the total number of divisions, and divides the signals of the DMP 3 to divide the program counter 5 and the swallow counter 7. Apply a reset signal.

The swallow counter 7 generates a DMP control signal signal MC to control the division ratio of the DMP 3. When the swallow counter 7 is in operation, the division ratio of the DMP 3 is set to 1 / (N + 1) .If the swallow counter 7 counts S pulses, the division ratio of the DMP 3 is 1 /. Is set to N. The swallow counter 7 keeps the output at " 0 " while counting the S value, and outputs the MC value, which is the swallow signal, as " 1 " when the counting value reaches the S value. Here, the setting value P of the program counter 5 and the setting value S of the swallow counter are external input values and have a relationship of S <P.

With this arrangement, the DMP 3 initially operates at a division ratio of (N + 1) to divide the input frequency Fin by N + 1, and the output of the DMP 3 is a program counter 5 and a swallow counter. Simultaneously applied at (7), two counters each count the number of clocks.

Here, the set value P of the program counter 5 and the set value S of the swallow counter 7 have a relationship of "S <P". When the swallow counter 7 first reaches the S value, 1 "is output.

The division ratio of the DMP 3 is changed from 1 / (N + 1) to 1 / N by this MC value, and the clock divided by 1 / N at the DMP 3 is input to the program counter 5. The program counter 5 receives the N-divided clock, counts the number of clocks up to the P value, and outputs an RST value of "1" when the P counter reaches the P value. Thus, the counting values (P value, S value) of the program counter 5 and the swallow counter 7 are initialized to "0", and the operation so far is repeated. According to the operation sequence, the division ratio is as follows.

Accordingly, the final dividing ratio of the frequency divider 1 may be calculated through Equation 1 below.

M = (N + 1) × S + N × (P-S) = N × P + S (1)

M: final dispensing ratio

N: basic division ratio of DMP

P: External input value of Program Counter

S: External input value of Swallow Counter (S <P)

As described above, the conventional programmable divider employs two counters that count the same signal for control of the DMP. As a result, an area occupied by a circuit implemented by an integrated circuit (IC) increases, resulting in an increase in manufacturing cost and noise in a digital circuit, thereby degrading the performance of the entire system.

In addition, since the DMP simultaneously supplies clocks to two counters, fanout is increased to limit high-speed operation, and power consumption increases because two identical counters simultaneously count the same counter.

Accordingly, the problem to be solved by the present invention is to provide a programmable divider and a control method thereof that simplify the circuit configuration of the divider, enable a compact design, reduce power consumption, and enable high-speed operation.

In order to solve the above problems, the present invention includes a prescaler for dividing an input signal and outputting a clock signal; A down counter which receives the clock signal and down counts from a preset reference counting value to output a counting signal, and outputs a divider output signal according to the counting result; And a curl detector for outputting a prescaler control signal for controlling the division ratio of the prescaler when the counting signal coincides with a preset division ratio change value.

Here, the prescaler preferably divides an input signal with a division ratio of any one of 1 / N and 1 / (N + 1) to output the clock signal.

The down counter outputs a low signal as the divider output signal when the counting signal is not 0, and outputs a high signal as the divider output signal when the counting signal is 0. It is possible to.

The down counter may reset the reference counting value by processing the high signal output when the counting result is 0 as a reload signal.

When the counting signal coincides with a preset division ratio change value, the curl detector may output the prescaler control signal as a high signal to change the division ratio of the prescaler.

Here, the coarse detector may include n XOR gates for comparing the division ratio change value of n-bits and the counting signal of n-bits in units of bits; It is possible to include a NOR (negative OR) gate that outputs a logical "1" if all of the outputs from the n XOR (exclusive OR) gates match.

In addition, the curl detector may further include a D-flip flop that maintains the logical " 1 " output from the NOR gate until the n-bit counting signal becomes " 0 ". It is possible to include.

In order to solve the above problems, the present invention provides a programmable divider control method including a prescaler for dividing an input signal and outputting a clock signal, wherein the division ratio of the prescaler and Receiving a reference counting value and a division ratio change value for controlling the division ratio of the prescaler; Dividing the input signal according to the division ratio to output a clock signal; Receiving the clock signal and counting down the reference counting value to output a counting signal; Outputting a divider output signal according to the counting result; Determining whether the counting signal coincides with the division ratio change value; Changing the division ratio of the prescaler when the counting signal coincides with the division ratio change value; And resetting the reference counting value when the counting signal down counted from the reference counting value becomes 0, resetting the reference counting value.

Here, the prescaler may output the clock signal by dividing the input signal with a division ratio of any one of 1 / N and 1 / (N + 1).

The outputting of the divider output signal according to the counting result may include outputting a low signal as the divider output signal when the counting result is not 0, and high when the counting result is 0. Outputting the signal as the divider output signal.

The resetting of the reference counting value may include resetting the reference counting value by processing the divider output signal having the high value as a reload signal when the counting signal is zero. It is possible.

According to the programmable divider of the present invention and its control method, the circuit configuration of the divider can be simplified, which enables a compact design, reduces the production cost, and enables high-speed operation with low power.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, embodiments of the present invention illustrated below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the invention are provided to more fully illustrate the invention to those skilled in the art.

2 is a control block diagram of a programmable divider in accordance with the present invention. As shown in FIG. 2, the programmable divider 10 of the present invention has a dual modulus prescaler that divides an input signal input from the outside with two or more division ratios and outputs a clock signal P _out . Dual Modulus Prescaler (hereinafter referred to as DMP) 20 and a down counting output count signal R _out by down counting the output clock signal P _out of the DMP 20 from a reference counting value P input from an external source. A counter 30 and a coarse detector 40 for comparing the counting signal R _out with an externally divided frequency division change value S are included.

The DMP 20 divides the input signal Fin from the voltage controlled oscillator (not shown) at a division ratio of 1 / N and 1 / (N + 1) according to the value of the control signal MC to divide the divided clock signal ( P _out ) is input to the down counter 30. The DMP 20 operates at a 1 / N division ratio when the MC signal has a low value during initial driving, and switches the division ratio to 1 / (N + 1) when the MC signal is input at a high value. do.

The down counter 30 receives the clock signal P _out from the DMP 20, down-counts the clock signal P _out from the reference counting value P input from the outside, and counts the signal N _{out of the} bit R _out . Outputs In addition, the down counter 30 outputs a low signal as the output signal Fout of the frequency divider 10 when the P value being counted is not " 0 &quot;, and when the P value is &quot; 0 &quot; high) outputs a signal. The output signal F _out of the high state output by the down counter 30 is processed as a reload (RLD) signal and input to the down counter 30 again, whereby the P of the down counter 30 is received. The value is reset.

The curls detector 40 compares the counting signal R _out of the down counter 30 with the division ratio change value S input from the outside, and controls the DMP 20 when the counting signal R _out reaches the S value. The control signal MC is output as a high signal. Here, the set value P of the down counter 30 and the set value S of the curl detector 40 are external input values and have a relationship of S <P.

With such a configuration, the programmable frequency divider 10 according to the present invention includes N, which is the basic division ratio of the DMP 20, the reference counting value P of the down counter 30, and the division ratio change value S of the curl detector 40. The input signal is divided by setting. Here, the set value P of the down counter 30 becomes the frequency of division, and the S value of the curl detector 40 is a time point where the division ratio of the DMP 20 changes. Accordingly, the S value and the P value are set to satisfy "S <P".

When the N, P, and S values are set, the DMP 20 divides the input signal F _in N and outputs the clock signal P _out . Accordingly, the down counter 30 counts down the output of the DMP 20 by one from the P value and outputs a counting signal R _out . The curls detector 40 detects whether the counting signal R _out of the down counter 30 reaches the S value. When the counting signal R _out reaches the division ratio change value S, the curling detector 40 determines the division ratio of the DMP 20. The control signal MC for changing is output as a high signal. The division ratio of the DMP 20 is changed to N + 1 by the MC signal, and the down counter 30 continues to count the clock signal P _out which is divided and output according to the changed division ratio. Here, when the P value becomes "0", the down counter 30 outputs the output signal F _out as a high signal, which is processed as a reload (RLD) signal by the down counter 30 to P. Causes the value to be reset. By repeating this operation, the final division ratio M can be obtained as in Equation 2 below.

M = N × (P-S) + (N + 1) × S = N × P + S (2)

M: final dispensing ratio

N: basic division ratio of DMP

P: External input value of down counter

S: External input value of the curl detector (S <P)

FIG. 3 is an output waveform diagram of a programmable divider according to the present invention. When N = 4, P = 8, and S = 3 are input, the down counter 30 according to the clock signal P _out of the DMP 20 is shown. Is a waveform diagram showing the output state of the reload (RLD) signal of the &lt; RTI ID = 0.0 &gt;)&lt; / RTI &gt;

The first signal waveform represents the clock signal P _out of the DMP 20. When the division ratio N is set to 4, the DMP 20 divides the input signal F _in output from the oscillator (not shown) into 4 and applies the clock signal P _out divided by 4 to the down counter 30. Thereafter, the DMP 20 sets the frequency division ratio to 5 according to the DMP control signal MC to apply the five-divided clock signal P _out to the down counter 30. The number described in the clock signal P _out describes the counting value R _out of the down counter 30 for the clock.

The second signal waveform represents an output F _out signal of the frequency divider 10 output by the down counter 30. When the output F _out signal becomes high, the down counter 30 It is processed as a reload (RLD) signal that resets the P value of. When the reference counting value P is set to 8, the down counter 30 counts down the clock signal P _out from 8 and applies the counting signal R _out to the curl detector 40. In addition, the down counter 30 outputs a low signal to the output F _out of the frequency divider 10 when the counting value is not 0, and a high signal when the P value becomes “0”. Outputs Accordingly, a high signal is generated in the output F _out signal of the divider 10 with a cycle of eight output clocks P _out of the DMP 20. Meanwhile, the high output signal F _out output by the down counter 30 is processed as a reload (RLD) signal and input again to the down counter 30, whereby the down counter 30 is received. P value of is reset to " 8 " previously input.

The third signal waveform represents the DMP control signal MC output from the curl detector 40. When the division ratio change value S is set to 3, the curl detector 40 checks whether the n-bit counting signal R _out of the down counter 30 is 3 or not. In the first operation, the curls detector 40 outputs the DMP control signal MC low and sets the DMP control signal MC high when the counting signal R _out outputted from the down counter 30 is three. The output is made high and the division ratio of the DMP 20 is changed from four divisions to five divisions.

4 is a block diagram of a programmable frequency divider according to the present invention modeled using a simulation program. Various simulation programs may be used to analyze various systems and verify performance. In this description, a case in which the divider 10 is modeled using the MATLAB / Simulink program of Mathworks will be illustrated.

D-Flip Flop block 42 for performing DMP block 32, down counter block 22, and curl detector 40 using a tool box of a simulation program. It is possible to configure a programmable divider 10 comprising a.

FIG. 5 is a waveform diagram of the simulation result of the frequency divider of FIG. 4, and illustrates the results of simulation performed by setting N = 4, P = 8, and S = 3.

The DMP block 32 divides the input signal F _in into four and outputs the clock signal P _out to the down counter block 22.

The down counter block 22 calculates the first counting value R _out . Remember P _out . The down counter block 22 sets the counting signal R _out from 8 (= P values) to 7, 6, 5, every time the positive edge of the clock signal P _out of the DMP block 32 is received. Count down one by one like .., 2, 1. When the counting value R _out decreases by 1 and becomes 3 (= S value), the D-flip-flop block 42 which performs the curl detector 40 function outputs the DMP control signal MC high. do. Accordingly, the division ratio of the DMP block 32 is changed from 4 to 5, so that the clock signal P _out is generated every five clocks of the input signal F _in .

Thereafter, when the counting value R _out continues to decrease and becomes '0', the down counter block 22 generates the reload RLD signal '1'. The down counter block 22 receiving the reload RLD signal repeatedly sets the P value to 8 to repeat the above-described operation.

Thus, the division ratio as in Equation 3 can be obtained.

M = 4 × 8 + 3 = 35 (3)

6 is a block diagram of a down counter of a programmable divider in accordance with the present invention modeled using a simulation program.

As shown in Fig. 6, in the present embodiment, the down counter block 22 is composed of four 1 bit unit cells 34, and one rising edge D per one bit unit cell 34 is provided. -It consists of the flip-flop 35, the 1st mux (MUX) 36, and the 2nd mux (MUX) 37. As shown in FIG.

The down counter block 22 having this configuration performs two operations, a reload mode and a down counter mode, and each mode is controlled by a reload (RLD) signal.

The reload mode enters when the reload (RLD) signal is high. In the re-input mode, an external 4-bit P value (P0 to P3) is input to each D-flip flop 35 and the P value to the 4-bit counting signal R _out (R0 to R3). This is remembered. At the same time, each D-flip-flop 35 is disconnected by the MUXs 36 and 37 so that the down count operation is stopped.

The down counter mode enters when the reload (RLD) signal is low. According to the clock signal P _out applied from the D-flip flop 35, the counting signal R _out value is decreased by “1” from the stored P value and counted down. Accordingly, when the P value becomes "0" as a result of the down counting, a reload (RLD) signal is generated and the P value is stored in each D-flip flop 35 again. .

7 is a waveform diagram of the simulation result of the down counter of FIG. 6.

For the simulation, when P = 8, a reload (RLD) signal high occurs so that four D-flip-flops 35 store 1000 ₍₂₎ = 8 ₍₂₎ values. Thereafter, as the clock signal P _out output from the DMP block 32 is input, the counting signal R _out is counted down to 8, 7, 6, ..., 2, 1.

As soon as the counting signal R _out becomes zero, a reload (RLD) signal high is generated, and 1000 ₍₂₎ = 8 ₍₂₎ is stored in four D-flip flops again. By repeating this operation, the desired division ratio can be obtained.

8 is a control block diagram of a curl detector 40 of a programmable divider 10 according to the present invention modeled using a simulation program. The curls detector 40 compares the 4-bit counting output R _out (In0 to In3) of the down counter block 22 and the preset 4-bit S value (S0 to S3) by 1 bit, respectively, and if they all match. Output the MC signal high. Accordingly, as shown in FIG. 8, the curl detector 40 includes an XOR logic block 44, 45, 46, and 47 for comparing the counting signals R _out and S values S0 to S3 by 1 bit. Only when the outputs of the XOR logic blocks 44, 45, 46, 47 are matched, the NOR logic block 42 which outputs "1" and the MC signal are maintained until the P value becomes "0". D-flip-flop 48 is included.

By such a configuration, the curls detector 40 stores the preset S value in each XOR logic block 44, 45, 46, 47 by 1 bit, and counts the output R _out (In0 ...) of the down counter block 22. In3) and the preset S values S0 to S3 are compared by 1 bit, and if they match, the MC signal is output high.

9 is a simulation result waveform diagram of the curl detector of FIG. 8.

For the simulation, when P = 8 and S = 3, the counting signal R _out output from the down counter block 22 decreases by 1 to 8, 7, 6, ..., 2, 1. Here, when the counting signal R _out is 3 because the set value S = 3 of the curl detector 40, it is confirmed that MC is output high because R _out and S are the same.

As described above, the programmable divider according to the present invention enables the high speed operation by reducing the fanout of the DMP by eliminating the swallow counter in the conventional divider. In addition, by using only one down counter, unnecessary counting operation is reduced compared to a conventional divider, thereby enabling a low power circuit and reducing chip area costs by reducing the chip area. In addition, since the generating portion of the MC (control signal) is simpler than the conventional divider, the stability of the operation can be improved.

Although the present invention has been described in detail with reference to exemplary embodiments above, those skilled in the art to which the present invention pertains can make various modifications to the above-described embodiments without departing from the scope of the present invention. I will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

1 is a control block diagram of a conventional programmable divider.

2 is a control block diagram of a programmable divider in accordance with the present invention.

3 is an output waveform diagram of a programmable divider in accordance with the present invention.

4 is a block diagram of a programmable frequency divider according to the present invention modeled using a simulation program.

5 is a waveform diagram of the simulation result of the frequency divider of FIG. 4.

6 is a block diagram of a down counter of a programmable divider in accordance with the present invention modeled using a simulation program.

7 is a waveform diagram of the simulation result of the down counter of FIG. 6.

8 is a control block diagram of a curl detector of a programmable frequency divider according to the present invention modeled using a simulation program.

9 is a simulation result waveform diagram of the curl detector of FIG. 8.

*** Explanation of symbols for the main parts of the drawing ***

10: divider

20: Dual Modulus Prescaler (DMP)

30: Down Counter

40: Coarse Detector

Claims (13)

A prescaler for dividing an input signal and outputting a clock signal; A down counter which receives the clock signal and down counts from a preset reference counting value to output a counting signal, and outputs a divider output signal according to the counting result; And a curl detector for outputting a prescaler control signal for controlling the division ratio of the prescaler when the counting signal coincides with a preset division ratio change value. The method of claim 1, The prescaler is, And a dual modulus prescaler for dividing an input signal by a division ratio of any one of 1 / N and 1 / (N + 1) and outputting the clock signal. The method of claim 1, The down counter, And when the counting signal is not 0, outputs a low signal as the divider output signal, and when the counting signal is 0, outputs a high signal as the divider output signal. Divider. The method of claim 3, wherein The down counter, And resetting the reference counting value by processing the high signal output as a reload signal when the counting result is zero. The method of claim 1, The curls detector, And when the counting signal coincides with a preset division ratio change value, outputs the prescaler control signal as a high signal to change the division ratio of the prescaler. The method of claim 1, The curls detector, n XOR (exclusive-OR) gates for comparing the division ratio change value of n-bits and the counting signal of n-bits in units of bits; And an NOR (negative OR) gate that outputs a logical "1" when all of the outputs from the n XOR (exclusive OR) gates match. The method of claim 6, The curls detector, And a D-flip-flop for keeping the logical " 1 " output from the NOR gate until the n-bit counting signal becomes " 0 ". Possible divider. In the programmable divider control method comprising a prescaler for dividing an input signal and outputting a clock signal, Receiving a division ratio of the prescaler, a reference counting value for counting the clock signal, and a division ratio change value for controlling the division ratio of the prescaler; Dividing the input signal according to the division ratio to output a clock signal; Receiving the clock signal and counting down the reference counting value to output a counting signal; Outputting a divider output signal according to the counting result; Determining whether the counting signal coincides with the division ratio change value; Changing the division ratio of the prescaler when the counting signal coincides with the division ratio change value; And resetting the reference counting value when the counting signal down counted from the reference counting value becomes zero. The method of claim 8, The prescaler is, And dividing the input signal by a division ratio of any one of 1 / N and 1 / (N + 1) to output the clock signal. The method of claim 8, The outputting of the divider output signal according to the counting result may include: Outputting a low signal as the divider output signal when the counting result is not 0, and outputting a high signal as the divider output signal when the counting result is 0. Programmable frequency divider control method. The method of claim 10, Resetting the reference counting value, And resetting the reference counting value by processing the divider output signal having the high value as a reload signal when the counting signal is zero. A dual modulus prescaler for dividing an input signal with a division ratio of any one of 1 / N and 1 / (N + 1) and outputting the clock signal; The clock signal is input and down counted from a preset reference counting value to output a counting signal. When the counting signal is not 0, a low signal is output as the divider output signal, and the counting signal is 0. A down counter for outputting a high signal as the divider output signal and resetting the reference counting value by processing the high signal output as a reload signal when the counting result is 0; And a coarse detector for outputting the prescaler control signal as a high signal and changing the division ratio of the prescaler when the counting signal coincides with a preset division ratio change value. . The method of claim 12, The dual modulus prescaler, And divide the input signal at a division ratio of 1 / N during initial driving, and change the division ratio to 1 / (N + 1) when the prescaler control signal is input from the curl detector.

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