JP2000111587A - Jitter detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a jitter detection circuit lowering the frequency of control clock externally inputting in jitter detection of input data signal and facilitating the change of jitter amplitude value for a detection object. SOLUTION: Constituted of are a change point detection circuit 2 producing the change point signal of input data, an m-phase clock producing circuit 3 producing m-phase clock with phase shift of 360 degree/m in turn against an input clock based on that of the same input data and frequency, a phase comparison circuit 4 separating a period of an input clock into (m) divisions with the m-phase clock and outputting a value indicating (m) divisions phase regions where the change point phase of the input data is existing as the change point phase information of the input data, a jitter amplitude value calculation circuit 5 calculating a jitter amplitude value based on the change point phase information of the input data from the past to the present, and a comparison circuit 6 judging whether or not the jitter amplitude value of the input data obtained by this jitter amplitude calculation circuit 5 undergoes a specific value and outputting it as a jitter detection result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jitter detection circuit, and more particularly, to a digital LSI (large-scale integrated circuit) or the like which malfunctions when a data signal containing jitter is input, the jitter amplitude value of input data is a predetermined value. The present invention relates to a jitter detection circuit that determines whether the value is equal to or less than a value.

[0002]

2. Description of the Related Art Conventionally, this kind of jitter detection circuit is disclosed in, for example, Japanese Patent Laid-Open Publication No. 1-123518.

As shown in FIG. 13, a jitter detection circuit disclosed in Japanese Patent Laid-Open No. 1-123518 has a D flip-flop in which a data input terminal 720 containing jitter is used as a signal input and a control clock input terminal 721 is used as a clock input. A flip-flop 701, a D-flip-flop 702 having the output of the D-flip-flop 701 as a signal input and a clock input to a control clock input terminal 721, and a D-flip
An EXOR circuit 703 which receives the outputs of the flop 701 and the D flip-flop 702 as inputs, a divide-by-2 circuit 704 which has its own inverted output as a signal input, and a control clock input terminal 721 as a clock input, and an EXOR circuit 703 AND circuit 705 that receives the output of the EXOR circuit 703 and the output of the inverting side of the divide-by-2 circuit 704 as inputs.
A circuit 706, a D flip-flop 707 in which an output of the AND circuit 705 is used as a signal input and a control clock input terminal 721 is used as a clock input, and a D flip-flop 707 in which the output of the AND circuit 706 is used as a signal input and the control clock input terminal 721 is used as a clock input. A flip-flop circuit 708 having an output of the D flip-flop circuit 707 as a set input and an RS flip-flop circuit 709 having an output of the D flip-flop circuit 708 as a reset input;
The circuit configuration is such that the output of the flip-flop circuit 709 is used as an output terminal.

The operation of the jitter detection circuit will be described with reference to a time chart shown in FIG.

The data input signal from the data input terminal 720 changes at the rise of the non-inverting side output of the divide-by-2 circuit 704 during the times 0 to 11. Therefore, the output of the EXOR circuit 703, which is the change point detection signal during this period, outputs a pulse during the period of “L” of the non-inverting side output of the divide-by-2 circuit 704.

[0006] This pulse is passed through an AND circuit 706 to D
The flip-flop circuit 708 resets the RS flip-flop 709.

This state corresponds to times 3, 7, and 11 in FIG.

When jitter occurs at time 12 in FIG.
The output of the XOR circuit 703 outputs a pulse during the period when the non-inverting side output of the divide-by-2 circuit 704 is “H”. This pulse is A
D flip-flop circuit 70 through ND circuit 705
7 to set the RS flip-flop circuit 709.

This state corresponds to times 14 and 18 in FIG.

The output of the RS flip-flop circuit 709 changes from "L" to "H" at time 14 to notify the outside that data input jitter has occurred.

[0011]

However, in this technique, the phase of the change point of the input data signal is compared with the "H" and "L" periods of the signal obtained by dividing the control clock input from the outside by two. In order to detect the jitter, the frequency of the control clock is required to be higher than the frequency of the input data signal by 2n times (n is an integer of 1 or more).

Further, there is a problem that the amplitude value of the detectable jitter depends on the frequency of the control clock, and the jitter amplitude value to be detected cannot be easily changed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional circumstances, and has been made to solve the above-mentioned disadvantages inherent in the prior art. It is another object of the present invention to provide a novel jitter detection circuit that can lower the frequency of a control clock input from the outside and easily change the jitter amplitude value to be detected.

[0014]

In order to achieve the above object, a jitter detection circuit according to the present invention comprises a jitter detection circuit for determining whether a jitter amplitude value of input data including jitter is equal to or smaller than a predetermined value. In the circuit, a change point detection circuit for generating a change point signal of input data, and a phase of 360 degrees / m (m is an integer of 2 or more) sequentially with respect to the input clock based on the input clock having the same frequency as the input data. An m-phase clock generation circuit for generating an m-phase clock shifted by one unit, and a value indicating an m-divided phase region where a change point phase of input data exists by dividing one cycle of the input clock by the m-phase clock and changing the input data A phase comparison circuit that outputs as point phase information, and a jitter that calculates a jitter amplitude value of input data based on input data change point phase information from the past to the present input from the phase comparison circuit. Configured with a width value calculation circuit, and a comparator circuit for jitter amplitude value of the input data obtained by the jitter amplitude value calculating circuit outputs as determined by the jitter detection results to or smaller than a predetermined value.

According to the present invention, the m-phase clock generating circuit includes m variable delay circuits provided in series for generating a delay amount for one cycle of the input clock, and two n-frequency dividing circuits (n Is an integer of 2 or more), a D-FF, and an up / down counter, and a clock signal to which a delay of one clock cycle is added by a variable delay circuit provided in series with m input clocks. It is composed of a phase synchronization circuit that adjusts m variable delay circuits provided in series so that the phases are synchronized.

The phase comparison circuit latches each of the m-phase clocks using the change point signal of the input data generated by the change point detection circuit, and inputs the values from the values of the m latch output results of the latch circuit. And an encoder that converts the data into values indicating the m-divided phase region where the data change point phase exists.

According to the present invention, the jitter amplitude value calculating circuit further comprises an m-bit storage circuit and an adder for determining the number of logical values "1" (or logical values "0") held by the storage circuit. For writing a logical value "1" (or a logical value "0") to each bit of the storage circuit corresponding to each value of the input data change point phase information inputted from the phase comparison circuit on a one-to-one basis. And a control circuit.

[0018]

Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Configuration of Embodiment] Referring to FIG.
The input data signal s101 is input to the change point detection circuit 2 via the data input terminal 1. Control clock signal s1
08 has the same frequency as the input data signal s101, and is input to the m-phase clock generation circuit (m is an integer of 2 or more) 3 via the control clock input terminal 8.

The change point detection circuit 2 receives the input data signal s1
Input data change point signal s102 indicating a change point phase of 01
Is generated and output.

The m-phase clock generation circuit 3 has the same frequency as the control clock signal s108 and a phase of 360
M-phase clock signals s103-1 to s103-1 sequentially shifted by degrees / m
Generate and output s103-m.

The phase comparison circuit 4 includes an input data change point signal s102 output from the change point detection circuit 2 and an m-phase clock signal s10 output from the m-phase clock generation circuit 3.
A phase comparison with 3-1 to s103-m is performed, and a value indicating which phase region of the phase region obtained by dividing one cycle of the control clock signal s108 by m is the rising edge phase of the input data change point signal s102 (this The value is represented by an m value), and output as input data change point phase information s104.

The jitter amplitude value calculating circuit 5 includes a phase comparing circuit 4
From the past to present values of the input data change point phase information s104 output from the
105 is generated and output.

The comparison circuit 6 includes input data amplitude value information s105 output from the jitter amplitude value calculation circuit 5 and detection jitter amplitude value information s109 input via the setting terminal 9 and indicating a jitter amplitude value to be detected. And generates and outputs a comparison result signal s106. Comparison result signal s1
06 is output via the jitter detection result output terminal 7 as a jitter detection result.

FIG. 2 is a circuit diagram showing a configuration example of the change point detection circuit 2 shown in FIG.

In FIG. 2, the input data signal s101
Is input to the EXOR 202 and the delay element 201. E
The exclusive OR of the input data signal s101 and the delay-added input data signal is obtained by the XOR 202, and only when the logical value of the input data signal s101 changes, "H" for the delay time of the delay element 201 is obtained. Output pulse.

FIG. 3 is a detailed block diagram showing a configuration example of the m-phase clock generation circuit 3 shown in FIG.

Referring to FIG. 3, m-phase clock generation circuit 3 includes first to m-th variable delay circuits 301 provided in series and having a delay amount of about one cycle of control clock signal s108. -1 to 301-m, the first and second n
Frequency dividing circuits (n is an integer of 2 or more) 302 and 303;
A D-FF (flip-flop) 304 and an up / down counter 305 are provided.
8 and a clock signal to which a delay of one clock cycle is added by the first to m-th variable delay circuits 301-1 to 301-m provided in series (the m-th variable delay circuit 301-m). The first to m-th variable delay circuits 301-1 to 301-m are synchronized so that both phases thereof are synchronized with the output s301-m).
It is composed of a phase synchronization circuit that adjusts 301-m.

In this configuration, the delay amounts of the first to m-th variable delay circuits 301-1 to 301-m provided in series with m are locked with the delay amount of about one cycle of the control clock signal s108. Control clock signal s1
08 and the output s103- of the m-th variable delay circuit 301-m
Instead of directly comparing the phase with m, the signals s302 and s303 that have been frequency-divided by the first and second n-frequency dividing circuits 302 and 303 are compared with each other.

As a result of the phase comparison by the D-FF 304, if the phase of the signal s303 is ahead of the phase of the signal s302, the up / down counter 305 counts up, and the first to m-th variable delay circuits 301 -1 to
The delay amount of 301-m is uniformly increased.

On the other hand, when the phase of the signal s303 is behind that of the signal s302, the up / down counter 3
05 counts down, and the delay amounts of the first to m-th variable delay circuits 301-1 to 301-m are reduced uniformly.

By repeating this operation, phase synchronization is achieved, and the first to m-th variable delay circuits 301-1 to 301-1
The control clock signal s1 is output from each output of the control clock signal 301-m.
08, and m-phase clocks s103-1 to s3103-m having the same frequency and a phase sequentially shifted by 360 degrees / m can be obtained.

FIG. 4 shows the first to m-th variable delay circuits 30 used in the m-phase clock generation circuit 3 shown in FIG.
FIG. 2 is a circuit block configuration diagram illustrating a configuration example of 1-1 to 301-m.

Referring to FIG. 4, first to m-th variable delay circuits 301-1 to 301-m include first to i-th delay elements 307-1 to 307-i (i is one or more). ) And a selector 308, and the control signal CN
By controlling the number of delay elements through which the input signal IN passes according to the value of T, the amount of delay added to the input signal IN is controlled.

FIG. 5 is a circuit block diagram showing a configuration example of the phase comparison circuit 4 shown in FIG.

In FIG. 5, D-FFs 401-1 to 40-1
The 1-m data inputs have m-phase clock signals s, respectively.
103-1 to s103-m are input, and an input data change point signal s102 is input to a clock input.

The latch output data s401-1 to s401-m of the D-FFs 401-1 to 401-m are encoded by the encoder 4
02, the rising edge phase of the input data change point signal s102 is converted into input data change point phase information s104 which is a value indicating which phase area of the phase area obtained by dividing one cycle of the control clock signal s108 by m. .

FIG. 6 is a block diagram showing a configuration example of the jitter amplitude value calculation circuit 5 shown in FIG.

In FIG. 6, a jitter amplitude value calculating circuit 5
Are the decoder 501 and the OR circuits 502-1 to 502-
m, D-FFs 503-1 to 503-m, and an adder 50
And 4.

The reset signal s110 is input to the reset inputs of the D-FFs 503-1 to 503-m via the reset input terminal 10, and the D-FFs 503-1 to 503-m are initialized (set to the logical value "0"). )I do. Further, DF
To the data inputs of F503-1 to F503-m, a signal obtained by ORing the output signal of the decoder 501 and the non-inverting output (Q output) of the D-FFs 503-1 to 503-m is input.

According to this configuration, when the logical value "1" is latched in the D-FF corresponding to 1: 1 according to the value of the input data change point phase information s104, and the logical value "1" is latched once, Is held until the initialization by the reset signal s110 is performed.

The adder 504 includes a D-FF 503-
This is a 1-bit m-input adder for adding all the logical values "1" held by 1 to 503-m. Adder 5
The addition result of 04 indicates how many phase areas the change point phase of the input data has existed from the past to the present with respect to m phase areas obtained by dividing one cycle of the control clock signal s108 by m. , And output as jitter amplitude value information s105.

[Operation of Embodiment] Next, the operation of this embodiment will be described with reference to timing charts.

FIG. 7 shows a case where the number m of m-phase clocks generated by the m-phase clock generation circuit 3 in the embodiment shown in FIG. 1 is set to 8, and the jitter amplitude value information to be detected is set to 2 ( Data s101 having a jitter amplitude value of 3 (corresponding to three regions of the m-divided phase region) and a change point phase at times 10, 21, 32, 41, and 50 of the m-divided phase region are obtained. 6 is a timing chart showing an operation when an input is made.

In this case, the change point detection circuit 2 generates and outputs an input data change point signal s102 which rises at times 10, 21, 32, 41 and 50 and has an edge.

The m-phase clock generation circuit 3 has the same frequency as the control clock signal s108 and the phase is 360 degrees / m sequentially.
8-phase clock signals s103-1 to s103- shifted by
8 is generated and output.

The phase comparison circuit 4 receives the input data transition point signal s102 and the 8-phase clock signals s103-1 to s103-
8, the input data change point phase information s104 in which the phase of the rising edge of the input data change point signal s102 is indicated by the m-divided phase region number is generated and output (the m-divided phase region corresponds to the 8-phase clock signal). In this case, there are eight, and in the example of FIG.
７7).

Therefore, the input data change point phase information s10
4 is “0” at times 10 and 50, “1” at times 21 and 41, and “2” at time 32.

The jitter amplitude value calculation circuit 5 obtains the number of the m-divided phase regions indicated by the input data change point phase information s104 from the past to the present, and outputs it as input jitter amplitude value information s105. Input jitter amplitude value information s10
In 5, the number of areas 1 until time 20 at time 21, the number of areas 2 until time 31 at time 32, and the number of areas 3 until time 40 at time 41 are output.

The comparison circuit 6 always compares the input jitter amplitude information s105 with the value of the jitter amplitude information to be detected and outputs the result as a jitter detection result.

Therefore, if the jitter amplitude value information to be detected is 2, "H" indicating that jitter has been detected at time 32 is output.

FIG. 8 shows a state in which the first and second n-divider circuits 302 and 303 in the m-phase clock generation circuit 3 are constituted by four-divider circuits (n = 4), and the phase synchronization circuit is locked. 3 is a timing chart showing the phase relationship between the signals of FIG.

FIG. 9 is a timing chart showing an operation example of the phase comparison circuit 4.

The 8-phase clock signals s103-1 to s103-8 generated by the m-phase clock generation circuit 3 are respectively supplied to the D-FFs 401-1 to 401-8 by using the rising edge of the input data change point signal s102. Latched.

The latch result signals s401-1 to s40
1-8 are 8-phase clock signals s103-1 to s103-
8 indicates the phase region in which the rising edge phase of the input data change point signal s102 is in a phase region obtained by dividing one cycle of the clock by 8 and is converted into a value of 0 to 7 by the encoder 402. You.

FIG. 10 shows the conversion logic of the encoder 402.

FIG. 11 is a timing chart showing an operation example of the jitter amplitude value calculating circuit 5.

FIG. 12 shows the decoding logic of the decoder circuit 501 used in the jitter amplitude value calculation circuit 5.

The input data amplitude value information s104 generated by the phase comparison circuit 4 is decoded by the decoder 501, and only one of the eight bits of the decoded output signals 501 (0) to (7) has a logical value "1". Is converted to The decoded output signals 501 (0) to 501 (7) are OR5
DF corresponding to each of the DFs via 02-1 to 502-8
For example, the logical value “1” of the decoder output signal 501 (0) in FIG. 11 is latched and held by the D-FF 503-1 in FIG.

The 1-bit 8-input adder 504 outputs the DF
The logical value “1” held by F503-1 to F503-8 is added.

[0062]

As described above, according to the jitter detection circuit of the present invention, the change point signal of the input data generated by the change point detection circuit and the m-phase clock from the input clock having the same frequency as the input data. Since the phase comparison is performed with the m-phase clock generated by the generation circuit, external high-speed clock input is not required.

The phase comparison circuit quantifies the change point phase information of the input data into a numerical value (converts it into an m value), obtains the amount of change in the numerical value by the jitter amplitude value calculation circuit, and expresses the value as the m value in the same manner as the phase comparison circuit. Because of the method, the jitter amplitude value to be detected can be easily changed.

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration example of a change point detection circuit 2.

FIG. 3 is a block diagram showing a configuration example of an m-phase clock generation circuit 3;

FIG. 4 is a circuit block diagram showing a configuration example of variable delay circuits 301-1 to 301-m.

FIG. 5 is a block diagram showing a configuration example of a phase comparison circuit 4;

FIG. 6 is a circuit block diagram showing a configuration example of a jitter amplitude value calculation circuit 5;

FIG. 7 is a timing chart showing an operation example of the embodiment shown in FIG. 1;

FIG. 8 is a timing chart showing an operation example of the m-phase clock generation circuit 3.

9 is a timing chart illustrating an operation example of the phase comparison circuit 4. FIG.

FIG. 10 is a diagram showing the logic of encoding by an encoder 504.

FIG. 11 is a timing chart illustrating an operation example of the jitter amplitude value calculation circuit 5;

FIG. 12 is a diagram illustrating decoding logic of a decoder 501.

FIG. 13 is a block diagram showing a conventional circuit configuration example.

FIG. 14 is a timing chart showing an operation example of a conventional circuit configuration example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Data input terminal 2 ... Change point detection circuit 3 ... m phase clock generation circuit 4 ... Phase comparison circuit 5 ... Jitter amplitude value calculation circuit 6 ... Comparison circuit 7 ... Jitter detection result output terminal 8 ... Control clock input terminal 9 ... Setting Terminal 10: Reset input terminal 301-1 to 301-m Variable delay circuit 302, 303 N-divider circuit 304 D-FF 305 Up / down counter 307-1 to 307-i Delay element 308 Selector 402 ... Encoder 501 ... Decoder 504 ... Adder

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Minoru Chino 3--18-21 Shibaura, Minato-ku, Tokyo Inside NEC Engineering Ring Co., Ltd. (72) Tomi Katayama 3--18 Shibaura, Minato-ku, Tokyo No. 21 NEC Engineering Co., Ltd. F term (reference) 2G035 AA08 AB10 AB13 AC05 AC15 AC24 AD23 AD25 AD27 AD28 AD29 AD52 AD61 AD62 5J039 JJ02 JJ05 JJ13 JJ20 KK09 KK10 KK11 KK13 KK20 KK25 KK27 KK31 MM05 MM10

Claims (5)

[Claims] 1. A jitter detection circuit for determining whether or not a jitter amplitude value of input data including jitter is equal to or less than a predetermined value, wherein the input data is input and a change point signal of the input data is output. Output circuit, and the phase of the input clock is sequentially 360 degrees / m (m is an integer of 2 or more) based on the input clock having the same frequency as the input data.
An m-phase clock generating circuit for generating an m-phase clock shifted by 1; an input data change point signal and the m-phase clock being input, and one cycle of the input clock being divided into m by the m-phase clock to change the input data; A phase comparison circuit that outputs a value indicating an m-divided phase region in which a point phase exists as change point phase information of the input data, and the input data change point from the past to the present by using the change point phase information of the input data as an input A jitter amplitude value calculating circuit that calculates a jitter amplitude value of the input data based on phase information; and determining whether a jitter amplitude value of the input data input from the jitter amplitude value calculating circuit is equal to or less than a predetermined value. A jitter detection circuit, comprising: a comparison circuit for judging and outputting as a jitter detection result. A delay element for delaying the input data, a delay output of the delay element and the input data, the delay detection element being configured to receive the delay only when a logical value of the input data changes; 2. The jitter detection circuit according to claim 1, further comprising: an exclusive OR circuit that generates a pulse corresponding to a delay time of the element. 3. The m-phase clock generation circuit includes m variable delay circuits for generating a delay amount for one cycle of the input clock, and two n frequency divider circuits (where n is 2 or more). Integer), a D-FF, and an up / down counter, and both phases of the input clock and the clock signal delayed by one clock cycle by the m variable delay circuits provided in series are synchronized. 2. The jitter detection circuit according to claim 1, further comprising a phase synchronization circuit that adjusts the m variable delay circuits provided in series so as to perform the operation. 4. A latch circuit for latching each of the m-phase clocks using a transition point signal of the input data generated by the transition point detection circuit; 2. The jitter detection circuit according to claim 1, further comprising an encoder configured to convert a value of a latch output result into a value indicating an m-divided phase region in which a change point phase of the input data exists. 5. The jitter amplitude value calculating circuit, comprising: an m-bit storage circuit; an adder for calculating the number of logical values “1” (or logical value “0”) held by the storage circuit; A logic value "1" (or a logic value "0") is written to each bit of the storage circuit corresponding to each value of the input data change point phase information inputted from the phase comparison circuit. The jitter detection circuit according to claim 1, further comprising a control circuit.