JP3031206B2 - Divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider, and more particularly, to a frequency divider which outputs a phase-controlled clock signal which is a reference for circuit operation.

[0002]

2. Description of the Related Art In recent microprocessors or microcontrollers, a clock multiplying circuit built in an LSI generates a clock several to several tens of times (usually a factor of 2) an externally supplied clock. In many cases, the internal operation is performed in synchronization with this clock to improve the performance while keeping the frequency of the clock used for interfacing with the outside relatively low.

In such a case, at least two clocks are required in the LSI, a clock used for an interface with the outside and a clock used for an internal operation. In practice, a higher speed is required for a specific circuit. In many cases, a plurality of clocks are used, such as using a clock. For this reason, a method of generating a plurality of clocks by generating the fastest clock in the clock multiplying circuit and sequentially dividing the frequency of the clock is employed.

A problem that arises when a plurality of clocks having different frequencies are generated from a single clock by a frequency divider is how to adjust the phases of the plurality of clocks to a specific state. That is. In general, the phase of the fastest clock signal and the phase of the signal obtained by dividing the frequency by 2n (n is a natural number) are divided by counting the rising edge of the original clock signal or by dividing the frequency by counting the falling edge. It does not matter because it is uniquely determined by

However, when a signal obtained by dividing the highest-speed clock signal by 2 and a signal obtained by dividing by 2n are used, the phase of the two signals is such that the 2n-divided signal rises at the rising edge of the 2-divided signal. There is a case where the signal rises, and a case where the 2n frequency-divided signal rises at the fall of the frequency-divided signal 2 irrespective of whether a rising edge or a falling edge is counted. Since it is determined by the initial state of the frequency dividing circuit and the 2n frequency dividing circuit, it is usually not uniquely determined. In such a case, transmission and reception of signals between the circuit block operating with the divide-by-2 signal and the circuit block operating with the divide-by-2 signal cannot be designed well, so that phase adjustment is usually performed by some method.

A method for adjusting the phases of a plurality of frequency-divided signals to a specific state as described above is disclosed in Japanese Patent Application Laid-Open No. Sho 56-14962.
There is a “timing signal generation circuit” disclosed in Japanese Patent Application Laid-Open No. 4 (1999) -86. This circuit has a frequency higher than this basic clock and lower than the original oscillation frequency with respect to a basic clock obtained by dividing a certain oscillation frequency, and has a desired phase relationship with the basic clock. A circuit for generating a timing signal is described. Hereinafter, FIG. 4 will be described with reference to FIG. 5 in the case where this circuit is applied to the case of a divide-by-2 circuit and a divide-by-2n circuit.

The original clock signal is a 2n frequency dividing circuit 4
3, D-type flip-flops 51 and 52, gates 53 to
The signal is frequency-divided by a frequency-divided-by-2 circuit 45 comprising an inverter 59 and a frequency-divided-by-2 signal CLK and a frequency-divided-by-2 signal T1. In this case, the 2n frequency-divided signal CLK, that is, the lower frequency is the basic clock. Output of 2n frequency-divided signal is D with reset
Connected to the latch signal input of the flip-flop 44,
The data input of this flip-flop 44 is connected to VDD. The output of the flip-flop 44 is reset when the inverted signal of the original clock signal 42 falls. Therefore, the output of the flip-flop 44 becomes “1” at the rise of the basic clock 42 and becomes “0” at the fall of the inverted signal of the original clock signal. ".

In this circuit, the output of the flip-flop 44 initializes the divide-by-2 circuit 45 to a desired state, thereby adjusting the phases of the 2n-divided signal and the divide-by-2 signal to a desired state. Further, in general, as a method of adjusting the phase of each frequency-divided signal, a method of initializing all frequency dividers at a specific timing has been conventionally often used. An example in which this method is applied to a divide-by-2 circuit and a divide-by-6 circuit is shown in FIG. 6 and its operation will be described.

In FIG. 6, reference numerals 31 to 35 denote D with reset for latching a data input signal at a rising edge of a latch input signal.
Type flip-flops, 36 and 37 are D-type flip-flops for latching a data input signal at the falling edge of the latch input signal, 18 and 20 are selectors, and 17 and 19 are NO
R and CLK are the original clock signals to be divided, RESET
Is a reset signal externally supplied to initialize all the frequency dividers.

D-type flip-flops 31 to 3 with reset
5 latches the value of the data D at the rising edge of the clock C, outputs the value to the output Q, outputs the inverted signal to the Q bar,
When the reset R becomes "1" (R bar becomes "0"), Q becomes "0" and Q bar is reset to "1". The D-type flip-flops 36 and 37 perform a falling edge latch operation of latching the value of the data D at the falling edge of the clock C and outputting the output Q (Q bar is an inverted output). The selectors 18 and 20 output data D1 to Q when the selection signal S is “0”, and output data D2 when the selection signal S is “1”.

The D-type flip-flop with reset 31 constitutes a frequency divider by an inverted signal of the data output being fed back to the data input.
.. Constitute a counter that repeatedly counts as “00 → 01 → 10 → 00...” And constitutes a 6-frequency divider together with the flip-flop 34. The CLK signal is connected to latch inputs of a flip-flop 31 forming a frequency divider and a flip-flop 32-34 forming a frequency divider,
A divided signal and a divided-by-6 signal are obtained.

In this circuit, the frequency-divided signal by 2 and 6
The phase adjustment of the frequency-divided signal is performed by initializing the above-described frequency-divider 2 and frequency-divider 6 with a RESET signal. However, the RESET signal is usually provided from the outside, and is often completely asynchronous with the CLK signal. Therefore, in order to prevent the frequency divider from malfunctioning, the RESET signal is synchronized by the CLK signal, and the release timing of the initialization signal is set to the CLK signal.
It is necessary to deviate from the rising timing of the signal. The flip-flops 35 to 37 synchronize the RESET signal. First, the reset D-type flip-flop 35 detects the rising edge of the RESET signal and outputs "1".
And the D-type flip-flops 36 and 3 receiving the output
7 synchronizes with the falling edge of the CLK signal, and when the output of the flip-flop 37 becomes "1", the flip-flop 35 is reset by the output.

Therefore, the output of the flip-flop 37 is
After the RESET signal rises, the signal always becomes "1" for one cycle from the fall of the CLK signal to the next fall. Therefore, this signal is used to initialize the 2 divider and the 6 divider. In this case, the frequency-divided signal of 2 and 6
The phase of the divided signal can be adjusted.

FIG. 7 shows a timing chart of this circuit. As is clear from the figure, before the RESET signal was set to “1”, the 6-frequency-divided signal rose at the fall of the 2-divided signal, but after the RESET signal was set to “1”, A 6-frequency-divided signal rises at the rise of the frequency-divided signal. Of course, it is also possible to easily configure the circuit to have the opposite phase.

[0015]

In the above-described conventional circuit (FIG. 5), the flip-flop 44 is used to generate a load signal for initializing the frequency divider. And the passing time is slow.
Therefore, the cost is increased due to the large circuit scale,
The slow transit time causes a problem that the maximum frequency of the original clock signal to be divided, at which the circuit can operate, is reduced. Further, the above-described load signal is set at the rising or falling of the basic clock signal generated by dividing the original clock signal, and after the setting, the original clock signal half a cycle of the original clock signal is set. Is generated by a flip-flop that resets at the rising or falling edge of the clock, the change timing is always shifted by a half cycle of the original clock, and a timing signal that changes at exactly the same change timing as the change timing of the basic clock signal cannot be generated. There was a point.

In FIG. 6 in which the full frequency divider is initialized at the specific timing described above, the signal for initializing the full frequency divider must be synchronized, so that the circuit becomes very large. There was a problem that the cost increased. Further, in order to reliably perform the initialization operation of the frequency divider, RE
Set the SET signal to “0” first, then to “1”,
After that, since the signal must be kept at "1" for at least one cycle of the CLK signal and then set to "0" again, a circuit for generating such a RESET signal is also required, which has increased the cost.

An object of the present invention is to provide a frequency dividing circuit capable of performing a frequency divided output in which a phase of a frequency divided signal is adjusted to a specific state by adding a simple circuit.

[0018]

According to the structure of the frequency dividing circuit of the present invention, an input signal is connected to a latch signal input terminal and an output signal is output.
The first data signal output is latched at the rising edge or the falling edge of the input signal by inverting the inverted signal of the first data signal output to the data signal input terminal. A first D-type flip-flop that outputs a frequency-divided signal of the input signal, and sets a rising edge or a falling edge of the input signal to n so as to divide the input signal by 2n (n is a natural number of 2 or more). a counter for counting repeatedly times, the output signal at the rising or falling edge of the input signal in accordance with the output of the counter
A second data signal output or this second data signal
A second D-type flip-flop for latching an inverted signal of the signal output and outputting a 2n frequency-divided signal of the input signal; and a counter when the value of the counter and the output of the second flip-flop become a specific logical value. A logic circuit for masking the data signal input of the first D-type flip-flop to 0 or 1; and the phase of the divide-by-2 signal of the input signal and the phase of the 2n-divided signal of the input signal are automatically specified. It is characterized by being adapted to a logical value.

[0019]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
2 is a circuit diagram of a divide-by-2 circuit and a divide-by-6 circuit in the embodiment, and FIG. 2 is a timing chart of the circuit of FIG. In this circuit, the circuit is configured so that the divide-by-6 signal finally rises at the rise of the divide-by-2 signal. It can be easily set to rise.

Hereinafter, the operation of the circuit of this embodiment will be described.
In FIG. 1, reference numerals 11 to 14 denote D-type flip-flops for latching a data input signal at a rising edge of a latch signal.
15 is a 2-input NAND, 16 is a 3-input NAND, 17,
19 is a 2-input NOR, and 18 and 20 are selectors.

In the flip-flop 11, a data output signal is feedback-connected to a data input signal to form a divide-by-2 circuit. The flip-flops 12 and 13 are “00 →
01 → 10 → 00... ”, And constitutes a 6-frequency divider together with the flip-flop 14. The CLK signal is supplied to a flip-flop 11 forming a 2 frequency divider and a flip-flop 12 to a 6 frequency divider.
14 are connected as latch signals, and become a divide-by-2 signal and a divide-by-6 signal, respectively.

In this circuit, the phases of the divide-by-2 signal and the divide-by-6 signal are adjusted by the three-input NAND 16 connected to the inverted outputs of the flip-flops 12 to 14 and the flip-flop 1
Two-input NAND inserted before the one data input signal
Perform at 15.

The flip-flops 12 and 13 use the flip-flop 13 as an upper bit, 00 → 01 → 10 →
00... Are repeatedly counted.
When the data output of the flip-flop 13 is the CLK signal rises when the "1", but inverts the data output, the data output up CLK signal when the output of the flip-flop 13 is "0" is standing Is not changed, the output of the three-input NAND 16 is connected to the flip-flop 1
It becomes "1" only in a specific state of the 6-frequency divider, that is, the state of the counter composed of 2 and 13 is "00" and the output of the flip-flop 14 is "0". Therefore, by masking the data input signal of the flip-flop 11 to "1" by the two-input NAND 15 when this signal is "1", when the 6-divider is in a specific state, the 2-divider is specified. It can be initialized to the state, and the phase of the divide-by-2 signal and the divide-by-6 signal can be adjusted.

In the timing chart of FIG. 2, before the time T1, the 6-divided signal rises at the falling timing of the 2-divided signal, but when the CLK signal rises at the time T1, the 6-divider is used. , The divided-by-6 signal becomes "0" and the output of the three-input NAND 16 becomes "0", so that the data input signal of the flip-flop 11 is masked to "1". Thereafter, when the CLK signal rises at T2, since the data input signal of the flip-flop 11 is masked to 1 in the frequency-divided-by-2 signal, the signal which normally changes to "0" continues to output "1". Therefore, the time T
After 2, the 6-divided signal rises at the rising timing of the 2-divided signal.

At time T2, the flip-flop 11
For masking the data input signal of
6 changes, the change occurs after the rise of the CLK signal at time T2 and the output of the 6-frequency divider changes. Therefore, a delay always occurs, and before the change, the flip-flop 11 Normally, there is no problem because the latch operation is completed.

Conversely, to configure a circuit so that a 6-divided signal rises at the fall of a 2-divided signal, a three-input NA
The ND 16 may be changed to a three-input AND, and the two-input NAND 15 may be changed to a two-input NOR. With this circuit configuration, the data input signal of the flip-flop 11 is masked to “0” when the value of the counter of the 6-divider is “00” and the divided-by-6 signal is “0”. Thereafter, the divide-by-6 signal rises at the fall of the divide-by-2 signal.

As described above, according to the present invention,
Since it is possible to match the phases of the divide-by-2 signal and the divide-by-6 signal to a specific state by adding only a few circuits to the ordinary set of the divide-by-2 and divide-by-6 circuits, The cost and operating frequency are greatly improved in comparison.

FIG. 3 is a circuit diagram of a divide-by-2 circuit and a divide-by-10 circuit according to the second embodiment of the present invention, and FIG.
3 is a timing chart of the circuit of FIG. In this circuit, a 10-frequency-divided signal rises at the rising edge of the 2-cycle signal.
Configure the circuit. Hereinafter, with reference to FIGS. 3 and 4,
The operation of the circuit will be described.

In FIG. 3, reference numerals 11 to 14 and 21 denote data input signals at the rising edge of the latch signal.
D-type flip-flop similar to the above, 15 is a 2-input NAN
D and 24 are 4-input NANDs, 17, 19 and 22 are 2-input NORs, and 18, 20, and 24 are selectors. The flip-flop 11 has a data output signal fed back to the data input signal and forms a divide-by-2 circuit.

The flip-flops 12 to 14 are "000 →
001 → 010 → 011 → 100 → 000... ”, And the flip-flop 21
Together with the frequency divider. The CLK signal is connected as a latch signal to a flip-flop 11 constituting a divide-by-2 frequency divider and flip-flops 12 to 14 and 21 constituting a divide-by-10 frequency divider, and becomes a divide-by-2 signal and a divide-by-10 signal, respectively.

Also in this circuit, the phase adjustment of the divide-by-2 signal and the divide-by-10 signal is performed by a 4-input NAND 24 connected to the inverted outputs of the flip-flops 12 to 14, 21 and a data input signal of the flip-flop 11. This is performed with the two-input NAND 15 inserted.

The flip-flops 12 to 14 use the flip-flop 14 as the most significant bit and write "000 → 001".
→ 010 → 011 → 100 → 000... ”, And the flip-flop 21 inverts the data output when the CLK signal rises while the data output of the flip-flop 14 is“ 1 ”. Since the data output is not changed even when the CLK signal rises when the output is "0", the 4-input NAND 24
Is "1" only when the state of the counter composed of the flip-flops 12 to 4 is "000" and the output of the flip-flop 21 is "0" in a specific state of the 10-frequency divider. Therefore, when this signal is “1”, the data input signal of the flip-flop 11 is masked to “1” by the two-input NAND 15 to specify the divide-by-2 group when the divide-by-10 group is in a specific state. And the phase of the divide-by-2 signal and the divide-by-10 signal can be adjusted.

In the timing chart of FIG. 4, before the time T1, the divide-by-10 signal has risen at the falling timing of the divide-by-2 signal. When the CLK signal rises at time T1,
The data input signal of the flip-flop 31 is masked to “1” because the value of the counter of the 10-frequency divider is “000”, the signal of the 10-frequency divider is “0”, and the output of the 3-input NAND 37 is “0”. Is done. Thereafter, when the CLK signal rises at T2, the divide-by-2 signal is normally "0" because the data input signal of the flip-flop 11 is masked to "1".
, Continues to output “1”. Therefore, before the time T2, the divide-by-10 signal rises at the rising timing of the divide-by-2 signal.

Therefore, according to the circuit of the present invention, the ordinary 2
The phase of the two-frequency signal and the frequency of the ten-frequency signal can be adjusted to a specific state by adding only a few circuits to the frequency divider and the frequency-divider set. The operating frequency is greatly improved.

[0035]

As described above, according to the present invention, in a system using a divide-by-2 signal and a 2n (n is a natural number of 2 or more) divided signal generated from an original clock signal, Compared to the conventional example, it is possible to match the phase of the 2 divided signal and the 2n divided signal to a specific state by adding a very small circuit to the set of the 2 divider and the 2n divider. Thus, there is an effect that the cost can be greatly reduced and the operating frequency does not decrease.

Furthermore, the present invention does not have a problem that a timing signal that changes at exactly the same change timing as the change timing of the basic clock signal existing in the conventional circuit cannot be generated. It can be said that.

[Brief description of the drawings]

FIG. 1 is a circuit diagram for adjusting the phases of a divide-by-2 signal and a divide-by-6 signal according to the first embodiment of the present invention.

FIG. 2 is a timing chart according to the first embodiment.

FIG. 3 is a circuit diagram for adjusting the phases of a divide-by-2 signal and a divide-by-10 signal according to the second embodiment of the present invention.

FIG. 4 is a timing chart according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram of a frequency dividing circuit of a conventional example.

FIG. 6 is a circuit diagram for adjusting the phases of a divide-by-2 signal and a divide-by-6 signal in a conventional example.

FIG. 7 is a timing chart showing the operation of FIG.

[Explanation of symbols]

11 to 14, 21, 36, 37, 51, 52 D-type flip-flops 31 to 35, 44 D-type flip-flop with reset 15 2-input NAND circuit 16 3-input NAND circuit 17, 19, 22 2-input NOR circuit 18, 20 , 23 selector 24 4-input NAND circuit 43 2n frequency dividing circuit 45 2-frequency dividing circuit 53-57 AND circuit 58, 59 2-input OR circuit 60-62 inverter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 23/40 H03K 23/00

Claims (3)

(57) [Claims] An input signal is connected to a latch signal input terminal, and an inverted signal of a first data signal output serving as an output signal is feedback-connected to a data signal input terminal, so that a rising edge or a rising edge of the input signal is provided. A first D-type flip-flop for latching the first data signal output at a falling edge and outputting a frequency-divided signal of the input signal;
A counter for repeatedly counting the rising edge or the falling edge of the input signal n times so as to divide the input signal by 2n (n is a natural number of 2 or more), and the rising or falling of the input signal according to the output of the counter A second data signal output which becomes an output signal at the edge or the second data signal output
A second D-type flip-flop that latches an inverted signal of the data signal output of the above and outputs a 2n frequency-divided signal of the input signal, and the value of the counter and the output of the second flip-flop become a specific logical value. At least a logic circuit for masking the data signal input of the first D-type flip-flop to 0 or 1. The phase of the divide-by-2 signal of the input signal and the 2n-divided signal of the input signal is provided. Is automatically adjusted to the specific logical value. 2. The frequency dividing circuit according to claim 1, wherein n is 3, the counter is a ternary counter, and the logic circuit comprises a three-input NAND circuit. 3. The frequency dividing circuit according to claim 1, wherein n is 5, the counter is a quinary counter, and the logic circuit is a 4-input NAND circuit.