JPH0923153A - Frequency dividing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent operation frequency from being reduced by providing this frequency dividing circuit with 1st and 2nd flip flops(FFs) and a logic circuit and automatically setting up the 2-frequency divided signal of an input signal and the 2n-frequency divided signal of the input signal to specific states. SOLUTION: In the FFs 13, 14, the FF 13 is regarded as an upper bit and 00→01→10→00→... are repeatedly counted up. If a CLK signal is raised when a data output from the FF 13 is '1', the FF 14 inverts the data output, but when the output of the FF 13 is '0', the FF 14 does not change the data output even when the CLK signal is raised. Thereby an output from a three-input NAND 16 becomes '1' only in a specific state of a 6-frequency divider, i.e., the state of a counter constituted of the FFs 12, 13 is 00 and the output of the FF 14 is '0'. If a data input signal to an FF 11 is masked to '1' by a two-input NAND 15 when the signal is '1', a 2-frequency divider can be initialized to a specific state when the 6-frequency divider is in the specific state and phase matching between a 2-frequency divided signal and a 6-frequency divided signal can be executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider circuit, and more particularly to a frequency divider circuit that outputs a phase-controlled clock signal that serves as a reference for circuit operation.

[0002]

2. Description of the Related Art In recent microprocessors or microcontrollers, a clock multiplication circuit built in an LSI generates a clock that is several times to several tens times (usually a factorial multiplication of 2) of the clock supplied from the outside. By operating the inside in synchronization with this clock, the frequency of the clock used for the interface with the outside is kept relatively low and the performance is improved in many cases.

In such a case, at least two clocks, a clock used for interface with the outside and a clock used for internal operation, are required inside the LSI, and in fact, a higher speed is required for a specific circuit. It is not uncommon to use multiple clocks, such as using clocks. Therefore, a method of generating a plurality of clocks by generating the fastest clock in the clock multiplication circuit and sequentially dividing this clock is adopted.

As described above, a problem arises when a frequency divider generates a plurality of clocks having different frequencies from one clock. How to match the phases of these plurality of clocks to a certain specific state. That is. In general, the phase of the fastest clock signal and a signal obtained by dividing it by 2n (n is a natural number) is divided by counting rising edges of the original clock signal or by counting falling edges. Since it is uniquely determined by, it does not matter.

However, when a signal obtained by dividing the highest speed clock signal by 2 and a signal obtained by dividing 2n are used, the phase of these two signals is 2n divided at the rising edge of the divided 2 signal. There are cases where the signal rises and cases where the 2n frequency-divided signal rises at the falling edge of the frequency-divided 2 signal. It does not matter whether the rising edge or the falling edge is counted, and the 2 Since it is determined by the initial state of the frequency dividing circuit and the 2n frequency dividing circuit, it cannot normally be uniquely determined. In such a case, transmission / reception of a signal between the circuit block that operates with the frequency-divided 2 signal and the circuit block that operates with the 2n-frequency-divided signal cannot be designed properly, and thus phase matching is usually performed by some method.

A method for adjusting the phases of a plurality of frequency-divided signals to a specific state in this way is disclosed in JP-A-56-14962.
There is a "timing signal generation circuit" shown in Japanese Patent No. 4 publication. This circuit has a frequency higher than the basic clock and lower than the original oscillation frequency with respect to the basic clock obtained by dividing a certain oscillation frequency, and has a desired phase relationship with the basic clock. A circuit for generating a timing signal is described. Hereinafter, FIG. 4 will be described with reference to FIG. 5 in the case where this circuit is applied to the case of the frequency dividing circuit of 2 and the frequency dividing circuit of 2n.

The original clock signal is the 2n frequency dividing circuit 4
3, D-type flip-flops 51 and 52, and gates 53 to
59 and the frequency dividing circuit 45 composed of the inverter 60 to divide the frequency into a 2n frequency dividing signal CLK and a 2 frequency dividing signal T1. In this case, the 2n frequency-divided signal CLK, that is, the lower frequency becomes the basic clock. 2n frequency division signal output with reset D
Connected to the latch signal input of the type flip-flop 44,
The data input of this flip-flop 44 is connected to VDD. The output of the flip-flop 44 is reset at the fall of the inverted signal of the original clock signal 42. Therefore, the output of the flip-flop 44 becomes "1" at the rising edge of the basic clock 42 and becomes "0" at the falling edge of the inverted signal of the original clock signal. It becomes the signal which shows.

In this circuit, the output of the flip-flop 44 is used to initialize the divide-by-2 circuit 45 to a desired state, thereby adjusting the phases of the 2n-divided signal and the divided-by-2 signal to the desired state. Further, generally, as a method of matching the phases of the respective frequency-divided signals, a method of initializing all frequency dividers at a specific timing has been often used conventionally. An example of applying this method to the divide-by-2 circuit and the divide-by-6 circuit is shown in FIG. 6 and its operation will be described.

In FIG. 6, reference numerals 31 to 35 denote reset D for latching the data input signal at the rising edge of the latch input signal.
Type flip-flops, 36 and 37 are D-type flip-flops that latch the data input signal at the falling edge of the latch input signal, 18 and 20 are selectors, and 17 and 19 are NO.
R and CLK are the original clock signal to be divided, RESET
Is a reset signal supplied from the outside to initialize the entire frequency divider.

D-type flip-flops 31 to 3 with reset
5 latches the value of the data D at the rising edge of the clock C, outputs it to the output Q, and outputs its inverted signal to the Q bar,
When the reset R becomes "1" (R bar becomes "0"), Q becomes "0" and the Q bar is reset to "1". The D-type flip-flops 36 and 37 perform the falling edge latch operation of latching the value of the data D at the falling edge of the clock C and outputting the output Q (Q bar is an inverted output). The selectors 18 and 20 output the data D1 to Q when the selection signal S is "0", and output the data D2 when the selection signal S is "1".

In the D-type flip-flop 31 with reset, the inverted signal of the data output is feedback-connected to the data input to form a divide-by-2 frequency divider, and the flip-flops 32 and 33 are provided.
Constitutes a counter that repeatedly counts "00 → 01 → 10 → 00 ...", and constitutes a 6-divider together with the flip-flop 34. The CLK signal is connected to the latch inputs of the flip-flop 31 that constitutes the frequency divider by 2 and the flip-flops 32 to 34 that constitute the frequency divider by 6, and is respectively 2
It becomes a frequency division signal and a frequency division signal by 6.

Now, in this circuit, the divided-by-two signal and 6
The phase matching of the frequency-divided signal is performed by initializing the above-described frequency divider 2 and frequency divider 6 with the RESET signal. However, the RESET signal is usually given from the outside and is often completely asynchronous with the CLK signal. Therefore, in order to prevent the frequency divider from malfunctioning, the CLK signal of the RESET signal is used for synchronization, and the release timing of the initialization signal is set to CLK.
It is necessary to shift it from the rising timing of the signal. The flip-flops 35 to 37 perform the synchronization processing of the RESET signal. First, the D-type flip-flop with reset 35 detects the rising edge of the RESET signal and outputs "1".
And the D-type flip-flops 36, 3 that received the output
7 synchronizes at the falling edge of the CLK signal, and when the output of the flip-flop 37 becomes "1", the flip-flop 35 is reset by the output.

Therefore, the output of the flip-flop 37 is
After the RESET signal rises, the signal is always "1" for one cycle from the falling edge of the CLK signal to the next falling edge, so this signal is used to initialize the 2 divider and 6 divider. By doing so, the frequency-divided signal of 6 and the frequency-divided signal of 6 can be generated without causing malfunction of the frequency divider.
The phase of the divided signal can be adjusted.

A timing chart of this circuit is shown in FIG. As is apparent from the figure, before the RESET signal is set to "1", the divided-by-6 signal rises at the falling edge of the divided-by-2 signal, but after the RESET signal is set to "1", it becomes 2 The divide-by-6 signal rises at the rising edge of the divided signal. Of course, it is also possible to easily configure the circuit so as to have the opposite phase.

[0015]

In the conventional circuit (FIG. 5) described above, the flip-flop 44 is used to generate the load signal for initializing the frequency divider. The number of additional circuits is increased and the transit time is slow.
Therefore, the large circuit scale causes an increase in cost,
Due to the slow passage time, there is a problem that the maximum frequency of the original clock signal to be frequency-divided, which allows the circuit to operate, is lowered. Furthermore, the load signal described above is set at the rising or falling edge of the basic clock signal generated by dividing the original clock signal, and after the setting, the original clock signal half cycle after the original clock signal. Since it is generated by a flip-flop that resets at the rise or fall of the clock, the change timing is always deviated by a half cycle of the original clock, and a timing signal that changes at the same change timing as the change timing of the basic clock signal cannot be generated. There was a point.

Further, in FIG. 6 which initializes all the frequency dividers at the above-mentioned specific timing, the signal for initializing all the frequency dividers must be synchronized, so that the circuit becomes very large, There was a problem that the cost would increase. Furthermore, in order to perform the initialization operation of the frequency divider surely, RE
Set the SET signal to "0" first and then to "1",
After that, the circuit must be kept at "1" for at least one cycle of the CLK signal and then set to "0" again. Therefore, a circuit for generating such a RESET signal is also required, resulting in an increase in cost.

An object of the present invention is to provide a frequency dividing circuit capable of performing frequency division output in which the phase of the frequency divided signal is adjusted to a specific state by adding a simple circuit.

[0018]

The frequency divider circuit according to the present invention has a configuration in which an input signal is connected to a latch signal input terminal and an inverted signal of a data signal output is feedback-connected to a data signal input terminal. A first D-type flip-flop that outputs the frequency-divided signal of the input signal by latching the data signal output at the rising edge or the falling edge of the input signal, and the input signal is 2n (n is a natural number of 2 or more) A counter that repeatedly counts rising edges or falling edges of the input signal n times so as to divide the frequency;
A second D-type flip-flop that latches the data signal output at a rising edge or a falling edge of the input signal according to the output of the counter and outputs a 2n frequency-divided signal of the input signal, the counter value, and the second value. And a logic circuit for fixing the data signal input of the first flip-flop to 0 or 1 when the output of the flip-flop reaches a specific value, and divides the input signal by 2 and the input signal 2n. It is characterized in that the phase of the divided signal is automatically adjusted to a specific state.

[0019]

Next, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the first embodiment of the present invention.
FIG. 2 is a circuit diagram of a frequency divider circuit of 2 and a frequency divider circuit of 6 in the embodiment, and FIG. 2 is a timing chart of the circuit of FIG. 1. In this circuit, the circuit is configured so that the divided-by-6 signal finally rises at the rising edge of the divided-by-2 signal. However, the reverse setting, that is, the divided-by-6 signal is generated at the falling edge of the divided-by-2 signal. It is also possible to easily set to stand up.

The operation of the circuit of this embodiment will be described below.
In FIG. 1, 11 to 14 are D-type flip-flops that latch the data input signal at the rising edge of the latch signal,
15 is a 2-input NAND, 16 is a 3-input NAND, 17,
Reference numeral 19 is a 2-input NOR, and 18 and 20 are selectors.

In the flip-flop 11, the data output signal is feedback-connected to the data input signal to form a divide-by-2 circuit. The flip-flops 12 and 13 are "00 →
A counter that repeatedly counts "01 → 10 → 00 ..." Is configured, and together with the flip-flop 14, a 6-divider is configured. The CLK signal includes a flip-flop 11 forming a frequency divider of 2 and a flip-flop 12 forming a frequency divider of 6 to
It is connected to 14 as a latch signal, and becomes a divided-by-2 signal and a divided-by-6 signal, respectively.

In the present circuit, the phase-division of the divided-by-2 signal and the divided-by-6 signal is performed by the 3-input NAND 16 connected to the inverted outputs of the flip-flops 12-14 and the flip-flop 1.
2-input NAND inserted before the 1-data input signal
Do at 15.

The flip-flops 12 and 13 have 00.fwdarw.01.fwdarw.10.fwdarw.
00 ... is repeatedly counted, and the flip-flop 14
Inverts the data output when the data output of the flip-flop 13 is "1", especially when the CLK signal rises. However, when the output of the flip-flop 13 is "0", the data output is inverted even if the CLK signal rises. Since the configuration does not change, the output of the 3-input NAND 16 is the flip-flop 1
It becomes "1" only when the state of the counter composed of 2 and 13 is "00" and the output of the flip-flop 14 is "0", and in a specific state of the 6-frequency divider. Therefore, when this signal is "1", the 2-input NAND 15 masks the data input signal of the flip-flop 11 to "1", so that when the 6-divider is in a specific state, the 2-divider is specified. It can be initialized to the state, and the phases of the divided-by-2 signal and the divided-by-6 signal can be matched.

In the timing chart of FIG. 2, before the time T1, the divide-by-6 signal rises at the falling timing of the divide-by-2 signal, but when the CLK signal rises at the time T1, the divide-by-6 frequency divider. Since the value of the counter is “00”, the divide-by-6 signal is “0”, and the output of the 3-input NAND 16 is “0”, the data input signal of the flip-flop 11 is masked to “1”. After that, when the CLK signal rises at T2, since the data input signal of the flip-flop 11 is masked to 1 in the divided-by-two signal, "1" is normally output where it changes to "0". Therefore, time T
After 2, the frequency-divided 6 signal rises at the rising timing of the frequency-divided 2 signal.

At time T2, the flip-flop 11
Signal for masking the data input signal of NAND1, NAND1
The output of 6 changes, but this change occurs after the CLK signal rises at time T2 and the output of the 6-divider changes, so there is always a delay, and before the change, the flip-flop 11 Since the latch operation is completed, there is usually no problem.

On the contrary, in order to configure the circuit so that the divided-by-6 signal rises at the fall of the divided-by-2 signal, the 3-input NA is used.
The ND 16 may be changed to a 3-input AND, and the 2-power NAND 15 may be changed to a 2-input NOR. If the circuit is configured in this way, the data input signal of the flip-flop 11 is masked to "0" when the counter value of the divide-by-6 frequency divider is "00" and the divide-by-6 signal is "0". After that, the divided-by-6 signal rises when the divided-by-2 signal falls.

As described above, according to the present invention,
Since it is possible to match the phases of the divided-by-2 signal and the divided-by-6 signal to a specific state by adding a few circuits to the set of the normal divide-by-2 frequency divider and the divide-by-6 frequency divider, The cost and operating frequency are significantly improved in comparison.

FIG. 3 is a circuit diagram of a divide-by-2 circuit and a divide-by-10 circuit according to the second embodiment of the present invention, and FIG. 4 is shown in FIG.
3 is a timing chart of the circuit. In this circuit, the divided-by-10 signal rises at the rising edge of the divided-two signal,
Configure the circuit. Hereinafter, with reference to these FIG. 3 and FIG.
The operation of the circuit will be described.

In FIG. 3, 11 to 14 and 21 latch the data input signal at the rising edge of the latch signal.
D-type flip-flop similar to the above, 15 is a 2-input NAN
D and 24 are 4-input NANDs, 17, 19 and 22 are 2-input NORs, and 18, 20, and 24 are selectors. The data output signal of the flip-flop 11 is feedback-connected to the data input signal to form a divide-by-2 circuit.

The flip-flops 12 to 14 are "000 →
The counter that repeatedly counts "001 → 010 → 011 → 100 → 000 ...
Together with the 10 divider. The CLK signal is connected as a latch signal to the flip-flop 11 that constitutes the frequency divider by 2 and the flip-flops 12 to 14 and 21 that constitute the frequency divider by 10, and becomes a frequency-divided signal by 2 and a frequency-divided signal by 10, respectively.

Also in this circuit, the phase division of the divided-by-2 signal and the divided-by-10 signal is performed before the 4-input NAND 24 connected to the inverted outputs of the flip-flops 12 to 14 and 21 and the data input signal of the flip-flop 11. This is done with the inserted 2-input NAND 15.

The flip-flops 12 to 14 use the flip-flop 14 as the most significant bit, “000 → 001”.
→ 010 → 011 → 100 → 000 ... ”, and the flip-flop 21 inverts the data output when the CLK signal rises when the data output of the flip-flop 14 is“ 1 ”. Since the data output is not changed even when the CLK signal rises when the output is “0”, the 4-input NAND 24
The output of is only "1" when the state of the counter constituted by the flip-flops 12 to 4 is "000" and the output of the flip-flop 21 is "0" in a specific state of the frequency divider 10. Therefore, when this signal is "1", the 2-input NAND 15 masks the data input signal of the flip-flop 11 to "1" to specify the divide-by-2 basis when the divide-by-10 basis is in a specific state. The signal can be initialized to the state of (1), and the phases of the divided-by-2 signal and the divided-by-10 signal can be adjusted.

In the timing chart of FIG. 4, before the time T1, the divided-by-10 signal rises at the falling timing of the divided-by-2 signal. When the CLK signal rises at time T1,
Since the counter value of the frequency divider 10 is "000", the frequency division signal is "0", and the output of the 3-input NAND 37 is "0", the data input signal of the flip-flop 31 is masked to "1". To be done. After that, when the CLK signal rises at T2, the divided-by-2 signal is normally "0" because the data input signal of the flip-flop 11 is masked by "1".
However, it continues to output "1". Therefore, before the time T2, the 10-divided signal rises at the rising timing of the 2-divided signal.

Therefore, according to the circuit of the present invention, the normal 2
Since it is possible to match the phases of the frequency-divided 2 signal and the frequency-divided 10 signal to a specific state by simply adding a small number of circuits to the set of the frequency divider and the frequency divider 10, the cost compared to the conventional example, The operating frequency is greatly improved.

[0035]

As described above, according to the present invention, in a system using a frequency-divided 2 signal and a frequency-divided signal 2n (n is a natural number of 2 or more) generated from an original clock signal, Compared with the conventional example, it is possible to match the phase of the divided-by-2 signal and the divided-by-2n signal to a specific state by adding a very small number of circuits to the set of divided-by-2 and divided-by-2n circuits. Thus, there is an effect that the cost can be significantly reduced and the operating frequency is not lowered.

Furthermore, the problem that a timing signal that changes at exactly the same change timing as the change timing of the basic clock signal that exists in the conventional circuit cannot be generated does not exist in the present invention, and is a very effective circuit. Can be said.

[Brief description of drawings]

FIG. 1 is a circuit diagram for matching the phases of a divided-by-2 signal and a divided-by-6 signal in a first embodiment of the present invention.

FIG. 2 is a timing chart of the first embodiment.

FIG. 3 is a circuit diagram that matches the phases of a divided-by-2 signal and a divided-by-10 signal in the second embodiment of the present invention.

FIG. 4 is a timing chart of the second embodiment of the present invention.

FIG. 5 is a circuit diagram of a conventional frequency divider circuit.

FIG. 6 is a circuit diagram for matching the phases of a divided-by-2 signal and a divided-by-6 signal in a conventional example.

FIG. 7 is a timing chart showing the operation of FIG.

[Explanation of symbols]

11-14, 21, 36, 37, 51, 52 D-type flip-flop 31-35, 44 D-type flip-flop with reset 15 2-input NAND circuit 16 3-input NAND circuit 17, 19, 22 2-input NOR circuit 18, 20 , 23 selector 24 4-input NAND circuit 43 2n frequency dividing circuit 45 2 frequency dividing circuit 53-57 AND circuit 58,59 2-input OR circuit 60-62 inverter

Claims (3)

[Claims] 1. A data signal output at a rising edge or a falling edge of the input signal, wherein an input signal is connected to a latch signal input terminal and an inverted signal of a data signal output is feedback-connected to a data signal input terminal. Is latched and outputs a frequency-divided signal of the input signal by a first D-type flip-flop and the input signal by 2n (n is 2).
A counter that repeatedly counts the rising edge or falling edge of the input signal n times so as to divide the frequency, and the data signal output is latched at the rising or falling edge of the input signal according to the output of this counter. A second D that outputs a 2n-divided signal of the input signal
A flip-flop and a logic circuit for fixing the data signal input of the first flip-flop to 0 or 1 when the value of the counter and the output of the second flip-flop reach a certain value. A frequency dividing circuit, wherein phases of a frequency-divided signal of the input signal and a frequency-divided signal of the input signal 2n are automatically adjusted to a specific state. 2. The frequency dividing circuit according to claim 1, wherein n is 3, the counter is a ternary counter, and the logic circuit is a 3-input NAND circuit. 3. The frequency dividing circuit according to claim 1, wherein n is 5, the counter is a quinary counter, and the logic circuit is a 4-input NAND circuit.