JP2631662B2 - Ultrasonic wave receiving phasing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an ultrasonic wave receiving and phasing circuit in an electronic scanning ultrasonic tomography apparatus.

[Conventional technology]

A conventional wave receiving phasing circuit, for example, as described in JP-A-58-141142, samples each received signal at twice or more the highest frequency of the signal band, and places the signal value in each delay time. After the corresponding time is held, the reception is phased by adding.

[Problems to be solved by the invention]

According to the above-mentioned prior art, when the focus point is switched,
The sampling phase is changed by a method of increasing the delay time so that the focus point is switched at the same phase point of the received signal in each element (hereinafter, this is referred to as wavefront synchronization switching).

For example, in a phasing circuit by sampling as shown in FIG. 1A, 1 to n are array elements for transmitting and receiving ultrasonic waves, D _{1 to} D _n are delay means by sampling, 2-1 is an adder, -1 resampling means, phi ₁ to [phi] _n sampling signals to the respective sampling delay means D ₁ ~D _{n, φ 0} resampling signal, F _1, F ₂ is the focal point. FIG. 2A shows a sampling wavefront in a conventional phasing method. From a large phase front curvature relative to the focus point F ₁ of the short range, when Setsu換Ru sampling points in a small phase front curvature relative to the focus point F ₂ of To距than F _1,
Although the sampling cycle for the central array element i is constant at T, the delay time increases as approaching the element (1, n) at the end of the reception aperture. Will come. For example, to increase the signal delay and the elements of the end 1 of the central element i with respect to the focus point F _1, or the difference between the signal delay and n as tau _i, the delay of the end element with respect to the focus point F ₂ by delta _i, end sampling interval for element becomes T-delta _i in switching point. FIG. 2B shows the sampling signals φ ₁ and φ _i and the resampled signal φ _o for the end element 1 and the center element i when switching from F ₁ to F ₂ in the conventional method. Here, T _s is sampling means D _{1 to} D _n , 3
-1 is the minimum sampling time (acquisition time + settling time) of the circuit used. Received signal of each array element, the signal value at time of fall of the sampling pulse phi ₁ to [phi] _n is held as a result of the adder 3-1, it is resampled at the timing of the fall of phi ₀ You. In FIG. 2 (b), when increasing the delay of the end elements 1 of the signal delta _i, it is necessary Setsu換Ru sample pulse phi ₁ to a time earlier by delta _i. In that case, as shown by the dashed arrow of p,
Since sampled signal with a pulse phi ₁ after was switching to hold the addition output by resampling pulse phi ₀ before settling, delay-and-sum output signal value errors, there is a problem that deteriorates the image as switching noise .

An object of the present invention is to provide an ultrasonic wave receiving and phasing circuit in which switching noise does not occur in focus switching.

[Means for solving the problem]

The object of the present invention is to set the sampling signals φ _{1 to} φ _n so that the delay time of the element at the end is constant and the delay time of the other elements on the central side (other than 1, n) is monotonously reduced at the time of focus switching.
, The phasing addition is performed without dulling the sampling interval, so that the focus point can be switched without switching noise.

[Action]

FIG. 1 (b) shows a sampling wavefront in the phasing system of the present invention. The meaning of each number is the same as in FIG. 2 (a). If Setsu換Ru focus point from F ₁ to F _2, the sampling period for element 1, n end is fixed at T, by reducing the delay time toward the center of the element i, the sampling interval in the switching point is how It is T or more for the element. For example, the signal delay of the central elements i when Setsu換Ru from F ₁ to F ₂ as delta _i, the sampling interval in the switching point becomes T + delta _i.

Figure 1 (c), in the present invention, illustrating an end element 1 and the sampling signal phi ₁ to the central element i, phi _i the resampled signal phi ₀ when Setsu換Ru from F ₁ to F _2. Other signals are the same as in FIG. 2 (b). The signal delay of the central element i is Δ
When decreasing by _i , the sample pulse φ _i may be switched to a time delayed by Δ _i . At this time, the switched sample pulse is a pulse φ ₁ giving the minimum delay to the end element _1.
It will not be later. Therefore, since the phasing addition output is resampled at the timing of φ ₀ after the received signal to any element is settled, switching noise does not occur.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 4
-1, the sampling signal phi ₁ to [phi] _n, the control circuit for generating a phi _0, 5-1 is a memory that stores the switching time of the delay data and the focus point of each element signals for each focus point. Other symbols are the same as those in FIG.

The control circuit 4-1 includes a master clock CLK for sampling and a signal Reset for starting reception focus.
Receiving, by generating an address for the memory 5-1 reads the data of the delayed data and the focus switching time TD _j for each element from 5-1, the sampling signal as corresponding to the delay phi ₁ to [phi] _n, phi ₀ , and each delay means D
_{1 to} D _n are sent to the resampling means 3-1. Control circuit 4-1
In, after counting the switching time TD _j, generates the address for the next focal point, after reading the next delay data from 5-1, the sampling signal corresponding to the next focal point φ _'1 ~φ' _n Occurs. At this time, the delay data for the end elements 1 and n of the receiving aperture is the same before and after the focus switch, and the delay data for the other elements is
The delay time is set to decrease. Therefore, according to the present embodiment, the sampling intervals at the time of focus switching can be switched so as to be the same or to increase.

Further, as the sampling delay means, Japanese Patent Laid-Open No.
For example, a sample-hold circuit and a capacitor memory circuit proposed in Japanese Patent Application No. 150193 or Japanese Patent Application No. 60-262447, or a combination thereof can be used. In such a delay means comprising a multistage configuration of such a sample-and-hold circuit (hereinafter abbreviated as S / H) or a capacitor memory circuit (hereinafter abbreviated as SC), there is a specific problem that a delay error occurs at the time of switching a delay pattern. Having.

For example, if the SC has a two-stage configuration, and if the delay amounts of the preceding and succeeding stages are switched at the same time as in the prior art, the delay amount of the subsequent stage will change while the data is retained in the preceding stage, and the preceding stage will have the delay before switching. , The subsequent stage is a delay after switching. For this reason, there has been a problem that the amount of change in the delay amount at the subsequent stage becomes a delay error. This delay amount error becomes switching noise.

Hereinafter, an ultrasonic wave receiving and phasing circuit capable of eliminating the switching delay error and minimizing the switching noise will be described.

The above problem can be solved by newly adding a write / read signal timing control circuit using a shift register or the like to a switch control circuit for generating S / H or SC write / read signals. That is, the read signal timing control circuit has a multi-stage configuration.
It operates so as to change the delay switching timing of the subsequent stage of S / H, SC according to the switching of the preceding stage. Thereby, S / H, SC
Can be sequentially switched from the first stage, so that a delay error at the time of switching can be eliminated.

Hereinafter, another embodiment of the present invention which solves this problem will be described in detail with reference to the drawings.

FIG. 4 is a diagram showing a configuration of a sampling ultrasonic wave receiving circuit according to the present invention.

The signal input from the IN terminal is
, And then delayed by the switched capacitor circuits 2 and 3 and again delayed by the sample and hold circuit 4, and then a delay signal is output to the output terminal. Reference numeral ₅ denotes a control circuit for the write signals φ _{W1 to} φ _W4 and the read signals φ _{R1 to} φ _{R4 for} the sample hold circuits 1, 4 and the switched capacitors 2, 3, and reads the delay data D1 from the delay data storage circuit 6. Thereby, control signals φ _{W1 to} φ _W4 and φ _{R1 to} φ _R4 for executing an arbitrary delay are generated. Reference numeral 8 denotes output signals φ _{W1 to} φ _W of the control circuit 5.
_W4, phi _R1 is a circuit for generating a timing for switching to [phi] _R4, by reading the switching timing data from switching timing data storage circuit 7, a control signal phi _W1 to [phi] _W4 for executing an arbitrary delay, A timing signal K for switching φ _{R1 to} φ _R4 at an arbitrary time is generated. In the switching timing generation circuit 9 of the present invention,
Based on the switching timing signal K, the respective sample-hold circuits and the switched capacitor circuits φ _W1 to φ _W4 ,
generating a timing signal A1~A4 switching the φ _R1 ~φ _R4. M input signals with different phases are input terminal IN
1 to INM, then delayed by variable delay circuits DL1 to DLM shown in FIG. 4 (B) so that the phases become the same, added by an addition AMP10, and output from an output terminal. In this embodiment, a series connection of a sample-and-hold circuit and a switched capacitor circuit as shown in FIG. 4 will be described. However, the present invention relates to each connection, number, series or parallel connection and the like. Not effective.

FIG. 5 is a diagram showing an example of a specific circuit configuration.
The switching timing signal K is input to the shift register 13 and is shifted in synchronization with the shift register clock CLK. The multiplexer 12 selects the output signals SRQ1 to SRQn of the shift register 13 and outputs the respective sample-hold circuits and switched capacitor circuits φ _W1 to φ _W4 and φ _{R1 to} φ _R1 .
_It generates timing signals A1 to A4 for switching _R4 . Also,
The multiplexer address control circuit 11 outputs the delay data D1
To determine which timing to select, and generate a multiplexer address.

Next, referring to FIGS. 6 and 7, a description will be given while comparing the conventional example with the method of the present invention.

FIG. 6 shows a conventional delay switching system. It is assumed that the write signals φ _{W1 to} φ _W4 and the read signals φ _{R1 to} φ _R4 of the respective sample and hold circuits and switching capacitor circuits have a relationship as shown in the figure. Here, OA is a delay time of the sample and hold circuit 1, OB is a delay time of the switched capacitor circuit 2, OC is a delay time of the switched capacitor circuit 3, and OD is a delay time of the sample and hold circuit 4. This is the delay time. In the conventional method, all the sample-hold circuits and the switched capacitor circuits φ _W1
~φ _W4, φ _R1 ~φ _R4 is switched. Therefore, the waveform shown by the broken line is thereafter obtained. Here, attention is paid to data sampled by the pulse S shown in the figure. Since this sample data is sampled before the generation of the switching timing signal K, it must be delayed according to the delay data before switching. In other words, if the delay before switching is as shown in the figure, the delay before switching = OA + OB + OC + OD. However, the actual delay amount of the data sampled by the pulse S is equal to the actual delay = OA '+ OB' + OC '+ OD' since switching is performed at the timing indicated by the broken line in the figure. The difference between the delay amounts becomes a delay error at the time of switching.

Delay error = (OA−OA ′) + (OB−OB ′) + (OC−OC ′) + (OD−OD ′) Therefore, in the present invention, as a countermeasure, a circuit as shown in FIG. This delay error is eliminated.

 Hereinafter, this method will be described with reference to FIG.

FIG. 7 shows a timing chart of the switching timing control according to the present invention. The switching timing signal K is shifted by a shift register like SRQ1 to SRQn in the figure. Based on the delay data of each sample and hold circuit and switched capacitor circuit, the multiplexer address control circuit 11
Generates an address that selects A1 to A4 in the figure, and then the multiplexer 12 to which this address is input outputs switching timing signals A1 to A4. Based on the timing of the switching timing signals A1 to A4, the control circuit 5
Are the write signals φ _{W1 to} φ _W4 and the read signals φ _{R1 to} φ _R4
Switch. Then, the sample data when the switching timing signal K is generated is delayed by OA to OD indicated by solid lines in FIG.

As described above, in the embodiment shown in FIGS. 4 and 5, the delay amount error at the time of switching the delay amount can be eliminated in the ultrasonic wave receiving and phasing circuit using the sample hold or the switched capacitor. A good ultrasonic image with less noise can be obtained. In particular, the present invention is particularly effective in a dynamic focus type ultrasonic imaging apparatus that performs delay amount switching many times.

〔The invention's effect〕

According to the present invention, since the output signals of the respective delay means by sampling are settled and then added in phase, the focus can be switched without switching noise.

[Brief description of the drawings]

FIG. 1 is a diagram showing a focus switching system according to the present invention, FIG. 2 is a diagram showing a conventional focus switching system, and FIG. 3 is an embodiment of the present invention. 4 and 5 are block diagrams of another embodiment of the present invention, FIG. 6 is a time chart of the conventional example, and FIG. 7 is a time chart of the embodiment of FIGS. 1 to n ... sequence element, D ₁ to D _n ... sample delay means, 2
-1 adder, 3-1 resampling means, 4-1 control circuit, 5-1 memory.

Claims (1)

(57) [Claims] 1. An ultrasonic wave receiving apparatus comprising: a plurality of elements constituting a receiving aperture for receiving an ultrasonic wave; and generating a phasing signal for obtaining a tomographic image based on each of the received signals from the plurality of elements. In the wave phasing circuit, sampling delay means for a received signal of each element constituting the reception aperture, control means for generating a sampling signal for the delay means, delay data for the received signal of each element and reception focus Storage means for storing the switching time of the point, and the control means reads the delay data and the switching time of the reception focus point from the storage means, and receives the reception signal of the element at the end of the reception aperture. The sampling interval is set to be equal, and at the switching time of the reception focus point, the sampling for the element at the center of the reception aperture is performed. Septum, and ultrasonic receiving phasing circuit, characterized in that for controlling to set larger than the sampling interval for received signals of the respective elements of both end portions of the receiving bore.