JPH02168183A - A/d sampling method and apparatus - Google Patents

Abstract

PURPOSE:To reduce sampling loss by mounting a delay device for delaying a digital signal, a memory device outputting a signal on every other sample holding circuit and a comparator comparing digital signals to output a signal having a larger value among them. CONSTITUTION:The analogue input signal 1 being the single pulse of a receiving video signal is inputted to a sample holding device 5 to output an analogue signal 6. This signal 6 is converted to a digital signal having frequency twice sampling frequency by an A/D converter 7 and a delay device 9 to which the digital signal 8 corresponding to the signal 6 delays the signal by one sampling point to store the same in a memory device 10. This delayed signal 8 and the digital signal 8 from the converter 7 are compared on every other one by a comparator 11 and one having a larger value is outputted from the comparator 11. As mentioned above, in the case of the same signal velocity, data quantity becomes almost equal to that obtained when A/D conversion is performed at twice sampling frequency and, therefore, sampling loss can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sampling method and apparatus for AID conversion of a single pulse of a radar received signal and signal processing.

[Conventional technology]

FIG. 2 is a configuration block diagram of a signal processing device using a conventional A/D sampling method, in which (1) is an analog input signal, (2) is a sampling pulse generator, and (3) is a sampling frequency input device i41. is Sanbri Jig Pulse,
(5) is sample hold l, (61 is sample hold l)
A held analog signal, (7) is an A/D converter,
(81 is a digital signal, (12) is a signal processor.

The conventional device is configured as described above, and receives analog input by timing the sampling pulse (4) generated by the sampling pulse generator (2) using the value set by the sampling frequency input device (3). The signal (1) is converted into a sampled and held analog signal (6) in a sample and hold gain (5), and the sampled and held analog signal (6) is converted into a digital signal by an A/D converter (7). The digital signal (8) is converted into a signal (8) and transmitted to a signal processor (12).

Next, the operation will be explained using figures.

The radar received video (analog input signal (11), which is a single pulse of No. 3, as shown in Fig. 3(a),
With the rise of the sampling pulse (4) generated by the sampling pulse generator (2) using the value set by the sampling frequency input device (3) such as l, the analog input signal (1) becomes (6 ), and the sampled and held analog signal (6) is converted into a digital signal ( 8).

[Problem to be solved by the invention]

The sampling pulse (4) generated by the radar received video (No. 3 single pulse analog input signal (2 at 11, for example, sampling pulse generation! +2) as shown in Fig. 3(a) is shown in Fig. 3(b). With sampling, there is no loss in the sampled and held analog signal (6), but when the analog input signal +11, which is a single pulse of the radar received video signal as shown in Fig. ) The sampling pulse (4) generated in Fig. 4(b) is shown in Fig. 4(b).
As shown in Figure 4(a), when the sampled and held analog signal (6) approaches 0, a resampling loss occurs, and when sampling at the frequency e of the pulse width, a sampling loss occurs due to the relationship between the phase and the signal. There was a problem.

This invention was made to solve the above-mentioned problems, and aims to increase the sampling frequency and reduce sampling loss without changing the signal processing speed.

[Means to solve the problem]

The A/D sampling device according to the present invention compares a delay type that delays a digital signal, a recorder that outputs the digital signal every other sample/hold, and the digital signal, and outputs the one with a larger value. It is equipped with a comparator to

[For production]

In this invention, the analog input signal, which is a single pulse of the received video signal, is A/D converted at a sampling frequency twice the sampling frequency for signal processing. The larger value of two sampling points is selected as a sample value, and the sampling loss is reduced without changing the equalization processing speed after A/D conversion of the sample value.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 8, (11, +21. (31, (41, +51.)
+6L +71°+81. (12) is the same as the conventional device described above.

(9) is a delay device, and QOl is a memory! , (111 is a comparator.

The A/D sampling device configured as described above receives an analog input signal +13 which is a single pulse of the received video signal.
The sampled and held analog signal (6) is A/D converted by the A/D converter (7) at a sampling frequency twice as high as the sampling frequency for signal processing. analog signal (
A digital signal (8) corresponding to No. 6) is output, the digital signal (8) is delayed by a sampling point l−1 in a delay device (9), and the delayed digital signal (No. 5 ( 8) and the above digital signal (8)
) is stored and output at every other sampling point, and the comparator (11) selects the value of the stored and delayed digital signal (8) and the stored digital signal (8). The larger one will be output.

FIG. 5 shows the above A/D sampling method.

This will be explained using FIG. In the figure (11, +41. (8
1 is the same as above.

As shown in FIG. 5(a), the sampled and held analog signal (6) is converted into an A/D converter (7).
The converted tcodigital signals (8) are A, B, and C.

In the case of columns D, E, and F, the digital signal (8) is delayed by one sampling point in the delay device (9).
The column becomes as shown in FIG. 5(b), and the memory device (101) outputs the values of Pi, P3, and P5 in FIGS. 5(a) and (b), and the comparison 1 (11) Figures (a), (b)
) of the digital signals (8), the one with the larger value should be output. For example, when the analog input signal (1) in Figure 6(a) is output, the larger value of the sampling pulses (4) in a set as shown in Figure 6(b) is The set of digital signals (8) is obtained, and the A/D signal for the above analog input signal (1) is output as the processing result.
The conversion result is a signal sequence as shown in Figure 6(c) as a whole, and compared to the conventional A/D sampling method and its device, when the pta processing speed is the same, the amount of information is A
/D conversion is almost the same as when the sampling frequency is doubled.

Sampling loss can be small.

In the above embodiment, the memory device 01 is used to output the digital signal (8) at every other sampling point, but a sample-and-hold device may be used instead of the memory device 01.

〔Effect of the invention〕

As described above, the present invention includes a delay device that delays a digital signal by one sampling point, a memory device that stores the digital signal and outputs it every other sampling point, and a delay device that delays the digital signal by one sampling point. Compared to the conventional A/D sampling method and device, by using the A/D sampling method and device for selecting one digital signal from two sampling points by providing a comparator that outputs When the signal processing speed is the same, the amount of information is almost the same as when A/D conversion is performed at twice the sampling frequency, so the sampling loss can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.
Figure 2 is a block diagram of the configuration of an apparatus using the conventional A/D sampling method, Figures 3 and 4 are diagrams showing the conventional sampling method, and Figures 5 and 6 are the sampling method of the present invention. FIG. In the figure, (2) is a sampling pulse generator. (3) is between the sampling frequency inputs, (5) is the sampling/holding device, (7) is the A/D converter, (9) is the delay device, (lot is the tQ device, (II) is the comparison W, (
12) is a signal processor. In Figure 2, the same reference numerals represent the same or corresponding parts.

Claims (2)

[Claims] (1) In A/D conversion of an analog input signal that is a single pulse of a radar received video signal to be processed, A/D conversion is performed at a sampling frequency twice that of the sampling frequency used to process the analog input signal. The A/D converted digital signal is converted into a digital signal, and the one with the larger value is selected from the two digital signals adjacent on the time axis, and the selected digital signal is converted into a signal processor as a result of the A/D conversion. A/D sampling method to transmit to. (2) In order to realize the above A/D sampling method, a sampling frequency input device that sets the sampling frequency, and a sampling pulse generator that generates sampling pulses using the value set by the sampling frequency input device. , a sample and hold device that samples and holds the analog input signal according to the timing of the sampling pulse, an A/D converter that converts the sampled and held analog signal from analog to digital;
comparing the digital signal with a delay device that delays the digital signal converted by the /D converter and a memory device that outputs the digital signal at every other sampling point;
An A/D sampling device comprising: a comparator that outputs a larger value; and a signal processor that processes the digital signal.