JP2644682B2 - Correlation processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlation processing circuit that can be used when performing correlation processing in a digital circuit.

[0002]

2. Description of the Related Art Conventionally, as a correlation processing circuit, there is a configuration in which a plurality of analog signals are respectively converted into digital signals by an A / D converter, and then a correlation processing operation between the digital signals is performed.

[0003]

When an analog signal, which is an input signal, is converted into a digital signal by an A / D converter to perform a correlation process, the frequency is limited by the frequency of the sampling clock of the A / D converter. Could only be processed. That is, as a drawback in circuit digitization, the upper limit frequency is limited by the frequency of the sampling clock of the A / D converter, and generally, 1/2 of the sampling clock frequency is the upper limit frequency.

The inventor of the present invention pays attention to the timing of sampling and holding each analog signal as an input signal when a sample / hold amplifier is provided in a stage preceding the A / D converter, and synchronizes the timing of the sample / hold with the A / D converter. It has been found that the correlation processing operation can be performed without being limited by the upper limit frequency by the sampling clock of the / D converter.

Accordingly, an object of the present invention is to provide a correlation processing circuit which can execute a correlation processing operation without being limited by an upper limit frequency by a sampling clock of an A / D converter and can be used in a wide frequency range. .

[0006]

In order to achieve the above object, a correlation processing circuit according to the present invention has a plurality of sample and hold sections each receiving an analog signal, and the sample and hold timing of each sample and hold section is adjusted. A synchronized sample-and-hold amplifier, an A / D converter that converts the output of each sample-and-hold unit of the sample-and-hold amplifier into a digital signal, and a correlation processing calculator that performs a correlation calculation of the output of each A / D converter , Each A / D
The correlation processing operation is performed without being limited by the upper limit frequency by the sampling clock of the converter.

[0007]

In the correlation processing circuit according to the present invention, since the sample and hold timings of a plurality of sample and hold sections each receiving an analog signal are synchronized, A / D conversion is performed.
Correlation processing of a signal having a frequency of twice or more the frequency of the sampling clock of the converter can also be performed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a correlation processing circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a correlation processing circuit. In this figure, 1 is a sample and hold amplifier, 2 and 3 are A / D converters, respectively, and 4 is a correlation processing calculator. As shown in FIG. 2, the sample and hold amplifier 1 includes a sample and hold section 1a to which an analog signal X ₁ (t) as a _first input signal is input, and an analog signal X ₂ (t) as a _second input signal. And a hold command unit 1c that outputs a common hold command to the sample hold units 1a and 1b at the same timing at a constant period. As shown in FIG. 3, the correlation processor 4 multiplies the output signals of the A / D converters 2 and 3 for converting the analog signal X ₁ (t) and the analog signal X ₂ (t) into digital signals, respectively. Vessel 4a,
And an integrator 4b for integrating the output of the multiplier 4a.

In the configuration of the above embodiment, when a plurality of input analog signals X ₁ (t) and X ₂ (t) are converted into digital signals, the analog signals X ₁ (t) are The signal level of the signal X ₂ (t) is fixed periodically. At this time, the sample and hold timing of the analog signal X ₁ (t) and the analog signal X ₂ (t) is synchronized in the sample and hold amplifier 1. That is,
A common hold command is output to each of the sample and hold units 1a and 1b at the same timing at a constant period. Then, A /
The sample and hold units 1a,
1b is converted to a digital signal, and the correlation processing
To perform a correlation processing operation. That is, A
After the outputs of the / D converters 2 and 3 are multiplied by each other, they are integrated by the integrator 4b to output an output signal.

In such a correlation processing operation, an average value of the multiplied values is obtained. Therefore, the upper limit frequency of the correlation processing operation is limited by the speed (frequency of the sampling clock of the A / D converters 2 and 3). ) Is considered to be a difference between the sample and hold timings of the plurality of sample and hold units 1a and 1b.

The procedure of consideration will be described below with reference to FIGS.

FIG. 4 shows the timing of the sample and hold amplifier 1, and the sample and hold sections 1a and 1b
When a hold command is issued at the same timing, the analog signals X ₁ (t) and X ₂ (t), which are input signals, are fixed (held) after a time delay (aperture) actually occurs. As described above, when a plurality of sample-and-hold units are used in parallel, irregularities in the time delay (such as aperture jitter) cause a difference Δt (where Δt
= | T ₁ −t ₂ |), but the circuit operates normally only when this is smaller than the quantization error. In this case, the upper limit frequency is the number of quantization bits and the timing difference Δt between the sample and hold units 1a and 1b. It is considered to be determined by

FIG. 5 shows an error of a sample value due to a timing difference Δt between the sample hold units 1a and 1b. Consider the upper limit frequency based on this.

In this case, the error of the sample value due to the timing difference = | Δtdy / d
t |.

If y = Asinωt (A: amplitude, ω: angular frequency), then | dy / dt | = | Aωcosωt |, and the maximum value is | Aωcosωt | _max = Aω = 2πfA (f: frequency). _{Therefore, | Δtdy / dt | max =} 2πfΔtA ... (1) then the quantization error _{(y max -y min) / 2} b: When (b number of quantization _{bits), y max = A, y} min = - Since A, (y _max −y _min ) / 2 ^b = 2A / 2 ^b (2) Thus, (1), for the error of the sample value of the timing difference from (2) is equal to or less than the quantization error, 2πfΔtA ≦ 2A / 2 ^b That is, the maximum frequency at which ^{f ≦ 1 / (2 b πΔt} ) It becomes the upper limit frequency. Timing difference Δ
By making t sufficiently small, the upper limit frequency can be made higher than the frequency of the sampling clock of the A / D converters 2 and 3.

The inventor of the present invention has made A / D
Set the sampling clock frequency of converters 2 and 3 to 10
As a result of changing from 5 MHz to 5 MHz, even if the sampling clock frequency is 5 MHz, 10 MHz
It was confirmed that almost the same characteristics as in the case of z were exhibited.

Although the embodiment of the present invention has been described above, it is obvious to those skilled in the art that the present invention is not limited to this and various modifications and changes can be made within the scope of the claims. Would.

[0019]

As described above, according to the correlation processing circuit of the present invention, when performing the correlation processing of a plurality of signals by the digital circuit, the A / D is synchronized by synchronizing the sample and hold timing of each input signal. Correlation processing can be performed regardless of the frequency of the sampling clock of the converter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a correlation processing circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a sample hold amplifier according to the embodiment.

FIG. 3 is a block diagram illustrating a configuration of a correlation processing calculator according to the embodiment.

FIG. 4 is a diagram illustrating the operation of a sample-hold amplifier.

FIG. 5 is an explanatory diagram showing an error of a sample value due to a timing difference of a sample hold amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sample hold amplifier 1a, 1b Sample hold part 1c Hold command part 2, 3 A / D converter 4 Correlation processing arithmetic unit 4a Multiplier 4b Integrator

Claims (1)

(57) [Claims] 1. A sample-and-hold amplifier having a plurality of sample-and-hold units for receiving analog signals and synchronizing the sample-and-hold timing of each of the sample-and-hold units, and a digital output of each of the sample-and-hold units of the sample-and-hold amplifier. An A / D converter for converting the signal into a signal; and a correlation processing unit for performing a correlation processing operation on the output of each A / D converter, wherein the correlation is performed without being limited by an upper limit frequency by a sampling clock of each A / D converter. A correlation processing circuit for performing a processing operation.