JP3412552B2 - Waveform storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform storage device that stores a waveform of an input signal and continuously reproduces it.

[0002]

2. Description of the Related Art Conventionally, for example, when a waveform of a radar or the like is processed, the waveform is stored and reproduced to obtain a desired waveform. As an example of a device that performs this kind of waveform processing, YHP "1990 General Catalog"
There is a waveform storage device described in the above, and FIG. 9 shows a schematic block diagram of the device configuration. As shown in the figure, this waveform storage device includes an AD converter 101, a memory 102, a DA converter 103, and a control circuit 10 for controlling these memories and the like.
It is composed of four.

In the conventional waveform storage device shown in FIG. 9, an analog converter input signal is converted into digital data by an AD converter 101 under the control of a control circuit 104, and the digital input data is stored in a memory 102. Further, when reproducing the waveform, the digital data read from the memory 102 is DA-controlled by the control of the control circuit 104.
The converter 103 converts the analog signal. As a result, the same waveform as the original input signal is reproduced.

[0004]

However, in the conventional waveform storage device having the above configuration, when the signals stored in the memory 102 are continuously reproduced, a phase difference occurs between the waveforms and the connection portion between the waveforms. . For example, the time width (pulse width) of the waveform stored in the memory is T, and the frequency of the input signal is f.
Then, if there is a relationship of T = n × (1 / f) (where n is an integer), the phase difference at the connecting portion of the waveform is 0.

However, when the frequency f of the input signal cannot be predicted or when the memory time T cannot be determined, T ≠ n
Since it is x (1 / f), the phase difference at the connecting portion cannot be zero. When the phase difference is large, there is a problem that the spectrum component of the frequency f becomes small and the energy loss becomes large even if the signal waveform stored in the memory is reproduced.

FIG. 7 shows an example of a spectrum waveform when a signal of frequency fc is connected with a phase difference of 180 degrees at the connection portion. As shown in the figure, since the waveforms are connected with a phase difference of 180 degrees, the original frequency component fc
It can be seen that the spectral component in the vicinity becomes smaller and the energy loss becomes larger.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce phase discontinuity in a waveform connecting portion even when an input signal stored in a memory is continuously reproduced. A waveform storage device is provided.

[0008]

In order to achieve the above object, the present invention provides a waveform storage device for continuously reproducing the waveform of an input signal, a storage means for storing the input signal, and the stored input. based the phase difference calculating means, the phase difference to determine the phase difference between the leading and trailing edges of the signal Goha type,
Phase shift amount determining means for determining the phase shift amount corresponding to the number of times of reproduction, phase shift processing means for performing the phase shift processing on the stored input signal based on the phase shift amount, and the signal after the phase shift processing Provided is a waveform storage device having means for continuously reproducing a waveform in the processing order.

The waveform storage device according to the present invention further includes means for separating the input signal into a first signal and a second signal having two different phases, and the phase difference calculation means includes the first and second signals. Then, the phase difference is obtained based on the second signal.

Preferably, the phase difference calculating means detects the phase of the input signal at the storage start timing and the storage end timing for sending the input signal to the storage means.

Preferably, the storage means is provided corresponding to the first and second signals, and the phase difference calculation means is the first and second storage means stored in these storage means.
The phase difference is obtained for each of the signals.

Preferably, the phase shift amount determining means is
The phase shift amount is provided corresponding to the first and second signals, and is determined by the phase difference obtained for the first and second signals.

Further, preferably, the phase shift amount determining means changes the phase shift amount according to the phase difference detection accuracy of the phase difference calculating means.

Preferably, the phase shift amount determining means determines the phase shift amount as an analog amount, and the phase shift processing means executes the phase shift process based on the analog phase shift amount. . Further, preferably, the means for determining the amount of phase shift is
The phase shift amount is determined as a digital amount, and the phase shift processing means executes the phase shift process based on the digital phase shift amount.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Embodiment 1. First, the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the waveform storage device according to the present embodiment. The device shown in the figure is a phase detection circuit 11 for detecting the phase of an input signal, an AD converter 1, a memory 2 for storing the input signal converted into digital data by the AD converter 1, and an output of the memory 2. A DA converter 3 for converting digital data into an analog signal, a phase shifter 12 for changing the phase of an output signal of the DA converter 3, these phase detection circuits 11, an AD converter 1, a memory 2, a DA converter 3, and a shifter. A control circuit 4 for controlling the phase shifter 12 is provided.

The operation of the waveform storage device according to the present embodiment shown in FIG. 1 will be described below. Input signal is AD converter 1
To the phase detection circuit 11, the AD converter 1 converts the analog input signal into digital data, and stores the converted data in the memory 2. Further, the phase detection circuit 11 detects the phase of the input signal and sends the result to the control circuit 4.

That is, in the waveform storage device according to the present embodiment, the clock signal corresponding to the sampling period generated by the control circuit 4 is output to the AD converter 1.
The AD converter 1 performs analog / digital conversion based on this signal. The output data from the AD converter 1 is output in synchronization with this clock signal, and the memory 2 also stores the output data from the AD converter 1 in synchronization with this clock. At this time, the memory 2 outputs the address information of the storage location to the control circuit 4.

On the other hand, when reproducing data, the control circuit 4 outputs to the memory 2 the address of the reproduced data and the clock signal for reproduction. Therefore, the data stored therein is read from the memory 2 in synchronization with this clock, and the read data is output to the DA converter 3. Then, the DA converter 3 takes in the data from the memory 2 in synchronization with the clock and converts the data into analog data. The analog data thus converted is finally sent to the phase shifter 12.

The phase detection circuit 11 detects the phase of the input signal at the start timing and the stop timing instructed by the control circuit 4, that is, the storage start timing and the storage end timing sent to the memory 2, and the value thereof is controlled by the control circuit. Output to 4.

The control circuit 4 is thus provided with the phase detection circuit 1
Based on the phase of the input signal at the start timing and the stop timing detected by No. 1, the first phase and the last phase of the signal stored in the memory 2 (that is, the leading edge portion and the trailing edge of one stored waveform). Phase), the phase difference Φ of the waveform is calculated.

Then, the control circuit 4 calculates the control amount of the phase shifter 12 (phase shifter control amount) from the phase of the input signal at the above start timing and stop timing,
The control amount is sent to the phase shifter 12 as a phase control signal in synchronization with the reproduction timing.

Specifically, if the phase difference Φ = 0 for the input signal, the control circuit 4 does not perform any phase shift operation (phase shift processing) on the signal. However, when Φ ≠ 0, when the signal stored in the memory 2 is continuously reproduced, as shown in FIG. 8, the control circuit 4 causes the phase shift amount in the phase shifter 12 to be 0, The second time is controlled to be Φ, ..., The nth time is controlled to be (n−1) Φ.

The phase shift processing here is based on the waveform obtained first, and the phase of the basic waveform itself is changed according to the number of times of reproduction shown in FIG. 8 (at first, the phase shift amount is as described above). 0), thereby finally setting the phase difference of the connection portion between the waveforms to zero.

As described above, according to the present embodiment, the phase of the input signal is detected, the first phase and the last phase of the signal are compared, and the signal to be reproduced is reproduced according to the number of times of reproduction. By applying the phase shift process to the, it is possible to eliminate the phase difference in the connection portion of the regenerated waveforms, it is possible to reduce the energy loss in the original frequency component of the signal,
There is an effect.

In the above-described first embodiment, the phase difference of the waveform connection portion is set to 0, but this value depends on the detection accuracy of the phase detection circuit 11 that detects the phase of the input signal. However, it is basically impossible to match the phase below this detection accuracy.

Therefore, in order to simplify the circuit, the phase difference of the waveform connecting portion should be made as small as possible according to the detection accuracy of the phase detection circuit 11 used in the apparatus (for example, phase difference <45 degrees). , The phase shifter 12 may be controlled.
For example, the detection accuracy of the phase detection circuit is 5.625 degrees and 45 degrees.
In terms of degrees, it is necessary for the former to perform phase detection with a fineness of 8 times, and the circuit scale also becomes large (in this example, 3 bits increase in terms of bits).

Embodiment 2. The second embodiment of the present invention will be described below. In the first embodiment shown in FIG. 1, the input signal is directly input to the phase detection circuit 11, but the waveform storage device according to the present embodiment converts the input signal into two signals having different phases. After dividing, the phase is detected.

FIG. 2 is a block diagram showing the configuration of the waveform storage device according to the present embodiment. In the figure,
The same components as those of the waveform storage device according to the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here.

The waveform storage device according to the present embodiment is provided with an IQ converter 13 at its input stage, and by using it, input signals are I (in-phase) signals and Q (quadrat) signals.
ure-phase) signal. Then, the phase detection circuit 11 arranged at the subsequent stage of the IQ converter 13
The phase is detected from the I signal and Q signal output from the Q converter 13.

Since the method of detecting the phase from these I signal and Q signal is a known technique, its explanation is omitted here. Further, the processing after the phase detection in the phase detection circuit 11 is the same as that of the device according to the first embodiment.

As described above, in the waveform storage device according to the present embodiment, the input signal is separated into the I signal and the Q signal, and the phases are detected and compared based on these separated signals. The processing can be performed smoothly, and the processing for eliminating the phase difference in the connection portion between the reproduced waveforms based on the smooth processing can be efficiently executed.

Embodiment 3. The third embodiment of the present invention will be described below. FIG. 3 is a block diagram showing the configuration of the waveform storage device according to the present embodiment. The device shown in the figure is configured by using an IQ converter 13 and an IQ combiner 14, and the output (I signal, Q signal) of the IQ converter 13 is input to the phase detection circuit 11 and the I signal, It reaches the IQ combiner 14 via an AD converter, a memory, and a DA converter provided corresponding to each Q signal.

That is, the I signal obtained by separating the input signal by the IQ converter 13 is input to the AD converter 1a,
Therefore, the analog signal is converted into digital data, and the converted data is stored in the memory 2a. The data output from the memory 2a is DA
After being converted into an analog signal again by the converter 3a, IQ
It is sent to the synthesizer 14. Similarly, the Q signal is also input to the IQ combiner 14 via the AD converter 1b, the memory 2b, and the DA converter 3b.

On the other hand, the phase detection circuit 11 also includes the IQ converter 1.
The I signal and the Q signal which are the outputs of 3 are input and the phase is detected from these signals. The control circuit 4 is provided with an AD provided for each system of the I signal and the Q signal having different phases.
It controls the converter, memory and DA converter.

More specifically, the control circuit 4 includes a memory 2
From the first phase and the last phase of the I signal stored in a (the leading edge portion and the trailing edge portion of one waveform stored in the memory), the phase difference between the waveforms is obtained, and similarly stored in the memory 2b. Find the first and last phases of the stored Q signal. Further, each DA converter takes in the data output from each memory in synchronization with the clock given by the control circuit 4, and converts the data into analog data.
Then, the IQ synthesizer 14 re-synthesizes the analog data for each system and sends it to the phase shifter 12.

On the other hand, the control circuit 4 obtains the phase difference Φ of the waveforms from the first phase and the last phase of the system-specific signals stored in the memories 2a and 2b, and controls the phase shifter 12 ( Phase shifter control amount) is calculated. Then, the control circuit 4
The calculated control amount is sent to the phase shifter 12 as a phase control signal in synchronization with the reproduction timing. Also here, the phase is detected from the I signal and the Q signal by a known method, and the phase shift processing is the same as the processing in the first embodiment.

As described above, according to the present embodiment, the AD converter, the memory, and the DA converter are provided corresponding to the I signal and the Q signal obtained by separating the input signal, and the I signal and the Q signal are individually provided. Since the phase is detected in, it is not necessary to make the frequency used for sampling the signal more than twice the signal band, phase information of the input signal can be easily obtained, and the reproduced waveform can be efficiently reproduced based on the phase information. It is possible to reduce the phase difference between the mutually connected portions.

Fourth Embodiment Hereinafter, the fourth embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of the waveform storage device according to the present embodiment. In the figure, the same components as those of the waveform storage device according to the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here.

The waveform storage device shown in FIG. 4 is shown in FIG.
In the device according to the first embodiment, the phase shifter 12 is installed before the DA converter 3. That is, the apparatus according to the present embodiment performs DA conversion after changing the phase of digital data.

The data analog-to-digital converted by the AD converter 1 of the device according to the present embodiment is output in synchronization with the clock signal from the control circuit 4 as in the first embodiment, and the memory 2 is also output. The output data from the AD converter 1 is stored in synchronization with this clock.

At the time of reproducing the data, the address of the reproduced data and the clock signal for reproduction are output from the control circuit 4 to the memory 2, and the data is read from the memory 2 in synchronization with this clock. In the device according to the present embodiment, the data thus read out is sent to the phase shifter 12.

The phase detection circuit 11 detects the phase of the input signal at the start timing and stop timing instructed by the control circuit 4, and the value thereof is used as the control circuit 4.
Output to. Based on the phases of the input signals at the start timing and the stop timing, the control circuit 4 determines the first phase and the last phase of the signal stored in the memory 2 (that is, the leading edge portion and the trailing edge portion of one stored waveform). Phase), the phase difference Φ of the waveform is calculated.

Further, the control circuit 4 calculates the control amount of the phase shifter 12 (phase shifter control amount) from the phase of the input signal at the above start timing and stop timing, and uses the control amount as the reproduction timing. It is synchronized and sent to the phase shifter 12 as a phase control signal. In this embodiment,
The phase shifter 12 changes the phase of the input signal as it is as digital data. Therefore, the phase shifter 12 executes, for example, an operation of adding or subtracting a digital value corresponding to the phase change amount (the above-mentioned phase shifter control amount) to the digital value of the signal.

The signal thus phase-shifted is output from the phase shifter 12 to the DA converter 3. At this time, the DA converter 3 takes in the data in synchronization with the above-mentioned clock and converts the data into analog data. The converted analog data becomes the final output from this device.

As described above, according to the present embodiment, the input signal is converted into the digital data format, and the process of adding or subtracting the digital value corresponding to the phase change is performed to change the phase. By converting to an analog signal after that, the phase shift processing can be performed without being restricted by the frequency characteristic of the signal, and as a result, the phase accuracy can be improved.

In other words, by controlling the phase shift in the digital data format, the frequency to be used, the frequency bandwidth and the phase accuracy are not affected by the limitation or the frequency characteristic as compared with the phase shifter for the analog signal. The phase can be changed more accurately by increasing the number of bits of the digital signal to be handled.

Embodiment 5. Hereinafter, a fifth embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration of a waveform storage device according to the fifth embodiment. The device shown in the figure is configured by using the IQ converter 13 and the IQ combiner 14 as in the device according to the third embodiment shown in FIG. It is different from the device according to the third embodiment in that it is installed in the previous stage.

That is, in the device according to the present embodiment,
The I signal and the Q signal which are the outputs of the IQ converter 13 are input to the phase detection circuit 11, and the AD converter, the memory, the DA converter, and the phase shifter are provided corresponding to the I signal and the Q signal, respectively. To reach the IQ combiner 14.

More specifically, the I signal is the AD converter 1
It is input to a, where it is converted from an analog signal to digital data and then stored in the memory 2a.
The data output from the memory 2a is the DA converter 3
The signal is converted into an analog signal again at a, and a predetermined phase shift process is performed at the phase shifter 12a. In addition, the Q signal passes through the AD converter 1b, the memory 2b, and the DA converter 3b, and the phase shifter 1
Sent to 2b. Then, these phase shifters 12a and 12b
The signal that has been subjected to the phase shift processing in (1) is input to the IQ combiner 14.

The control circuit 4 of the device according to the present embodiment is
Similar to the device according to the third embodiment, the phase difference between the waveforms is obtained from the first phase and the last phase of the I signal stored in the memory 2a, and the first phase of the Q signal stored in the memory 2b is calculated. Find the phase and the last phase. Then, each of the DA converters 3a and 3b takes in the output data from each memory in synchronization with the clock given by the control circuit 4, and converts the data into analog data.

That is, the control circuit 4 includes the memories 2a and 2a.
From the first phase and the last phase of the system-specific signals stored in b, the phase difference Φ of the waveform is obtained, and the control amount of the phase shifter 12 (phase shifter control amount) is calculated. And the control circuit 4
Synchronizes the calculated control amount with the reproduction timing, and outputs the phase control signals as phase control signals.
Send to b. Note that the phase detection from the I signal and the Q signal is performed by a known method, and the phase shift processing here is also the same as the processing in the first embodiment.

Then, the IQ combiner 14 re-combines the analog data from the phase shifters 12a and 12b, which are phase-shift-controlled for each system, and outputs it as a final output.

As described above, according to the present embodiment, the AD converter, the memory, the DA converter, and the phase shifter are provided corresponding to the I signal and the Q signal obtained by separating the input signal. , By individually detecting the phase of each of the Q signals and controlling the phase shift, for example, the sampling frequency of the signal can be suppressed to a low level, the phase information of the input signal can be easily obtained, and the phase difference of the connection portion between the reproduced waveforms can be obtained. Can be made smaller.

Sixth Embodiment The sixth embodiment of the present invention will be described below. FIG. 6 is a block diagram showing the configuration of the waveform storage device according to the present embodiment. The device shown in the figure has a configuration in which the positions of the DA converters 3a and 3b and the phase shifters 12a and 12b are replaced with each other in the device according to the fifth embodiment shown in FIG.

In the apparatus according to the present embodiment, the I signal and the Q signal which are the outputs of the IQ converter 13 are input to the phase detection circuit 11 and the I signal as in the apparatus according to the fifth embodiment. , The Q signal is reached through the AD converter, the memory, the phase shifter, and the DA converter provided corresponding to the Q signal and the Q signal, respectively.

That is, the I signal is input to the AD converter 1a, converted from an analog signal to digital data, and then stored in the memory 2a. This memory 2a
The output data from is sent to the phase shifter 12a, where
A phase shift process described later is performed. Then, the digital data after the phase shift control is converted into an analog signal again by the DA converter 3a.

On the other hand, also for the Q signal, the AD converter 1
b, the memory 2b, and the phase shifter 12b, the DA converter 3
sent to b. The phase shifter 12b also performs a phase shift process described later, and the DA converter 3b subsequent thereto converts the digital data into an analog signal.

The control circuit 4 obtains the phase difference between the waveforms from the first phase and the last phase of the I signal stored in the memory 2a, as in the device according to the third embodiment, and the like.
The first phase and the last phase of the Q signal stored in the memory 2b are obtained. That is, the control circuit 4 controls the memories 2a and 2b.
The phase difference Φ of the waveform is obtained from the first phase and the last phase of the system-specific signals stored in the phase shifters 12a, 12
The control amount of b (phase shifter control amount) is calculated.

The phase shifter 12a of the device according to the present embodiment,
12b changes the phase of the input data in the digital form. Therefore, the phase shifters 12a and 12b are
Similar to the fourth embodiment, for example, an operation of adding or subtracting a digital value corresponding to the phase change amount (the above-mentioned phase shifter control amount) to the digital value of the signal is executed.

Then, the control circuit 4 sends the phase shifter control amount calculated in this way to the respective phase shifters 12a and 12b as a phase control signal in synchronization with the reproduction timing. The phase detection from the I signal and the Q signal is performed by a known method, and the phase shift process here is the same as the process in the first embodiment.

Each of the DA converters 3a and 3b includes a phase shifter 1
The output data from 2a and 12b is taken in in synchronization with the clock given by the control circuit 4, and the data is converted into analog data. Then, the IQ synthesizer 14
Performs phase shift control for each system and re-synthesizes the data converted into analog format, and uses it as the final output.

As described above, according to the present embodiment, the AD converter, the memory, the phase shifter, and the DA converter are provided corresponding to the I signal and the Q signal obtained by separating the input signal. , By individually detecting the phase of the Q signal and controlling the phase shift in digital form, phase shift processing can be performed without being limited by the frequency characteristics of the signal, and as a result, the phase accuracy can be improved. You can

[0063]

As described above, according to the present invention,
In the waveform storage device for reproducing the waveform of the input signal continuously, the phase difference calculation for obtaining the storage means for storing the input signal, the phase difference between the leading and trailing edges of the input signal Goha type described above stores Means, a phase shift amount determining means for determining a phase shift amount corresponding to the number of times of reproduction based on the phase difference, and a phase shift process for subjecting the stored input signal to a phase shift process based on the phase shift amount. By providing the processing means and the means for continuously reproducing the signal waveform after the phase shift processing in the processing order, it is possible to eliminate the phase difference in the connection portion between the reproduced waveforms, and the original frequency component of the signal. The energy loss in can be reduced.

The waveform storage device according to the present invention further comprises means for separating the input signal into a first signal and a second signal having two different phases. Since the phase difference is obtained based on the second signal and the second signal, the smooth phase detection can be performed, and the process of eliminating the phase difference in the connection portion between the reproduced waveforms can be efficiently executed.

Since the phase difference calculating means detects the phase of the input signal at the storage start timing and the storage end timing of sending the input signal to the storage means, the phase difference of the input signal can be easily calculated.

Further, the storage means is provided corresponding to the first and second signals, and the phase difference calculating means is provided for each of the first and second signals stored in these storage means. Since the phase difference is obtained, the phase information of the input signal can be easily obtained, and on the basis of this, the phase difference of the connection portion between the reproduced waveforms can be efficiently reduced.

Further, the phase shift amount determining means is provided corresponding to the first and second signals, and the phase shift amount is determined from the phase difference obtained for the first and second signals. As a result, the phase information of the input signal can be easily obtained, and the phase difference between the connection portions of the reproduced waveforms can be reduced.

Further, the phase shift amount determining means changes the phase shift amount according to the phase difference detection accuracy of the phase difference calculating means, whereby the circuit scale can be reduced.

Further, the phase shift amount determining means determines the phase shift amount as an analog amount, and the phase shift processing means executes the phase shift process based on the analog phase shift amount.
Phase shift processing becomes easy.

Further, the phase shift amount determining means determines the phase shift amount as a digital amount, and the phase shift processing means executes the phase shift process based on the digital phase shift amount. The phase shift processing can be performed without being restricted by the frequency characteristic of the signal, and as a result, the phase accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a waveform storage device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a waveform storage device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a waveform storage device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a waveform storage device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a waveform storage device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a waveform storage device according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing an example of a spectrum when waveforms having a phase difference of 180 degrees are connected.

FIG. 8 is a diagram showing a phase shift amount when continuously reproducing a signal stored in a memory.

FIG. 9 is a block diagram showing a configuration of a conventional waveform storage device.

[Explanation of symbols]

1 ... AD converter, 2 ... memory, 3 ... DA converter, 12 ...
Phase shifter, 4 ... Control circuit, 11 ... Phase detection circuit, 13 ... I
Q converter, 14 ... IQ combiner

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01R 13/00-13/42

Claims (8)

(57) [Claims] 1. A waveform storage device for reproducing the waveform of the input signal continuously, the phase difference between the leading and trailing edges of the input signal Goha type storage means, in which the stored for storing the input signal And a phase shift amount determining means for determining a phase shift amount corresponding to the number of times of reproduction based on the phase difference, and a phase shift amount based on the phase shift amount for the stored input signal. A waveform storage device comprising: a phase shift processing means for performing processing; and means for continuously reproducing the signal waveform after the phase shift processing in the processing order. 2. The apparatus further comprises means for separating the input signal into a first signal and a second signal having two different phases, and the phase difference calculating means includes the first and second signals.
2. The waveform storage device according to claim 1, wherein the phase difference is obtained based on the signal of. 3. The waveform storage according to claim 2, wherein the phase difference calculation means detects a phase of the input signal at a storage start timing and a storage end timing at which the input signal is sent to the storage means. apparatus. 4. The storage means is provided corresponding to the first and second signals, and the phase difference calculation means is provided for each of the first and second signals stored in these storage means. The waveform storage device according to claim 3, wherein the phase difference is obtained. 5. The phase shift amount determining means is provided corresponding to the first and second signals, and the phase shift amount is determined from the phase difference obtained for these first and second signals. The waveform storage device according to claim 4, wherein 6. The waveform storage according to claim 1, wherein the phase shift amount determining means changes the phase shift amount according to the phase difference detection accuracy of the phase difference calculating means. apparatus. 7. The phase shift amount determining means determines the phase shift amount as an analog amount, and the phase shift processing means executes the phase shift process based on the analog phase shift amount. The waveform storage device according to claim 6. 8. The phase shift amount determining means determines the phase shift amount as a digital amount, and the phase shift processing means executes the phase shift process based on the digital phase shift amount. The waveform storage device according to claim 6.