JPH01194505A - Variable speed simplified digital filter circuit - Google Patents

Abstract

PURPOSE:To cause a reproducing speed to be variable by adopting an external memory, which can arbitrarily control a data reading at the time of D/A conversion, as a reproducing medium and storing A/D converted data to the memory in the order of time series. CONSTITUTION:A variable speed simplified digital filter circuit has an address control part 6 to generate a memory reading address in order to read the A/D converting data of the external memory, first end second registers 9 and 10 to latch the data of preceding and following two sample timings to be read from the external memory, an arithmetic circuit 11, which interpolates the data of the intermediate sampling timing from the contents of the first and second registers 9 and 10, a third register 16 to latch the data for D-A conversion and a control clock generating part 1 to control the reading of the external memory and the output timing of the D/A converting data. The data of the external memory (reproducing medium) are directly accessed at random. Thus, the D/A converting and reproducing speed can be set to be variable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter, and particularly to one that converts the sampling frequency at the stage before DA conversion and makes the DA conversion speed variable.

[Prior Art] Conventionally, this type of digital filter performs digital signal processing on the sampling frequency and quantization bit number when extracting the original analog waveform from the digital signal, and then processes the original signal waveform during A-D conversion. The main processing of digital signals is to move the time axis of D-A conversion playback closer to A-D.
Match the time axis of the conversion, double or quadruple the sampling frequency of the D-A conversion, subdivide the sample interval of the A-D conversion, and interpolate the data between them based on the averageness of the difference between the previous and subsequent data. and converts the reproduction sampling frequency.

[Problems to be solved] The conventional digital filter described above
This is to bring the reproduced analog signal waveform closer to the original signal for D-A conversion in the CM transmission system.
D-A conversion was performed at the same timing as the time axis during D conversion, and processing could only be performed at a constant playback speed. That is, D-
A The data to be converted is from the serially transmitted signal,
The data readout speed was basically constant, and the data was not read as digital data until bit synchronization, frame synchronization, data clock extraction, etc. were performed.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a variable speed simple digital filter that can vary the playback speed.

[Means for solving the problem] The variable speed simple digital filter circuit of the present invention has a D-A
An external memory whose data reading speed during conversion can be arbitrarily controlled is used as a reproduction medium, and the A-D converted data is stored in the memory in chronological order.

The variable speed simple digital filter circuit has an address control section that generates a re-memory read address to read A/D conversion data from the external memory, and a two-stage circuit that latches data at two sample timings before and after read from the external memory. A register, an arithmetic circuit that interpolates data at intermediate sampling timing from the contents of this register, a register that latches data for DA conversion, and a control clock that controls external memory readout and DA conversion data output timing. It has a generating part.

In addition, the arithmetic circuit can be configured with one that outputs the average difference value,
Furthermore, the control clock generation section consists of a clock generation section with a frequency twice as high as the original signal A-D conversion sampling frequency f, a clock frequency divider for constant speed reproduction, and a clock frequency divider for slow reproduction. Can be configured.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
This is an example of a configuration for implementing the signal processing shown in the figure. First, the operating principle of the present invention will be explained below using FIG. 2.

The curve shown in Fig. 2e (L) is the A-D conversion input waveform, and the timing of the sampling frequency f.

In ~6, the quantized data values are D1~D2, respectively.
It shows that it corresponds to D (shi) is the waveform (solid line) when the A-D converted value of e (shi) is D-A converted at the sampling frequency, and the waveform shown by hatching is sampled at twice the sampling frequency. When L□', t1'
Interpolated data (average difference value: D
n+(Do+1-Do)/2) Do', D1', D2'
.

This is the waveform after I)-A conversion with D3' applied.

D(t, F) does not show the DA conversion output waveform due to 1/2 sampling and its interpolation data during double-speed playback. Even-numbered data thinning, sampling frequency f.

D<t, ), which is D to A converted at , does not show the D to A conversion output waveform due to interpolated data during 1/2 slot playback.

According to this embodiment, the average difference value is calculated as interpolated data from data before and after data read out by A-D conversion, and the waveform is improved by data reading timing 2 (@sampling).

Next, the configuration and operation of the digital filter that performs the above-mentioned signal processing will be explained below with reference to FIGS. 1 and 3.

In FIG. 1, this variable speed simple digital filter includes an address control section 6 that generates a memory read address for reading A/D conversion data from an external memory, and an address control section 6 that generates a memory read address to read A/D conversion data from an external memory, and an address control section 6 that generates a memory read address for reading A/D conversion data from an external memory. The first of two latching stages. second register 9,
10 and this first. An arithmetic circuit 11 that interpolates data at intermediate sampling timing from the contents of the second registers 9 and 10, a third register 16 that latches data for DA conversion, and external memory readout and DA conversion data. Control clock generator 1 that controls output timing
and has.

The control clock generator 1 includes a clock generator 2 that generates a frequency 2f, which is twice the sampling frequency rS, 1/2 clock frequency dividers 3 and 4, and f, /2 clock, . . . l during slow mode. Specifically, it is comprised of a memory read speed changeover switch S1 that switches to f and clock during normal operation, and a memory read double speed switch S2 that supplies a clock to a shift register 8, which will be described later, when closed.

The address control unit 6 includes a counter 7 that increments based on the clock from the switch S1, and a counter 7 that increments the counter based on the clock from the switch S1, and a switch S2.
The shift register 8 outputs the value of the counter 7 as the address An when there is no clock from the switch S2.

The arithmetic circuit 11 includes a two's complement arithmetic unit 1.2, an adder 13, a shift register 14, and an adder 15.

Next, the operation of the variable speed simple digital filter having the above configuration will be explained with reference to FIG.

The clock generator 2 generates a sampling frequency f of the original data, and a frequency TI (2f5) twice that of the clock 17 (one clock in FIG. 3). This one clock is converted into a clock of frequency f5 by the 1/2 frequency divider 3, which generates a memory read signal 20 (CE) for normal reproduction and is used as an up-count clock of the counter 7. The output of the counter 7 becomes the value of address 21<AN) and is output to the shift register 8. In the shift register 8, when the switch S2 is closed, the value of the counter 7 is doubled (shifted by 1 bit) to even address 22 (A
F> occurs and switch s2 is open, AN
The value is output as is as the memory read address. And data D from external memory. is latched into the first register 9 at timing 23 of OE (see 23.24 in FIG. 3 for the latch timing).

Next, the contents of the first register 9 are transferred to the second register 10 at the timing of the trailing edge of CB. Further, at the timing of the leading edge of the next CE, the next OE (H pulse is generated, and the next sample data D of Do, 1 is latched in the first register 9. At this time, the first register 9 is Dn+
1. The second register 0 contains the previous data D. +1 is held, and during this time, at timing 'I'2 (inversion of T), the arithmetic circuit 11 calculates the contents of the first register 9 (Do+1) and the contents of the second register 0 <Dn). is performed, and intermediate data Dn' between D and Dn+1 is generated.Here, the clock 'r' with a sampling frequency of 2f is generated.
3, the interpolated data 26 is latched into the third register 16, and when this operation is repeated continuously in time, the contents of the register are read out as shown in 27.

Note that the operation of the arithmetic circuit 11 is as follows. The A-D conversion data at the timing is set to 0, and the next sampling timing is set. , 1 as Dn+1, the average difference value of Dn and +1 is expressed by the following equation.

Difference ΔD ”D D =D, +1n n
+1 n + (Dn's complement of 2) Difference average value D'=D +ΔD,/2 n Here, Dn=OO10 (hexadecimal), Dn, 1-002
0 < hexadecimal), then in the two's complement arithmetic unit D
The two's complement (-D)=FFFO(16)n.

Next, the difference ΔD is calculated by the adder 13 as ΔDn2Dn(1+<Dn)=OO20(
16)+FFFO(,6)=0010(16).

Next, ΔDo/2 is equivalent to shifting the data one bit to the right in the shift register 14, so the output of the shift register 14 is ΔD, / 2 = OOO8 (1
6), the output 26 of the adder 15, '=OO10
(16)” 0008(16)”” 0018(16)
Then, D.

and Dn+1. In addition, in the case of Dn=Dn+1, '=D, -ri. 41, all data passing through the arithmetic circuit is processed with the clock of T3<2f,).

Next, in the case of 1/22 o- playback, the 0 operation is - 17 of Ti-
CE is controlled by a clock divided by 4 (frequency f, /2), and T
2, the control clock of T3 is operated at the timings 28 to 33 shown in FIG. 3 using a clock (frequency f) divided by 1/2 of T1.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible within the scope of the invention.

[Effects of the Invention] As explained above, the present invention is directed to data reproduction from a memory medium that stores A-D converted data in chronological order, and is superior to the conventional A-D converted PCM serial transmission method. There is no need for redundant bit processing such as necessary bit synchronization and error correction, and the reproduction circuit for D-A conversion can be configured with a digital filter circuit and a D-A converter, so the circuit is simple and easy to use. This can be achieved at low cost.

Furthermore, since the digital filter of the present invention directly and randomly accesses the data on the playback storage medium, the D-A conversion playback speed can be variably set, and the playback waveform after D-A conversion can be compressed and expanded in the time axis. It can be used for analysis such as In particular, in the case of audio signals, it can be used for double-speed search.

Furthermore, since sampling frequency conversion is performed using double-speed sampling, it is possible to cope with playback when A-D conversion data is compressed to 1/2.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram of the digital filter processing of the present invention, and FIG. 3 is a timing chart explaining the operation of the digital filter of the present invention. 1... Control L7 clock generation section 2... Clock generation section 3.4... 1/2 clock frequency divider S1... Memory read speed selection switch S2...
Memory read double speed switch 6... Address control unit 7... Counter 8... Shift register CB' (chip enable): Read clock, OE (output enable): Data S sale timing signal, D Near address A . Memory contents read data at address 9...First register 9 10...Second register 0 11...Arithmetic circuit 12...2's complement arithmetic unit 13...Adder (binary) 14 ...Shift register (1 bit shift x 2-1)
15... Adder. D = content of second register 0, D: content of first register 9 (nth 1 sampling data after Do), D: two's complement of D, Dn ΔD = difference between D and D (ΔD= Do+1n
n n+1 n-D ), ΔD
/2: Dn take. , 1 difference average n Detention 16...Third register e(t)...A-D conversion human analog signal, shi ~
70: Sampling frequency sampling timing, D"D: Sampling data from t□ to 70 (A-D conversion value) D(t)...D-A conversion output waveform, t□', tl', L2', L3': 2 (n sampling timing, D□', Dl', D2', D3': t□'
~t3' interpolated data D <tF>...DA conversion output waveform during double speed playback,
D (t,)...D-A conversion output waveform 17 during 1/2 slot 1 playback...A-D conversion sampling timing 1゛o (standardized frequency f,) of e (shi) 18... 17 sampling data D119...2
Output waveform 20...CE signal output waveform 2]...Output address value of 8 (at normal time) 22...
・Output address value of 8 (double speed) 23...Input waveform of OE signal 24...Latch content of first register 9 25...Latch content of second register 10 26...Output of 11 Contents 27: Latch contents of register 3 28: CE output waveform (when playing 1/2 slot) 29
... Read address value of 28 (when playing back 1/2 slot) 30... Input waveform of OE (when playing back 1/2 slot) 31
...29 read data 32...Control clock (1/2 slot temporary: f5) 33
...Latch contents of the third register (when playing 1/2 slot) Agent Patent attorney Ki Watanabe;SP? Φ 100

Claims (1)

[Claims] D when sequentially reading out an external memory that stores A-D converted data in chronological order, performing D-A conversion, and reproducing waveforms.
- In the digital filter before A conversion, there is an address control unit that generates the external memory read address, a two-stage register that latches the external memory read data, and two sampling timings before and after based on the contents of these two registers. an arithmetic circuit that interpolates intermediate data; a register that latches data for DA conversion; and a control clock generator that controls external memory readout and DA conversion data output timing. Variable speed simple digital filter circuit.