JPH06186976A - Waveform data output device - Google Patents

Abstract

PURPOSE:To calculate a waveform data output only by accessing difference waveform data, stored in a waveform memory in each sampling period, once for each tone. CONSTITUTION:One of difference waveform data DVL and DVH which are outputted from the waveform memory to 501 and 502 at the same time is selected in each sampling period on the basis of a data select bit as and outputted as the difference waveform data for interpolation arithmetic through 503 or 504. An integral value arithmetic part 505, on the other hand, calculates an integral value IV for interpolation arithmetic from the DVL or DVH, as, and data of a carry signal CC and an integral arithmetic value I1 outputted from an integral arithmetic memory 507 through 508 and outputs it through 509, and also calculates an integral arithmetic value update value Im and writes it in the integral arithmetic value memory 507 through 506. An external interpolation arithmetic part uses the DV and IV for interpolation arithmetic based upon address data for interpolation arithmetic to calculate the waveform data output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform data output device for outputting waveform data for generating a tone signal or the like by reading out differential waveform data stored in a waveform memory.

[0002]

2. Description of the Related Art DPCM (Differencia) is used as a method for generating high quality musical tone signals in electronic musical instruments.
l Pulse Code Modulation) method or ADPCM (Adapt
A waveform readout method called iveDifferencial Pulse Code Modulation) is known.

In these methods, the difference waveform data of the original waveform data is stored in the waveform memory, and these are read out while sequentially integrating (accumulating) with a step width corresponding to a designated pitch. As a result, the storage capacity of the waveform memory can be reduced as compared with the case where the original waveform data is directly stored.

FIG. 11 is a block diagram of a conventional example of a DPCM type waveform data output device. In the tone generator LSI 1101, the address counter register 1102 is set with real address data generated by an address counter (not shown).

In addition, carry register 1103 is set with carry signal CC indicating carry from a lower address to a higher address which can occur when real number address data is generated in an address counter (not shown).

Within one sampling period, the selector 1105 decrements the upper address AD, which is the integer address part of the real number address data set in the address counter register 1102, and the upper address AD by -1 by the decrementer 1104. The obtained decrement address AD-1 is sequentially selected and sequentially set in the address register 1106. The lower address ad, which is the decimal address part of the real number address data set in the address register 1102, is the interpolation calculation 111
It is output to 1. Further, the carry signal CC set in the carry register 1103 is used as an integrator 111 to be described later.
It is output to 0.

As a result, from the address bus AA to the waveform memory 1107, as shown in FIG.
D is output, and the decrement address AD-
1 is output, and the first differential waveform data DV ₁ and the second differential waveform data DV ₂ are sequentially output from the waveform memory 1107 to the data bus DD corresponding to each address, as shown in FIG. 12 (b). The data output is shown in FIG.
It is set in the first data register 1108 and the second data register 1109 at the timings shown in (c) and FIG. 12 (d).

In the integrating section 1110, the carry register 1
When the carry signal CC = 0 supplied from 103, that is, the address counter value obtained in the previous sampling period and the address counter value obtained in the current sampling period, the upper address AD changes. If there is not, the integration unit 11 is executed at the timing shown in FIG.
The value of the integrated value memory in 10 is the integrated value output I as it is.
The value of the integrated value memory itself is not updated, and the second differential waveform data DV ₂ set in the second data register 1109 is ignored. On the other hand, when the carry signal CC = 1 supplied from the carry register 1103, that is, the address counter value obtained in the previous sampling period and the address counter value obtained in the current sampling period, If the AD is changed, the second differential waveform data DV ₂ set in the second data register 1109 is accumulated in the value of the integrated value memory in the integrating section 1110, and the accumulated result is shown in FIG.
It is output as the integrated value output IV at the timing shown in (e), and the value of the integrated value memory itself is updated and stored again.

The interpolating operation section 1111 includes the first differential waveform data DV ₁ set in the first data register 1108,
The waveform data output D _out shown in FIG. _12F is calculated from the integrated value output IV output from the integrator 1110 and the lower address ad input from the address counter register 1102.

FIG. 13 is a block diagram of the interpolation calculator 1111 of FIG. The interpolation calculation unit 1111 includes an adder 1301 and a multiplier 1302 to execute the interpolation calculation processing shown in FIG.

[0011]

## EQU1 ## The waveform data output D _out is calculated by executing the linear interpolation calculation represented by D _out = IV + DV × ad.

FIG. 14 is a DPCM having the above-mentioned configuration.
It is a principle explanatory view of the conventional example of the waveform data output device of the method. At each address of the waveform memory 1107 in FIG. 11, as shown in FIG. 14B, the amplitude value of the original waveform data at the time of each address and the amplitude value of the original waveform data at the time of the next address are stored. The difference value is stored as the difference waveform data DV.

Now, as shown in FIG. 14A, the upper address AD = AD _now in a certain sampling period.
= (Address n on waveform memory 1107), lower address ad = ad _now , integrated value output IV = IV _now = (original waveform value corresponding to address n on waveform memory 1107),
First difference waveform data DV ₁ = DV _now = (waveform memory 1
Differential waveform data DV _n at address n on 107)
And carry signal CC = 0.

In this case, the interpolation calculation unit 1111 shown in FIG.
Calculates the waveform data output D _out = D _now by executing the interpolation calculation represented by D _now = IV _now + DV _now × ad _now from the equation (1).

Here, as shown in FIG. 14 (a), if the step width PD = PD _next , the sampling cycle shown by the subscript next next to the sampling cycle shown by the subscript now As a result of adding the step width to the real number address data of, the upper address AD does not change from AD _now at AD _next = (address n on the waveform memory 1107), and only the lower address ad changes to ad _next . . In this case, since the upper address AD does not change, carry signal CC = 0. Therefore, the integrated value output IV in the integrator 1110 does not change from IV _now with IV _next = (original waveform value corresponding to address n on the waveform memory 1107).

In this case, the interpolation calculation unit 1111 of FIG.
Calculates the waveform data output D _out = D _next by executing the interpolation calculation represented by D _next = IV _next + DV _next × ad _next from the equation (1).

[0017] On the contrary, if stepping width PD as shown in FIG. 14 (a) is assumed to be PD in _next without PD _next ', the next sampling period indicated by the subscript now subscript As a result of adding the above step width to the current real number address data at the sampling cycle indicated by next ′,
The upper address AD is AD _next ′ = (waveform memory 1107
At the above address n + 1), go +1 from AD _now ,
The lower address ad changes to ad _next '. In this case, the first difference waveform data DV ₁ read from the waveform memory 1107 becomes DV _next ′ = (difference waveform data DV _{n + 1} at address n + 1 on the waveform memory 1107) and the second difference waveform data DV ₂ is DV _now = (difference waveform data DV _{n at} the address n on the waveform memory 1107). The carry signal CC = 1 because the upper address AD has changed. Therefore, the integrated value output IV in the integrator 1110 is IV = IV _next ′ as a result of accumulating the second differential waveform data DV ₂ = DV _n.
= IV _now + DV _n = a (original waveform value corresponding to the address n + 1 on the waveform memory 1107).

In this case, the interpolation calculation unit 1111 shown in FIG.
Calculates the waveform data output D _next ′ = D _out by executing the interpolation calculation represented by D _next ′ = IV _next ′ + DV _next ′ × ad _next ′ from the equation (1).

[0019]

In the above-mentioned conventional example, in order to calculate the waveform data output D _out corresponding to the designated real number address for each sampling period, 1
By accessing the waveform memory twice with an integer address corresponding to a real number address and an integer address decremented by 1 from the integer address within the sampling period, two difference waveform data D for interpolation calculation and integration calculation are obtained.
It is necessary to read V and DV '.

Further, as shown in FIG. 15A, for example, the step width PD is a value P longer than one integer address length.
D _next ″ (which means that the pitch of the output waveform data is higher than the pitch of the original waveform data), it is indicated by the subscript next ″ next to the sampling cycle indicated by the subscript now. As a result of adding the above step width to the current real number address data at the sampling cycle, the upper address AD is advanced by +2 from AD _now at AD _next ″ = (address n + 1 on the waveform memory 1107), and the lower address ad. Changes to ad _next ″. In this case, the integrated value output IV needs to be IV _next ″ = IV _now + DV _n + DV _{n + 1} because the upper address AD has advanced by +2. Further, from the formula 1, D _next ″ = IV _next ″. In order to execute the interpolation calculation represented by + DV _next ″ × ad _next ″, it is also necessary to read the differential waveform data DV _next ″ = DV _{n + 2} from the waveform memory.

Therefore, in such a case, the configuration of the conventional example shown in FIG.
It becomes necessary to read three differential waveform data of V _n , DV _{n + 1} , and DV _{n + 2} from the waveform memory.

In this way, the pitch of the waveform data output is
In order to make the pitch higher than the pitch of the original waveform data indicated by the differential waveform data stored in the waveform memory, it is necessary to read the number of differential waveform data corresponding to the pitch change width for each sampling cycle.

The number of times the above-mentioned waveform memory is accessed is the waveform data output D _out for one channel for each sampling period.
It is assumed that only waveforms are output, and in order to simultaneously output waveform data for a plurality of channels in a time-division manner, the number of times the waveform memory is accessed further increases according to the number of channels.

Here, the basic specifications of the sound source LSI have been increasing due to the recent sophistication of the semiconductor technology, and in particular, the maximum number of simultaneous outputs and the sampling frequency have been increasing. Sound source L
In the conventional example in which the waveform memory connected to the SI must be accessed multiple times, the processing performance of the sound source LSI is limited by the access speed of the waveform memory, and as a result, the maximum number of simultaneous outputs and the sampling frequency are fixed. There is a problem that it cannot be raised above the level.

An object of the present invention is to make it possible to calculate the waveform data output only by accessing the waveform memory once for each sound in each sampling period.

[0026]

In the present invention, first,
While updating the value of the address data by the value corresponding to the step data at each sampling cycle, the upper address data that is the integer part and the lower address data that is the decimal part are output, and the value of the upper address data is It has address counter means for outputting address change data indicating that when 1 is incremented.

Next, there is provided waveform storage means for storing a predetermined number of differential waveform data in the storage area of each address. For example, two temporally continuous difference waveform data are stored in the lower bit portion and the upper bit portion of each storage area, respectively.

Next, there is provided waveform access means for simultaneously reading out the above-mentioned predetermined number of differential waveform data from the waveform storage means by accessing the waveform storage means by the upper address data output from the address counter means.

Further, at each sampling cycle, one or more of a predetermined number of differential waveform data read from the waveform storage means by the waveform access means are selected based on the value of the lower address data and the address change data. And has an accumulating means for accumulating the selected difference waveform data.

Then, for each sampling period, one of a predetermined number of differential waveform data read from the waveform storage means by the waveform access means and the accumulating means based on the value of the lower address data and the address change data. It has an interpolation calculation executing means for executing an interpolation calculation such as linear interpolation using the accumulated value output by and outputting the waveform data output.

[0031]

In the acoustic waveform, the fact that the differential waveform data has a narrower dynamic range than the original waveform data is utilized, and a predetermined number of pieces of differential waveform data are stored in the storage area indicated by the same address on the waveform storage means. The predetermined number of pieces of difference waveform data are stored and simultaneously read out by one memory access. For example, a total of two pieces of difference waveform data are stored in the lower bit portion and the upper bit portion of each storage area, and are simultaneously accessed.

As a result, a step width equal to or larger than one sample width of the original waveform data represented by the difference waveform data stored in the waveform storage means is designated as the step data, and is equal to or larger than the pitch of the original waveform data. Even when the waveform data output having a pitch is reproduced, the waveform data output can be calculated by accessing the waveform storage means once for each sound for each sampling period.

In this case, the accumulating means is not the value of the original waveform data corresponding to the currently accessed address on the waveform storing means, but the original corresponding to the sample position two points ahead of the original waveform data at every sampling cycle. The value of the waveform data is calculated as the accumulated calculation value.

More specifically, when the accumulating means determines that the upper address data designated to the waveform storing means is not updated depending on the presence or absence of the address change data in each sampling cycle, the lower means For example, according to the value of the most significant bit of the address data, a value obtained by subtracting either one or both of the values of the two difference waveform data currently read from the current waveform storage means from the current accumulated operation value, It is output to the interpolation calculation executing means as an accumulated value output for interpolation calculation. After that, the accumulating means holds the current accumulated operation value without updating, in order to obtain the accumulated value output for the interpolation operation in the next sampling cycle.

On the other hand, the accumulating means determines, for example, the most significant bit of the lower address data when the accumulating means determines that the upper address data designated for the waveform storing means is updated depending on the presence or absence of the address change data in each sampling cycle. Depending on the value of, the current cumulative calculated value or a value obtained by adding, for example, one of the differential waveform data newly read from the waveform storage means to the current cumulative calculated value is used for a new interpolation calculation. The accumulated value is output to the interpolation calculation executing means. Thereafter, the accumulating means updates the accumulated operation value with a value obtained by accumulating the two difference waveform data newly read from the waveform storage means to the current accumulated operation value, and in the next sampling cycle. Hold to get accumulated value output for interpolation operation.

The interpolating calculation means, for each sampling period,
As described above, the accumulated value obtained from the accumulating means is output, and, for example, the two accumulated read values are read from the current accumulated storage value from the current accumulated storage value in accordance with the value of the most significant bit of the lower address data. Either one of the values of the differential waveform data is selectively input, the interpolation operation is executed based on the value of the lower address data, and the waveform data output is output.

As described above, for example, when two difference waveform data are stored in the storage area indicated by the same address on the waveform storage means, the difference is less than twice the pitch of the original waveform data (one octave above). In any case, if the waveform data output has a pitch of (less than), the waveform data output can be calculated by only accessing the waveform storage unit once per sound for each sampling period.

[0038]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

The waveform data output D _out is calculated by the tone generator LSI 101 accessing the waveform memory 104 composed of a ROM. Here, the waveform memory 10
In the storage area indicated by the same address on 4 as shown in FIG.
Two pieces of differential waveform data (DV ₀ , DV ₁ ) (D
_{V 2, DV 3) (DV} 4, DV 5) (DV 6, DV 7)
Is stored, and two differential waveform data are simultaneously read out by one memory access. That is, in the acoustic waveform, since the differential waveform data has a narrower dynamic range than the original waveform data, two data can be stored in the storage area indicated by one address.

In the sound source LSI 101, the control unit 102
_Expresses a control signal On for instructing whether to start or stop the output of the waveform data output D _out based on an instruction from a CPU (central processing unit) (not shown). Output to.

The address counter unit 103 has a step size based on the pitch data set by the CPU from the start address set by the CPU (not shown).
The address for calculating the waveform data output D _out is updated.

FIG. 3 shows the address counter unit 103 of FIG.
It is a block diagram of. The address update operation itself is the same as a known operation. When the output of the waveform data output D _out is started, first, the selector 301
The desired start address of the differential waveform data group on the waveform memory 104 is set in the address counter memory 302 via. Further, pitch data PD is set in the pitch memory 305 from a CPU (not shown). After that, based on an instruction from the CPU (not shown), FIG.
The control signal On input from the control unit 102 to the AND gate group 306 is set to the high level. As a result, the pitch data PD set in the pitch memory 305 becomes
It becomes possible to input to the lower address adder 307 described later via the AND gate group 306.

After the output of the waveform data output D _out is started, the address counter value ADRS output from the address counter memory 302 and the pitch data PD output from the pitch memory 305 are added every sampling cycle. The contents of the address counter memory 302 are updated.

Specifically, as shown in FIG. 8 (a),
Address counter value AD output from the address counter memory 302 in the first half section within one sampling period T
Among RSs, the higher-order bit string has a higher-order address adder 3
03, and its lower bit string is output to the lower address adder 307.

The lower address adder 307 is provided with the lower bit string of the address counter value ADRS and the pitch memory 30.
5 and the pitch data PD input at the timing shown in FIG. 8 (b) via the AND gate group 306, and the most significant bit of the addition result is as shown in FIG. 8 (d). Is stored in the data select bit register 310 as the data select bit as, and the lower bits except the most significant bit are as shown in FIG. 8 (e).
It is stored in the lower address register 308 as the lower address ad.

If a carry 1 does not occur as a result of the addition operation in the lower address adder 307, the upper address adder 303 keeps the upper bit string of the address counter value ADRS as it is, at the timing shown in FIG. When the carry 1 is stored in the upper address register 304 as the upper address AD, the carry 1 is added to the upper bit string of the address counter value ADRS, and the addition result is obtained at the timing shown in FIG. 8 (c). , And stores it in the upper address register 304 as the upper address AD.

Further, the carry output from the lower address adder 307 is at the timing shown in FIG.
It is stored in carry register 309 as carry signal CC.

The high-order address AD stored in the high-order address register 304 is output to the waveform memory 104 via the address bus AA shown in FIG. 1, and stored in the data select bit register 310 and the carry register 309. Stored carry signal CC
Is output to the integration unit 106 in FIG. 1, and the lower address ad stored in the lower address register 308 is output to the interpolation calculation unit 106 in FIG.

Further, the content of the address counter memory 302 has one sampling period T as shown in FIG. 8 (a).
In the latter half section, the upper address AD, the data select bit as, and the lower address ad input from the upper address register 304, the data select bit register 310, and the lower address register 308 via the selector 301 are updated.

The format of each data in the address counter section 103 is shown in FIG. Of the address counter value ADRS, the high-order bit string is the integer part,
The lower bit string is the fractional part. Also, the pitch data PD
Is a decimal. Then, in the lower address adder 307 configured by the full bit adder, the lower bit string of the address counter value ADRS, which is a decimal number, and the pitch data PD are added, and the upper address adder 303 configured by the incrementer. At, the upper address AD of the address counter value ADRS is selectively incremented by +1 based on the carry from the lower address adder 307.

In this case, the upper address AD is used as an address for accessing the waveform memory 104. However, as described above with reference to FIG. 2, the lower bit portion is stored in the storage area indicated by the same address on the waveform memory 104. And a total of two difference waveform data are stored in the upper bit part. Therefore, when the upper address AD advances by 1, the sample position on the original waveform data advances by 2. When the data select bit as, which is the most significant bit of the lower address output from the lower address adder 307, changes from 0 to 1, the sample position on the original waveform data becomes 1
Will move forward.

That is, the data select bit as has a function of selecting one of the two differential waveform data in the address on the waveform memory 104 indicated by the upper address AD.

The lower address ad excluding the most significant bit of the lower address output from the lower address adder 307 has a function of indicating the interpolation position in the interpolation calculation unit 107.

Further, the carry signal CC has a function of notifying the integrating unit 106 that the upper address AD has been updated by the address counter unit 103 in the current sampling period.

From the above relation, in the present embodiment, the pitch data PD can specify the step width up to less than 2 samples of the original waveform data represented by the differential waveform data stored in the waveform memory 104. It is possible to reproduce the waveform data output D _out having a pitch less than twice the pitch of the original waveform data (less than one octave above).

In the address counter unit 103 shown in FIG. 3, for simplification of description, the structure for terminating the address updating operation by comparing the count end address with the address counter value ADRS is omitted. .

Next, FIG. 5 is a block diagram of the integrating unit 106 of FIG. Now, every sampling period T, the upper address register 303 in the address counter unit 103 (FIG. 1) is
Waveform memory 10 from (FIG. 3) via address bus AA
4, when the upper address AD is output as shown in FIG. 8 (c), two differential waveform data sets DV _L and DV _H corresponding to the address are output from the waveform memory 104 to the data bus DD. It is output and stored in the data register 105 of FIG. 1 at the timing shown in FIG. 8 (g).
DV _L and DV _H are stored in the DV _L register 501 and the DV _H register 502 at the timings shown in FIGS. 8 (h) and 8 (i), respectively.

Then, the selector 503 inputs the data select bit as = from the address counter section 103.
If it is 0, the differential waveform data DV _L stored in the DV _L register 501 is selected, and conversely, the data select bit as = 1
If so, the differential waveform data DV _H stored in the DV _H register 502 is selected. The selected difference waveform data is stored in the DV register 504 as the interpolation calculation difference waveform data DV at the timing shown in FIG. 8 (j).

The integral value calculation unit 505 stores the integral calculation value memory 507 to the I ₁ register 508 every sampling period.
The integral calculation value I ₁ which is output through the, DV difference waveform data DV _L output from the _L register 501, DV _H register 502 differential waveform data DV _H outputted from the data select bits as, and the carry signal CC On the basis of the above, the integral value IV for interpolation calculation is calculated and stored in the IV register 509 at the timing shown in FIG.

Further, the integral value calculation unit 505 is configured to convert the integral value memory 507 to the I ₁ register 50 for each sampling cycle.
Integral with the calculated value I ₁ which is output through the 8, differential waveform data DV _L output from the DV _L register 501, DV _H
Difference waveform data DV _H output from the register 502,
Based on the carry signal CC and the integrated calculation value update value I
By calculating _m , the contents stored in the integral calculation value memory 507 are updated via the AND gate group 506 at the timing shown in FIG.

During the address update operation, a control signal input from the control unit 102 of FIG. 1 to the AND gate group 506.
On is at a high level, but when the address update operation is forcibly stopped, that is, when the output operation of the waveform data output D _out is forcibly stopped, an instruction from a CPU (not shown) Based on the above, the control signal On input to the AND gate group 506 from the control unit 102 of FIG. 1 is set to the low level. As a result, the integrated calculation value update value I
The input of _m is blocked, the output becomes all 0, and the contents of the integral calculation value memory 507 are cleared.

The interpolation calculation unit 107 of FIG. 1 uses the difference waveform data DV and IV register 5 for interpolation calculation set in the DV register 504 of FIG. 5 at the timing shown in FIG. 8 (j).
09, the integrated value IV for interpolation calculation set at the timing shown in FIG. 8 (k), and the address counter unit 1 in FIG.
From 03 to the lower address ad input at the timing shown in FIG. 8 (e), the waveform data output D _out is calculated and output at the timing shown in FIG. 8 (m). The calculation operation here is the same as that in the configuration shown in FIG. 13 described above in the description of the conventional example, and the integrated value IV, the first difference waveform data DV ₁ and the address counter register (lower order) in FIG. They correspond to the interpolation calculation integrated value IV, the interpolation calculation difference waveform data DV, and the lower address ad, respectively.

FIG. 6 is a block diagram of a circuit for calculating the integral calculation value update value I _m in the integral value calculator 505. The adder 601 adds the difference waveform data DV _L and DV _H.

The AND gate group 602 has a carry signal C.
When C = 1, the addition value D output from the adder 601
The V _L + _D V _H is output to the adder 603. When carry signal CC = 0, 0 is output to adder 603.

The adder 603 is the I ₁ register 50 of FIG.
AND gate group 60 to the integral calculation value I ₁ output from 8
The outputs of 2 are added, and the addition result is the integrated calculation value update value I
_{The value m} is output to the integral calculation value memory 507 via the AND gate group 506 in FIG.

As can be understood from the above configuration, the integral calculation value update value I _m is

[0067]

## EQU00002 ## I _m = I ₁ (when CC = 0)

[0068]

## EQU3 ## It is calculated as I _m = I ₁ + DV _L + _D V _H (when CC = 1).

FIG. 7 is a block diagram of a circuit for calculating the interpolation calculation integral value IV in the integral value calculating section 505. First, if the carry signal CC = 0 and the data select bit as = 0, the AND gates 706 and 70.
Both outputs of 8 become "0" and the output of the OR gate 709 becomes "0", so that the output of the inverter 710 becomes "1". Therefore, the AND gate group 701 is turned on, and the differential waveform data DV _L is input to the adder / subtractor 702 from the DV _L register 501 in FIG.

The adder / subtractor 702 receives the carry signal CC = 0.
In this case, the I ₁ register 508 operates as a subtractor.
AND gate group 70 from the integral calculation value I ₁ input from
The difference waveform data DV _L input from 1 is subtracted, and the subtraction result is output to the subtractor 704.

When the carry signal CC = 0, the subtracter 704 subtracts the differential waveform data DV _H input from the DV _H register 502 of FIG. 5 via the AND gate group 703 from the output of the adder / subtractor 702. , And outputs the subtraction result to the IV register 509 of FIG. 5 as the integration value IV for interpolation calculation.

As can be seen from the above operation, the following equation is established.

[0073]

Equation 4] _{IV = I 1 -DV L -DV H} ( case of CC = 0 and the as = 0) Then, at the carry signal CC = 0, and when the data select bit the as = 1 is an AND gate Since the output of 706 is "1" and the output of the OR gate 709 is "1", the output of the inverter 710 is "0". Therefore,
The AND gate group 701 is turned off, and the adder / subtractor 702
Is the integral calculation value I ₁ input from the I ₁ register 508.
Is output to the subtractor 704 as it is.

When the carry signal CC = 0, the subtracter 704 subtracts the differential waveform data DV _H input from the DV _H register 502 of FIG. 5 via the AND gate group 703 from the output of the adder / subtractor 702. , And outputs the subtraction result to the IV register 509 of FIG. 5 as the integration value IV for interpolation calculation.

As can be seen from the above operation, the following equation holds.

[0076]

IV = I ₁ −DV _H (when CC = 0 and as = 1) Then, when carry signal CC = 1 and data select bit as = 0, the output of AND gate 708. Is "1" and the output of the OR gate 709 is "1", so that the output of the inverter 710 is "0". Therefore,
The AND gate group 701 is turned off, and the adder / subtractor 702
Is the integral calculation value I ₁ input from the I ₁ register 508.
Is output to the subtractor 704 as it is.

When the carry signal CC = 1, the subtractor 704 outputs the output of the adder / subtractor 702 to the IV register 509 of FIG. 5 as the integrated value IV for interpolation calculation as it is. As can be seen from the above operation, the following equation holds.

[0078]

## EQU6 ## IV = I ₁ (CC = 1 and a
When s = 0) Finally, when carry signal CC = 1 and data select bit as = 1, both outputs of AND gates 706 and 708 are “0” and an output of OR gate 709 is “0”. Therefore, the output of the inverter 710 becomes “1”. Therefore, the AND gate group 701 is turned on, and the differential waveform data DV _L is input to the adder / subtractor 702 from the DV _L register 501 in FIG.

The adder / subtractor 702 receives the carry signal CC = 1.
In the case of, it operates as an adder, and I ₁ register 508
The AND gate group 701 is added to the integral calculation value I ₁ input from
The difference waveform data DV _L input from the above is added, and the addition result is output to the subtractor 704.

When the carry signal CC = 1, the subtractor 704 outputs the output of the adder / subtractor 702 as it is to the IV register 509 of FIG. 5 as the interpolation operation integral value IV. As can be seen from the above operation, the following equation holds.

[0081]

(7) IV = I ₁ + DV _L (CC = 1 and a
In the case of s = 1) A specific operation of the embodiment of the present invention centering on the integrating unit 106 of FIG. 1 described above will be described below.

First, as described above with reference to FIG. 2, the storage area corresponding to each address on the waveform memory 104 of FIG.
As shown in FIG. 9 (b), in the lower bit part, the difference waveform data DV _L between the amplitude value of the original waveform data at the time of each address and the amplitude value of the original waveform data at the time of the next address, Difference waveform data DV _H between the amplitude value of the original waveform data at the time point of the address next to each address and the amplitude value of the original waveform data at the time point of the next address is stored as a set in the upper bit portion.

Now, as shown in FIG.
Assume that the upper address AD = AD _now = (address n on the waveform memory 104), the lower address ad = ad _now , the carry signal CC = 0, and the data select bit as = 0 at an arbitrary sampling period indicated by w. To do.

In this case, the differential waveform data DV _Lnow stored in the DV _L register 501 of FIG.
4 becomes the data DV _Ln of the lower bit portion of the address n, and the differential waveform data DV _Hnow stored in the DV _H register 502 of FIG. 5 becomes the data DV _Hn of the upper bit portion of the address n on the waveform memory 104. . And as = 0
_Therefore , the selector 503 in FIG. 5 selects the differential waveform data DV _Lnow = DV _Ln stored in the DV _L register 501, and the differential waveform data for interpolation calculation DV = DV _Lnow = DV set in the DV register 504. It becomes _Ln .

On the other hand, the integral calculation value I_{1 now}Is the waveform memory 1
Source wave of sample position corresponding to address n + 1 on 04
It corresponds to the amplitude of the shape data, and therefore CC = 0, a
Since s = 0, set in the IV register 509 of FIG.
Integrated value IV for interpolation calculation _nowFrom the equation (4), IV_now= I_{1 now}-DV_Lnow-DV_Hnow Is calculated as
A value corresponding to the amplitude of the original waveform data at the corresponding sample position
become.

[0086] In this case, the interpolation operation unit 107 of FIG. 1, from equation 1, by performing the interpolation calculation represented by _{D now = IV now + DV Lnow} × ad now, the waveform data output D _out = D _now calculate. The correctness of this calculation is clear from the positional relationship of each data in FIG. 9 (a).

Further, the integral calculation value update value I _mnow is CC =
Since it is 0, it is calculated by the equation 2 as I _mnow = I _1now , and the contents of the integral operation value memory 507 in FIG. 5 are not updated.

Here, in the first case, as shown in FIG. 9A, if the step width PD = PD _next , the subscript no.
As a result of the above step size being added to the current real number address data at the sampling period indicated by the next index next to the sampling period indicated by w, the upper address AD is A
AD at D _next = (address n on waveform memory 1107)
_Since it does not change from _{now, the} carry signal CC = 0,
Since the lower address ad _next is smaller than 0.5,
The data select bit as = 0.

Therefore, the differential waveform data DV _Lnext is DV
_Lnow = DV _Ln remains and the differential waveform data DV _Hnext
Also _holds DV _Hnow = DV _Hn , and as = 0, so that the interpolation calculation difference waveform data DV = DV _Lnext = DV _Ln set in the DV register 504 of FIG.

Further, the integral calculation value I _1next is I _mnow = I
_It is equal to _1now and corresponds to the amplitude of the original waveform data at the sample position corresponding to the address n + 1 on the waveform memory 104. Therefore, since CC = 0 and as = 0, the integral value I for interpolation calculation set in the IV register 509 of FIG.
V _next is calculated as IV _next = I _1next −DV _Lnext −DV _Hnext from the equation 4, and becomes a value corresponding to the amplitude of the original waveform data at the sample position corresponding to the address n on the waveform memory 104.

In this case, the interpolation calculation unit 107 of FIG. 1 executes the interpolation calculation represented by D _next = IV _next + DV _Lnext × ad _next from the formula 1 to obtain the waveform data output D _out = D _next . calculate. The correctness of this calculation is clear from the positional relationship of each data in FIG. 9 (a).

Further, the integral calculation value update value I _mnext is CC
Since = 0, the equation (2 ₎ is calculated as I _mnext = I _1next , and the contents of the integral operation value memory 507 in FIG. 5 are not updated.

On the other hand, as a second case, FIG.
As shown in (a), if the step size PD is PD _next ′ instead of PD _next ′, in the sampling period indicated by the subscript next ′ next to the sampling period indicated by the subscript now, As a result of the above step width being added to the current real number address data, the upper address AD is AD _next ′.
= (Address n on the waveform memory 1107), the carry signal CC = 0 because it does not change from AD _now , and
Since the lower address ad _next 'is larger than 0.5, the data select bit as = 1.

Therefore, the difference waveform data DV _Lnext ′ is D
V _Lnow = DV _Ln remains and the difference waveform data DV
_Hnext 'also remains DV _Hnow = DV _Hn , while as
= 1, the differential waveform data for interpolation calculation DV = DV _Hnext ′ = D set in the DV register 504 of FIG.
It becomes V _Hn .

Further, the integral operation value I _1next ′ is I _mnow = I
_It is equal to _1now and corresponds to the amplitude of the original waveform data at the sample position corresponding to the address n + 1 on the waveform memory 104. Therefore, since CC = 0 and as = 1, IV in FIG.
Interpolation calculation integral value IV set in the register 509
_next 'is calculated as IV _next ′ = I _1next ′ −DV _Hnext ′ from the equation 5, and corresponds to the amplitude of the original waveform data at the sample position next to the sample position corresponding to the address n on the waveform memory 104. It becomes a value.

In this case, the interpolation calculation unit 107 in FIG. 1 executes the interpolation calculation represented by D _next ′ = IV _next ′ + DV _Hnext ′ × ad _next ′ from the equation 1 to output the waveform data D _out = D _next 'is calculated. The correctness of this calculation is clear from the positional relationship of each data in FIG. 9 (a).

Further, the integral calculation value update value I _mnext ′ is C
Since C = 0, it is calculated as I _mnext ′ = I _1next ′ from the equation (2), and the contents of the integral operation value memory 507 in FIG. 5 are not updated.

In the third case, as shown in FIG. 10 (a), if the step width PD = PD _next , the sampling period indicated by the _next index _next to the sampling period indicated by the subscript now. Then, as a result of adding the step width to the current real number address data, the upper address AD is advanced by +1 from AD _now at the higher address AD at AD _next = (address n + 1 on the waveform memory 1107), and the carry signal C
C = 1. Since the lower address ad _next is smaller than 0.5, the data select bit as = 0.

In this case, the differential waveform data DV _Lnext is
Address n on the waveform memory 104 shown in FIG.
The data of the lower bit portion of +1 becomes DV _{Ln + 1} , and the differential waveform data DV _Hnext is the address n on the waveform memory 104.
It becomes the data DV _{Hn + 1} of the high-order bit portion of +1. And a
Since s = 0, the differential waveform data for interpolation calculation set in the DV register 504 of FIG. 5 DV = DV _Lnext = D
It becomes V _{Ln + 1} .

Further, the integrated operation value I _1next is equal to I _mnow = I _1now , as in the case of FIG.
4 corresponds to the amplitude of the original waveform data at the sample position corresponding to address n + 1. Therefore, CC = 1, as
= 0, the integral value IV _next for interpolation calculation set in the IV register 509 is calculated from equation 6 as IV _next = I _1next , and the address n + 1 on the waveform memory 104 is calculated.
Is a value corresponding to the amplitude of the original waveform data at the sample position corresponding to.

In this case, the interpolation calculation unit 107 in FIG. 1 executes the interpolation calculation represented by the following equation 1 by the following equation: D _next = IV _next + DV _Lnext × ad _next to obtain the waveform data output D _out = D _next . calculate. The correctness of this calculation is clear from the positional relationship of each data in FIG.

Further, the integral calculation value update value I _mnext is CC
Since = 1, it is calculated by the following equation 3 as I _mnext = I _1next + DV _Lnext + DV _Hnext , and the content of the integral operation value memory 507 in FIG. It is updated to a value corresponding to the amplitude of the waveform data.

As a fourth case, as shown in FIG. 10A, if the step size PD = PD _next ', the subscript now.
As a result of adding the above step width to the current real number address data at the sampling period indicated by the subscript next 'next to the sampling period indicated by, the upper address AD, the upper address AD is AD _next ' = (waveform At the address n + 1) on the memory 1107, +1 is advanced from AD _now , and the carry signal CC = 1. Since the lower address ad _next 'is larger than 0.5, the data select bit as = 1
Is.

In this case, the differential waveform data DV _Lnext '
Is the data DV _{Ln + 1} of the lower bit part of the address n + 1 on the waveform memory 104 shown in FIG. 10B, and the differential waveform data DV _Hnext ′ is the upper bit part of the address n + 1 on the waveform memory 104. Data DV _{Hn + 1} . Since as = 1, the differential waveform data for interpolation calculation DV = DV _Hnext ′ set in the DV register 504 of FIG.
= DV _{Hn + 1} .

Further, the integral calculation value I _1next ′ is shown in FIG.
As in the case of, I _mnow = I _1now and the waveform memory 1
04 corresponds to the amplitude of the original waveform data at the sample position corresponding to the address n + 1. Therefore, CC = 1, as =
Since it is 1, the integral value IV _next ′ for interpolation calculation set in the IV register 509 of FIG. 5 is calculated as IV _next ′ = I _1next ′ + DV _Lnext ′ from the equation 7, and the address on the waveform memory 104 n + 1
Is a value corresponding to the amplitude of the original waveform data at the sample position next to the sample position corresponding to.

In this case, the interpolation calculation unit 107 of FIG. 1 executes the interpolation calculation represented by the following formula 1 by D _next ′ = IV _next ′ + DV _Hnext ′ × ad _next ′, thereby outputting the waveform data output D _out = D _next 'is calculated. The correctness of this calculation is clear from the positional relationship of each data in FIG.

Further, the integral calculation value update value I _mnext ′ is C
Since C = 1, it is calculated from the formula 3 as I _mnext ′ = I _1next ′ + DV _Lnext ′ + DV _Hnext ′, and the contents of the integral operation value memory 507 in FIG. The value is updated to a value corresponding to the amplitude of the original waveform data at the sample position.

As is clear from the above description of FIGS. 9 and 10, if the waveform data has a pitch less than twice the pitch of the original waveform data (less than one octave above),
In any case, the waveform memory can be output by accessing the waveform memory once for each sound in each sampling cycle.

Although the embodiment described above has a configuration for outputting the waveform data output D _out for one channel, in order to be able to output the waveform data output for a plurality of channels at the same time, 1, the control unit 102, the address counter memory 302 and the pitch memory 305 in FIG. 3, and FIG.
8 is configured to store and output data for a plurality of channels, and the sampling cycle is time-divided so that addresses can be updated and interpolation operations for a plurality of channels can be performed. Similar control may be performed.

The present invention can also be applied to the ADPCM system. Further, in the above-described embodiment, the storage area indicated by the same address on the waveform memory 104 is
As shown in FIG. 2, a total of two differential waveform data are stored in each of the lower bit part and the upper bit part, and
Two differential waveform data are simultaneously read by one memory access, but in relation to the dynamic range, a plurality of differential waveform data are stored in the storage area indicated by the same address and they are stored. It is also possible to make a configuration such that the memory is read simultaneously by one memory access.

[0111]

According to the present invention, one of the original waveform data represented by the differential waveform data stored in the waveform storage means is used.
Even when the step width equal to or larger than the sample width is designated as the step data and the waveform data output having the pitch equal to or greater than the pitch of the original waveform data is reproduced, the waveform storage means is set to 1 per tone for each sampling period. It is possible to calculate the waveform data output with just one access.

Conventionally, 2 per sound is taken every sampling period.
In a waveform data output sound source device of the DPCM system or the ADPCM system in which a single access to the waveform memory occurs,
When the sampling frequency is 48kHz, the sampling period is 1/48000 = 20.83μsec. On the other hand, the access time of the standard ROM that constitutes the waveform memory is 20
It is 0 nsec. Therefore, the number of waveform data output channels that can be simultaneously output is limited to 52 channels. When two waveform data outputs are mixed and used for improving sound quality, or when the waveform data outputs are output in stereo (2 channels), the number of channels of waveform data output that can be output at the same time is as described above. This results in 26 channels, which is half the number of channels. Further, when reproducing a waveform data output having a pitch equal to or greater than the pitch of the original waveform data, access to the waveform memory is further increased and the number of channels is further reduced. With this, the PCM type waveform data output sound source device cannot be mounted on an electronic piano or the like.

On the other hand, in the waveform data output sound source device according to the present invention, even when an attempt is made to reproduce the waveform data output having a pitch equal to or greater than the pitch of the original waveform data, the waveform data output to the waveform memory generated at each sampling cycle is performed. Since the number of accesses is only once per sound, the number of waveform data output channels that can be simultaneously output is 104. That is, by using the waveform data output sound source device according to the present invention, full polyphonic can be realized with an 88-key electronic piano.

Even when two waveform data outputs are mixed and used for improving sound quality, or the waveform data outputs are output in stereo, the number of waveform data outputs that can be simultaneously output is 52. it can.

Furthermore, when it is not necessary to increase the number of channels of waveform data output that can be output simultaneously, the processing frequency can be increased, so that the sampling frequency can be doubled as compared with the conventional one, and the sound quality can be greatly improved. It is possible to improve.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing stored contents of a waveform memory.

FIG. 3 is a configuration diagram of an address counter unit in the embodiment of the present invention.

FIG. 4 is a diagram showing a data format of an address counter unit in the embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of an integrating unit in the embodiment of the present invention.

FIG. 6 is a configuration diagram (I _m calculation circuit) of an integral value calculation unit.

FIG. 7 is a configuration diagram (IV calculation circuit) of an integrated value calculation unit.

FIG. 8 is an operation timing chart of the embodiment of the present invention.

FIG. 9 is an explanatory diagram of an example of the present invention (when CC = 0).

FIG. 10 is an explanatory diagram of an embodiment of the present invention (when CC = 1)
Is.

FIG. 11 is a configuration diagram of a conventional example.

FIG. 12 is an operation timing chart of a conventional example.

FIG. 13 is a configuration diagram of an interpolation calculation unit in a conventional example.

FIG. 14 is a diagram illustrating the principle of a conventional DPCM method.

FIG. 15 is an explanatory diagram of problems in the conventional DPCM method.

[Explanation of symbols]

101 tone generator LSI 102 control unit 103 address counter unit 104 waveform memory 105 data register 106 integration unit 107 interpolation calculation unit 301 selector 302 address counter memory 303 upper address adder 304 upper address register 305 pitch memory 306 AND gate group 307 lower address adder 308 Lower address register 309 Carry register 310 Data select bit register 501 DV _L register 502 DV _H register 503 Selector 504 DV register 505 Integral value calculation unit 506 AND gate group 507 Integral operation value memory 508 I ₁ register 509 IV register 601, 603 Addition Device 602 AND gate group 701, 703 AND gate group 702 Adder / subtractor 704 Subtractor 705, 70 , 710 inverter 706, 708 AND gate 709 OR gates ADRS address counter value AD upper address ad lower address as data select bit CC carry signal PD pitch data On the control signal D _out waveform data output DV _L, DV _H differential waveform data DV interpolation calculation Differential waveform data IV Interpolation calculation integration value I _m Integration calculation value update value I ₁ Integration calculation value

Claims (1)

[Claims] 1. An upper-order address data, which is an integer part thereof, and a lower-order address data, which is a fractional part thereof, are each output while updating the value of the address data by the value corresponding to the step data for each sampling cycle, Address counter means for outputting address change data indicating that when the value of the higher-order address data is incremented by 1, waveform storage means for storing a predetermined number of difference waveform data in the storage area of each address, and the address counter Waveform access means for simultaneously reading the predetermined number of differential waveform data from the waveform storage means by accessing the waveform storage means with the upper address data output from the means; and the lower address data for each sampling period. Waveform access means based on the value of the address and the address change data. Accumulating means for accumulating the selected difference waveform data by selecting any one or more of the predetermined number of difference waveform data read from the waveform storage means by: Based on the value of the lower address data and the address change data, any one of the predetermined number of difference waveform data read from the waveform storage means by the waveform access means and the accumulation output by the accumulation means. A waveform data output device, comprising: interpolation calculation executing means for executing an interpolation calculation using a calculated value and outputting a waveform data output.