JP2768241B2 - Signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus used for an electronic musical instrument or the like and for giving various effects to signals.

[0002]

2. Description of the Related Art A DSP is used as a signal processing device of an electronic musical instrument. The DSP performs various arithmetic processing on a digitized signal waveform to give various effects such as reverberation and vibrato. The DSP operates with a multi-step microprogram, and the coefficients used in this program and the arithmetic processing of each step are determined in advance by the DSP.
Was set to

[0003]

However, in recent years, DSP
It is considered that the effect given to the musical sound is changed in real time by changing the coefficient in real time. However, for example, if all the coefficients of a DSP operating in a number of steps are to be changeable, it is necessary to interpolate all the coefficients so that the effect does not suddenly change. If all the interpolations are performed, the configuration of the interpolator becomes large.

An object of the present invention is to provide a signal processing apparatus which solves the above problem by interpolating only coefficients to be changed.

[0005]

According to the present invention, there is provided an arithmetic means for performing a waveform processing operation using a plurality of coefficients, a coefficient storage means for storing the plurality of coefficients, and a description of the coefficient storage means.
Coefficient change that changes the value of one or more stored coefficients
And a plurality of parameters stored in the coefficient storage means.
A coefficient designating means for designating some of the coefficients
That the input coefficient has been changed by the coefficient changing means.
Come, and interpolation means having channel number smaller than the number of the arithmetic means and said plurality of coefficients interpolated channel supplied to while interpolating the value after the change from the value before the change, the coefficient designation
And assignment means for inputting the specified coefficients are selectively said interpolation channel by means, the coefficient designation
The above calculation is performed on the coefficients not specified by the means.
Direct supply means for co-supplying the means .

[0006]

In the signal processing device according to the present invention, a plurality of coefficients used in the calculating means are stored in the coefficient storing means. When the coefficient value is changed, the result of the waveform processing calculation also changes, and the processing content of the signal (for example, the effect given to the tone signal) also changes.
Usually, the coefficient that is changed simultaneously is a part of a plurality of coefficients.
Therefore, a part of the stored coefficients to be changed smoothly is specified (coefficient specifying means) . The designated coefficient is assigned to the channel of the interpolation means and the old coefficient−
While interpolating between the new coefficients are supplied to the arithmetic unit. As a result, only the necessary coefficients are smoothly changed. Other coefficients
Is directly supplied to the arithmetic means without going through the interpolation means.
Some of the coefficients to be changed may be selectable at that time, or may be fixedly determined in advance.

[0007]

FIG. 1 is a block diagram of an electronic musical instrument provided with a DSP according to an embodiment of the present invention. CPU 1 has bus 1
1, ROM 12, RAM 13, keyboard 14, pedal 15, wheel 16, panel switch 17, display 1
8, a timer 19, a sound source 20, and a DSP 21 are connected. The ROM 12 stores a control program for controlling the operation of the electronic musical instrument. The RAM 13 stores data generated at the time of performance, such as data on the amount of operation of keys and controls. Keyboard 14 has 5 octaves (61
Key). The pedal 15 is a control operator that outputs operation amount data of a continuous value according to the depression angle. The wheel 16 is a so-called modulation wheel, and outputs operation amount data according to the rotation angle. The operation amount data of these control operators is stored in the RAM 13.
Is stored in a predetermined area.

The panel switch 17 and the display 18 are provided on the operation panel, and select a tone, select an effect of the DSP 21, and display the selected contents. Timer 19
Is a timer for counting the tempo during automatic accompaniment. The sound source 20 is a conventional sampling sound source or F
M sound sources may be used.

The DSP 21 is a circuit for giving various effects to the tone signal formed by the sound source 20. Although details will be described later, the built-in arithmetic unit and the external delay R
A digital tone signal is arithmetically processed by an operation such as AM22. Examples of the effect to be provided include reverberation and vibrato. Some of the parameters (coefficients) for controlling the operation of the DSP 21 are updated in real time by the CPU 10 based on initial touch and after touch of the keyboard 14, operation amount data of the pedal 15 and the wheel 16, and the like.

A DAC 23 is connected to the DSP 21. The DAC 23 converts digital tone waveform data output from the DSP 21 into analog tone signals.
The converted tone signal is input to the sound system 24. The sound system 24 amplifies this signal and emits the sound from a speaker or the like.

FIG. 2 is a block diagram of the DSP 21. The tone signal input from the sound source 20 is input to the DSP calculation unit 33 via the input register 36. DSP calculation unit 33
Is based on a 256-step microprogram, coefficients and parameters input from various registers,
The tone signal is processed using the delay RAM 22 to provide various effects. The tone signal processed by the DSP calculation unit 33 is output to the DAC 23 via the output register 44.

One coefficient is used for each of the 256-step arithmetic processing of the DSP arithmetic unit 33. This coefficient is set in the coefficient register 37 in advance prior to the start of the operation of the DSP 21 (for example, when the power is turned on or when reverberation / effect selection is set). Of these 256 coefficients, only 16 coefficients are designed to be smoothly changed while simultaneously interpolating in real time.

The DSP operation unit 33 includes an input register 3
6. In addition to the output register 44, the following registers are connected to input various data and the like. An address generator 35 for instructing an address for delaying a waveform by accessing the delay RAM 22, an interpolator 39 for inputting a coefficient for calculation, a register 40 for other control for controlling other elements, and A microprogram memory 43 for inputting a microprogram.

The address generator 35 is connected to a delay control register 34. Delay control register 34
Inputs a delay parameter to the address generator 35. The delay parameter is a parameter for instructing how long the musical tone waveform data input to the DSP 21 is output using the delay RAM 22. The address generator 35 determines D based on this parameter.
The SP calculation unit 33 generates an address to be written / read to / from the delay RAM 22. The DSP calculation unit 33 stores the tone waveform data input for each sampling clock in the delay RAM 22 on the basis of the address, and delays the delay RAM 22 before a predetermined clock (delay time).
The tone waveform data stored in the memory is read out. Therefore, the delay RAM 22 is used like a shift register. The delay parameter is input from the CPU 10 via the bus 11, the CPU interface 30, and the interface bus 31.

The microprogram memory 43 has 256
It stores a microprogram consisting of microcode of steps. The microcode is specified by an 8-bit step number CNT. Each microcode is DS
Predetermined processing operations for the P operation unit 33 (for example, input of musical tone waveform data, memory writing, memory reading, calculation, output of musical tone waveform data input, parameter reading, etc.)
Instruct. An 8-bit counter 42 is connected to an address terminal of the microprogram memory 43. The system clock generator 41 is connected to the count terminal of the counter 42. The system clock φ is a clock having a frequency sufficiently higher than the sampling clock. This is because it is necessary to execute one microprogram during one sampling clock. According to the input of the system clock φ, the counter 42 repeatedly outputs the count value CNT of 0 to 255 (FF).
That is, the counter 42 returns to 0 after the overflow reset. The microprogram memory 43 is accessed with the count value CNT, and outputs a microcode corresponding to the count value CNT to the DSP calculation unit 33. That is, the count value CNT represents a step.

The coefficient register 37 is a register for storing the coefficients required for the operation in each step of the above-mentioned microprogram.
An area for storing 56 coefficients is set. The CPU 10 writes the coefficients into the coefficient register 37, and the interpolator 39 reads the stored coefficients. CP
U10 writes the coefficients in all 256 areas at the start of the operation, and when changing the coefficients of a specific step during the operation (in real time), rewrites the coefficients only in that area.

The interpolator 39 inputs coefficients used in the processing of each step of the microprogram to the DSP calculation unit 33. A coefficient register 37 and an interpolation control unit 38 are connected to the interpolator 39. Interpolator 39 is
In the step where the value of the coefficient is not changed, the coefficient stored in the coefficient
To supply. In addition, in the step of changing the value of the coefficient by interpolation in real time, the start value (old coefficient) read in advance from the coefficient register 37, the target value (coefficient) newly read, and the interpolation rate stored in the interpolation control unit 38, etc. , An intermediate value between the new and old coefficients is generated and input to the DSP calculation unit 33.

The interpolator 39 has 16 interpolation calculation circuits (interpolation channels), and can simultaneously change the coefficients of 16 steps in real time. Step of interpolating and changing coefficients in real time (interpolation step)
Can be arbitrarily specified by setting. As the interpolation step, a step in which the tone can be effectively changed by changing the coefficient may be selected from the microprograms operating at that time. The CPU 10 specifies the interpolation step for the DSP 21 by the coefficient register 37 and the interpolation control unit 3.
8 by inputting interpolation data.

The interpolation data includes an interpolation step number, an interpolation channel number, an interpolation rate, and the like. The interpolation channel number is one of 16 interpolation channels.
This data is transmitted and received as a channel select signal CHSEL in the DSP 21 to specify an interpolation rate and an interpolation channel at the time of writing an interpolation step. The interpolation step number is information indicating a step in which interpolation is to be performed in the designated interpolation channel. The interpolation step number is sent and received as a step select signal from the CPU 10 and latched at the position of the designated interpolation channel in the interpolation step latch 71. New coefficient is in coefficient register 3
7 is stored. The interpolation rate is transmitted and received as write data, and stored in the interpolation rate latch 70 in the interpolation control unit 38 at the position of the designated interpolation channel. The new coefficient to be interpolated is generated based on the operation amount of the assigned operation element (pedal, modulation wheel, keyboard after touch sensor, etc.). As the interpolation channel number, the number of a free channel at that time (an interpolation channel not in charge of coefficient interpolation at that time) among the 16 interpolation channels is selected. The selected interpolation channel performs the interpolation operation of the coefficient specified by the interpolation data. When the interpolation operation is completed, E
A Q signal is generated, and the EQ signal is latched at a corresponding position of the latch 54 (see FIG. 3) in the CPU interface 30. The CPU 10 can detect the end of the interpolation processing operation of the channel by reading the EQ signal of the latch 54 via the buffer 56, and can use this interpolation channel for the next new interpolation processing.

It should be noted that the interpolation data of the vacant interpolation channel may be deleted by the CPU 10 after the coefficient interpolation operation is completed, and the interpolation channel may be released to be used for other arithmetic processing.

FIG. 3 is a detailed block diagram of the CPU interface 30. The CPU interface 30
This circuit writes various data input from the CPU bus 11 to necessary timing positions (steps) of necessary registers.

The CPU 10 outputs an 8-bit address, of which the upper 3 bits are converted into a chip select signal CS by a 3-8 decoder. When the predetermined upper three bits are input to the 3-8 decoder, a CS signal is output to the DSP 21. This CS signal is input to the I / O control unit 51. In addition to the CS signal, signals such as the write signal WR and the read signal RD are input to the I / O control unit 51. When the CS signal and the WR signal are input, the I / O control unit 51 controls the data latch 50 and the address latch 52
Output a latch pulse. On the other hand, the CS signal and R
When the D signal is input, a latch pulse is output to the address latch 52 and an enable signal is output to the buffer 56.

When the latch pulse is output, the lower 5 bits of the address are latched by the address latch 52.
The lower 5 bits of this address serve as an address code for specifying various registers and the like in the DSP 21. The 5-bit address code is input to the decoder 57. Decoder 57 instructs write pulse generator 58 on the register specified by the 5-bit address code. When a trigger signal is input from I / O control section 51, write pulse generating section 58 outputs a write pulse to the designated register. The I / O control unit 51 generates a trigger signal at a predetermined timing in consideration of the number of delay clocks until the data taken into the data latch 50 reaches a predetermined register or the like. The register from which the write pulse is output includes the latch 60 of the coefficient register 37, the write control unit 62, and the interpolation control unit 38.
Write control units 81 and 82 and other control registers 4
Each register in 0, etc.

Data input from the data bus of the CPU bus 11 is latched by the data latch 50. To the data latch 50, parameters (coefficient data) to be input to the various registers 34, 37, 38, 40 and the like, including the above-described interpolation data, are input from the CPU 10. The parameters are output to the interface bus 31 as write data.

When newly designating which step coefficient of a plurality of coefficients is to be interpolated, the CPU 10
The PU interface 30 is accessed, and first, the interpolation channel number is written into the channel latch 53, and then the interpolation rate and the interpolation step number are written into the interpolation rate latch 70 and the interpolation step latch 71, respectively. By this series of writing, interpolation data is set in the interpolation control unit 38 in the following procedure.

First, the interpolation channel number written in the interpolation channel latch 53 is used as a channel selection signal CHSEL as the write control unit 81 of the interpolation control unit 38.
82. In the subsequent writing to the interpolation rate latch 70, the value of the interpolation rate to be written from the CPU 10 is supplied to the interpolation rate latch 70 via the data latch 50 as write data. CPU1
The write pulse generator 58 outputs an interpolation rate write pulse to the write controller 81 in response to a write operation in which the address of the 0 interpolation rate latch 70 is specified. At this time, a channel select signal designating an interpolation channel number is supplied to the write control unit 81, and the write control unit 81 selects one of the interpolation rate latches 70 corresponding to the designated channel number. A latch pulse is output only for the latch. That is, the interpolation rate supplied as the write data is written to one of the 16 latches of the interpolation rate latch 70 specified by the interpolation channel number.

The writing process for the interpolation step latch 71 is the same as the writing for the interpolation rate latch 70, and the interpolation step number supplied as the write data is the interpolation channel among the 16 latches constituting the interpolation step latch 71. It is written to the one specified by the number. As described above, one of the interpolation rate latch 70 and the interpolation step latch 71 is designated by the interpolation channel number, and the interpolation rate and the interpolation step are set, whereby the coefficient designated by the interpolation step by the interpolation channel is set. Preparation for interpolation is completed.

Thereafter, when a new coefficient value is written by the CPU 10 for the coefficient of the interpolation step, the coefficient is interpolated by the interpolation channel of the interpolator 39 at the speed indicated by the interpolation rate. Starts. The output value of the coefficient from the interpolator 39 gradually approaches the value of the new coefficient at the speed of the interpolation rate, with the value immediately before writing as the initial value, and the output value becomes the new value of the coefficient. The interpolation operation ends when the coefficient value matches the coefficient value, and thereafter, the matched value is held as the output value. The signal EQ generated at the end of the interpolation operation is latched by the latch 54 of the CPU
By reading this data through the selector 55 and the buffer 56, the interpolation end timing of each interpolation channel can be detected.

FIG. 4 is a detailed block diagram of the coefficient register 37. This register has a RAM 61. This RAM 61 stores the coefficients used in each operation process of 256 steps in the DSP operation unit 33. The storage area is 16 × 256 bits. This RAM6
One data input terminal is connected to the CPU interface 30 (interface bus 31) and the output terminal of the latch 60. The input terminal of the latch 60 is connected to the CPU interface 30 (interface bus 3) in the same manner as the RAM 61.
1). The latch 60 converts coefficient data sent between the CPU 10 and the interface bus 31 in 8-bit units into 16 bits.
That is, the 16-bit coefficient data is transmitted after being divided into upper 8 bits and lower 8 bits. When the coefficient register receives the upper 8 bits of the coefficient data, it latches the upper 8 bits.
Latch once. Next, when the lower 8 bits are received, the upper 8 bits latched by the latch
Write to M61. Thus, 8 / 16-bit conversion is performed.

Therefore, separate write pulses (coefficient register write pulse A and coefficient register write pulse B) are applied to the latch 60 and the RAM 61.

At the time of the first 8-bit input, a coefficient register write pulse A is input to the latch 60, and this data is latched. When the next 8 bits are input, a coefficient register write pulse B is input to the RAM 61, and the RAM 61 inputs the 16 bits of the 8 bits and the 8 bits previously latched by the latch 60, and writes them into the corresponding area.

These write pulses are generated by the write pulse generator 58 in synchronization with the input timing of the 8-bit data, and the coefficient write pulse A is directly input to the latch 60.
The coefficient register write pulse B is supplied to R through the write control unit 62.
AM61.

On the other hand, the output terminal of the RAM 61 is connected to the interpolator 39.
It is connected to the.

The read / write address of the RAM 61 is supplied to the RAM 61 via the selector 63. The selector 63 outputs the step number C output by the counter 42.
CHSEL output by NT and channel latch 53
Is entered. Of these, the step number CNT is R
AM61 is a read address, and CHSEL is a RAM61 write address. Selector 6
3 outputs CNT or CHSEL to the RAM 61 based on the select signal input from the write control unit 62.

The counter 42 performs a counting operation in synchronism with the operation step of the DSP 33. By reading the RAM 61 by the step number CNT which is the count value, the coefficient corresponding to each operation step of the DSP 33 is supplied from the RAM 61. .

On the other hand, CHSEL is a channel latch 5
When writing the coefficient into the RAM 61, the CPU 10 causes the channel latch 53 to latch a step number designating which step of the coefficient in the RAM 61 is to be rewritten before writing the coefficient into the RAM 61. When data is written to the RAM 61 after the latch operation (write pulses A and B are generated), the above-described 16-bit converted data is written to the storage position of the RAM 61 at the designated step.

The select signal output by the write control unit 62 normally selects CNT, and the CPU 10
Only when a new coefficient is written to M61, the CHSEL side is temporarily selected in synchronization with the write pulse to RAM61. The generation of the select signal and the write pulse for this write is performed by DCNT by the CNT.
It is executed at the back timing which does not prevent the reading of the coefficient of SP33.

FIG. 5 is a detailed block diagram of the interpolation control unit 38. This register monitors an operation step of the DSP operation unit 33 and interpolates a coefficient (interpolation step).
Is a circuit that outputs a signal to that effect, an interpolation rate, and the like. The interpolation step latch 71 for storing the interpolation step number and the interpolation rate latch 70 for latching the interpolation rate of each interpolation step are provided in parallel for each interpolation channel. Interpolation rate latch 70
The interpolation step latch 71 is connected to the CPU interface 30 (interface bus 31), and stores the interpolation rate and the interpolation step number input as the write data in the manner described above. Further, write control units 81 and 82 are connected to the interpolation rate latch 70 and the interpolation step latch 71, respectively. The write control unit 81 outputs a write pulse to a corresponding one of the 16 interpolation rate latches at a timing when the interpolation rate is input as the write data. Further, the writing control unit 82
At the timing when the interpolation step number is input as the write data, a write pulse is output to a corresponding one of the 16 interpolation step latches.

A write control unit 81 has a channel select signal CHSEL for designating an interpolation channel for writing.
And an interpolation rate write pulse is input from the write pulse generator 58. The write control unit 81 outputs a write pulse to a latch of a predetermined channel at a predetermined timing (timing at which an interpolation rate is supplied as write data) based on these signals. On the other hand, the channel selection signal CHSEL is input to the write control unit 82, and an interpolation step write pulse is input from the write pulse generation unit 58. The write controller 82 outputs a write pulse to a corresponding channel of the interpolation step latch at a predetermined timing (timing at which the interpolation step number is supplied as write data) based on these signals.
The write pulse of the write control unit 82 is also input to the latch 75. Sixteen latches 75 are provided corresponding to the 16 interpolation channels, and store that new interpolation data has been set in the interpolation channel.

The interpolation step number latched by the interpolation step latch 71 in the above operation is input to the comparator 73. Sixteen comparators 73 are provided in parallel corresponding to each interpolation step latch 71 (interpolation channel). Each comparator 73 compares the interpolation step number latched in each interpolation step latch 71 with the value of the CNT at that time (current operation step). If any one of the comparators matches the interpolation step number with CNT, the comparator outputs a match signal. This coincidence signal is input to the encoder 74 and the coincidence detection circuit 78,
The signal is input to the clear terminal of the latch 75 and the control terminal of the gate 76.

The encoder 74 converts the channel number of the coincidence signal into 4-bit binary data and outputs it as an interpolation channel number (processing channel number) ICH on which the interpolation operation is to be performed at present. This ICH is an interpolator 39
And input to the selector 72. The selector 72 sets the interpolation rate of the channel corresponding to ICH in the interpolation rate latch 70 as IRATE, and
9 is output. The coincidence detection circuit 78 outputs a coincidence pulse IP to the interpolator 39 when any one of the comparators 73 outputs a coincidence signal. The coincidence pulse IP generated by the coincidence detection circuit 78 is output to the same line regardless of the channel to which the coincidence signal is input.

The latch 75 is connected to a write detection circuit 77 via a gate 76. Interpolation step latch 7
When a write pulse is output to any one channel, one of the 16 latches 75 provided in parallel at the same time corresponds to the interpolation channel to which the write pulse has been output.
Each time the pulse is latched. When the operation step number CNT and the written interpolation step number match for the first time (in the first interpolation processing operation) after the generation of the write pulse, the latched pulse is a match signal output from the comparator 73 and the gate 76 is output. Is output to the write detection circuit 77 by opening. The write detection circuit 77 generates a coefficient change pulse CC when a pulse is input, and
Output to The coefficient change pulse CC generated by the write detection circuit 77 is the same regardless of the channel to which the pulse is input. Here, as described above, the coincidence signal of the comparator 73 also serves as the clear signal of the latch 75 and the control signal of the gate 76 (the gate 76 is triggered by the rising edge of the pulse, and the latch 75 is the clear signal The pulse is input to the write detection circuit 77 only once when the comparator 73 outputs a match signal immediately after the write control unit 82 outputs a write pulse. Therefore, the coefficient change pulse CC is output only at the time of outputting the first coincidence pulse IP immediately after writing the interpolation step number. This coefficient change pulse C
C is input to the interpolator 39 and functions as a pulse for discarding the contents stored so far and setting the current coefficient of the step indicated by the newly set interpolation step number as an initial value.

FIG. 6 is a detailed block diagram of the interpolator 39. The coefficient data input from the coefficient register 37 is input to the input terminals 0 of the comparator 90, the selector 93 and the selector 101. The other input terminal 1 of the selector 101 is connected to a dual port RAM 96 via a delay. When the select signal is not input to the selector 101 (at the time of non-interpolation: 0), the coefficient input from the coefficient register 37 is output to the DSP calculation unit 33 as it is. When the select signal is input (at the time of interpolation: 1), the data of the dual port RAM 96 is transferred to the DSP calculation unit 33.
Output to

The gate 106 is connected to the select signal terminal of the selector 101. The gate 106 receives a * CC signal obtained by inverting the coincidence pulse IP and the coefficient change pulse CC. Therefore, the timing at which the coincidence pulse IP is not output (at the time of non-interpolation) and the coincidence pulse I
The timing at which both P and the coefficient change pulse CC are output, that is, in the first interpolation processing when the interpolation channel performs interpolation processing with new interpolation data, the coefficient data input from the coefficient register is directly used by the DSP.
Output to the calculation unit 33. That is, in the interpolation step immediately after the new interpolation step is set, the current value of the coefficient of the step is output from the selector 101 for the time being. This value is written as initial data at the position of the interpolation channel in the RAM 96 by the operation of the selector 93 described later. The interpolation channel is I
Specified by CH. Timing at which the coincidence pulse IP is output and the coefficient change pulse CC is not output, ie,
In the second and subsequent interpolation processing timings, the selector 101
Outputs the data of the dual port RAM 96 delayed by one to the DSP operation unit 33.

A circuit for increasing the coefficient toward the target value includes a comparator 90, a sign control circuit 91, an adder 92,
It comprises a selector 93, the dual-port RAM 96, a write pulse generator 99, and a plurality of delays appropriately provided for adjusting the timing of signals. The comparator 90 compares the current (interpolated) coefficient value A (the value read from the dual port RAM 96) with the target value B (new coefficient data input from the coefficient register),
This circuit outputs a coincidence signal EQ when almost coincident, and outputs a non-coincidence signal “A> B” when A> B. Comparator 9
The comparator control data CP from the rate decoder 102 is set to 0.
C is input. The comparator control data CPC is data of the same kind as the step amount. The comparator 90 sets the target when the next step is performed when the difference between the coefficient being interpolated and the target value (new coefficient) becomes smaller than the step amount. Since the value exceeds the value, the coincidence signal EQ is output.

The rate decoder 102 receives a 3-bit interpolation rate IRATE from the interpolation control unit. Based on the value of the interpolation rate IRATE, the rate decoder 102 refers to the interpolation rate table shown in FIG. When IRATE is 7 (111), since it is specified that the target value is directly output without interpolation, DIR is output without outputting the step amount.
Outputs an IRECT signal. This signal is input to the gate 97.

The comparator control data CPC is equal to one of the increments determined by the interpolation rate table shown in FIG.
Is data indicating a bit (digit) in which is set. When the coefficient being interpolated is incremented by using this increment, bits lower than this bit do not change.
For 0, it is sufficient to compare only the bits higher than this, and when the difference becomes the value of the bit where 1 is set, it is only necessary to output the coincidence signal EQ.

The comparator 90 outputs a mismatch signal “A> B” only when A> B, and this signal is input to the sign control circuit 91. The code control circuit 91 receives the step amount from the rate decoder 102 as described above. The sign control circuit 91 determines whether the step amount is positive or negative based on the mismatch signal and outputs it to the adder 92. That is, when the mismatch signal is output, the target value is below (A>
B), the step amount is made negative, and when the mismatch signal is not output, the target value is above (A <B), so that the step amount is made positive and output to the adder 92. It should be noted that no mismatch signal is output when A ≒ B, but in this case, since the EQ signal is output and the selector 93 is switched to use no stepping amount, the sign does not matter.

The other input terminal of the adder 92 is connected to the dual port RAM 9 similarly to the terminal A of the comparator 90.
The value (current coefficient value) output from 6 is input. The adder 92 adds (subtracts) the step amount to this coefficient value and outputs a new stepped coefficient value. This interpolation value is input to the input terminal 0 of the selector 93. The coefficient data output from the coefficient register is input to the input terminal 1 of the selector 93. An OR circuit 97 is connected to a select signal terminal of the selector 93. The OR circuit 97 receives a coefficient change pulse CC, a DIRCT signal, and a coincidence signal EQ. When any one of these signals is input, the selector 93 inputs the coefficient data supplied from the coefficient register 37 to the write data terminal of the dual port RAM 96, and when no signal is input, the adder 92
Is input to the dual port RAM 96. When the coefficient change pulse CC is input, it is the start of a new interpolation processing operation in the channel. Therefore, the input of the selector 93 is performed in order to replace the interpolation data up to that time with a new interpolation data coefficient (old coefficient). Input coefficient data from terminal 1. The DIRECT signal is a signal corresponding to the maximum interpolation rate, and when this signal is output, it is directly switched from the old coefficient to the new coefficient without interpolation. Therefore, in this interpolation processing operation, the selector is always switched to the coefficient data side by the DIRECT signal, and the operation is performed at the timing of the next interpolation step after the coefficient data input from the coefficient register 37 is rewritten to the new coefficient. It is going to end. When the coincidence signal EQ is output, the coefficient data, which is the target value of the interpolation, is taken into the dual port RAM 96, and the interpolation processing is completed. In the interpolation step, the value of the coefficient data is output each time.

The write pulse for the dual port RAM 96 is based on the coincidence pulse IP.
9 occurs. The coincidence channel ICH is supplied to the dual port RAM 96 as a write address and a read address. To store the interpolated coefficients at the same address, the write address is supplied after two delays from the read address.

When the comparator 90 outputs the coincidence signal EQ, the interpolation operation ends. The coincidence signal EQ indicating the end of this interpolation processing operation is output from the CPU interface 30
Is input to the latch 54. Referring to FIG.
Are provided in parallel (16 bits) for each interpolation channel. The data of the latch 54 is input to the selector 55. The address decoder 57 is connected to the selector 55, and the selector 55 selects one of the upper 8 bits and the lower 8 bits of the 16-channel latch 55 according to the signal of the decoder 57. The selected 8-bit data is stored in the buffer 56. The data stored in the buffer 56 is read by the CPU 10 according to the enable signal of the I / O control unit 51, whereby the CPU
10 can determine which interpolation channel has completed the interpolation processing operation.

In the description of the interpolator 39 (FIG. 6), the description of the delay circuit is omitted, but in order to match the operation timings of the respective parts, a delay of a tone signal in sampling clock units, a delay in CNT clock units, A delay of a system clock φ unit is appropriately inserted.

With the above configuration, of the coefficients used for each step of the microprogram, only the coefficients specified by the interpolation data are changed (interpolated) in real time, and D
Output to the SP calculation unit 33. The operation of the DSP 21 will be described in time series as follows.

Prior to the performance (when the power is turned on or when the tone is designated, when the effect to be given by the DSP is selected, etc.), the microprogram of the effect to be given is set.
Coefficient data used for each of the six steps is sequentially stored in the RAM 61. This storage operation is from the 0th step to
This is performed by inputting the coefficient of the 256th step into the RAM 61.

With the start of the performance operation, the DSP 2
1 also works. The musical tone waveform data is fetched from the input register 36, and the DSP arithmetic unit 33 uses the coefficients output from the interpolator 39 for the musical tone waveform data, and performs the performance processing specified by the microprogram set in the microprogram memory 43. And outputs it to the DAC 23 via the output register 44.

At the same time, of the 256 step coefficients, one of 16 interpolation channels is used for the coefficient specified by the performer to be controlled in real time by a performance operator such as a pedal or a wheel during the performance. Is set in the latch corresponding to the assigned channel in the interpolation control unit 38, and an interpolation step number indicating the step of the coefficient and an interpolation rate according to the operator controlling the value of the coefficient are set (interpolation data Setting). In addition,
As for the coefficient for which the value is variably controlled in real time, when a new coefficient value is supplied, noise such as a click noise may occur when the value is suddenly changed to that value. It is desirable to set the interpolation data so that When the number of coefficients to be controlled in real time is large and the number of interpolation channels is insufficient, the CPU 10 is allowed to perform interpolation for channels for which interpolation channels could not be prepared, or rounds up processing of interpolation channels for coefficients with little time change in real time control. It is preferable to perform processing such as passing the coefficient to a coefficient that changes frequently.

When an operation element such as a pedal or a wheel is operated during a performance, the CPU 10 determines a new coefficient corresponding to the operation amount of the operation element for the coefficient set to be controlled by the operated operation element. Is written in the coefficient register 37 at the step position of the coefficient. If the interpolation has been set for any of the interpolation channels for the coefficient, the CPU 10 may write the coefficient to the coefficient register 37 without any concern even if the value of the coefficient greatly changes from the original value. Even a large change is supplied to the DSP calculation unit 33 as a coefficient that changes smoothly by the operation of the interpolator 39.

The method of changing and controlling the coefficient in real time is not a control in accordance with the performance operator, but a time change of the coefficient is set in advance starting from the time of generation or end of a musical tone, and the setting is performed. May be sequentially changed to the coefficient value in accordance with In this case, at the start of each state, the change rate of the state is interpolated by the interpolation channel of the interpolation channel for which the coefficient is being controlled, following the well-known "state control method by the CPU for generating an envelope using an interpolator". The target value is supplied to the rate latch 70, and the target value is supplied to the coefficient register 37 as a new coefficient. In this case, the CPU 10 detects the end of each state by reading the EQ signal of the corresponding interpolation channel of the latch 54, and performs control while sequentially proceeding with the states.

[0059] As for the allocation of the interpolation channel for the coefficients, in addition to set prior to the performance operation to each tone and effects, also conceivable going allocated in real time to the performance operator for which the input .

The interpolation operation can be performed on 16 channels in parallel. The correspondence between the interpolation step and the interpolation channel is arbitrary.

It should be noted that the interpolator 39 performs the interpolation operation only in a maximum of 16 steps out of 256 steps.
Therefore, an arithmetic circuit such as an adder and a comparator may be used as an auxiliary arithmetic circuit of the DSP arithmetic unit 33 when the interpolator 39 is idle. This can be achieved by setting the microcode as such. In this case, whether or not the idle time can be determined can be determined based on whether or not the coincidence pulse IP is output. DSP operation unit
Reference numeral 33 corresponds to the calculation means of the form. Coefficient register 3
7 corresponds to the coefficient storage means of the present invention. CPU interface
Coefficient changing operation executed by the face 30 and the CPU 10
Corresponds to the coefficient changing means of the present invention. Interpolator 39 is
Corresponds to the interpolation means of the invention. The interpolation control unit 38
It corresponds to the light assignment means. Select of the interpolator 39
And the signal system for switching this selector.
Corresponds to the direct supply means of the invention.

[0062]

As described above, according to the present invention, a part of a plurality of coefficients is designated and the number of complements is smaller than the number of coefficients.
Since the interpolation can be smoothly performed by allocating to the inter-channel, the coefficient can be effectively changed with a minimum hardware configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of an electronic musical instrument to which the present invention is applied;

FIG. 2 is a block diagram of a DSP of the electronic musical instrument.

FIG. 3 is a block diagram of a CPU interface of the DSP.

FIG. 4 is a block diagram of a coefficient register of the DSP.

FIG. 5 is a block diagram of an interpolation control unit of the DSP.

FIG. 6 is a block diagram of an interpolator of the DSP.

FIG. 7 is a diagram showing a relationship between an interpolation rate and a step amount used in the DSP.

[Explanation of symbols]

30-CPU interface 31-DSP operation unit 37-coefficient register 38-interpolation control unit 39-interpolator 61-RAM (for storing coefficients) 70-interpolation rate latch 71-interpolation step latch

Claims (1)

(57) [Claims] An arithmetic unit for performing a waveform processing operation using a plurality of coefficients; a coefficient storage unit for storing the plurality of coefficients; and a value of one or a plurality of coefficients stored in the coefficient storage unit. Coefficient changing means for changing, coefficient specifying means for specifying a part of coefficients among a plurality of coefficients stored in the coefficient storage means, and input coefficient changed by the coefficient changing means.
When the interpolation means having channel number smaller than the number of the arithmetic means and said plurality of coefficients interpolated channel supplied to while interpolating the value after the change from the value before the change, the coefficients designated by the coefficient specifying means Allocating means for selectively inputting to each of the interpolation channels, and a coefficient not specified by the coefficient specifying means.
And a direct supply means for supplying the operation means directly .