CN100492256C

CN100492256C - Digital signal processing device

Info

Publication number: CN100492256C
Application number: CNB2007100908666A
Authority: CN
Inventors: 浦纯也
Original assignee: Yamaha Corp
Current assignee: Yamaha Corp
Priority date: 2006-04-12
Filing date: 2007-04-10
Publication date: 2009-05-27
Anticipated expiration: 2027-04-10
Also published as: CN101055492A; KR100899258B1; JP2007280310A; KR20070101779A; JP4404065B2

Abstract

A digital signal processing device has: program counter generating address data in order; coefficient memory memorizing plural coefficient which processes output corresponding to the address data when the chip selecting signal is effective electrical level; program memory memorizing plural orders, which processes output corresponding to the address data; and operation part operating prescriptive operation according to the order output from the program memory. In addition, the invention confirms whether setting the chip selecting signal to be effective electrical level based on the order output from the program memory. It substitutes the address data and supports the prescriptive value (''0'') to the coefficient memory when the chip selecting signal is inactive electrical level.

Description

Digital signal processing device

Technical field

The present invention relates to a kind of digital signal processing device that in electronic equipments such as mobile phone, information terminal and personal computer, uses, particularly a kind of digital signal processing device that is applicable in the audio frequency apparatus.

To the present invention is based on Japan's number of patent application of filing an application on April 12nd, 2006 be 2006-109233 application and require its right of priority, quotes its content here.

Background technology

At present, in various electronic equipments, use DSP (Digital Signal Processor) as digital signal processing device.As everyone knows, DSP has following function: for sampling period of length at the appointed time realizes using the convolution algorithm (convolution operation) of the coefficient sequence of regulation to input audio sample sequence (input audio samplestring), carry out various calculation process such as quadrature computing or additive operation repeatedly.At present, DSP is equipped in the small-sized mobile electronic devices such as mobile phone, but because this small-sized mobile electronic device is by needs storage batteries driving at any time, therefore for the small-sized electronic equipment that carries is worked long hours, wish that the element that carries is a power conservation type in this small-sized mobile electronic device.Open the example of the DSP that discloses this realization power saving in 2000-No. 57122 the spy.

Inside at above-mentioned DSP is provided with: coefficient memory, the coefficient that uses in its storage computing; Address (read address) generative circuit, it generates the address of reading to this coefficient memory; And operational part, it carries out signal Processing, usually, reads the address by supplying with to coefficient memory from address generating circuit, and reads in the coefficient that uses the signal Processing from this coefficient memory, thereby carry out signal Processing based on the coefficient that reads in operational part.But, in operational part, exist do not use new coefficient and carry out signal Processing during, in existing DSP, read the address also continuing to carry out during this period to supply with to coefficient memory from address generating circuit, have the problem of waste electric power.

Summary of the invention

The objective of the invention is to, in digital signal processing devices such as DSP, further reduce its power consumption.

The digital signal processing device that the present invention relates to possesses: programmable counter, and it produces address date successively, and output repeatedly; Coefficient memory, it has a plurality of zones and stores a plurality of coefficients, and when chip select signal was significant level, this coefficient memory was corresponding with reading command, and output is stored in by the coefficient the zone of the address date appointment of exporting from programmable counter; Program storage, it has a plurality of zones and stores a plurality of orders, and this program storage output is stored in by the order the zone of the address date appointment of exporting from programmable counter; And operational part, it is according to the order from program storage output, the computing that puts rules into practice.Here, based on order from program storage output, carry out whether chip select signal being made as the switching of significant level, be under the situation of non-significant level at chip select signal simultaneously, replace address date and setting (for example, " 0 ") is supplied with to described coefficient memory.In addition, a plurality of instructions that are stored in a plurality of zones in the program storage comprise the coefficient memory permission bits respectively, according to this coefficient memory permission bits, carry out whether will being made as the switching of significant level to the chip select signal that coefficient memory is supplied with.

In the above-described configuration,, therefore do not need to be provided with in addition to read address production electric circuit, can correspondingly reduce power consumption owing to will supply with to coefficient memory as reading the address from the address date of programmable counter output.In addition, owing to is unit with the order, carry out whether chip select signal being made as the switching of significant level, therefore carrying out when not needing to read the order of coefficient, to be made as non-significant level to the chip select signal that coefficient memory is supplied with, power consumption that thus can the rejection coefficient storer.

Description of drawings

Accompanying drawing is the block diagram of the structure of the related digital signal processing device of expression the preferred embodiments of the present invention.

Embodiment

With reference to the accompanying drawings, the related digital signal processing device of the preferred embodiments of the present invention is at length described.

Accompanying drawing is the block diagram of the structure of the specific DSP of the expression digital signal processing device that present embodiment is related.In DSP shown in Figure 1, programmable counter 1 was counted its count value from " 0 " to " N-1 " repeatedly every the sampling period of regulation duration, thereby the output count value is as address date ADR.Address date ADR supplies with to program RAM 2 as reading the address, simultaneously via selector switch 5, supplies with to coefficients R AM4 as reading the address.

Program RAM 2 has a plurality of zones corresponding with 0～address, address N-1, the order of N the step that storage should be carried out during 1 sampling period in each zone.Be stored in the order in each zone of program RAM 2, comprise coefficients R AM permission bits (coefficient RAM enable bit) EN, whether this coefficients R AM permission bits EN is used to specify will be made as significant level to the chip select signal CS of coefficients R AM4.Program RAM2 output is stored in by the order in the zone of address date ADR appointment.When the coefficients R AM permission bits EN that comprises is " 1 ", will be made as significant level (being the H level) to the chip select signal CS that coefficients R AM4 supplies with from the order of program RAM2 output.When coefficients R AM permission bits EN is " 0 ", chip select signal CS is made as non-significant level (being the L level).Command decoder 3 is explained the order of reading from program RAM 2, thereby output is used for exectorial various control signal to the reading command of coefficients R AM4 etc.

Operational part 6 is carried out the computing that is used to realize the specified signal processing with corresponding from the control signal of command decoder 3 outputs.With general known DSP in the same manner, the DSP that present embodiment relates to can use from the coefficient sequence of coefficients R AM 4 outputs, the sample sequence of the signal processing results that the input audio sample sequence that provides from the outside or expression have been carried out among this DSP is carried out convolution algorithm.In order to realize this convolution algorithm, multiplier 61, totalizer 62 and register 63 are set in operational part 6.

The data of the intermediate result of the signal Processing that the input audio samples that the 7 temporary transient storages of RAM group are supplied with via input part 8, simultaneously temporary transient storage representation are carried out by operational part 6 or represent the output audio sampling of the net result of this signal Processing.The input audio sample that temporarily is stored in the RAM group 7 is supplied with to operational part 6.In addition, with the output audio sampling that temporarily is stored in the RAM group 7, export to the outside via efferent 9.

Coefficients R AM 4 is used for being stored in the coefficient that convolution algorithm uses, and it has a plurality of zones corresponding with 0～address, address N-1.Each regional memory contents is corresponding with each regional memory contents of program RAM 2 among the coefficients R AM 4.That is, under the situation of the order of the computing of storage indication execution coefficient of performance, this coefficient storage is in the k of the address of coefficients R AM4 in the k of the address of program RAM 2.At the chip select signal CS that supplies with to coefficients R AM 4 is under the situation of significant level (H level), and selector switch 5 will read the address from the address date ADR conduct of programmable counter 1 output, supply with to coefficients R AM4.In addition, be under the situation of non-significant level (L level) at chip select signal CS, selector switch 5 selects fixed value " 0 " as reading the address, supplies with to coefficients R AM 4.With general known RAM in the same manner, coefficients R AM 4 has and is used to read its storage data and to the sensor amplifier of outside output, at chip select signal CS is under the situation of significant level, to the sensor amplifier supply capability, on the other hand, at chip select signal CS is under the situation of non-significant level, disconnects to the electric power of sensor amplifier supplying with.In addition, chip select signal CS be in the state of significant level to allowing to read under the situation that terminal RE supplies with reading command, sensor amplifier is driven, thus coefficient is read in the zone corresponding with reading the address from coefficients R AM 4, and to operational part 6 supplies.

Outside the foregoing circuit key element, DSP possesses and is used for corresponding with the data that provide from the outside and refreshes the circuit of the memory contents of coefficients R AM 4 or program RAM 2, but because and the correlativity between purport of the present invention a little less than, therefore omit its diagram and explanation.

In having the DSP of above-mentioned formation, from the address date ADR of programmable counter 1 output, supply with to program RAM 2 as reading the address, thus the order of from program RAM 2 reads zone by address date ADR appointment, storing.In this order is that indication is read coefficient and carried out under the situation of calculation process from coefficients R AM 4, and the coefficients R AM permission bits EN that comprises in this order is set at " 1 ".In this case, the chip select signal CS of coefficients R AM 4 is become significant level, selector switch 5 will be supplied with to coefficients R AM 4 from the address date ADR of programmable counter 1 output as reading the address.In addition, be that indication is read coefficient and carried out under the situation of calculation process from coefficients R AM 4 in the order that provides by program RAM 2, command decoder 3 is supplied with reading command to coefficients R AM 4.Thus, the coefficient of from coefficients R AM4 reads in zone by address date ADR appointment, storing, thus in operational part 6, carry out the calculation process of using this coefficient.

On the other hand, not to read coefficient from coefficients R AM 4 but indication is carried out under the situation of calculation process in the order that provides by program RAM 2, the coefficients R AM permission bits EN that comprises in this order is set at " 0 ".In this case, the chip select signal CS of coefficients R AM 4 is become non-significant level, selector switch 5 is not selected to replace from the address date ADR of programmable counter 1 output, and fixed value " 0 " is exported as reading the address.Thus, in coefficients R AM 4, do not carry out read operation (read operation), thereby can avoid waste electric power.

As mentioned above, according to present embodiment,, supply with to coefficients R AM 4 owing to will read the address from the address date ADR conduct of programmable counter 1 output, therefore do not need to be provided in addition this coefficients R AM 4 produced and read the circuit of address, can correspondingly reduce power consumption.In addition, in the present embodiment,, will be made as significant level, and therefore can reduce the power consumption of this coefficients R AM 4 the chip select signal CS of coefficients R AM 4 owing to only reading the order that coefficient is carried out calculation process from coefficients R AM4 for indication.

In addition, only when chip select signal CS is non-significant level, select fixed value " 0 " as reading the address by selector switch 5.Therefore, can reduce the power consumption of the address decoder (not shown) that is arranged on coefficients R AM 4 inside.In addition, coefficients R AM 4 is constituted, address decoder is not worked when chip select signal CS is non-significant level, does not need selector switch 5 in this case.

In the present embodiment, use RAM, still also can use other storeies such as ROM as the storage part that is used for storage coefficient or order.In addition, in the present embodiment, from the order of program RAM 2 outputs, comprising coefficients R AM permission bits EN, but not necessarily this specific command bit is being included in the order.That is, also can be based on the code that comprises in the order, command decoder 3 judges whether that the coefficient that carries out from coefficients R AM 4 reads, and according to its judged result, the level that carries out chip select signal CS switches.

And the present invention is not limited to present embodiment, in the invention scope that can stipulate in the claims of enclosing, carries out various changes.

Claims

1. digital signal processing device, it possesses:

Programmable counter, it produces address date successively, and output repeatedly, and the current address data are supplied with to coefficient memory and program storage simultaneously;

Coefficient memory, it has a plurality of zones and stores a plurality of coefficients, and when chip select signal was significant level, this coefficient memory was corresponding with reading command, and output is stored in by the coefficient in the zone of described current address data appointment;

Program storage, it has a plurality of zones and stores a plurality of orders, and this program storage output is stored in by the order in the zone of described current address data appointment; And

Operational part, it is according to the order from the output of described program storage, the computing that puts rules into practice,

Based on order from described program storage output, carry out whether described chip select signal being made as the switching of significant level, be under the situation of non-significant level simultaneously, replace described current address data and setting is supplied with to described coefficient memory at described chip select signal.

2. according to the digital signal processing device described in the claim 1,

The a plurality of orders that are stored in a plurality of zones in the described program storage comprise the coefficient memory permission bits respectively, according to this coefficient memory permission bits, carry out whether will being made as the switching of significant level to the described chip select signal that described coefficient memory is supplied with.

3. digital signal processing device according to claim 1 and 2,

Described setting is " 0 ".