KR100899258B1 - Digital signal processing device - Google Patents

Abstract

The digital signal processing apparatus stores a program counter which sequentially generates address data, a coefficient memory for storing a plurality of coefficients and outputting the chip select signal in accordance with the address data when the chip select signal is at an active level, and storing a plurality of instructions. A program memory to output in accordance with the data, and an operation unit for performing a predetermined operation in accordance with the command output from the program memory. Further, based on the command output from the program memory, it is determined whether or not to make the chip select signal active level. On the other hand, when the chip select signal is inactive level, a predetermined value ("0") is used instead of the address data. Is supplied to the coefficient memory.

Program memory, address data, active level, inactive level

Description

Digital signal processing device {DIGITAL SIGNAL PROCESSING DEVICE}

1 is a block diagram showing the configuration of a digital signal processing apparatus according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: program counter

2: program RAM

3: command decoder

5: selector

[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-57122

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital signal processing apparatuses applied to electronic devices such as mobile phones, information terminals, and personal computers, and more particularly, to digital signal processing apparatuses suitable for audio equipment.

This application claims priority based on Japanese Patent Application No. 2006-109233 of an application on April 12, 2006, and uses the content here.

DESCRIPTION OF RELATED ART Conventionally, DSP (Digital_Signal_Processor) is used for various electronic devices as a digital signal processing apparatus. As is well known, the DSP performs various operations, such as integration and addition, for realizing a convolution operation using a predetermined coefficient sequence for an input audio sample string (input_audio_sample_string) for each sampling period of a predetermined length of time. It has the function of repeating the process. At present, the DSP has been mounted in small portable electronic devices such as mobile phones. However, since these small portable electronic devices are driven by batteries which need to be charged at any time, in order to operate the small portable electronic devices for a long time, It is preferable that the element to be mounted is a power saving type. Patent Document 1 discloses an example of a DSP that realizes power saving.

Inside the DSP, a coefficient memory that stores coefficients used for calculation, an address generation circuit for generating a read address for the coefficient memory, and an arithmetic unit for performing signal processing are usually provided. By supplying a read address from the address generation circuit to the coefficient memory, the coefficients used for signal processing are read from the coefficient memory, whereby signal processing based on the coefficients read by the calculation unit is executed. However, even though there is a period during which the signal processing is executed without using a new coefficient in the calculation unit, in the conventional DSP, even in this period, the supply of the read address from the address generation circuit to the coefficient memory is continued. There was a problem that it is wasted.

An object of the present invention is to further reduce the power consumption in a digital signal processing apparatus such as DSP.

The digital signal processing apparatus according to the present invention is a program counter for sequentially generating and repeatedly outputting address data, and a coefficient memory for storing a plurality of coefficients having a plurality of areas, the program counter when the chip select signal is at an active level. A coefficient memory for outputting, according to a read command, coefficients stored in an area designated by address data outputted from the program; A program memory for outputting a command stored in the program, and an operation unit for executing a predetermined operation in accordance with the command output from the program memory. Here, based on the command output from the program memory, the chip select signal is switched to the active level, and when the chip select signal is at the inactive level, a predetermined value (for example, For example, "0") is supplied to the coefficient memory. Each of the plurality of instructions stored in the plurality of areas in the program memory includes a coefficient memory enable bit, and according to the coefficient memory enable bit, whether or not the chip select signal supplied to the coefficient memory is set to an active level. Switch whether or not.

In the above configuration, since address data output from the program counter is supplied to the count memory as the read address, it is not necessary to provide a read address generation circuit separately, so that power consumption can be reduced. Since the chip select signal is switched to the active level in units of instructions, the chip select signal supplied to the coefficient memory is set to the inactive level at the time of execution of an instruction not requiring coefficient reading. Thus, power consumption of the counting memory can be suppressed.

<Example>

With reference to the accompanying drawings, a digital signal processing apparatus according to a preferred embodiment of the present invention will be described in detail.

Fig. 1 is a block diagram showing the configuration of a DS that embodies the digital signal processing apparatus according to the present embodiment. In the DS shown in Fig. 1, the program counter 1 repeatedly counts the count value from &quot; 0 &quot; to &quot; N-1 &quot; for each sampling period of a predetermined length of time, thereby outputting the count value as the address data ADR. . The address data ADR is supplied as a read address to the program RAM 2, and is supplied as a read address to the coefficient RAM 4 through the selector 5.

The program RAM 2 has a plurality of areas corresponding to addresses 0 to N-1, and stores N step instructions in each area to be executed during one sampling period. The instructions stored in each area of the program RAM (2) include a coefficient RAM enable bit (EN) which specifies whether or not the chip select signal CS with respect to the coefficient RAM4 is set to the active level. have. The program RAM 2 outputs an instruction stored in the area designated by the address data AD. When the coefficient RAM enable bit EN included in the instruction output from the program RAM 2 is "1", the chip select signal CS supplied to the coefficient RAM 4 is set to an active level (ie, H level). When the coefficient RAM enable bit EN is "0", the chip select signal is set to the CS inactive level (that is, the L level). The command decoder 3 interprets the command read from the program RAM 2, and thereby outputs various control signals for executing the command, such as a read command to the coefficient RAM 4.

The calculating part 6 performs the operation which implement | achieves a predetermined signal process according to the control signal output from the instruction decoder 3. Similarly to the generally known DSP, the DSP according to the present embodiment uses a coefficient string output from the coefficient RAM 4 to output an input audio sample string supplied from the outside, or a result of signal processing already performed in this DSP. You can perform a convolution operation on the sample column that represents. In order to realize this convolution operation, the computing unit 6 is provided with a multiplier 61, an adder 62, and a register 63.

The RAM group 7 temporarily stores the input audio sample supplied through the input unit 8, and displays data indicating an intermediate result of the signal processing executed by the calculating unit 6, or a final result of the signal processing. The stored output audio sample is temporarily stored. The input audio sample temporarily stored in the RAM group 7 is supplied to the calculation unit 6. In addition, the output audio sample temporarily stored in the RAM group 7 is output to the outside via the output unit 9.

The coefficient RAM 4 stores coefficients used for the convolution operation and has a plurality of areas corresponding to addresses 0 to N-1. The stored contents of each area in the coefficient RAM 4 correspond to the stored contents of each area of the program RAM 2. That is, when an instruction for instructing execution of an operation using a coefficient is stored at the address of the program RAM 2, the coefficient is stored at the address of the coefficient RAM 4. When the chip select signal CS supplied to the coefficient RAM 4 is the active level (H level), the selector 5 supplies the address data ADR output from the program counter 1 to the coefficient RAM 4 as a read address. . In addition, when the chip select signal CS is inactive level (L level), the selector 5 selects the fixed value "0" and supplies it to the coefficient RAM 4 as a read address. Like the generally known RAM, the coefficient RAM 4 has a sense amplifier for reading the stored data and outputting it to the outside. When the chip select signal CS is at the active level, power is supplied to the sense amplifier. When the chip select signal CS is at an inactive level, power supply to the sense amplifier is cut off. In addition, when the read command is supplied to the read enable terminal RE while the chip select signal CS is in the active level, the sense amplifier is driven, whereby the coefficient is read from the area corresponding to the read address in the coefficient RAM 4. And is supplied to the calculating part 6.

In addition to the above circuit elements, the DSP is provided with a circuit for rewriting the contents of the coefficients RAM 4 and the program RAM 2 in accordance with data provided from the outside. However, the DSP is less relevant to the gist of the present invention. Omit the illustration or description.

In the DSP having the above-described configuration, the address data ADR output from the program counter 1 is supplied to the program RAM 2 as a read address, whereby the instruction stored in the area designated by the address data AD from the program RAM 2 is stored. Is read. When the instruction is to instruct to read a coefficient from the coefficient RAM 4 and execute arithmetic processing, the coefficient RAM enable bit EN included in this instruction is set to "1". In this case, the chip select signal CS with respect to the coefficient RAM 4 becomes an active level, and the selector 5 supplies the address data ADR output from the program counter 1 to the coefficient RAM 4 as a read address. In addition, when the instruction supplied from the program RAM 2 is to instruct to read the coefficient from the coefficient RAM 4 to execute the arithmetic processing, the instruction decoder 3 issues a read instruction to the coefficient RAM 4. Supply. Thereby, the coefficient stored in the area | region designated by the address data ADR is read from the coefficient RAM 4, and the arithmetic process using this coefficient is performed by the calculating part 6 by this.

On the other hand, when the instruction supplied from the program RAM2 instructs execution of arithmetic processing without reading the coefficient from the coefficient RAM4, the coefficient RAM enable bit EN included in this instruction is set to "0". do. In this case, the chip select signal CS with respect to the coefficient RAM 4 becomes inactive level, and the selector 5 does not select the address data ADR output from the program counter 1, but instead the fixed value "0". Is output as a read address. As a result, the read operation is not performed in the coefficient RAM 4, thereby preventing unnecessary power consumption.

As described above, according to this embodiment, since the address data ADR output from the program counter 1 is supplied to the coefficient RAM 4 as a read address, a circuit for generating a read address for this coefficient RAM 4 is provided. There is no need to install separately, and the power consumption can be reduced by that much. In addition, in the present embodiment, since the chip select signal CS to the coefficient RAM 4 becomes the active level only for the instruction instructing to read the coefficient from the coefficient RAM 4 to execute the arithmetic processing, this coefficient RAM (4) power consumption can be reduced.

In addition, the fixed value "0" is selected as the read address by the selector 5 only when the chip select signal CS is at an inactive level. Therefore, the power consumption of the address decoder (not shown) provided inside the coefficient RAM 4 can be reduced. It is also possible to configure the coefficient RAM 4 so that the address decoder does not operate when the chip select signal CS is inactive level, in which case the selector 5 becomes unnecessary.

In this embodiment, although RAM is used as a storage unit for storing coefficients and instructions, other memories such as ROM may be used. In addition, in the present embodiment, although the coefficient RAM enable bit EN is included in the instruction output from the program RAM 2, it is not necessary to include such a specific bit in the instruction. That is, it is determined whether or not the instruction decoder 3 reads the coefficient from the coefficient RAM 4 based on the code included in the instruction, and level switching of the chip select signal CS is performed in accordance with the determination result. It is also possible.

In addition, this invention is not limited to a present Example, A various change can be implement | achieved within the scope of the invention prescribed | regulated to the attached claim.

As mentioned above, according to this invention, the power consumption can be further reduced by digital signal processing apparatuses, such as DSP.

Claims (3)

A program counter that sequentially generates and repeatedly outputs address data; A coefficient memory for storing a plurality of coefficients having a plurality of regions, the coefficient memory for outputting coefficients stored in an area designated by address data output from the program counter according to a read command when the chip select signal is at an active level; , A program memory having a plurality of areas and storing a plurality of instructions, comprising: a program memory for outputting a command stored in an area designated by address data output from the program counter; An operation unit configured to execute a predetermined operation according to an instruction output from the program memory, On the basis of the command output from the program memory, the chip select signal is switched to an active level, and when the chip select signal is inactive, a predetermined value is substituted for the address data. Digital signal processing apparatus adapted to supply to the counting memory. The method of claim 1, Each of the plurality of instructions stored in the plurality of areas in the program memory includes a coefficient memory enable bit, and whether or not the chip select signal supplied to the coefficient memory is set to an active level according to the coefficient memory enable bit. A digital signal processing device for switching whether or not. The method according to claim 1 or 2, The said predetermined value is a digital signal processing apparatus.

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