CN113571071B - Audio and video signal processing chip and method - Google Patents
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/008—Multichannel audio signal coding or decoding using interchannel correlation to reduce redundancy, e.g. joint-stereo, intensity-coding or matrixing
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS OR SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
- G10L19/16—Vocoder architecture
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides an audio and video signal processing chip and a method, comprising the following steps: flexibly configurable processors, programmable processor units, shared registers; the flexible configuration processor is connected with the programmable processor unit through the shared register; the flexible configuration processor is used for processing the audio and video signals input into the chip to obtain first data, and sending the first data to the programmable processor unit; the programmable processor unit is used for receiving the first data, processing the first data to obtain second data, and sending the second data to the flexibly configurable processor; the programmable processor unit includes a plurality of custom instruction registers for custom instruction processing the first data. By using the scheme provided by the application, the audio and video signals can be processed by the custom instruction, and the processing efficiency of the audio and video signals is improved.
Description
Technical Field
The application relates to the field of audio and video signal processing, in particular to an audio and video signal processing chip and method.
Background
In recent years, embedded chips have been widely used in palm computers, cellular phones, digital cameras, and other digital products. However, with the continuous increase of the performance requirements of applications, chips are often required to cope with a large amount of computationally intensive tasks facing a certain field. Although general purpose processors are inexpensive and flexible in function, they often fail to meet the performance requirements of these specific field applications.
At present, with the increasing progress of social sharing of mobile internet contents, the media such as characters and pictures are increasingly meeting the diversified demands of social users, and compared with the situation that more visual video and audio social contact is in progress, the audio and video is taken as the most visual media and is increasingly and frequently applied to various information service occasions. However, the processing mode of video and audio often adopts a conventional mode of processing pictures and the like, so that the user experience of audio and video and the processing efficiency of audio and video signals are greatly reduced.
Disclosure of Invention
In view of this, the present application provides an audio/video signal processing chip and method, which can improve audio/video signal processing efficiency by customizing instructions.
Specifically, the application is realized by the following technical scheme:
according to a first aspect of the present application, there is provided an audio-visual signal processing chip comprising: flexibly configurable processors, programmable processor units, shared registers; the flexible configuration processor is connected with the programmable processor unit through the shared register;
the flexible configuration processor is used for processing the audio and video signals input into the chip to obtain first data, and sending the first data to the programmable processor unit;
the programmable processor unit is used for receiving the first data, processing the first data to obtain second data, and sending the second data to the flexibly configurable processor; the programmable processor unit includes a plurality of custom instruction registers for custom instruction processing the first data.
Optionally, the programmable processor unit includes a plurality of custom instruction registers, where the custom instruction registers are used for custom instruction processing the first data, and further includes:
the programmable processor unit comprises N custom instruction registers, and is used for processing first data of M data channels by the custom instruction, wherein the custom instruction is used for performing vector operation on the first data of the M data channels.
Optionally, the custom instruction register further includes a control register, and the programmable processor unit stores data from 0 to M-1 into the control register, for starting the first data of the corresponding data channel to perform vector operation.
Optionally, the custom instruction register further includes a channel index register, where the channel index register is configured to store a corresponding data channel index when the vector operation is completed.
Optionally, the custom instruction register further includes an instruction address register, where the instruction address register is configured to store a start address of the vector operation instruction of the M data channels in an instruction memory, and the instruction memory is configured to store a custom instruction for performing a vector operation.
Optionally, the programmable processor unit further includes a channel data storage memory, configured to store first data of the M data channels and second data of the M data channels after vector operation.
Optionally, the flexible processor is configured to process the audio and video signals input into the chip to obtain first data, store the first data into the shared register, and send an interrupt signal to the programmable processor unit to request the programmable processor unit to receive the first data;
and the programmable processor unit is used for receiving the first data, processing the first data to obtain second data, storing the second data into the shared register, and sending an interrupt signal to the flexible configuration processor to request the flexible configuration processor to receive the second data.
Optionally, the chip further includes a signal input interface and a signal output interface, where the signal input interface and the signal output interface are connected with the flexible configurable processor and are used for inputting and outputting audio and video signals.
On the other hand, the application provides an audio and video signal processing method, which comprises the steps that an audio and video signal is input to a flexibly configurable processor, first data is obtained after the audio and video signal is processed by the flexibly configurable processor, the first data is stored in the shared register, and an interrupt signal is sent to the programmable processor unit to request the programmable processor unit to receive the first data; the programmable processor unit is used for receiving the first data, processing the first data to obtain second data, storing the second data into the shared register, and sending an interrupt signal to the flexible configuration processor to request the flexible configuration processor to receive the second data; after the flexibly configurable processor receives the second data, outputting the second data; the programmable processor unit includes a plurality of custom instruction registers for custom instruction processing the first data.
Optionally, the programmable processor unit includes a plurality of custom instruction registers, where the custom instruction registers are used for custom instruction processing the first data, and further includes:
the programmable processor unit comprises N custom instruction registers, and is used for processing first data of M data channels by the custom instruction, wherein the custom instruction is used for performing vector operation on the first data of the M data channels.
As can be seen from the above description, the combination of the flexible configuration processor and the programmable processor unit, and the custom instruction in the programmable processor unit performs vector operation on the audio/video signal, thereby improving the audio/video signal processing efficiency.
Drawings
Fig. 1 is a schematic diagram of an audio/video signal processing chip according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
Technical terms appearing in the present application are explained first:
PDM, pulse density modulation, the amplitude of an analog signal is represented by the density of the corresponding region of the output pulse. The PWM wave is a special case of fixed PDM wave conversion frequency, in a bit data stream actually output, only "1" and "0" exist, the greater the density of 1, the greater the amplitude of the analog signal corresponding to the area, otherwise, the greater the density of 0, the smaller the amplitude of the analog signal representing the area. The areas of successive transitions 1 and 0 correspond to intermediate magnitudes. After filtering the PDM signal using a low pass filter, a continuous analog signal waveform can be recovered.
PCM, pulse code modulation, which is to convert an analog signal with continuous time and continuous value into a digital signal with discrete time and discrete value, and then transmit the digital signal in a channel. Pulse code modulation is the ADC quantization process of sampling analog signals, quantizing the amplitude of the sample, and encoding.
PWM, pulse width modulation is an analog control mode, and the bias of the base electrode of the transistor or the grid electrode of the MOS tube is modulated according to the change of corresponding load, so that the change of the on time of the transistor or the MOS tube is realized, and the change of the output of the switching regulated power supply is realized. This way, the output voltage of the power supply can be kept constant when the operating conditions change, and is a very effective technique for controlling the analog circuit by means of the digital signal of the microprocessor. Pulse width modulation is a very effective technique for controlling analog circuits using the digital output of a microprocessor, and is widely used in many fields from measurement, communication to power control and conversion.
Referring to fig. 1, fig. 1 is a schematic diagram of an audio/video signal processing chip according to an exemplary embodiment of the present application.
The audio and video processing chip includes a flexibly configurable processor (Flexible Process Unit, FPU), a programmable processor unit (Programmable Process Unit, PPU), shared registers, a PDM decoder, a PWM encoder, a program memory, and a data memory.
The audio and video signals are input to the flexible configurable processor FPU via an input interface, which may be a PDM interface or a PCM/I2S interface. Signals input through the PDM interface need to be converted into PCM signals by a PDM decoder and then enter the FPU; signals input through the PCM/I2S interface go directly into the FPU without further processing.
The FPU and the programmable processor unit PPU are connected by shared registers. The FPU processes the input audio and video signals, buffers the data in a shared register after each round of calculation is completed, transmits an interrupt to the PPU, requests the PPU to receive, and transmits a feedback interrupt after the PPU receives. Similarly, after each round of calculation by the PPU is completed, the data is also cached in the shared register, and an interrupt is sent to the FPU to request the FPU to receive, and after the FPU receives, the feedback interrupt is sent. The FPU outputs the received data in two output modes, namely the received data can be directly output through PCM/I2S, and the received data can also be sent to a PWM encoder to be output to the moving iron for sounding. The chip can support two-way PDM signal input and simultaneously run two-way processing algorithms.
The flexibly configurable processor FPU is a parallel coprocessor in a chip and is mainly responsible for parallel processing of audio and video algorithms. The FPU is configured with a special data memory, and the data memory is mainly used for caching the FPU calculation result. The programmable processor unit PPU is used as a core processing module of a chip, a programmable 32bits DSP can be adopted, a harvard structure is adopted, and the harvard structure is a parallel system structure and is mainly characterized in that a program and data are stored in different storage spaces, namely a program memory and a data memory are two independent memories, and each memory is independently addressed and independently accessed. The peripheral interface is mainly I2C, an embedded clock generator and a clock management module, wherein the embedded clock generator is used for providing a reference clock for a chip, and the clock management module can be used for providing one or more stable clocks with different frequencies and different phases for the chip. The data bus and the address bus of the PPU module are both 32bits, and the bus is compatible with the WISHBONE standard; the PPU module is provided with 256 32bits registers as RAM; the PPU module is provided with 8 interrupts with priority settings; PPU is divided into two main types, namely a basic instruction set and an extended instruction set, wherein the basic instruction set comprises: data transfers, arithmetic operations, bit operations, execution transfers, other instructions, and the like. The multiplication and division in the basic instruction set are both 32bits. The extended instruction set is a special instruction set customized for completing video and audio rapid processing, and more than 40 special instructions are realized at present, including but not limited to logarithmic calculation, exponential calculation, square opening and the like.
Fig. 1 provides an audio/video signal processing chip for performing vector operation on an audio/video signal through a custom instruction, which is specifically implemented as follows:
after receiving the input audio and video signals, the processor FPU can be flexibly configured to perform algorithm processing on the audio and video signals to obtain first data, after each round of calculation of the FPU is completed, the first data is cached in a shared register connected with the FPU, an interrupt request is sent to the PPU, the PPU is requested to receive the first data, and interrupt feedback is sent to the FPU after the PPU receives the first data.
After the processor PPU is flexibly configured to receive the first data sent by the FPU, the first data is stored in the channel data storage memory, where the channel data storage memory can store a plurality of channel data. The PPU comprises a plurality of custom instruction registers, and the custom instruction registers can process first data of M data channels by a custom instruction, namely, vector operation is carried out on the first data of M data channels. The PPU also comprises a channel data storage memory for storing first data of M data channels and second data of M data channels after vector operation.
The PPU stores the processed second data into the shared register, sends an interrupt request to the FPU, requests the FPU to receive the second data, and sends interrupt feedback to the PPU after the FPU receives the second data.
The FPU outputs the first data or the second data through the output interface, and the first data or the second data can be output through the PCM/I2S output interface, and can also be sent to the PWM encoder to be output to the moving iron sounding.
The self-defined instruction register also comprises a control register, a channel label register and an instruction address register, wherein the PPU stores 0 to M-1 data into the control register and is used for starting the first data of the corresponding data channel to perform vector operation. The channel label register is used for storing corresponding data channel labels into the label register when the first data vector operation of the data channel is completed. The instruction address register is used for storing the initial addresses of vector operation instructions of M data channels in the instruction memory, and the instruction memory is used for storing custom instructions for vector operation. The instruction memory may be a data memory or a program memory, and the custom instruction may be one or more of data transfer, arithmetic operation, bit operation, execution transfer, logarithmic calculation, exponential calculation, square of opening, or other special instructions for customizing audio and video.
In one embodiment, the PPU includes 7 custom instruction registers numbered 0-6, where custom instruction register 0 is a control register, custom instruction registers 1-5 are instruction address registers, custom instruction register 6 is a channel index register, vector operations are performed on 10 channels of data, and channel numbers are represented by 0-9. The vector operation is controlled by the PPU through the data bus, and the vector operation is carried out on the first data in the data storage memory of the automatic read-write channel after the vector operation is started. When vector operation is required to be carried out on data of a certain channel, the PPU writes channel numbers of 0-9 into the custom instruction register 0, the corresponding channel is started to carry out vector operation, the PPU writes the corresponding channel number into the lower 4 bits of the custom instruction register 6 after the vector operation is completed, and an interrupt notification PPU is generated to complete the vector operation. The custom instruction registers 1-5 store the starting addresses of the instructions corresponding to the channels 0-9 in the data memory. The specific implementation process is as follows:
after the PPU writes data into the custom instruction register, selecting the initial address of the instruction of vector operation corresponding to channel data in the data memory from the custom instruction registers 1 to 5 according to the low 4-bit data of the custom instruction register 6, reading one instruction from the initial address each time and executing each instruction, judging the vector operation channel completion mark in the current instruction after each instruction is executed, if the mark is 1, writing the current channel vector operation into the custom instruction register 6, storing the second data obtained after vector operation into the channel data storage memory, generating vector operation interrupt, storing the second data in the channel data storage memory into the shared register after the data vector operation of the channel is completed, and sending interrupt to the FPU by the PPU to request the FPU to receive the second data; otherwise, the next instruction is read and executed until the vector operation channel completion flag is 1. Channel data for vector operations are stored in a channel data memory, and instructions are stored in a program memory or a data memory. When the PPU loads the program, instructions of vector operation of 10 data channels are loaded into a program memory or a data memory simultaneously, and the starting address of the first instruction of each channel is written into the custom instruction registers 1 to 5.
The FPU and the PPU are completely parallel to each other, the PPU can completely and independently work only by starting the FPU, and the PPU is notified by interrupt after the execution of the parallel codes of the FPU is completed.
The audio and video signal processing chip provided by the application can add a plurality of instructions special for an audio and video processing algorithm in the instruction set, and the processing of tens of instructions is required by adopting a general CPU and a common DSP.
In another embodiment of the present application, an audio/video signal processing method is provided, including inputting an audio/video signal to a flexibly configurable processor, obtaining first data after being processed by the flexibly configurable processor, storing the first data in a shared register, and sending an interrupt signal to a programmable processor unit, requesting the programmable processor unit to receive the first data; the programmable processor unit is used for receiving the first data, processing the first data to obtain second data, storing the second data into the shared register, and sending an interrupt signal to the flexibly configurable processor to request the flexibly configurable processor to receive the second data; after the flexibly configurable processor receives the second data, outputting the second data; the programmable processor unit comprises a plurality of custom instruction registers, and the custom instruction registers are used for custom instruction processing of first data. The programmable processor unit includes a plurality of custom instruction registers for custom instruction processing of first data, further comprising:
the programmable processor unit comprises N custom instruction registers, and is used for processing first data of M data channels by the custom instruction, wherein the custom instruction is used for performing vector operation on the first data of the M data channels.
For method embodiments, reference is made to the description of device embodiments for the relevant points, since they essentially correspond to the device embodiments. The method embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present application. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.
Claims (7)
1. An audio/video signal processing chip, comprising: flexibly configuring a processor FPU, a programmable processor unit PPU and a shared register; the flexible configurable processor FPU is connected with the programmable processor unit PPU through the shared register;
the flexible configuration processor FPU is used for processing the audio and video signals input into the chip to obtain first data, and sending the first data to the programmable processor unit PPU;
the programmable processor unit PPU is configured to receive the first data, process the first data to obtain second data, and send the second data to the flexible configurable processor FPU; the programmable processor unit PPU comprises a plurality of custom instruction registers for custom instruction processing of the first data;
the programmable processor unit PPU includes N custom instruction registers, configured to process first data of M data channels by using a custom instruction, where the custom instruction processes the first data of the M data channels to perform a vector operation on the first data of the M data channels; wherein N is an integer greater than or equal to 7, M is an integer greater than 1;
the flexible configuration processor FPU is used for processing an audio and video signal of an input chip to obtain first data, storing the first data into the shared register, and sending an interrupt signal to the programmable processor unit PPU to request the programmable processor unit PPU to receive the first data;
and the programmable processor unit PPU receives the first data, processes the first data to obtain second data, stores the second data into the shared register, and sends an interrupt signal to the flexible configuration processor FPU to request the flexible configuration processor FPU to receive the second data.
2. The chip of claim 1, wherein the custom instruction register further comprises a control register, and the programmable processor unit PPU stores data from 0 to M-1 into the control register for enabling vector operations on the first data of the corresponding data channel.
3. The chip of claim 1, wherein the custom instruction register further comprises a lane number register for storing a corresponding data lane number when a vector operation is completed.
4. The chip of claim 1, wherein the custom instruction register further comprises an instruction address register for storing a start address of the vector operation instruction of the M data lanes in an instruction memory for storing custom instructions for vector operations.
5. The chip of claim 1, wherein the programmable processor unit PPU further comprises a channel data storage memory for storing first data of the M data channels and second data of the M data channels after vector operations.
6. The chip of claim 1, further comprising a signal input interface and a signal output interface, the signal input interface and the signal output interface being coupled to the flexible configurable processor FPU for input and output of audio and video signals.
7. An audio/video signal processing method applied to the audio/video signal processing chip according to any one of claims 1 to 6, wherein the method includes inputting the audio/video signal to a flexible configurable processor FPU, obtaining first data after processing by the flexible configurable processor FPU, storing the first data in a shared register, and sending an interrupt signal to the programmable processor unit PPU, requesting the programmable processor unit PPU to receive the first data; a programmable processor unit PPU, configured to receive the first data, process the first data to obtain second data, store the second data into the shared register, and send an interrupt signal to the flexible configurable processor FPU, to request the flexible configurable processor FPU to receive the second data; after receiving the second data, the flexibly configurable processor FPU outputs the second data; the programmable processor unit PPU comprises a plurality of custom instruction registers for custom instruction processing of the first data.
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| GB2483225B (en) * | 2010-08-27 | 2018-07-11 | Nvidia Tech Uk Limited | Improved processor architecture |
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| US5537601A (en) * | 1993-07-21 | 1996-07-16 | Hitachi, Ltd. | Programmable digital signal processor for performing a plurality of signal processings |
| CN101000596A (en) * | 2007-01-22 | 2007-07-18 | 北京中星微电子有限公司 | Chip and communication method of implementing communicating between multi-kernel in chip and communication method |
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