JP2009265546A - Waveform generator and waveform generation processing program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a waveform generator preventing unnatural sound from being generated when an instruction is made to generate sound exceeding a maximum reproduction pitch. <P>SOLUTION: In a reproduction pitch limit circuit 10, when pitch data Pitch read out from a RAM 200 exceeds pitch limit data PL, the pitch data Pitch is shifted by octave to be a value not to exceed the pitch limit data PL. The sound pitch is lowered by a unit of octave to be equal to or below the pitch limit data PL while maintaining a pitch name of the reproduction pitch predetermined by the pitch data Pitch, so that the unnaturalness such as a sound interruption and sound delay can be avoided, which are caused when an instruction is made to generate the sound exceeding a maximum reproduction pitch (the reproduction pitch corresponding to a maximum address stepping value). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a waveform generation device and a waveform generation processing program suitable for use as a sound source of an electronic musical instrument.

  2. Description of the Related Art Conventionally, a waveform generator that reads differential waveform data that has been subjected to differential PCM encoding from a memory and generates a musical sound waveform is known. As this type of device, for example, in Patent Document 1, the step amount of the waveform address for reading the differential waveform data stored in the memory is larger than “1”, and the waveform address integer part updated thereby is the pre-update waveform portion. When the waveform address integer part becomes discontinuous, based on the waveform address decimal part while sequentially integrating the corresponding differential waveform data from the waveform address integer part before update to the updated waveform address integer part A technique is disclosed in which a musical sound waveform is generated at a reproduction pitch equal to or higher than the original sound pitch by performing an interpolation calculation.

Japanese Patent No. 3223560

  By the way, in the recent multi-timbral sound source, the period of the processing slot assigned to one tone generation channel is short due to the increase in the number of polyphonics. When such a sound source is equipped with a waveform generator that generates a musical sound waveform based on a differential waveform, the number of times of reading differential waveform data from the waveform memory during one processing slot period in which time division operation is performed is limited. The limitation on the number of waveform readouts is a limitation on the waveform address step value. Therefore, if a sound generation exceeding the maximum reproduction pitch (reproduction pitch corresponding to the maximum address step value) is instructed, the waveform address cannot be stepped up to a desired value within one processing slot period. For example, there is a risk that unnatural musical sounds such as sound interruptions and pronunciation delays may occur.

  The present invention has been made in view of such circumstances, and provides a waveform generation device and a waveform generation processing program capable of avoiding unnaturalness when a pronunciation exceeding the maximum reproduction pitch is instructed. It is aimed.

  In order to achieve the above object, according to the first aspect of the present invention, the comparison means for comparing the size of the pitch data representing the reproduction pitch with the pitch limit data for designating the upper limit of the reproduction pitch, and the pitch data by the comparison means. When it is determined that the pitch limit data is larger than the pitch limit data, the playback pitch limit means outputs the pitch data by octave shifting until the value does not exceed the pitch limit data, and the pitch data output from the playback pitch limit means Waveform generating means for generating a waveform by differential waveform reproduction.

  In the invention according to claim 2 subordinate to claim 1, the reproduction pitch limit means outputs the pitch data as it is when the comparison means determines that the pitch data is smaller than the pitch limit data. Features.

  In the invention according to claim 3, which is dependent on claim 1, pitch data representing a reproduction pitch and pitch limit data designating an upper limit of the reproduction pitch are provided for each channel slot corresponding to a plurality of sound generation channels performing time-division operation. Is further provided, and the comparison means reads out the corresponding pitch data and pitch limit data from the storage means for each channel slot to be processed, and compares the magnitudes.

  In the invention according to claim 4 subordinate to claim 1, pitch limit data storage means for storing pitch limit data common to all channel slots corresponding to a plurality of sound generation channels that perform time division operation, and time division operation Pitch data storage means for storing pitch data representing a reproduction pitch for each channel slot corresponding to a plurality of sound generation channels, and the comparing means corresponds to the pitch data storage means corresponding to the channel slot to be processed. Is compared with the pitch limit data common to all channel slots read from the pitch limit data storage means.

  According to the fifth aspect of the present invention, when the pitch data representing the playback pitch exceeds the playback pitch upper limit value corresponding to the pitch limit data specifying the upper limit of the playback pitch, the playback pitch upper limit value is output as pitch data. And a waveform generating means for generating a waveform by differential waveform reproduction based on the pitch data output from the reproduction pitch limiting means.

  The invention according to claim 6 that is dependent on claim 5 is characterized in that the reproduction pitch limiting means outputs the pitch data as it is when the pitch data is smaller than the reproduction pitch upper limit value.

  In the invention according to claim 7, which is dependent on claim 5, pitch data representing a reproduction pitch and pitch limit data designating an upper limit of the reproduction pitch are provided for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation. For each channel slot to be processed, the corresponding pitch data and pitch limit data are read from the storage means, and the pitch data specifies the upper limit of the playback pitch. When the playback pitch upper limit value corresponding to the pitch limit data to be exceeded is exceeded, the playback pitch upper limit value is output as pitch data.

  In the invention according to claim 8, which is dependent on claim 5, pitch limit data storage means for storing pitch limit data common to all channel slots corresponding to a plurality of sound generation channels that perform time division operation, and time division operation Pitch data storage means for storing pitch data representing a playback pitch for each channel slot corresponding to a plurality of tone generation channels, wherein the playback pitch limiting means corresponds to the pitch data corresponding to the channel slot to be processed. When the pitch data read from the storage means exceeds the playback pitch upper limit value corresponding to the pitch limit data common to all channel slots read from the pitch limit data storage means, the playback pitch upper limit value is used as the pitch data. It is characterized by outputting.

  According to the ninth aspect of the present invention, it is determined that the pitch data representing the playback pitch is compared with the pitch limit data specifying the upper limit of the playback pitch, and that the pitch data is larger than the pitch limit data by the comparison process. In this case, a playback pitch limit process for outputting the pitch data by octave shifting until the value does not exceed the pitch limit data, and a differential waveform playback based on the pitch data output by the playback pitch limit process. And a waveform generation process for generating a waveform.

In the invention according to claim 10, when the pitch data representing the playback pitch exceeds the playback pitch upper limit value corresponding to the pitch limit data specifying the upper limit of the playback pitch, the playback pitch upper limit value is used as the pitch data. A playback pitch limiting process to be output; and a waveform generation process to generate a waveform by differential waveform playback based on the pitch data output by the playback pitch limiting process.

  In the present invention, it is possible to avoid unnaturalness when a pronunciation that exceeds the maximum reproduction pitch is instructed.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
(1) Configuration FIG. 1 is a block diagram showing the main configuration of the first embodiment of the present invention, and shows a configuration example of a waveform generator mounted on a sound source of an electronic musical instrument. In this figure, the clock generator 100 is composed of a 10-bit counter that counts the basic clock ck, and a clock mc [3: 0] that is the lower 4 bits output (3SB to 0SB (LSB)) of the counter; A clock mc [9: 4] that is an upper 6-bit output (9SB (MSB) to 4SB) is generated.

  Here, a correspondence relationship between the basic clock ck, the clock mc [3: 0], and the clock mc [9: 4] will be described with reference to FIG. As shown in this figure, the clock mc [9: 4] forms channel slots CH0 to CH63 respectively corresponding to 64 (0h to 3Fh) sound generation channels that perform time-division operation in the sound source. The period of the channel slots CH0 to CH63 corresponds to one sampling period 1 / Fs (Fs: sampling frequency) of the differential waveform data.

  The clock mc [3: 0] divides one channel slot CH formed by the clock mc [9: 4] into 16 processing slots “0h (0)” to “Fh (15)”. Based on the clock mc [9: 4] and the clock mc [3: 0], the operation timing of each component of the waveform generator illustrated in FIG. 1 is controlled.

  In FIG. 1, a RAM 200 is used as a work memory of the waveform generator. As shown in FIG. 3, the RAM 200 includes channel areas CH <b> 0 to CH <b> 63 respectively associated with the 64 sound generation channels included in the sound source. Data read / write in these channel areas CH0 to CH63 is performed in synchronization with the processing slot formed by the above-described clock mc [3: 0], and the read / write operation is instructed by the control unit 300.

  In each channel area CH0 to CH63 of the RAM 200, an integer part address A, a fraction part address a, an integer part pitch data P, a fraction part pitch data p, an integer part pitch limit data Q, a fraction part pitch limit data q, and a peak value W Is stored. The 16-bit integer part address A and the 16-bit fractional part address a represent the current waveform address (the phase of the differential waveform currently specified). The integer part address A and the fractional part waveform address a are collectively referred to as the current waveform address AD.

The 3-bit integer part pitch data P and the 16-bit fractional part pitch data p represent address step values corresponding to the reproduction pitch (sounding pitch). The integer part pitch data P and the fractional part pitch data p are collectively referred to as pitch data Pitch. The 19-bit length pitch data Pitch [18: 0] is “10000h” for the original sound pitch reproduction, and “08000h” is the 1/2 pitch reproduction for which the pitch is half the original sound pitch. ”Designates +1 octave reproduction in which the pitch of the pronunciation is twice the original pitch.

Like the pitch data Pitch, the integer part pitch limit data Q and the fractional part pitch limit data q are 19-bit data, and specify the upper limit of the playback pitch (sounding pitch). The integer part pitch limit data Q and the fractional part pitch limit data q are collectively referred to as pitch limit data PL. The 16-bit peak value W is a peak value obtained by integrating the differential waveform data corresponding to the current waveform address AD before update.

The reproduction pitch limit circuit 10 includes a pitch limit register 11, a comparator 12, a shift control unit 13, a selector 14, and a pitch register 15. The pitch limit register 11 stores pitch limit data PL (integer part pitch limit data Q and fractional part pitch limit data q) read from the RAM 200 in accordance with a read instruction from the control unit 300. The pitch register 15 stores either pitch data Pitch (integer part pitch data P and fractional part pitch data p) read from the RAM 200 or pitch data Pitch output from the shift control unit 13 via the selector 14. The

  The comparator 12 compares the pitch limit data PL stored in the pitch limit register 11 with the pitch data Pitch stored in the pitch register 15, and if the pitch data Pitch is larger than the pitch limit data PL, the comparator 12 outputs a shift instruction signal. appear. When the shift instruction signal is supplied from the comparator 12, the shift control unit 13 shifts the pitch data Pitch stored in the pitch register 15 by 1 bit to the right (-1 octave shift), and outputs it. If no shift instruction signal is supplied from the device 12, the pitch data Pitch stored in the pitch register 15 is output through. The selector 14 selects and outputs either the pitch data Pitch read from the RAM 200 or the pitch data Pitch output from the shift control unit 13 in response to a switching instruction from the control unit 300.

  As described above, when the pitch data Pitch read from the RAM 200 exceeds the pitch limit data PL, the reproduction pitch limit circuit 10 shifts the pitch data Pitch by an octave until the value does not exceed the pitch limit data PL. That is, while maintaining the pitch name of the reproduction pitch specified by the pitch data Pitch, the tone pitch is lowered in octave units until the pitch limit data PL or less. In the present embodiment, the shift control unit 13 performs octave shift up to three times, as will be described later in the description of the operation.

  Next, in accordance with the switching instruction from the control unit 300, the selector 17 selects either the current waveform address AD (integer part address A and decimal part address a) read from the RAM 200 or the output of the adder 16 in a predetermined processing slot. Select and store in the next-stage ADC register 18. When the selector 17 selects the current waveform address AD read from the RAM 200, the output of the pitch register 15 and the current waveform address AD output from the ADC register 18 are added by the adder 16, thereby the current waveform address AD is updated. In the adder 16, when a decimal part carry occurs during addition of the output of the pitch register 15 and the output of the ADC register 18 (current waveform address AD), a decimal part carry is generated.

  The updated current waveform address AD is stored in the ADC register 18 via the selector 17. The updated current waveform address AD (integer part address A and decimal part address a) stored in the ADC register 18 is written to the corresponding channel area CH of the RAM 200 via the selector 40. Further, the least significant bit LSB of the integer part address A of the updated current waveform address AD stored in the ADC register 18 is stored in the ADC LSB register 19. Further, the decimal part address a of the updated current waveform address AD stored in the ADC register 18 is stored in the ADC dec register 27.

  The adder 20 adds the decimal part carry generated by the adder 16 to the output of the pitch register 15 to generate a waveform address step value. The waveform address step value generated by the adder 20 is stored in the STEP register 21. The save register 22 functions as a delay buffer of the STEP register 21 and saves and stores the waveform address step value of the STEP register 21.

The integer part address A of the updated current waveform address AD stored in the ADC register 18 is supplied to the adder 24 via the selector 23. The selector 23, the adder 24, and the WADR register 25 generate four read addresses WADR1 to WADR4 for reading the differential waveform data from the waveform memory 26.

That is, when the integer part address A of the current waveform address AD is first supplied to the adder 24 via the selector 23, "-6" is added to generate the read address WADR1 (integer part address A-6). . The read address WADR1 is stored in the WADR register 25. The read address WADR1 read from the WADR register 25 is input to the adder 24 via the selector 23, while the upper 15 bits excluding the least significant bit LSB are supplied to the waveform memory 26.

When the read address WADR1 is supplied via the selector 23, the adder 24 generates a read address WADR2 (integer part address A-4) obtained by adding “2” to the read address WADR1. The read address WADR2 is stored in the WADR register 25. The read address WADR2 read from the WADR register 25 is input to the adder 24 via the selector 23, while the upper 15 bits excluding the least significant bit LSB are supplied to the waveform memory 26.

When the read address WADR2 is supplied via the selector 23, the adder 24 generates a read address WADR3 (integer part address A-2) obtained by adding “2” to the read address WADR2. The read address WADR3 is stored in the WADR register 25. The read address WADR3 read from the WADR register 25 is input to the adder 24 via the selector 23, while the upper 15 bits excluding the least significant bit LSB are supplied to the waveform memory 26.

When the read address WADR3 is supplied via the selector 23, the adder 24 generates a read address WADR4 (integer part address A) obtained by adding “2” to the read address WADR2. The read address WADR4 is stored in the WADR register 25. The read address WADR4 read from the WADR register 25 is supplied to the waveform memory 26 for the upper 15 bits excluding the least significant bit LSB.

  As shown in FIG. 4, the waveform memory 26 has a storage area having a 16-bit width. In one storage area, 8-bit wide differential waveform data expressed as a mantissa in 2's complement is stored in the upper byte and the lower byte. The 8-bit width differential waveform data is bit-shifted by a differential waveform integration arithmetic circuit 30 to be described later, and becomes differential waveform data expressed as a real number with 16 bits.

  The waveform memory 26 reads the differential waveform data D0 to D3 according to the four read addresses WADR1 to WADR4 that are sequentially generated by the WADR register 25. The differential waveform data D0 is composed of high-order byte differential waveform data D0H and low-order byte differential waveform data D0L. Similarly, the differential waveform data D1 includes differential waveform data D1H and D1L, the differential waveform data D2 includes differential waveform data D2H and D2L, and the differential waveform data D3 includes differential waveform data D3H and D3L.

  The differential waveform integration circuit 30 includes components 31 to 38 and a controller 28. The differential waveform data D0 to D3 read from the waveform memory 26 described above are stored in the DW0 registers 31a to DW3 registers 31d. That is, the differential waveform data D0H and D0L are stored in the DW0 register 31a, the differential waveform data D1H and D1L are stored in the DW1 register 31b, the differential waveform data D2H and D2L are stored in the DW2 register 31c, and the differential waveform data D3H is stored in the DW3 register 31d. , D3L are stored respectively.

The controller 28 performs an integration operation according to an integration operation pattern determined by the waveform address step value stored in the save register 22 and the value of the ADC LSB register 19 (the least significant bit LSB of the integer part address A in the current waveform address AD). Specifies the differential waveform data to be applied. The selector 32 selectively outputs the differential waveform data specified by the controller 28 in accordance with the integral calculation pattern among the differential waveform data stored in the DW0 register 32 to DW3 register 35, respectively. The adder 35 adds (integrates) the peak value W output from the X register 34 to the differential waveform data output from the selector 32.

  Here, the contents of the integral calculation pattern will be described with reference to FIGS. FIG. 5 shows an integration calculation pattern when the value of the ADC LSB register 19 is “1”, and FIG. 6 shows an integration calculation pattern when the value of the ADC LSB register 19 is “0”. The integration calculation patterns shown in these figures are determined according to the waveform address step values “0” to “8” stored in the save register 22 and the addition orders “0” to “7” corresponding to the processing slots. The contents of the integral calculation are shown.

For example, it is assumed that the waveform address step value stored in the save register 22 is “8” (maximum address step value) when the value of the ADC LSB register 19 is “1”. Then, first, in the addition order “0”, an integration operation “W + D0L” is executed. “W + D0L” means that the differential waveform data D0L stored in the DW0 register 31a is bit-shifted to 16 bits, and then the 16-bit differential waveform data D0L is added to the peak value W output from the X register 34. Means that the integrated peak value is stored in the X register 34 via the selector 33.

  Next, in the addition order “1”, an integral operation “W + D0H” is executed. “W + D0H” means that the differential waveform data D0H stored in the DW0 register 31a is bit-shifted to 16 bits, and then the 16-bit differential waveform data D0H is added to the peak value W output from the X register 34. Means that the integrated peak value is stored in the X register 34 via the selector 33. Thereafter, in the same manner, “W + D1L” in the addition order “2”, “W + D1H” in the addition order “3”, “W + D2L” in the addition order “4”, “W + D2H” in the addition order “5”, and “6+” "" Indicates that the integral operation "W + D3L" is executed, and in the addition order "7", the integration operation "W + D3H" is executed.

  Now, the peak value W stored in the X register 34 by such integration operation is supplied to the adder 35 and the adder 37 as the peak value to be integrated next, while the channel area corresponding to the RAM 200 via the selector 40 is supplied. Written to CH. The multiplier 36, the adder 37, and the Y register 38 perform linear interpolation on the peak value W stored in the X register 34 based on the fractional part address a of the current waveform address AD stored in the ADC dec register 27. The peak value Y calculated by this is stored in the Y register 38.

The adder 50, the M register 51, and the selector 52 constitute a mixer circuit. In the mixer circuit, the waveform output wave is formed by accumulating all the peak values Y for the respective sound generation channels output from the Y register 38. This waveform output wave is D / A converted and output every sampling period in a sound source not shown.

(2) Operation
Next, the operation of the first embodiment having the above configuration will be described with reference to the timing chart shown in FIG. In the following description of the operation, a processing slot in the channel slot CH0 is referred to as a CH0 processing slot, and a processing slot in the channel slot CH1 is referred to as a CH1 processing slot.

  First, in the data period ro0 synchronized with the CH0 processing slot “0”, the pitch limit data PL (the integer part pitch limit data Q and the fractional part pitch limit data q) is read from the channel area CH0 of the RAM 200. The read pitch limit data PL is stored in the pitch limit register 11 in synchronization with the CH0 processing slot “1”.

Next, in the data period ro1 synchronized with the CH0 processing slot “1”, the pitch data Pitch (integer part pitch data P and fractional part pitch data p) is read from the channel area CH0 of the RAM 200. The read pitch data Pitch is stored in the pitch register 15 in the data period p0 synchronized with the CH0 processing slot “2”.

  Thus, when the pitch limit data PL is stored in the pitch limit register 11 and the pitch data Pitch is stored in the pitch register 15, the comparator 12 causes the pitch limit of the pitch limit register 11 in the data period c0 of the CH0 processing slot “2”. The data PL and the pitch data Pitch of the pitch register 15 are compared. If the pitch data Pitch is larger than the pitch limit data PL, a shift instruction signal is generated in the shift control unit 13.

  If the shift instruction signal is not supplied from the comparator 12, the shift control unit 13 outputs the pitch data Pitch stored in the pitch register 15 as a through output. Therefore, if the pitch data Pitch does not exceed the pitch limit data PL, the pitch data Pitch stored in the pitch register 15 is maintained during the data periods p1 to p3 of the CH0 processing slots “3” to “5”.

  On the other hand, when the pitch data Pitch is larger than the pitch limit data PL and a shift instruction signal is supplied from the comparator 12, the shift control unit 13 shifts the pitch data Pitch stored in the pitch register 15 to the right by 1 bit (-1 octave). shift. The pitch data Pitch shifted right by 1 bit is stored in the pitch register 15 in the data period p1 of the CH0 processing slot “3”.

  Thereafter, the comparator 12 and the shift control unit 13 set the pitch data Pitch to 1 until the pitch data Pitch does not exceed the pitch limit data PL in the data periods c1 to c2 of the CH0 processing slots “3” to “4”. Shift right by bit. That is, in the present embodiment, three 1-bit right shifts are possible for convenience, and the pitch data Pitch is shifted by -3 octaves at maximum so as not to exceed the pitch limit data PL.

As described above, when the pitch data Pitch read from the RAM 200 exceeds the pitch limit data PL, the reproduction pitch limit circuit 10 lowers the pitch data Pitch by −1 octave until the value does not exceed the pitch limit data PL. That is, while maintaining the pitch name of the playback pitch specified by the pitch data Pitch, the tone pitch is lowered in octave units until the pitch limit data PL or less is reached, so that a pronunciation exceeding the maximum playback pitch is instructed. It is possible to avoid unnaturalness in cases.

  On the other hand, in the data period ro2 synchronized with the CH0 processing slot “2”, the current waveform address AD (integer part address A and fractional part waveform address a) is read from the channel area CH0 of the RAM 200. In the data period a0 after the CH0 processing slot “3”, the current waveform address AD (integer part address A and fractional part waveform address a) read from the RAM 200 in the data period ro2 is stored in the ADC register 18. .

In the data period p3 after the CH0 processing slot “5”, as described above, when the pitch limit data PL is exceeded, the pitch data Pitch that is octave shifted to the pitch limit data PL or less is stored in the pitch register 15. Stored. In the data period s0 after the CH0 processing slot “6”, the waveform address step value obtained by adding the fractional part carry generated by the adder 16 to the output of the pitch register 15 is stored in the STEP register 21. .

  Further, in the data period a1 after the CH0 processing slot “6”, the output of the pitch register 15 is added to the current waveform address AD stored in the ADC register 18 in the data period a0, and the current waveform address AD of the ADC register 18 is added. Update. Then, the integer part address A and the decimal part address a of the updated current waveform address AD are stored in the channel area CH0 of the RAM 200 via the selector 17 in the data period ri0 synchronized with the CH0 processing slot “6”.

Then, in the data period WADR1 after the CH0 processing slot “7”, the integer part address A of the updated current waveform address AD output from the ADC register 18 and “−6” are added by the adder 24. The waveform read address WADR1 (integer part address A-6) generated in this manner is stored in the WADR register 25. The waveform read address WADR1 stored in the WADR register 25 is input to the adder 24 via the selector 23, while the upper 15 bits excluding the least significant bit LSB are supplied to the waveform memory 26.

Next, in the data period WADR2 after the CH0 processing slot “B”, the read address WADR1 and “2” input via the selector 23 are added by the adder 24 to obtain the waveform read address WADR2 (integer part address A−). 4) is generated and stored in the WADR register 25. The waveform readout address WADR2 stored in the WADR register 25 is input to the adder 24 via the selector 23, while the upper 15 bits excluding the least significant bit LSB are supplied to the waveform memory 26.

Thereafter, in the data period WADR3 after the CH0 processing slot “F” and the data period WADR4 after the CH1 processing slot “3”, similarly to the data period WADR2, the waveform readout address WADR3 (integer part address A-2) and A waveform read address WADR4 (integer part address A) is generated. Then, the upper 15 bits excluding the least significant bit LSB of these waveform read addresses WADR3 to WADR4 are supplied to the waveform memory 26, respectively.

  On the other hand, the waveform address step value read from the STEP register 21 is saved in the save register 22 in the data period s1 after the CH1 processing slot “0”. In the data period a2 after the CH1 processing slot “0”, the least significant bit LSB of the current waveform address AD stored in the ADC register 18 in the data period a1 of the CH0 processing slot “6” is stored in the ADC LSB register 19. . Further, in the data period a3 after the CH1 processing slot “0”, the decimal part address a of the current waveform address AD stored in the ADC register 18 in the data period a1 of the CH0 processing slot “6” is stored in the ADC dec register 27. .

  The differential waveform data D0 (D0H, D0L) to D3 (D3H, D3L) read from the waveform memory 26 in accordance with the four waveform read addresses WADR1 to WADR4 sequentially output from the WADR register 25 are the timing shown in FIG. Are stored in the DW0 register 31a to DW3 register 31d. That is, the differential waveform data D0H and D0L are stored in the DW0 register 31a, the differential waveform data D1H and D1L are stored in the DW1 register 31b, the differential waveform data D2H and D2L are stored in the DW2 register 31c, and the differential waveform data D3H is stored in the DW3 register 31d. , D3L are stored respectively.

  In the data period ro3 synchronized with the CH0 processing slot “F”, the peak value W is read from the channel area CH0 of the RAM 200 and stored in the X register 34 in the data period w0 after the CH1 processing slot “0”. The Thereafter, an integral calculation pattern (FIG. 5 or FIG. 5) determined according to the waveform address step value stored in the save register 22 and the value of the ADC LSB register 19 (the least significant bit LSB of the integer part address A in the current waveform address AD). Integration operation is performed according to FIG.

For example, as described above, when the value of the ADC LSB register 19 is “1” and the waveform address step value stored in the save register 22 is “8” (maximum address step value), FIG. The differential waveform data is integrated according to the integration pattern shown in FIG. First, in the data period w1 synchronized with the CH1 processing slot “3”, the integration operation of “W + D0L”, that is, the differential waveform data D0L stored in the DW0 register 31a is bit-shifted to 16 bits, and then the 16-bit differential waveform data. D0L and the peak value W of the X register 34 are integrated (added), and the integrated peak value is stored in the X register 34 via the selector 33.

  Thereafter, “W + D0H” is synchronized in the data period w2 synchronized with the CH1 processing slot “4”, “W + D1L” is synchronized in the data period w3 synchronized with the CH1 processing slot “5”, and the data period w4 is synchronized with the CH1 processing slot “6”. In “W + D1H”, “W + D2L” is synchronized with the CH1 processing slot “7”, “W + D2L” is synchronized with the CH1 processing slot “8”, and “W + D2H” is synchronized with the CH1 processing slot “9” in the data period w6 synchronized with the CH1 processing slot “8”. In the data period w7, “W + D3L” is executed, and in the data period w8 synchronized with the CH1 processing slot “A”, “W + D3H” is executed.

The peak value W accumulated in the X register 34 by such integration operation is stored in the channel area CH0 of the RAM 200 as the peak value W to be integrated next in the data period ri1 synchronized with the CH1 processing slot “A”. Further, the peak value W accumulated in the X register 34 by the integration operation is supplied to the adder 35 and the adder 37 as a peak value to be integrated next.

The multiplier 36, the adder 37, and the Y register 38 linearly interpolate the peak value W stored in the X register 34 based on the fractional part address a of the current waveform address AD stored in the ADC dec register 27. The calculation is executed at the timing shown in FIG. 7, and the peak value Y calculated thereby is stored in the Y register 38. Thereafter, the crest value Y is channel-accumulated in a mixer circuit composed of an adder 50, an M register 51, and a selector 52 to form a waveform output wave.

  As described above, in the first embodiment, when the pitch data Pitch indicating the pitch to be generated exceeds the pitch limit data PL, the pitch name is maintained while maintaining the pitch name of the reproduction pitch specified by the pitch data Pitch. Since the pitch pitch of the pitch data Pitch is lowered in octave units until the data becomes lower than the data PL, sound interruption or delay in sound generation when a sound is generated that exceeds the maximum playback pitch (playback pitch corresponding to the maximum address step value). It becomes possible to avoid such unnaturalness.

[Second Embodiment]
Next, a second embodiment will be described with reference to FIGS. In the first embodiment described above, the pitch limit data PL and the pitch data Pitch are compared, and when the pitch data Pitch exceeds the pitch limit data PL, the pitch data Pitch is changed to a value that does not exceed the pitch limit data PL. In contrast to the reduction shift by one octave, in the second embodiment, when the pitch data Pitch exceeds the reproduction pitch upper limit value specified by the 3-bit integer part pitch limit data Q, the pitch data Pitch is reproduced as the reproduction pitch. It differs in that it is replaced with the upper limit.

  FIG. 8 is a block diagram showing the configuration of the second embodiment. In this figure, the same number is attached | subjected to the same component as 1st Embodiment illustrated in FIG. 1, and the description is abbreviate | omitted. The configuration of the second embodiment shown in FIG. 9 is different from the first embodiment in that a playback pitch limit circuit 400 including a pitch limit register 11, a pitch register 15, and a pitch limiter 401 is provided, and a playback pitch is set. Corresponding to the limiting circuit 400, the RAM 200 has the data structure shown in FIG.

  That is, as shown in FIG. 9, the RAM 200 according to the second embodiment stores the current waveform address AD (the integer part address A and the fractional part address a) indicating the current waveform address (the phase of the differential waveform currently specified). ), Pitch data Pitch (integer part pitch data P and fractional part pitch data p) representing an address step value corresponding to the playback pitch (sounding pitch), and playback pitch that is the upper limit of the playback pitch (sounding pitch) For each channel area CH0 to CH63 in which 3-bit integer part pitch limit data Q designating the upper limit value and the peak value W obtained by integrating the differential waveform data corresponding to the current waveform address AD are associated with the sound generation channel. Stored in

  In the reproduction pitch limit circuit 400, the pitch limit register 11 stores 3-bit integer part pitch limit data Q read from the RAM 200 in accordance with a read instruction from the control unit 300. The pitch register 15 stores pitch data Pitch (integer part pitch data P and decimal part pitch data p) read from the RAM 200.

The pitch limiter 401 sets a playback pitch upper limit value corresponding to the output of the pitch limit register 11 (integer part pitch limit data Q), and the pitch data Pitch output from the pitch register 15 is set to the set playback pitch upper limit. If it is less than the value, the pitch data Pitch is output through to the adder 16 at the next stage. On the other hand, if it is equal to or greater than the set reproduction pitch upper limit value, the reproduction pitch upper limit value is output to the adder 16 at the next stage.

  Specifically, as shown in FIG. 10, when the output of the pitch limit register 11 (integer part pitch limit data Q) is “0”, the playback pitch upper limit value “7FFFFh” is output as the output of the pitch limit register 11. Is “1”, the playback pitch upper limit value is “78000h”, when the output of the pitch limit register 11 is “2”, the playback pitch upper limit value is “70000h”, and the output of the pitch limit register 11 is “3”. In this case, the reproduction pitch upper limit value “68000h” is generated and set internally.

Further, when the output of the pitch limit register 11 is “4”, the playback pitch upper limit value “60000h” is set. When the output of the pitch limit register 11 is “5”, the playback pitch upper limit value “58000h” is set. When the output of the register 11 is “6”, the reproduction pitch upper limit value “50000h” is generated, and when the output of the pitch limit register 11 is “7”, the reproduction pitch upper limit value “48000h” is generated and set internally. . As an aspect for generating the reproduction pitch upper limit value corresponding to the integer part pitch limit data Q, for example, the integer part pitch limit data Q is used as a read address, and the reproduction pitch upper limit value is realized by a known data table for reading the corresponding reproduction pitch upper limit value. .

  As described above, in the second embodiment, when the pitch data Pitch specifying the playback pitch (sounding pitch) exceeds the playback pitch upper limit value specified by the 3-bit integer part pitch limit data Q, the pitch data Pitch is changed. Since the differential waveform is played back by replacing the upper limit value with the playback pitch, it avoids unnaturalness such as sound interruptions and sound delays that occur when a sound that exceeds the maximum playback pitch (playback pitch corresponding to the maximum address step value) is specified. Can do.

[Modification of First Embodiment]
Next, a modification of the first embodiment will be described with reference to FIGS. In the reproduction pitch limit circuit 10 of the first embodiment described above, pitch limit data PL (integer part pitch limit data Q and fractional part pitch limit data q) read from the RAM 200 corresponding to the sound generation channel is stored in the pitch limit register 11. On the other hand, in the modification, as shown in FIG. 11, pitch limit data PL (integer part pitch limit data Q and fractional part pitch limit data q) common to all sound generation channels is pitched from a CPU (not shown). The difference is that it is stored in the restriction register 11.

Accordingly, as shown in FIG. 12, the RAM 200 stores the current waveform address AD (the integer part address A and the fractional part address a) excluding the pitch restriction data PL (the integer part pitch restriction data Q and the fractional part pitch restriction data q). ), Pitch data Pitch (integer part pitch data P and fractional part pitch data p), and peak value W are stored in each channel area CH0 to CH63. By doing so, it is possible to reduce the memory size of the RAM 200 while avoiding unnaturalness in the case where a sound generation exceeding the maximum reproduction pitch is instructed as in the first embodiment.

[Modification of Second Embodiment]
Next, a modification of the second embodiment will be described with reference to FIG. In the reproduction pitch limit circuit 400 of the second embodiment described above, the integer part pitch limit data Q read from the RAM 200 corresponding to the sound generation channel is stored in the pitch limit register 11, whereas in the modified example, as shown in FIG. As shown in the figure, the integer part pitch limit data Q common to all the sound generation channels is stored in the pitch limit register 11 from a CPU (not shown). By doing so, it is possible to reduce the memory size of the RAM 200 while avoiding unnaturalness when a sound generation exceeding the maximum reproduction pitch is instructed as in the second embodiment.

  In the above-described first to second embodiments and the modifications thereof, all have been described as waveform generators configured by hardware, but the gist of the present invention is not limited to hardware. Needless to say, the present invention can be applied even when the function is implemented by software.

It is a block diagram which shows the structure of 1st Embodiment by this invention. It is a figure which shows the correspondence of basic clock ck, clock mc [3: 0], and clock mc [9: 4]. It is a memory map which shows the data structure of RAM200 in 1st Embodiment. 3 is a memory map showing a data structure of a waveform memory 26. It is a figure which shows the integration calculation pattern in case the value of the ADC LSB register | resistor 19 is "1". It is a figure which shows the integral calculation pattern in case the value of the ADC LSB register | resistor 19 is "0". It is a time chart for demonstrating operation | movement of 1st Embodiment. It is a block diagram which shows the structure of 2nd Embodiment. It is a memory map which shows the data structure of RAM200 in 2nd Embodiment. It is a figure which shows the reproduction | regeneration pitch upper limit set internally in the pitch limiter 401 corresponding to the output (integer part pitch restriction data Q) of the pitch restriction register. It is a block diagram which shows the structure of the modification of 1st Embodiment. It is a memory map which shows the data structure of RAM200 in the modification of 1st Embodiment. It is a block diagram which shows the structure of the modification of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Playback pitch limit circuit 11 Pitch limit register 12 Comparator 13 Shift control part 14, 17, 23, 32, 33, 40, 52 Selector 15 Pitch register 16, 20, 24, 35, 37, 50 Adder 18 ADC register 19 ADC LSB register 21 STEP register 22 Save register 25 WADR register 26 Waveform memory 27 ADC dec register 28 Controller 30 Differential waveform integration arithmetic circuit 31a to 31d DW0 to DW3 register 34 X register 36 Multiplier 38 Y register 51 M register 100 Clock generator 200 RAM
300 Control unit

Claims (10)

A comparison means for comparing the size of the pitch data representing the playback pitch and the pitch limit data specifying the upper limit of the playback pitch;
Reproduction pitch limiting means for octave shifting and outputting the pitch data until the value does not exceed the pitch limit data when the comparing means determines that the pitch data is larger than the pitch limit data;
And a waveform generating means for generating a waveform by differential waveform reproduction based on the pitch data output from the reproduction pitch limiting means. 2. The waveform generating apparatus according to claim 1, wherein the reproduction pitch limiting means outputs the pitch data as it is when the comparing means determines that the pitch data is smaller than the pitch limiting data. Storage means for storing, for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation, pitch data that represents a playback pitch and pitch limit data that specifies an upper limit of the playback pitch;
2. The waveform generating apparatus according to claim 1, wherein said comparing means reads out the corresponding pitch data and pitch limit data from said storage means for each channel slot to be processed, and compares the magnitudes. Pitch limit data storage means for storing pitch limit data common to all channel slots corresponding to a plurality of sound generation channels that perform time division operation;
Pitch data storage means for storing pitch data representing a reproduction pitch for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation;
The comparison means compares the pitch data read from the pitch data storage means corresponding to the channel slot to be processed with the pitch limit data common to all channel slots read from the pitch limit data storage means. The waveform generator according to claim 1, wherein: Playback pitch limiting means for outputting the playback pitch upper limit value as pitch data when the pitch data representing the playback pitch exceeds the playback pitch upper limit value corresponding to the pitch limit data specifying the upper limit of the playback pitch;
And a waveform generating means for generating a waveform by differential waveform reproduction based on the pitch data output from the reproduction pitch limiting means. 6. The waveform generator according to claim 5, wherein the reproduction pitch limiting means outputs the pitch data as it is when the pitch data is smaller than the reproduction pitch upper limit value. Storage means for storing, for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation, pitch data that represents a playback pitch and pitch limit data that specifies an upper limit of the playback pitch;
The reproduction pitch limit means reads the corresponding pitch data and pitch limit data from the storage means for each channel slot to be processed, and the playback pitch upper limit corresponding to the pitch limit data in which the pitch data specifies the upper limit of the playback pitch 6. The waveform generator according to claim 5, wherein when the value is exceeded, the reproduction pitch upper limit value is output as pitch data. Pitch limit data storage means for storing pitch limit data common to all channel slots corresponding to a plurality of sound generation channels that perform time division operation;
Pitch data storage means for storing pitch data representing a reproduction pitch for each channel slot corresponding to a plurality of sound generation channels that perform time-division operation;
The reproduction pitch limiting means corresponds to the pitch limit data read from the pitch data storage means corresponding to the channel slot to be processed corresponding to the pitch limit data common to all channel slots read from the pitch limit data storage means. 6. The waveform generator according to claim 5, wherein when the reproduction pitch upper limit value is exceeded, the reproduction pitch upper limit value is output as pitch data. A comparison process for comparing the size of the pitch data representing the playback pitch with the pitch limit data specifying the upper limit of the playback pitch;
When it is determined by the comparison process that the pitch data is larger than the pitch limit data, a reproduction pitch limit process for outputting the pitch data by octave shifting until the value does not exceed the pitch limit data; and
A waveform generation processing program comprising: a waveform generation process for generating a waveform in differential waveform playback based on pitch data output in the playback pitch limiting process. When the pitch data representing the playback pitch exceeds the playback pitch upper limit value corresponding to the pitch limit data specifying the upper limit of the playback pitch, the playback pitch limit process for outputting the playback pitch upper limit value as pitch data;
A waveform generation processing program comprising: a waveform generation process for generating a waveform in differential waveform playback based on pitch data output in the playback pitch limiting process.

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