JPH0651778A - Waveform generating device - Google Patents

Abstract

PURPOSE:To reduce the cost by increasing a pitch-up width without increasing the memory capacity of a waveform memory. CONSTITUTION:The waveform memory is stored with plural blocks each consisting of waveform data (a) having one uncompressed waveform sample and three waveform data (b)-(c) having 8 compressed waveform samples; once musical performance data and a timbre number are determined, a specific block is read out and divided through a data divider into a 16-bit uncompressed waveform sample (d) and 8 6-bit compressed waveform samples (e)-(f), and 9 waveform samples are regenerated through a decoder. A 4-data sender selects four successive regenerated waveform samples among the 9 regenerated waveform samples, and one interpolative sample is generated from the four regenerated waveform samples, multiplied by the envelope output waveform of an envelope generator through a multiplier, and outputted as a musical sound signal to a sound system, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generator, and more particularly, to a desired waveform from a waveform memory which stores at least one uncompressed waveform sample and a plurality of compressed waveform samples into one block and stores data of a plurality of blocks. The present invention relates to a waveform generation device that reproduces a waveform sample.

[0002]

2. Description of the Related Art Heretofore, a waveform generator having a waveform memory for digitally converting a waveform sample and storing it has been used as a PCM sound source of an electronic keyboard instrument. Such a waveform generation device, in order to efficiently use the waveform memory,
The expression format of the waveform sample data stored in the waveform memory is not the PCM format but the compressed data expression format. Various types of expression formats have been proposed for the expression format of this compressed data.

For example, a so-called DPC which takes the deviation between each waveform sample and the next waveform sample and stores the deviation.
There is an expression format called the M method.

This DPCM scheme stores one uncompressed waveform sample initially sampled,
The obtained deviations are sequentially stored in a waveform memory. When reproducing a waveform sample before being compressed, the uncompressed waveform sample and the initially stored deviation are added to obtain the next The waveform sample is played,
The desired playback waveform sample is the previous playback waveform sample and the desired playback waveform sample, such that this waveform sample and the second stored deviation are added and the next waveform sample is played back. It is obtained by adding the correspondingly stored deviations.

[0005]

However, in the above-mentioned conventional waveform generating apparatus, when skipping the waveform sample stored in the waveform memory in order to reproduce the sound by pitching up the voice, the previous waveform sample is always read. Is reproduced and the next deviation is not added to the reproduced waveform sample, the desired waveform sample cannot be obtained. Therefore, for example, it is necessary to increase the capacity of the waveform memory that stores the compressed data of the waveform samples instead of increasing the pitch up width and using each waveform in a wide range, which causes a problem of increasing cost. .

Further, there have been cases where it is not possible to follow the fluctuation of the pitch such as the pitch EG because of the limitation of the pitch up.

The present invention has been made in view of the above problems, and it is possible to increase the pitch increase width without increasing the memory capacity of the waveform memory, and it is possible to reduce the cost. An object is to provide a generator.

[0008]

To achieve the above object, the present invention stores at least one uncompressed waveform sample and a plurality of compressed waveform samples into one block to store data of a plurality of blocks. Storage means, a pitch designating means for designating a pitch, a reading means for reading a waveform sample for each block from the storage means based on the pitch designated by the pitch designating means, and a block read by the reading means. And reproducing means for reproducing the compressed waveform sample into the uncompressed waveform sample and extracting means for taking out the waveform sample reproduced by the reproducing means as a desired musical tone signal.

Further, when a waveform is generated by always sampling at a constant sampling frequency irrespective of the frequency of the waveform to be generated, the plurality of reproduced waveform samples for generating the desired musical tone signal. Has an interpolating means for interpolating using m waveform samples, and the interpolating means, when performing interpolation using m waveform samples, selects m−1 from the end of the waveform samples of one block stored in the storage means. The waveform sample of is the same as the m−1 waveform samples from the beginning of the waveform sample of the next block.

[0010]

[Operation] When the pitch is designated by the pitch designating means,
Corresponding to the pitch, the waveform sample stored in the storage means is read out for each block by the reading means, the waveform sample before being compressed is reproduced by the reproducing means, and is output as a musical tone signal by the extracting means.

When a waveform is generated by always sampling at a constant sampling frequency irrespective of the frequency of the waveform to be generated, after the waveform sample before compression is reproduced, the interpolation means is used. The reproduced waveform sample is interpolated to generate an interpolated sample, which is output as a tone signal by the extracting means.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an electronic keyboard instrument having a waveform generating device according to the present invention.

This electronic keyboard instrument includes a tone color switch 1 for designating various tone colors, a detector 2 for detecting the state of the tone color switch 1, a keyboard 3, and a detector 4 for detecting a key depression state of the keyboard 3. The tone color number TN output from the detector 2 and the performance data PD (note code,
A tone generator (waveform generator) 5 that generates a tone signal waveform based on note-on / off data, etc., and a D / that converts a digital signal output by the tone generator 5 into an analog signal.
It is composed of an A converter 6 and a sound system 7 such as a speaker that converts the output signal of the D / A converter 6 into voice.

FIG. 2 is an explanatory diagram for explaining the compressed stored waveform samples stored in the waveform memory of the tone generator 5 and the reproduced waveform samples, which are the features of the present invention.

In the present embodiment, the waveform memory, which will be described later, includes waveform data (a) (FIG. 2a) consisting of 16-bit uncompressed waveform samples (hereinafter referred to as "uncompressed waveform samples"), and 6 Waveform data consisting of bit-compressed waveform samples (hereinafter referred to as "compressed waveform samples")-(b)-(d) (Fig. 2a) is shown in Fig. 2a).
As described above, one data length is 16 bits, and a plurality of blocks are stored with 4 data as one block (that is, nine waveform samples 1 to 9 are stored in one block). When the stored waveform sample is read, it is read in block units. Here, in order to use the memory effectively, the compressed waveform sample ~ is
As shown in (b) to (d) of FIG. 2 a), they are stored in the memory without any space.

FIG. 2B) shows a state in which the read-out waveform data of one block is divided by a data divider described later. For example, the first uncompressed waveform sample
(E) is based on the waveform data (a) of FIG. 2a), and the second compressed waveform sample (f) is based on the lower 6 bits of the waveform data (b) of FIG. 2a). ) Is the upper 4 bits and waveform data of the waveform data (b) in Figure 2a)
It is generated by the lower 2 bits of (c).

FIG. 2C) shows a state in which the waveform data divided in FIG. 2B) is decoded and the waveform sample before being compressed is reproduced. For example, playback waveform sample
(F) is generated by adding the decompressed data of the compressed waveform sample (f) to the uncompressed waveform sample (e) of Fig. 2b), and the reproduced waveform sample (yo) is shown in the waveform sample (f). 2 b)
It is generated by adding the decompressed data of the compressed waveform sample (G).

FIG. 3 is a principle diagram showing a process of reproducing a waveform sample before being compressed from the divided waveform data shown in FIG. 2B). In the figure, the uncompressed waveform sample (e) of FIG. 2B) is directly input to one input terminal of the selector 8 ₁ . On the other hand, the compressed waveform samples (f) to (wa) are
16-bit data is sequentially expanded via the data expansion table 8 ₂ and the expanded data is added by the adder 8 ₃ to the output value of the selector 8 ₁ delayed by the delay circuit 8 ₄ and via the limiter 8 ₅ . Is input to the other input terminal of the selector 8 ₁ .

For example, the compressed waveform sample of FIG. 2b)
When (f) is decompressed into 16-bit data by the data decompression table 8 ₂ and output, the output value of the selector 8 ₁ at this time is an uncompressed waveform sample (e), so the adder 8 ₃
So extended waveform samples and uncompressed waveform samples of the compressed waveform sample (f) and (e) is added, reproducing the waveform samples of Figure 2 c) from the selector 8 ₁ (f) is output. In the same manner, the compressed waveform sample (g) is stored in the data expansion table 8 ₂
By being stretched 16-bit data, when output, extended waveform samples of the compressed waveform sample (g) by the adder 8 ₃ is added to the reproduced waveform sample (f), the reproduced waveform sample from the selector 8 ₁ (Yo) is Is output.

The waveform memory stores not only the blocks having the above-mentioned compressed waveform samples but also all blocks made up of non-compressed waveform samples.

FIG. 2d) shows four reproduced waveform samples output from the four-data transmission circuit described later to the interpolation circuit. The four reproduced waveform samples are consecutive from the nine reproduced waveform samples shown in FIG. 2c). It is the one that was selected.

FIG. 4 is a block diagram showing a detailed configuration of the sound source section 5 as the waveform generating apparatus according to the present invention.

Performance data PD from the keyboard 3 of FIG. 1 is input to a tone generation channel assignment circuit (hereinafter referred to as "assignment circuit") 10. In general, the tone generator section uses each circuit in a time-division manner so that one circuit can generate a plurality of sounds, and the allocation circuit 10 determines which time-divided time slot the performance data PD is allocated to. decide. For convenience of explanation, the performance data PD ′ assigned to one time slot among the performance data PD assigned to a plurality of time-divided time slots will be described below.

An F-number generator 11 and a tone color data generator 13 are connected to the output side of the allocation circuit 10. The note code NC indicating the pitch of the performance data PD 'is sent to the F-number generator 11 and to the F-number generator 11. , Performance data PD ′ is input to the tone color data generator 13.

The F number generator 11 uses the note code NC
The value of F number proportional to the frequency of (pitch) is stored,
The F number value corresponding to the input note code NC is output. Further, when a waveform is generated by always sampling at a constant sampling frequency regardless of the frequency of the waveform to be generated (pitch asynchronous or fixed DAC cycle), the F number corresponds to the frequency specified by the note code NC. The F number generator 11 stores the waveform sample of the selected waveform memory 19 because it is determined as a numerical value consisting of a fractional part and an integer part in proportion to the sampling frequency of the waveform sample stored in the waveform memory 19. The tone data generator 13 supplies a signal FC which conveys information as to which sampling frequency was originally recorded. Then, the F number generator 11 outputs the F number according to the signal FC and the note code NC.

The output side of the F number generator 11 is connected to the input side of the main counter 12, and the main counter 12
Performs counting according to the F number value output from the F number generator 11, and outputs the count value. That is, the main counter 12 outputs a count value proportional to the frequency of the note code NC. Typically,
The count value is a positive real number.

As described above, the performance data PD 'assigned by the assigning circuit 10 is input to the tone color data generator 13 together with the tone color number TN. The tone color data generator 13 controls the envelope control data EC for controlling the envelope of the tone output waveform in accordance with these input signals,
A signal COMP indicating whether the selected waveform data is a compressed waveform sample or an uncompressed waveform sample, a waveform start address WS indicating the start address of a block in the waveform memory 19 of the selected waveform data described later, and the signal FC are output. . Here, the signal COMP is "H".
The level indicates that the selected waveform data is a compressed waveform sample, and the level “L” indicates that it is an uncompressed waveform sample.

As described above, the output value of the main counter 12 is a positive real number, and the signal INT indicating the integer part and the signal FRA indicating the fractional part respectively corresponding to one waveform sample.
C is fetched separately. The signal INT is branched into two, one of which is directly input to one input terminal of the selector 14,
The other is multiplied by 4 via the 2-bit shift circuit 15 and input to the other input end of the selector 14. Further, the signal COMP is input to the selector 14, and the selector 14
Is the directly input signal IN when the signal COMP is at "L" level (0), that is, when it is an uncompressed waveform sample.
T is output, and at the time of "H" level (1), that is, the compressed waveform sample, the signal INT multiplied by 4 is output.

The output side of the selector 14 has an adder 16
The waveform start address WS is input to the other input end of the adder 16, and the output value of the selector 14 is added to the waveform start address WS. That is, the start address of the block to be read from the waveform memory 19 is determined based on the pitch selected by the note code NC.

The output side of the adder 16 is connected to one input end of the adder 17, and the output side of the auxiliary counter 18 is connected to the other input end of the adder 17. Auxiliary counter 1
A waveform data reading counter 8 outputs an integer value from 0 to 3, and the counter value is added by the adder 17 to the adder 1
It is added to the address designated by the output value of 6, and the addresses of four continuous waveform data corresponding to one block are sequentially output to the waveform memory 19. That is, when a block having a compressed waveform sample is designated, the auxiliary counter 18 outputs "0" when the non-compressed waveform sample is read, and when the compressed waveform sample is read, the auxiliary counter 1 to 3 depending on its storage position. The value of is output.

The output side of the adder 17 is connected to the input side of the waveform memory 19, and the adder 17 sequentially inputs the addresses of the four waveform data to the waveform memory 19, and the waveform memory 19 Outputs the waveform data specified by the address value.

The output side of the waveform memory 19 is connected to the input side of the data divider 20 and the input side of the delay circuit 22.

FIG. 5 is a block diagram showing the detailed structure of the data divider 20. As described above, the data divider 20 is configured to divide the non-compressed waveform samples as they are into the compressed waveform samples 1 to 6 and output the divided 6-bit data. In FIG. 5, the data divider 20 includes a latch circuit 51, a selector 52, a delay circuit 53, and a timing adjustment circuit 54. All the output bits (0 to 15 bits) of the waveform memory 19, that is, the uncompressed waveform sample of the waveform data (a) in FIG. 2A is input to the latch circuit 51, and the latch circuit 5
When the select signal S1 is input, 1 outputs the latched data to the decoder described later.

On the other hand, each input terminal (I ₁ to
I ₈ ), from the waveform memory 19 shown in FIG.
The bits corresponding to the compressed waveform samples stored in waveform data (b) to (d) are input. For example, the input terminal I _1, 0 to 5 bits, i.e., the compressed waveform samples of the waveform data (b) is input directly, to the input terminal I _3,
12 to 15 bits and directly via the delay circuit 53,
0 to 1 bit, that is, waveform sample data (b) and
The compressed waveform sample of (C) is input.

Similarly, bits corresponding to other compressed waveform samples are input to the other input terminal of the selector 52 in the same manner. In this way, the delay circuit 53 delays the compressed waveform sample stored in the previous waveform data when the compressed waveform sample is stored across adjacent waveform data, like the compressed waveform sample and. , And is used to input to the selector 52 substantially at the same time as the compressed waveform sample stored in the subsequent waveform data.

Further, the selector 52 has a select signal Sn.
Is input, and the compressed waveform samples are sequentially output to the timing adjustment circuit 54 in accordance with the signal Sn.
The timing adjusting circuit 54 corrects the time slot intervals of the compressed waveform samples time-divided and output from the selector 52 in this way so as to be uniform.

Here, the tone generator section 5 has a system clock generator (not shown), and the system clock generator generates a system clock necessary for the operation of the entire apparatus.
Further, the system clock is supplied to a timing signal generator (not shown), and various timing signals are generated by the timing signal generator. Said signals S ₁ and Sn
Are generated and supplied by this timing generator.

The output side of the data divider 20 is the decoder 2
The compressed waveform sample which is connected to the input side of No. 1 and whose timing is adjusted by the timing adjustment circuit 54 is the decoder 2
1 is output as a signal Wb.

The decoder 21 performs the process of reproducing the compressed waveform sample into the non-compressed waveform sample based on the signal Wb, as described in FIG. 2c).

FIG. 6 is a block diagram showing a detailed configuration of the decoder 21. Since this diagram is substantially the same as the principle diagram described in FIG. 3, the same elements are designated by the same reference numerals, Detailed description is omitted.

As described with reference to FIG. 3, the data divider 20
Of the signal Wb output by the non-compressed waveform sample is directly input to one input terminal of the selector 8 ₁ .
After compression waveform sample-is, which is extended by the data decompression table ₈₂ in 16-bit data is added immediately before the signal output from the selector ₈₁ through the delay circuit 8 _4, a selector 8 ₁ via the limiter 8 ₅ Is input to the other input terminal of. The selector 8 ₁ outputs one of these two input signals according to the select signal SD supplied by the timing generator. The output signal of the selector 8 ₁ is input to the delay circuit 8 ₄ , and the delayed output signal is
It is branched into two, one is returned to the adder 8 ₃ and the other is output as a signal Wc.

The output side of the decoder 21 is connected to one input terminal of the 4-data transmitter 23, and the output side of the delay circuit 22 and a delay circuit 24, which will be described later, are connected to the other input terminal of the 4-data transmitter 23. 28 outputs are connected. Then, the signal Wc output from the decoder 21 is input to the 4-data sending circuit 23 together with the output signal Wa of the non-compressed waveform data of the waveform memory 19 delayed by the delay circuit 22. Further, in the 4-data transmission circuit 23, a fractional part FRAC, which will be described later, is multiplied by 6 and carried to the integer part FR.
A signal obtained by delaying INT through the delay circuit 24 (hereinafter,
The “sample selection signal” SS and the COMP signal delayed by the delay circuit 28 are input.

Now, the sample selection signal SS will be described.

As described above, the output signal of the main counter 12 is separated and taken out into the integer part INT and the decimal part FRAC, and the decimal part FRAC is further branched into two, one of which is the 1-bit shift circuit 25. , 26 and the adder 27, the signal is multiplied by 6 and input to the delay circuit 24, and the other is input directly to one input terminal of the selector 30. This 6-fold fractional part FRAC is separated into an integer part FRINT and a fractional part FRFRAC that carry up to an integer. The integer part FRINT is input to the 4-data transmitter 23 as the sample selection signal SS via the delay circuit 24.
This sample selection signal SS will be described later with reference to FIG.
4 consecutive from the 9 reproduced waveform samples shown in c)
Used to retrieve one playback waveform sample. On the other hand, the fractional part FFRRAC is input to the other input end of the selector 30. Further, the signal COMP is input to the select terminal of the selector 30, and the selector 30 outputs the fractional part FFRRAC when the signal COMP is at “H” level, and the decimal number from the main counter 12 when it is at “L” level. The section FRAC is output.

The reason for taking out the integer part FRINT by multiplying the fractional part FRAC by 6 is that there are 6 types of sample selection signals SS, as will be described later, and by multiplying by 6, these 6 types of sample selection signals This is because SS can be selected conveniently. That is, the range of the decimal part FRAC is 0 to
0.9 ···, and multiplying this by 6 gives 0 to 5.9 ···
Since the range of the integer part is 0 to 5, by associating each integer value with the 6 types of sample selection signals SS, the 4 data transmitter 23 will describe the 4 consecutive reproduction waveform samples described later. Can be sent to the interpolation circuit.

This is because nine waveforms can be reproduced for each compressed block, and there are six ways of selecting four samples for interpolation from among them. One block is the address for six samples during reproduction. It corresponds to.

The signal output from the selector 30 is input to the delay circuit 31 and output to the interpolating circuit 29 described later as the signal FRAC '.

FIG. 7 is a block diagram showing the detailed structure of the 4-data transmitter 23.

In the figure, the output Wc of the decoder 21
Is input to one input end of the selector 71, and the delayed signal Wa is input to the other input end of the selector 71. In addition, the select terminal of the selector 71 is connected to the signal COM.
P is input, and the signal COMP is similarly supplied to the selector 7
It is also input to the 2 select terminal.

A signal NP, which will be described later, is input to one input terminal of the selector 72, and the other input terminal is provided with six kinds of different timings generated by the selection pulse generator 73 according to the sample selection signal SS. Selection pulse SP (pulse number 4) is input.

The output side of the selector 71 is connected to the data input terminal of the delay circuit with a capture pulse 74, and the output side of the selector 72 is connected to the capture pulse input terminal of the delay circuit with a capture pulse 74.

The selector 71 responds to the signal COMP by
When the data is not compressed, the delayed data Wa is selected, and when the data is compressed, the output data Wc of the decoder 21 is selected and sent to the delay circuit with a pulse 74. Further, the selector 72 takes in the signal NP when the data is not compressed and the sample selection signal SS (selection pulse SP) when the data is compressed, and sends it to the delay circuit with pulse 74 in accordance with the signal COMP.

The delay circuit 74 with a fetch pulse is based on the output pulse output from the selector 72, and four playback waveform samples or delays from the playback waveform samples of the decoder output Wc output from the selector 71, '-'. Data output Wa data (a) to (d) (R ₁
To R ₄ ) (hereinafter, both are collectively referred to as “waveform data”) are output to the delay circuit 75. Like the delay circuit 74, the delay circuit 75 is also a delay circuit with a capture pulse,
Further, the delay circuit 75 has a signal NP which is a clock for outputting the waveform data input by the delay circuit 74.
Also, the load signal LD, which is a pulse for determining the timing of taking in the four waveform data and the timing of outputting the waveform data, is input from the delay circuit 74. The delay circuit 75 receives the four waveform data captured by the delay circuit 74 in response to the signal LD, and then outputs the signal NP.
The input waveform data is output as a signal Wd to the interpolation circuit 26 in synchronism with.

Here, the signals LD and NP are generated and supplied by the timing generator.

The present embodiment is an application of the present invention to a so-called pitch asynchronous type waveform generator which generates a waveform by always sampling at a constant sampling frequency regardless of the frequency of the waveform to be generated. , In this type of waveform generator, the frequency of the generated waveform is
Anharmonic folding noise may occur and needs to be removed. Therefore, for example, as described below, a four-point interpolation method for generating one output waveform from the four reproduced waveform samples is required, and an interpolation method similar to this is already applied to six-point interpolation. It has been disclosed (JP-A-63-168695).

Further, in the present embodiment, when a desired musical tone signal is generated, the musical tone signal is generated only from the waveform samples included in one block. This is because it is not necessary to read a plurality of blocks when generating the tone signal, and the interpolator can be configured with a simple circuit. Therefore, when the 4-point interpolation method is applied to this embodiment, the last three waveform samples of the read block and the first three waveform samples of the next block must have the same data in duplicate. That is, this embodiment is 1
Since there are 9 waveform samples in a block, and 3 of them are common to the next block, they actually correspond to the storage areas for 6 waveform samples.

FIG. 8 is a block diagram showing the detailed structure of the interpolation circuit.

In FIG. 8, the output signal Wd (four waveform data sequentially transmitted) from the four data transmission circuit 23 is input to one input end of the multiplier 81, and the other input end of the coefficient generator 82. Output is input. The coefficient generator 82 includes
The output signal FRAC 'from the delay circuit 31 and the output of the auxiliary counter 83 are input, a predetermined coefficient is selected based on both input signals, and the coefficient is multiplied by the input signal Wd by the multiplier 81. The multiplied input signal Wd is
It is input to the adder 84. The output of the adder 84 is delayed via the delay circuit 85 and branched into two. One is input to the gate 87 and the other is input to the latch circuit 88. Further, the interpolation timing signal IP supplied from the timing generator is inverted via the inverter 86 and input to the gate 87 and directly to the latch circuit 88.

Of the four waveform data of the signal Wd (which will be referred to as S1, S2, S3 and S4 in order), the waveform data S1 that is output first is the output "0" of the auxiliary counter 83.
And a coefficient selected by the signal FRAC ′ (hereinafter, α ₁
Is multiplied by the multiplier 81, and the resulting data α ₁ · S1 is input to the adder 84. At this time, the interpolation timing signal IP becomes "H" level and the gate 8
7 is closed, and the data α ₁ and S ₁ remain unchanged in the delay circuit 8
Input to 5. Next, the waveform data S ₂ of the signal Wd is
The output “1” of the auxiliary counter 83 is multiplied by the coefficient (hereinafter referred to as α ₂ ) selected by the signal FRAC, and the resulting data α ₂ · S2 is the data α ₁ · S1 delayed by the delay circuit 85. Is added and input to the delay circuit 85 again. Similarly, the data α ₃ · S ₃ is changed to α ₁ · S.
₁ + α ₂ · S ₂ is added, and α ₄ · S 4 is α ₁ · S ₁ + α ₂ ·
S ₂ + α ₃ · S ₃ is added, and the result of adding all in synchronization with the IP signal (hereinafter referred to as “interpolation sample”) is output from the delay circuit 85 at the latch circuit 88.
This interpolated sample We is output from the latch circuit 88 by the next rising pulse of the IP signal.

The output side of the interpolation circuit 29 is connected to one input end of the multiplier 34, and the other input end of the multiplier 34 is connected to the envelope generator 33.

The generated interpolation sample We is output from the tone color data generator 13 and based on the envelope control data EC delayed by the delay circuit 32, the envelope waveform generated by the envelope generator 33 and the multiplier 34. 1 and the resulting data is accumulated by the channel accumulator 35 for all of the multiple time division channels of one DAC cycle, and the resulting D / A of FIG.
It is converted into analog by the converter 6 and converted into a musical sound through the sound system 7.

The operation of this embodiment will be described in detail below with reference to FIG.

FIG. 9 is a timing chart showing the timing of data and timing signals until one interpolation sample is generated from the waveform data of one block (4 data) read from the waveform memory 19.

As described above, the waveform memory 19 shown in FIG. 4 stores a plurality of waveforms each including a compressed waveform sample and all non-compressed waveform samples, and the performance data PD and the tone color number TN are determined. For example, a waveform address corresponding to this is selected by the tone color data generator 13, and a waveform containing a compressed sample (COMP = 1) or a waveform containing no compressed sample (COMP) is selected according to the address of the selected block. = 0) is the waveform memory 19
Read from.

Hereinafter, description will be given separately for the case where the waveform is a waveform including a compressed waveform sample and the case where the waveform is a waveform including all non-compressed waveform samples.

First, the case where the waveform including the compressed waveform sample shown in FIG. 9A) is selected will be described.

When the performance data PD and the tone color number TN are determined, the assignment circuit 10 assigns the performance data PD 'to a certain time-divided time slot, and the performance data PD' is directly sent to the tone color data generator 13. The note code NC that has been input and is included in the performance data PD '.
Is also input to the F number generator 11.

The tone color data generator 13 outputs the signal FC to the F number generator 11 based on the input performance data PD and tone color number TN, and controls so that a predetermined F number is output. In this way, the main counter 12 counts according to the F number value generated based on the note code NC, and outputs the count value. Of this count value, the integer part INT is multiplied by 4 by the 2-bit shift circuit 15 in order to read the four waveform data at once, and is input to one input terminal of the selector 14. At this time, since the signal COMP input to the selector 14 selects the compressed waveform sample, the selector 14 outputs the integer part INT multiplied by four.

The output signal of the selector 14 is added to the waveform start address WS generated by the tone color data generator 13 by the adder 16, and the added value is added to the auxiliary counter 1
The output values 0 to 3 sequentially output from 8 are added by the adder 17, and the addresses of the four waveform data from the adder 17 are input to the waveform memory 19 as shown in FIG. 9A). The waveform data R1 to R4 of one block are sequentially output from the waveform memory 19.

The waveform data R1 output in this way
~ R4 is one uncompressed waveform sample (Fig. 9b) -2) and eight compressed waveform samples in the data divider 20 ~
(Fig. 9b) -4). That is, in FIG. 5, the waveform data R1 is latched by the latch circuit 51 and continuously output as shown in FIG. 9b) -2 by the timing signal S1 shown in FIG. 9b) -1.

On the other hand, the waveform data R2 to R4 are divided by the selector 52 into compressed waveform samples ~, and the compressed waveform samples ~ are adjusted in timing from the selector 52 by the timing signal Sn shown in Fig. 9b) -3. The signals are sequentially output to the circuit 54, and as shown in FIG. 9B) -4, each 6-bit compressed waveform sample is output at the same time interval.

The waveform samples divided by the data divider 20 are input to the decoder 21 as the output signal Wb, and the decoder 21 generates original reproduction samples based on the divided waveform samples.

As shown in FIG. 6, the waveform sample is input to one input terminal of the selector 8 ₁ , and when the select signal SD shown in FIG. 9c) -1 becomes "H" level, the selector 8 ₁ Output a waveform sample (Fig. 9c)-
2).

The waveform sample is expanded into 16-bit data by the data expansion table 8 ₂ and added by the adder 8 ₃ with the waveform sample output from the selector 8 ₁ and delayed by the delay circuit 8 ₄ , resulting in the addition result ( Hereinafter, it is input to the other input terminal of the selector 8 ₁ via a limiter 8 ₅ for preventing overflow of "reproduced waveform sample '"). This reproduced waveform sample 'is shown in FIG.
c) -1, the select signal SD is "L".
When it reaches the level, it is output from the selector 8 ₁ (see FIG. 9).
c) -2).

[0076] In the same manner, the waveform sample-is added to the immediately preceding waveform samples respectively, the reproduced waveform sample '~' are sequentially outputted from the selector ₈₁ (Fig. 9 c) -2).

The reproduced waveform samples ~ 'reproduced in this way are output to the 4 data transmitter 23 as the output signal Wc.
Is output to. As shown in FIG. 7, this output signal Wc
Is input to one input terminal of the selector 71. At this time, since the signal COMP input to the select terminal of the selector 71 is at the “H” level, it is output as it is to the delay circuit with a fetch pulse 74. Further, at this time, the output signal of the selector 72 is the signal COMP as in the selector 71.
Thus, the output signal SP of the selection pulse generator 73 is selected. That is, of the six types of selection pulses shown in FIG. 9 d) -1, one selection pulse SP selected by the value of the signal SS is input to the pulse input terminal of the delay circuit with a capture pulse 74. The delay circuit with capture pulse 74
Based on this selection pulse SP, four continuous reproduction waveform samples are selected from the reproduction waveform samples output from the selector 71, and when a pulse of the load signal LD is input, it is output to the delay circuit with a capture pulse 75. .

The four reproduced waveform samples captured by the delay circuit with capture pulse 75 in synchronization with the load signal LD (FIG. 9d) -4) are the pulses of the signal NP (FIG. 9d).
It is output as the signal Wd in synchronization with the falling edge of -2) (Fig. 9d) -5).

Reproduced waveform sample S1 of this output signal Wd
~ S4 are input to the interpolation circuit 29. As shown in FIG. 8, the reproduced waveform sample S1 is output by the multiplier 81 to the output value "0" of the auxiliary counter 83 and the fractional part F multiplied by 6.
Coefficient generator 8 whose fractional part FRFRAC of the RAC is selected by the delayed signal FRAC 'via the delay circuit 31.
It is multiplied by a coefficient α _{1 of} 2. The output signal α ₁ · S1 of the multiplier 81 is added to the output signal of the gate 87 by the adder 84. At this time, as shown in FIG. 9e) -1, the signal input to the gate 87. Since IP is at "H" level, it is inverted by the inverter 86 and becomes "L" level, and the output signal of the gate 87 becomes zero. Therefore, the output of the multiplier 81 is directly input to the delay circuit 85. The output signal delayed by the delay circuit 85 is branched into two, one of which is input to the gate 87 and the other of which is input to the latch circuit 88.

The reproduced waveform sample S2 is the output value "1" of the auxiliary counter 83, like the reproduced waveform sample S1.
And the coefficient selected by the signal FRAC 'and multiplied by the adder 84 with the output signal of the gate 87.
At this time, as shown in FIG.
Is at the “L” level, the delayed signal α ₁ · S1 is output from the gate 87, and the output signal of the adder 84 becomes α ₁ · S1 + α ₂ · S2, which is delayed by the delay circuit 85. It is latched by the latch circuit 88.

Similarly, reproduced waveform samples S3 and S4
Is multiplied by the coefficients α ₃ and α ₄ respectively by the multiplier 81, and is added to the previous addition result by the adder 84, and finally the signal α ₁ · S1 + α ₂ · S2 + α ₃ · S3
+ Α ₄ · S4 is delayed by the delay circuit 85, and the latch circuit 8
Latched by 8. As shown in FIG. 9 e) -1, 2, the interpolation sample We (signal α ₁ · S 1 + α ₂ · S 2 + α ₃ · S) is synchronized with the next rising pulse of the signal IP.
3 + α ₄ · S4) is output from the latch circuit 88.

This interpolated sample We is multiplied by the envelope waveform which is the output signal of the envelope generator 33 by the multiplier 34, and the output signal of each channel is accumulated by the channel accumulator 35. Is output as a musical sound through.

Next, a case will be described in which a block consisting of all uncompressed waveform samples is selected from the stored waveforms stored in the waveform memory 19 by the performance data PD and the tone color number TN.

When the performance data PD and the tone color number TN are determined, as described above, the performance data PD is assigned to a certain time slot which is time-divided by the assigning circuit 10, and the tone color data generator 13 outputs various control signals. , The F number generator 11 outputs the F number value,
The main counter 12 counts on the basis of this F number value, and the real count value is the integer part INT.
And a fractional part FRAC.

At this time, the integer part INT has the selector 14
Since the signal COMP input to the select terminal of is at "L" level, it is output from the selector 14 as it is.
This output signal INT is added to the waveform start address WS in the adder 16, and the addition result is sequentially added to the output values 0 to 3 of the auxiliary counter 18 in the adder 17 and designated by the output value of the adder 17. According to the address, four uncompressed waveform samples are sequentially output from the waveform memory 19, delayed by the delay circuit 22, and input to the four data transmitter 23.

As shown in FIG. 7, at this time, the selector 7
The signal COMP input to the select terminals 1 and 72 is
Since it is at the "L" level, the selector 71 outputs the non-compressed waveform sample delayed by the delay circuit 22 to the delay circuit 74 with a fetch pulse, and the selector 72 outputs the signal NP shown in FIG. Is output to the pulse input terminal of the delay circuit with a capture pulse 74, and the pulse of the load signal LD is input (FIG. 9d) -4),
In synchronism with the falling edge of the pulse of the signal NP, the delay circuit with a fetch pulse 74 delays the delay circuit 7 with a fetch pulse.
5, the uncompressed waveform samples R1 to R4 are output.

Non-compressed waveform sample R1 fetched in the delay circuit with fetch pulse 75 in synchronization with the load signal LD
~ R4 are the pulses of the signal NP (see FIG. 9) as described above.
The signal Wd is output in synchronization with the falling of d) -2) (Fig. 9d) -5).

The signal Wd is input to the interpolation circuit 29.
At this time, since the signal COMP input to the selector 30 is at “L” level, the selector 30 outputs the fractional part FRAC as it is, and the signal FRAC ′ delayed by the delay circuit 31 is input to the interpolation circuit 29. To be done.

The processing after the interpolation circuit 29 is the same as that when the block including the compressed waveform sample is selected, and therefore the detailed description thereof will be omitted.

As described above, according to the present embodiment, each block has one uncompressed waveform sample and the waveform sample is read out in block units. Therefore, even if the pitch is increased and skipped reading is performed. , The waveform sample can be regenerated, and the waveform memory can be used efficiently because it has the compressed waveform sample, thereby reducing the memory capacity and suppressing the increase in cost. be able to.

Although the waveform generating apparatus according to the present invention is applied to the sound source of an electronic musical instrument in this embodiment, the present invention is not limited to this. For example, it is stored in a memory such as an answering machine or a tape recorder equipped with a voice memory. It can also be applied to skipped reading of the waveform sample for the purpose of changing the pitch.

Further, in this embodiment, since four-point interpolation is performed, one block including a compressed waveform sample has six waveform samples as described above, but this interpolation may be stopped. In that case, one block is 9 because there is no need to have overlapping waveform samples between blocks.
It corresponds to the address of one waveform sample.

Further, although the DPCM is adopted as the method of compressing the waveform samples in the present embodiment, the method is not limited to this, and LPCM is used.
A compression method that can obtain the current reproduction value based on the past reproduction value and new data such as PC and ADPCM can be applied.

The present invention is also effective when applied to a compressed waveform memory sound source in which a part of the stored waveform samples is loop-read. By doing so, when returning to the loop start, no special processing is required.

Although one block is composed of one uncompressed waveform sample and eight compressed waveform samples, the number of compressed waveform samples in one block may be arbitrarily changed.

[0096]

As described above, according to the present invention,
By at least one uncompressed waveform sample and a plurality of compressed waveform samples as one block, storage means for storing data of a plurality of blocks, pitch designating means for designating a pitch, and the pitch designating means Reading means for reading the waveform sample from the storage means for each block based on a designated pitch; and reproducing means for reproducing the compressed waveform sample of the block read by the reading means into a waveform sample before compression. Since the waveform sample reproduced by the reproducing means is taken out as a desired musical tone signal, the waveform sample can be reproduced even if the pitch is increased and skip reading is performed, and the pitch increase range is increased. The size of the memory can be increased and the waveform memory can be used efficiently, which reduces the memory capacity and reduces the cost. An effect that it is possible to suppress the pressure.

Further, when a waveform is generated by always sampling at a constant sampling frequency regardless of the frequency of the waveform to be generated, the plurality of reproduced waveform samples for generating the desired musical tone signal. Has an interpolating means for interpolating using m waveform samples, and the interpolating means, when performing interpolation using m waveform samples, selects m−1 from the end of one block of waveform samples stored in the storage means. Since the waveform sample of is the same as the m−1 waveform samples from the beginning of the waveform block of the next block, when the desired musical tone signal is generated, the waveform sample in the next block is used without being read. The musical tone signal can be generated only from the waveform samples in one block that is output, which has the effect of simplifying the circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an electronic keyboard instrument having a waveform generation device according to the present invention.

FIG. 2 is an explanatory diagram illustrating a compressed stored waveform sample stored in a waveform memory that constitutes a waveform generation device according to the present invention and a reproduced waveform sample thereof.

FIG. 3 is a principle diagram showing a process of reproducing an original uncompressed waveform sample from waveform data divided by a data divider.

FIG. 4 is a block diagram showing a configuration of a waveform generation device according to the present invention.

5 is a block diagram showing a configuration of a data divider that constitutes the waveform generation device of FIG.

FIG. 6 is a block diagram showing a configuration of a decoder which constitutes the waveform generation device of FIG.

7 is a block diagram showing a detailed configuration of a 4-data transmission circuit 23 which constitutes the waveform generation device of FIG.

FIG. 8 is a block diagram showing a configuration of an interpolation circuit that constitutes the waveform generation device of FIG.

FIG. 9 is a timing chart showing the timing until one interpolation sample is generated from one block of waveform data read from the waveform memory.

[Explanation of symbols]

 1 tone color switch 2 keyboard 11 F number generator (reading means) 12 main counter (reading means) 13 tone color data generator 19 waveform memory (storage means) 20 data divider 21 decoder 23 4 data transmitter 29 interpolation circuit (interpolation means) ) 33 Envelope generator (take-out means)

Claims (2)

[Claims] 1. Storage means for storing data of a plurality of blocks by dividing at least one uncompressed waveform sample and a plurality of compressed waveform samples into one block,
Pitch designating means for designating a pitch, reading means for reading a waveform sample for each block from the storage means based on the pitch designated by the pitch designating means, and a compressed waveform of the block read by the reading means. A waveform generating apparatus comprising: a reproducing unit that reproduces a sample into a waveform sample before compression; and an extracting unit that extracts the waveform sample reproduced by the reproducing unit as a desired musical tone signal. 2. A plurality of regenerated waveform samples for generating the desired musical tone signal when a waveform is generated by always sampling at a constant sampling frequency regardless of the frequency of the waveform to be generated. Has an interpolating means for interpolating using m waveform samples, and the interpolating means, when interpolating using m waveform samples, selects m− from the end of one block of waveform samples stored in the storage means.
2. The waveform generating device according to claim 1, wherein one waveform sample is the same as m−1 waveform samples from the beginning of the waveform sample of the next block.