JPH08106299A - Voice signal time base conversion device - Google Patents

Abstract

PURPOSE: To realize a voice signal time base conversion device capable of changing arbitrarily the speaking speed of a voice signal reproduced at high speed and which is of a low cost. CONSTITUTION: The voice signal reproduced at high speed is inputted to a memory 22. A second clock signal having an N-fold frequency with respect to a first clock signal is applied to readout address counters 24, 25. Voice data of two adjacent sections are read out by address signals of these address counters to be respectively held in latches 27, 28. These signals are applied to a cross fade circuit 29 and two signals are added by simultaneously performing a fade-out and a fade-in. The added signal and the signal held in the latch 27 are changed over based on a reproducing speed setting signal. Then, the interval at the time of a recording is maintained and the voice signal whose speaking speed is arbitrarily conversed is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs high speed reproduction or low speed reproduction of an audio signal in an apparatus for reproducing an audio signal recorded in a video tape deck (hereinafter abbreviated as VTR), a multi-laser disc player or the like. The present invention relates to an audio signal time base conversion device used at that time.

[0002]

2. Description of the Related Art In recent years, by mounting a voice signal time base converter on a VTR, even if a voice is reproduced at a reproduction speed twice as fast as that at the time of recording, the pitch and the speed of voice (speech speed) at the time of recording can be improved. It is possible to play.

A voice signal time base conversion device (also referred to as C & P) in a first conventional example mounted on a VTR will be described below. FIG. 4 is a block diagram showing a configuration example of a conventional audio signal time base conversion device 100. In the figure, the audio signal time base converter 100 is an analog-digital converter (A
/ D converter) 101, memory 102, digital-analog converter (D / A converter) 103, write address counter 104, and read address counter 105. The input terminal 1 is an input terminal for the analog audio signal S1 to be subjected to speed conversion, the input terminal 3 is the input terminal for the clock signal S11 of the A / D converter 101, and the input terminal 4 is the clock for the D / A converter 103. Input terminal for signal S12,
The output terminal 2 is an output terminal of the speed-converted analog audio signal S2.

The operation of the audio signal time base converter 100 configured as described above will be described with reference to FIGS. 4 and 5. The audio signal S1 reproduced at a reproduction speed twice that at the time of recording is input to the A / D converter 101 via the input terminal 1. This signal is sampled at the cycle of the clock signal S11 and converted into a digital audio signal S21. This audio signal S2
1 is input to the memory 102. Further, the write address counter 104 inputs the clock signal S11 and gives the write address signal S22 to the memory 102. The audio signal S21 thus converted is written in the memory 102.

To read the audio data in the memory 102, the read address counter 105 uses the clock signal S12.
And the read address signal S23 is input to the memory 102.
Give to. Here, the cycle of the clock signal S12 is twice the cycle of the clock signal S11. Therefore, memory 1
The audio signal S21 written in 02 is read from the memory 102 as an audio signal (audio data) S24 having a double cycle. The audio data S24 is input to the D / A converter 103 and converted into an analog audio signal S2. The frequency of the audio signal S2 is half the frequency of the audio signal S1.
For example, when the audio signal S1 is a signal reproduced at a double speed by a special reproduction such as a VTR, the frequency thereof is twice that of the normal reproduction, and therefore the frequency of the audio signal S2 is the same as that of the normal reproduction (during recording). Become.

FIG. 5 is a diagram for explaining the operation of the audio signal time base converter 100, and schematically shows the time structure of the signal. FIG. 5A shows the time structure of the signal in the normal reproduction, and the audio signal is continuous like A, B, ... D. FIG. 5 (b) shows a case where the reproduction is performed at a double speed, and the audio signals are A to a, B to b, and so on.
The playback time of each audio signal is compressed in half.

Now, in the case of double speed reproduction, the reproduction frequency of the sound becomes twice the original frequency. On the other hand, FIG.
FIG. 3 shows a time structure of an output audio signal when the audio signal of (b) is input to the audio signal time base converter 100. Here, a is converted to A and d is converted to D, and the frequency becomes the same as that of the signal for normal reproduction. However, there is a drawback that b is only partially reproduced and becomes B ′, and c is not reproduced at all. The reason is that the capacity of the memory 102 is limited,
This is because the period of the clock signals S11 and S12 and the recordable time determined by the capacity of the memory 102 are limited.

Here, the speech speed means that, for example, meaningful voices A, B, C and D are as shown in FIG.
As shown in (c), when the content is converted into audible sounds A, B ', D, it indicates the ratio of the reproduction time of the audio signal of (a) to the reproduction time of the audio signal of (c). I shall.

The case where the audio signal reproduced at double speed is converted to the audio signal for normal reproduction, that is, the signal having the speech speed and the pitch during normal reproduction has been described above.

Next, as a second conventional example, an audio signal time base conversion device for converting an audio signal reproduced at double speed into an audio signal having an arbitrary speech speed while having a pitch during normal reproduction will be described. FIG. 6 is a block diagram showing the configuration of a second conventional audio signal time base converter 200. As shown in this figure, the audio signal time base conversion device 200 is composed of the same audio signal time base conversion device 100a and pitch conversion device 100b as in the first conventional example. Here, circuit blocks having the same functions as those of the first conventional example are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 6, a voice signal time base conversion device 1
Input terminal 3 for the first clock signal S11 input to the A / D converter 00a, audio signal time base conversion device 100a
First clock signal S12 input to the D / A converter of
In addition to the input terminal 3 of
An input terminal 5 for the third clock signal S13 input to the D converter and an input terminal 6 for the fourth clock signal S14 input to the D / A converter are newly provided.

The operation of the audio signal time base converter 200 configured as described above will be briefly described. 2 when recording
The audio signal S1 reproduced at the double reproduction speed is input to the input terminal 1
Is input to the A / D converter in the audio signal time base conversion device 100a, and by changing the frequency of the clock signal S12 with respect to the clock signal S11, an audio signal S2 having a speech speed different from that during normal reproduction is obtained. It has already been explained that it is converted. When the audio signal is reproduced at a reproduction speed twice as high as that at the time of recording, the frequency of the clock signal S11 is FS.
11. If the frequency of the clock signal S12 is FS12 and the speech speed for normal reproduction is SS1, the following equation (1) is established.

[Equation 1] Here, the constant 2 in the equation (1) indicates that the reproduction speed is twice the normal speed.

Further, the pitch for normal reproduction is set to KE1.
Then, the following equation (2) is established.

[Equation 2] For example, in the case of the first conventional example, SS1 is 1, and the speech speed is the same as in normal reproduction. Furthermore, KE1 in the equation (2) is 1
And the pitch is the same as in normal reproduction. But (1)
If an arbitrary voice speed different from the normal reproduction is set according to the formula, the output audio signal is automatically set to a pitch different from the normal reproduction according to the formula (2). Therefore, in order to obtain the audio signal S3 having the same pitch as that in the normal reproduction, the signal S2 output from the audio signal time base conversion device 100a is converted into the pitch conversion device 1.
Give to 00b. The clock signal S13 and the clock signal S14 are supplied to the pitch conversion device 100b as a write clock and a read clock to convert the pitch conversion ratio to a desired value.

If the pitch conversion ratio by the pitch converter 100b is KE2, the following equation (3) is established.

(Equation 3) The pitch conversion ratio KE2 is the writing clock signal S1.
It is a value obtained by dividing the period of 3 by the period of the read clock signal S14.

The pitch converting device 100b is disclosed in, for example, Japanese Patent Laid-Open No.
It is realized by the device disclosed in Japanese Patent Laid-Open No. 1-29000. FIG. 7 is a block diagram showing the configuration of the pitch converting device 100b of JP-A-61-29000. In this figure, blocks having the same functions as those of the audio signal time base converter 100 shown in FIG. Now, the pitch conversion device 100b is A /
D converter 101, memory 102, first D / A converter 1
03, a second D / A converter 106, a write address counter 104, a read address counter 105, a first electronic volume 107, a second electronic volume 108, and an adder 109. And the pitch conversion device 100
b, as in the device of FIG. 4, the input terminal 1 for the audio signal S2, the input terminal 3 for the clock signal S11, and the clock signal S
Twelve input terminals 4 and an output terminal 2 for the audio signal S3 are provided. Here, the description of the operation of the pitch converting apparatus 100b is omitted.

[0016]

However, the above-mentioned first problem
In the configuration of the conventional example, there is a problem that the reproduced voice signal cannot be set to an arbitrary speech rate. On the other hand, in the configuration of the second conventional example described above, although an arbitrary speech rate can be set, there is a problem in that two memories for storing voice signals are required, which causes a price increase.

The present invention has been made in view of the above-mentioned problems of the related art, and when the VTR or the like is reproduced at a high speed, the reproduced voice can be set to an arbitrary speech speed and a single voice can be set. An object of the present invention is to realize a low-priced audio signal time base conversion device that can be configured with an audio memory.

[0018]

According to the invention of claim 1 of the present application, an A / D conversion means for converting an input analog audio signal into a digital signal by a first clock signal, and an output of the A / D conversion means. Memory signal having a first memory area for holding preceding data in the time-series digital audio signal and a second memory area for holding subsequent data, and a first clock signal. Then, the output signal of the A / D conversion means is set to the first and second memory
Write address generating means for generating an address signal for writing to the memory area and a second clock signal for generating an address signal for reading the audio data stored in the first memory area of the memory means. First read address generating means, and second read address generating means for inputting the second clock signal and generating an address signal for reading the audio data stored in the second memory area of the memory means. First data holding means for inputting the second clock signal and holding the first audio data read by the first read address generating means,
With respect to the second data holding means for inputting the second clock signal and holding the second audio data read by the second read address generating means, and the first and second data holding means, A holding signal generating means for giving a data holding signal and a data output signal, and a cross for inputting the output signal of the first data holding means and the output signal of the second data holding means, controlling their amplitude values and adding them. The fader means, the selector means for inputting the output signal of the first data holding means and the output signal of the crossfade means, and switching based on the reproduction speed setting signal, and the output signal of the selector means for the second
A D / A conversion means for converting the clock signal into an analog signal and outputting a voice signal, and when an analog voice signal reproduced at N times the normal reproduction speed is input,
By making the frequency of the first clock signal N times the frequency of the second clock signal, the audio signal is reproduced at a speech speed M times the normal reproduction speed.

The invention of claim 2 of the present application has a first memory area for inputting a digital audio signal and holding preceding data in a time-series digital audio signal, and a second memory area for holding subsequent data. Memory means, write address generating means for inputting the first clock signal and generating address signals for writing in the first and second memory areas of the memory, and second clock signal for inputting the memory means First read address generating means for generating an address signal for reading the audio data stored in the first memory area, and a second clock signal are inputted and stored in the second memory area of the memory means. Second read address generating means for generating an address signal for reading the audio data, and a second read address generating means for inputting the second clock signal. A first data holding means for holding the first voice data read by the second clock signal and a second clock signal, and holds the second voice data read by the second read address generating means. Second data holding means, holding signal generating means for giving a data holding signal and a data output signal to the first and second data holding means, an output signal of the first data holding means and a second data holding means. A crossfade means for inputting the output signal of the data holding means and controlling and adding the amplitude values of the data holding means, and an output signal of the first data holding means and an output signal of the crossfade means are inputted and used as a reproduction speed setting signal. Selector circuit for switching based on the frequency of the first clock signal when the digital audio signal reproduced at N times the normal reproduction speed is input. By N times the number, is characterized in that for reproducing audio signal by M times the speech speed of the normal playback speed.

In the invention of claim 3 of the present application, the crossfade means controls the amplitude level of the output signal of the first data holding means so as to gradually decrease from the maximum to the minimum, and the second data holding means. It is characterized in that the amplitude level of the output signal of the means is added to the signal controlled so as to gradually increase from the minimum to the maximum.

In the invention of claim 4 of the present application, the selector means sets the signal time length output from the crossfade means to A
And the signal time length output from the first data holding means is B, when the reproduction speed M times the normal reproduction speed is set, input so as to satisfy M = (2A + B) / (A + B) It is characterized by switching signals.

In the invention of claim 5 of the present application, the read address difference which is the output signal difference between the first read address generating means and the second read address generating means is D, and the cycle of the read clock signal is T. , D and T are set within 125 milliseconds, and the time difference between the output signals of the first data holding means and the second data holding means is within 125 milliseconds.

[0023]

According to the invention of claim 1 of the present application having such characteristics, the analog audio signal reproduced at N times speed is digitally converted by the first clock signal, and the digital audio signal is converted into the first clock signal. Write to memory synchronously. Next, two audio data are read from the two memory areas of the memory in synchronism with the second clock signal having a cycle N times as long as the first clock signal from the memory, and the two audio data are stored in the first and second data holding means. Hold. These audio data are input to the crossfade means, and the amplitude values of the audio data of each are controlled and added. The audio data of the first data holding means and the audio data of the crossfade means are input to the selector means and switched based on the reproduction speed setting signal. When this voice data is converted into an analog signal with the second clock signal, a voice signal having an arbitrary talk speed and a normal reproduction pitch is reproduced.

Further, in the invention of claim 2 of the present application, the N-speed reproduced digital audio signal is written in the memory in synchronization with the first clock signal. Next, two audio data are read from the two memory areas of the memory in synchronism with the second clock signal having a cycle N times as long as the first clock signal from the memory, and the two audio data are stored in the first and second data holding means. Hold. These audio data are input to the crossfade means, and the amplitude values of the audio data of each are controlled and added. The audio data of the first data holding means and the audio data of the crossfade means are input to the selector means and switched based on the reproduction speed setting signal. In this way, a digital audio signal having an arbitrary speech speed and a normal reproduction pitch is reproduced.

Further, in the invention of claim 3 of the present application, the crossfade means controls the amplitude level of the audio data of the first data holding means so as to gradually decrease from the maximum to the minimum (fade out). Further, the amplitude level of the audio data of the second data holding means is controlled (fade in) so as to gradually increase from the minimum to the maximum. Next, audio data obtained by adding the fade-out signal and the fade-in signal is output and given to the selector means. In this way, an audio signal having a large number of repetitive signal components can be processed without losing the audio content even if it is time-compressed by the crossfade means.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An audio signal time base converter according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the audio signal time base converter according to this embodiment. In the figure, the audio signal S1 specially reproduced from the VTR or the like is given to the A / D converter 20 via the input terminal 11. The first clock signal S11 is input terminal 1
A / D converter 20 and write address counter 2 via
Given to 1. Further, the second clock signal S12 is given to the D / A converter 23, the first read address counter 24, the second read address counter 25, and the latch signal generation circuit 26 via the input terminal 14.

The memory 22 writes the audio signal S21 digitally converted by the A / D converter 20 into a write address counter 21.
Is a voice memory to be written by the write address signal S22 output by the. The memory 22 is a first memory area for holding preceding data in a time-series digital audio signal,
And a second memory area for holding subsequent data. The voice data S24 held in the memory 22 is simultaneously or inputted by the first address signal S31 output by the first read address counter 24 and the second address signal S32 output by the second read address counter 25. It is read in the (storing) order. The read address counter 24 reads the audio data stored in the first memory area (first address) of the memory 22, and the read address counter 25 is stored in the second memory area (second address) of the memory 22. To read the audio data
Both are driven by the clock signal S12.

When the audio data S24 stored in the first memory area of the memory 22 is read, it is output to the first latch 27 which is the first data holding means, and the audio data stored in the second address. When S24 is read,
It is output to the second latch 28 which is the second data holding means. The latches 27 and 28 are circuits that temporarily hold input data. The latch signal generating circuit 26, which is a holding signal generating means, gives the latch 27 a first control signal S37 and the latch 28 a second control signal S38. These control signals mean a data holding signal for holding the input signal in each latch and a data output signal for outputting the audio data held in the latch.

The crossfade circuit 29 is a circuit which inputs the audio data S35 held in the latch 27 and the audio data S33 held in the latch 28 and crossfades the signals. The crossfade means performing fade-out on one input signal and performing fade-in on the other input signal. The selector circuit 30 outputs either the audio data S34 output from the crossfade circuit 29 or the audio data S35 output from the latch 27 to the control signal S1 of the input terminal 15.
In the circuit that selects based on 5, the selected audio data S3
6 is input to the D / A converter 23 and converted into an analog audio signal S2. The audio signal output from the output terminal 12 is applied to an audio output circuit (not shown).

The operation of the audio signal time base converter according to the present embodiment thus constructed will be described with reference to FIGS. The audio signal time base conversion device of the present embodiment is
Although it is possible to support any reproduction speed including the normal reproduction speed, the case of double speed reproduction will be described here as an example.
FIG. 2 is an operation explanatory diagram in the case of reproducing an audio signal at a speech speed of 1.5 times when the recording medium is reproduced at double speed, and FIG. 3 shows an audio signal when the recording medium is reproduced at double speed. 1.
It is operation | movement explanatory drawing at the time of reproducing at the voice speed of 33 times and 1.17 times, respectively.

The double speed reproduction audio signal S1 input to the input terminal 11 is converted by the A / D converter 20 into a digital audio signal S21 synchronized with the clock signal S11. The voice signal S21 is input to the memory 22 and sequentially written in the memory 22 in accordance with the address signal S22 of the write address counter 21. The audio signal S21 written in the memory 22 is the first and second read address counters 24,
In accordance with the 25 address signals S31 and S32, the memory 2
2 is read.

The pitch of the audio signal S1 reproduced at double speed is
It is twice the pitch of the normally reproduced signal. In order to make the pitch of the audio signal S2 to be output to the output terminal 12 the same as in normal reproduction, the cycle of the clock signal S12 is set to be twice the cycle of the clock signal S11. Generally, when the input audio signal S1 is an N times speed reproduction signal of normal reproduction,
The cycle of the clock signal S12 may be set to N times the cycle of the clock signal S11.

Read address counter 2 from memory 22
4 and 25 are time-divisionally read with different read address values. One of the audio data S24 read by the address signal S31 of the read address counter 24 is the first
Is input to the latch 27 and latched (held) by the control signal S37 of the latch signal generation circuit 26. The audio data held here is the audio data S by the next control signal S37.
Is output as 35. The voice data S35 is the same as the signal read by the address signal S31 of the read address counter 24.

The other of the audio data S24 read by the address signal S32 of the read address counter 25 is input to the second latch 28 and latched by the control signal S38 of the latch signal generating circuit 26. The audio data held here is audio data S3 by the next control signal S38.
It is output as 3. The voice data S33 is the same as the voice data read by the address signal S32 of the read address counter 25.

Audio data S35 held in the latch 27
Is applied to the first input terminal of the selector circuit 30 and is also applied to the first input terminal of the crossfade circuit 29. The audio data S33 held in the latch 28 is given to the second input terminal of the crossfade circuit 29. The crossfade circuit 29 crossfades the two audio data S35 and S33. Next, the selector circuit 30 selects either the voice data S35 or the cross-faded voice data S34 based on the control signal S15 for setting the voice speed input to the input terminal 15. Here, FIG.
The functions of the crossfade circuit 29 and the selector circuit 30 will be described in detail with reference to FIG.

In FIG. 2, assuming that the time unit for the audio signal at the time of normal reproduction is t, (a) shows the audio signal S1 reproduced at double speed as time as s, t, u, v, w ... It is the figure which divided | segmented for every unit t / 2 and was shown typically. As described above, the frequency of the audio signal S1 is 2 as compared with the normal reproduction.
Times the cycle, and the cycle is 1/2. 2B, as in the conventional example shown in FIG. 4, the audio signal S1 reproduced at double speed is written in the memory 22 by the clock signal S11 and read by the clock signal S12 having a cycle twice that of the clock signal S11. This is audio data in the case. The output signal is S,
The frequency and cycle of the output audio signal such as T, U, V, W ... Are the same as in the case of normal reproduction, and the time unit is double that in double speed reproduction, that is, t. Further, the speech speed is the same as that in the normal reproduction, and the speech speed cannot be changed as it is.

Now, consider the case where the speech speed is set to 1.5 times, for example. Here, without changing the time unit t,
As shown in (b), the time unit 3t required for reproducing S, T, and U may be set to the time unit 2t as shown in FIG. 2 (c). Therefore, time compression of time t is required. In this embodiment, the audio signal S and the audio signal T following the audio signal S
It is realized by cross-fading the two signals and the two signals are present in the first time unit t. FIG. 2 (c) shows a voice signal S2 converted when the speech speed is set to 1.5 times in the device shown in FIG. 1, in S / T, U, V / W, X and time unit t. Output is separated. The S / T shown in FIG.
V / W means cross-fading two signals, and for example, times t1 to t shown in FIGS. 2 (c) and 2 (d).
2, the S / T fades out the audio signal S,
This means that the audio signal T is faded in and added. U and X mean that the audio signals U and X are output as they are in this order.

FIG. 2D shows the operation of the selector circuit 30 according to the control signal S15. At times t1 to t2,
Since the selector circuit 30 selects the cross-faded signal S / T, it selects the audio data S34 at the times t2 to t.
3 outputs the audio data as it is, so latch 2
The audio data S35 to be output by 7 is selected. As described above, the content described with reference to FIG. 2 is a new concept of the present embodiment in which only the speech speed can be arbitrarily set and the pitch is the same as that in the normal reproduction.

The minimum value in the range that can be set as the time unit t shown in FIG. 2 is determined by the minimum frequency of the audio data S35 processed and output by the memory 22. Further, the maximum value is determined by an audible experiment such as a feeling of strangeness caused by a time delay of two signals at the time of crossfading. Here, the time unit t is set to around 32 milliseconds. Here, the time unit t is the address signals S31 and S3.
If the address difference from 2 is D and the cycle of the clock signal S12 is T, then it is equal to D × T.

FIG. 3 is a schematic diagram of the voice data S36 at the voice speeds of 1.33 times and 1.17 times. FIG. 3 (a) is shown in FIG.
It is the same as the signal shown in (b). FIG. 3B shows the audio signal S2 output from the output terminal 12 when the speech speed is set to 1.33 times, and S / T, U, V, W /
It is output by being separated by X, Y, Z and time unit t. In this case, the time unit required to reproduce the audio signal sequence (S, T, U, V) in FIG. 3A is 4t, while that in FIG.
The time unit required for reproducing the audio signal sequence (S / T, U, V) is 3t. Therefore, the speech rate is 4/3 = 1.33.
Double.

FIG. 3 (c) shows the case where the speech speed is 1.17 times. In this case, the audio signal string (S,
(T, U, V, W, X, Y) time unit required for playback is 7
However, the audio signal sequence (S /
T, U, V, W, X, Y) time unit required for playback is 6
Thus, the speech speed is 7/6 = 1.17 times.

As described above, the M-times arbitrary speech speed, which is different from the normal reproduction speed, is applied to the voice data S of the crossfade circuit 29.
When the time length of 34 is A and the time length of the audio data S35 output from the latch 27 is B, M = (2A + B) /
It can be realized by satisfying (A + B).

The first and second read address counters 24,
If the address difference output by 25 is D, the audio data S
A time delay occurs between 31 and the audio data S33. When the time delay value is Dt, the address difference D and the cycle T of the read clock S12 input to the input terminal 14
, The following expression (4) is established.

[Equation 4] When this time delay value Dt is large, an echo is perceptually perceived, resulting in a decrease in clarity and an increase in discomfort. For the detection limit of the time delay value Dt, for example, in 290 Seikiro Namba, "Hearing Handbook," published by Nakanishiya Publishing in November 1984, "Extend the interval to 50 msec to 100 msec or more in order to obtain a feeling of two clearly separated sounds." Need to be done ". In addition, a report by Thomas et al. “Temporal order in the perception of vowels
Journal Acoustic Society of America 48,1010-1013 (1
970) ”, an audio material experiment reported that it was 125 milliseconds. In any case, in this embodiment, the time delay value Dt is set to 125 based on the contents of these reports.
Set within milliseconds.

The case of the normal double speed reproduction as the input audio signal S1 has been described above.
In the case of normal reproduction, the speech speed can be changed in the same manner. In that case, the clock signal S11 input to the input terminal 13 and the clock signal S input to the input terminal 14
The 12 frequencies may be set to be the same.

In addition to controlling the speech speed from the outside, it is possible to gradually change the speech speed automatically according to the contents of the input signal. For example, by compressing only the silent section included in the signal, the speech speed can be made slower than that of the input signal, and such an audio signal time base conversion device can be realized at low cost. Furthermore, this audio signal time base conversion device is a custom L in which the memory 22 which is an existing LSI and the other circuits are integrated into an LSI.
It can also be configured by SI.

In the audio signal time base converter of this embodiment,
It is assumed that an analog voice signal is input and an analog voice signal in which the voice speed and pitch are converted is output. However, when used in a digital AV device, a digital audio signal is input to the memory 22 and the digital audio signal of the selector circuit 30 is directly used.

[0047]

As described above, if the audio signal time base conversion device of the present invention is applied to a VTR or other AV equipment, for example, in the case of double speed reproduction in special reproduction, an image is reproduced at double speed. The audio signal will be reproduced at an arbitrary speech rate set by the user of the AV device from 1 to 2 times and at a normal pitch. Therefore, by halving the reproduction time, it is possible to effectively utilize the time, and it is possible to reproduce the content of the voice at a desired speech speed slower than double speed. Therefore, in the special reproduction of the audio information recording / reproducing apparatus such as the VTR, the excellent curing that the audio contents can be easily understood can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a voice signal time base conversion device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an audio signal time base conversion device according to the present embodiment,
It is operation | movement explanatory drawing when a speech speed is set to 1.5 times.

FIG. 3 is a diagram showing an audio signal time base conversion device according to the present embodiment.
It is operation | movement explanatory drawing when the speech speed is set to 1.33 times and 1.17 times.

FIG. 4 is a block diagram showing a configuration of an audio signal time base conversion device in a first conventional example.

FIG. 5 is an explanatory diagram of a speech speed conversion operation in a conventional audio signal time base conversion device.

FIG. 6 is a configuration diagram of an audio signal time base converter according to a second conventional example.

FIG. 7 is a block diagram showing a configuration of a pitch conversion device used in a conventional audio signal time base conversion device.

[Explanation of symbols]

 11, 13, 14, 15 Input terminal 12 Output terminal 20 A / D converter 21 Write address counter 22 Memory 23 D / A converter 24 First read address counter 25 Second read address counter 26 Latch signal generation circuit 27 First Latch 28 Second Latch 29 Crossfade Circuit 30 Selector Circuit

Claims (5)

[Claims] 1. A time-series digital signal receiving an A / D conversion unit for converting an input analog audio signal into a digital signal with a first clock signal and a digital audio signal output from the A / D conversion unit. Memory means having a first memory area for holding preceding data in the audio signal, and a second memory area for holding subsequent data; and an output signal of the A / D converting means for inputting the first clock signal. Write address generating means for generating an address signal for writing into the first and second memory areas of the memory, and a second clock signal, which is stored in the first memory area of the memory means. First read address generating means for generating an address signal for reading the audio data, and the second memory of the memory means for inputting the second clock signal. Second read address generating means for generating an address signal for reading the audio data stored in the area, and a first read address generating means for inputting the second clock signal and read by the first read address generating means. First data holding means for holding the second audio data, and second data holding means for inputting the second clock signal and holding the second audio data read by the second read address generating means. Means, holding signal generating means for giving a data holding signal and a data output signal to the first and second data holding means, an output signal of the first data holding means and the second data holding means Means for inputting the output signal of the means, controlling and adding the amplitude values to each other, a crossfade means, an output signal of the first data holding means and an output signal of the crossfade means Type and outputs an audio signal into an analog signal and selector means for switching based on the reproduction speed setting signal, by the second clock signal the output signal of the selector means D /
A conversion means is provided, and when an analog audio signal reproduced at N times the normal reproduction speed is input, the frequency of the first clock signal is made N times the frequency of the second clock signal. By
An audio signal time base conversion device, which reproduces an audio signal at a speech speed M times as high as a normal reproduction speed. 2. A memory means having a first memory area for inputting a digital audio signal and holding preceding data in a time-series digital audio signal, and a second memory area for holding subsequent data, and a first memory area. Write address generating means for inputting a clock signal and generating an address signal for writing to the first and second memory areas of the memory; and a second clock signal for inputting a first clock signal of the memory means. A first read address generating means for generating an address signal for reading the audio data stored in the memory area; and an audio signal stored in the second memory area of the memory means by inputting the second clock signal. Second read address generating means for generating an address signal for reading data, and the first read address by inputting the second clock signal. A first data holding means for holding the first voice data read by the generating means, and a second voice read by the second read address generating means by inputting the second clock signal. A second data holding means for holding data; a holding signal generating means for giving a data holding signal and a data output signal to the first and second data holding means; and a first data holding means A crossfade means for inputting an output signal and an output signal of the second data holding means, controlling and adding amplitude values of each other, and an output signal of the first data holding means and an output signal of the crossfade means. And selector means for switching based on the reproduction speed setting signal, and when the digital audio signal reproduced at N times the normal reproduction speed is inputted, the first clock signal is input. The frequency of click signal, by the N times the frequency of the second clock signal,
An audio signal time base conversion device, which reproduces an audio signal at a speech speed M times as high as a normal reproduction speed. 3. The crossfading means controls the amplitude level of the output signal of the first data holding means so as to gradually decrease from the maximum to the minimum, and the output signal of the second data holding means. 3. The audio signal time base converter according to claim 1 or 2, wherein the signal is controlled so that the amplitude level thereof is gradually increased from the minimum to the maximum. 4. The selector means sets the signal time length output from the crossfade means to A
When the signal time length output from the first data holding means is B, M = (2A + B) / (A + B) is satisfied when a reproduction speed M times the normal reproduction speed is set. The audio signal time base conversion device according to any one of claims 1 to 3, wherein the input signal is switched. 5. When the read address difference which is the output signal difference between the first read address generating means and the second read address generating means is D and the cycle of the read clock signal is T, D and T 5. The product is set within 125 milliseconds and the time difference between the output signals of the first data holding means and the second data holding means is within 125 milliseconds. The audio signal time base conversion device according to item 1.