JP3003502B2 - Gain adjustment device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain adjusting device for an AC signal, and more particularly to a gain adjusting device for an AC signal including analog-to-digital conversion means for performing an analog-to-digital conversion operation.

[0002]

2. Description of the Related Art To reproduce and listen to recorded information on a recording medium on which an acoustic signal is recorded in a shorter time than the time required for recording, for example, from a magnetic tape recorder or a video tape recorder. It is well known that the reproduction is conventionally performed. For example, when reproducing the recording information from the recording medium on which the video signal and the information signal such as the audio signal accompanying the video signal are recorded, the recording medium having a speed higher than the recording medium speed during the recording operation By viewing a reproduced image obtained by performing a high-speed reproducing operation, that is, a high-speed reproducing operation, the image content recorded on the recording medium can be read within a shorter time than the time required for recording the image. For example, it has been conventionally performed in a helical scan type VTR or the like to enable confirmation. When the high-speed reproduction of the image content is performed as described above, since the sound signal accompanying the reproduced video signal is pitch-converted to a higher frequency,
Usually, it is impossible to grasp the information content.

By the way, if the information content of an audio signal reproduced when a recording medium on which an information signal such as an audio signal accompanying an image signal is recorded at a high speed can be known clearly can be used for various purposes. The present applicant has also proposed a video / audio reproduction apparatus having a signal processing means for performing pitch conversion for returning a high-speed reproduced audio signal to an original audio signal. (Japanese Patent Application No. 328 filed on November 13, 1992
644, "Acoustic signal processing device", and Japanese Patent Application No. 356217, filed on December 21, 1992, "Acoustic signal processing device".

As described above, when a high-speed reproduction of image content is performed, a pitch conversion of an audio signal accompanying a video signal is performed so that an audio information content can be grasped. Writes an audio signal reproduced at a high speed to the memory during the T / N period (an audio signal whose time axis is compressed to 1 / N ... a time axis compressed audio signal) in synchronization with a write clock, A configuration in which the time-axis compressed sound signal written in the memory can be reproduced as a reproduction sound signal in a time-axis-expanded state using a read clock signal having a period N times as long as the write clock. FIG. 6 illustrates a time axis compression operation and an expansion operation of an audio signal in the above-described apparatus.

FIG. 6A shows an audio signal reproduced from a recording medium when the recording / reproducing apparatus is performing an N-times reproducing operation, that is, an original audio signal to be recorded. This shows that only the time-axis compressed sound signal having the time length of T / N in the time-axis compressed sound signal in a state where the time axis is compressed to 1 / N is intermittently written into the memory at every time T. FIG. 6 (b) shows a time axis compressed acoustic signal having a time length of T / N stored in the memory described above as an acoustic signal having a time length of T obtained by extending the time axis by N times. This shows a state where data is being read from the memory.

As apparent from FIGS. 6 (a) and 6 (b), in the apparatus having the above-described structure, the time axis compression reproduced from the recording medium of the recording / reproducing apparatus performing the reproducing operation at N times speed is performed. For the audio signal, a time-axis compressed audio signal having a time length of T / N in the time-axis compressed audio signal divided on the time axis for each time length T is obtained as a reproduced audio signal having the same pitch as the original audio signal. Therefore, the above-mentioned time length T is appropriately selected, and T /
If valid acoustic information exists for a period of time N,
The reproduced sound signal having the same pitch as the above-mentioned original sound signal is N N even though it is a discrete signal portion in the original sound signal.
It is considered to be useful for confirming the information content of the audio signal reproduced at the double speed.

By the way, during a high-speed reproduction operation in which the reproducing element reproduces a recording signal from the recording medium at a relative speed larger than the relative speed between the recording element and the recording medium during the recording operation, the acoustic signal reproduced from the recording medium is Since the signal level is higher than that of the reproduced sound signal during the normal reproduction operation, the pitch of the sound signal accompanying the video signal is converted when the high-speed reproduction is performed, so that the contents of the sound information can be grasped. In such a device having the above-described configuration, that is, a device that converts an audio signal into a digital signal, writes the digital signal into a memory, and then expands and reads out the time axis from the memory, a high-speed playback operation is performed. When the signal level of the audio signal becomes higher than the input signal level specified for the analog-to-digital converter, data is clipped and distortion occurs. To. It is well known that when the input signal to the analog-to-digital converter becomes very small, the effect of the quantization error appears greatly, which causes a problem of sound quality deterioration.

Therefore, as shown in FIG. 5, attempts have been made to solve the above-mentioned problem by automatically controlling an input analog signal supplied to an analog-to-digital converter. In FIG. 5, 35 is an automatic gain adjustment amplifier, 36 is an analog-to-digital converter, 37
Is a memory, 38 is a digital-to-analog converter, and 39 is a control circuit. The automatic gain adjustment amplifier 35 in FIG. 5 includes a variable gain amplifier 40, a detection circuit 42, and a low-pass filter 41, for example, as shown in a configuration example in FIG. An AC signal output from a variable gain amplifier 40 used as a component of the automatic gain adjustment amplifier 35 is rectified by a detection circuit 42, and then smoothed by a low-pass filter 41 to be converted to DC. By being supplied to the variable gain amplifier 40 as a gain control signal, the output signal from the variable gain amplifier 40 is output from the automatic gain adjustment amplifier 35 as a signal held at a substantially constant signal level. Is output.

The automatic gain adjustment amplifier 35 converts the reproduced signal whose signal level has increased during high-speed reproduction into a digital signal in a state where the signal level has been reduced to an appropriate signal level after a predetermined time delay. Converter 36
The reproduction signal having a small signal level is supplied to the analog-to-digital converter 36 as a reproduction signal whose signal level has been raised to an appropriate signal level after a predetermined time delay. Since it operates, the automatic gain adjusting amplifier 35 converts the analog to digital converter 36.
Is supplied with an input signal of an appropriate signal level which is not higher than the input signal level defined for the analog-to-digital converter 36 and which does not cause a problem of the quantization error. The digital signal output from the analog-to-digital converter 36 is written to the memory 37, then read out by extending the time axis from the memory 37, converted to an analog signal by the digital-to-analog converter 38, and output. . The control circuit 39 controls the operations of the above-described analog-to-digital converter 36, memory 37, digital-to-analog converter 38, and the like.

[0010]

In the conventional apparatus described with reference to FIGS. 5 and 7, etc., the conventional apparatus is provided in a loop of a control loop in an automatic gain adjustment amplifier 35 used as a component thereof. Since a time delay occurs in the control due to the time constant of the low-pass filter 41, the automatic gain adjustment amplifier 35 does not perform gain adjustment when a large-amplitude signal is input instantaneously. However, there is a problem in that the input signal to the analog-to-digital converter 36 exceeds the input signal level specified for the analog-to-digital converter, and the data is clipped to cause distortion in the output signal. In order to solve the above-mentioned problem, the time constant of the low-pass filter 41 provided in the control loop of the automatic gain control amplifier 35 is reduced. Expediently, the gain adjustment by the automatic gain control amplifier 35 will be happened that would take place, that only hesitation sound not heard not play becomes a problem by the intonation of the speech.

One of the means for solving the problem of the automatic gain adjustment technique used in the conventional apparatus described above with reference to FIGS. 5 and 7 is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 4-369697. It has been proposed to perform automatic gain adjustment after separating an input signal into signal components of a number of frequency bands and performing frequency analysis, such as automatic gain adjustment means applied to a voice recognition device. . However, when the above-mentioned proposed automatic gain adjustment means is adopted, since it is necessary to use an extra component for frequency analysis which is not required for the automatic gain adjustment, the apparatus is required. Has the drawback that it becomes large and expensive, and since the level is set only once, it cannot cope with a change in the level of the input signal after the level is set. A solution that does not have the above problems has been sought.

[0012]

According to the present invention, there is provided an analog-to-digital conversion means for performing an analog-to-digital conversion operation on an AC signal, a gain control means provided prior to the analog-to-digital conversion means, If the output value from the analog-to-digital converter is close to the maximum conversion value,
When it is preset value near because the set value or converted minimum value, the gain setting is performed in the gain control means gain is the so only decreases a predetermined amount of the gain control means described above Means, and the above-described gain at a rate of once every predetermined time.
Means for setting the gain in the gain control means so that the gain of the control means is increased by a predetermined amount, and a gain adjustment apparatus comprising: The recorded information of the acoustic signal
A time T / N shorter than the time T required for recording (however,
(N is a natural number of 2 or more). The analog-to-digital conversion means for analog-to-digital conversion of the time-axis compressed sound signal obtained by reproduction with the digital signal of the time-axis compressed sound signal output from the analog-to-digital conversion means. A memory, means for reading out digital data of the time-axis compressed sound signal stored in the memory as digital data of a reproduced sound signal in a state where the time axis is expanded by N times, and a means preceding the analog-digital conversion means. The gain control means provided and the output value from the analog-to-digital conversion means are set to a predetermined value or a conversion value near the maximum conversion value.
When it reaches a preset value near the minimum value ,
Means for as gain settings in the above-mentioned gain control means so that the gain of the gain control means decreases by a predetermined amount is performed, when the writing of the digital data of a predetermined amount to the memory has been completed, or memory with every other when starting the writing of digital data to, so that the gain setting is performed in the gain control means gain is the to be larger by a predetermined amount to a predetermined gain control means described above And a gain adjustment device comprising:

[0013]

The analog-to-digital conversion is performed by a minimum value detector and a maximum value detector supplied with an output value of an analog-to-digital converter supplied with an AC signal whose signal level is adjusted by a programmable gain control amplifier. the output values from the vessel is, when it became converted maximum or converted minimum value is detected, by generating gain control data, such as gain of the programmable gain control amplifier is reduced by a predetermined amount Supply it to a programmable gain control amplifier. In addition, the above-described programmable gain control is performed at a rate of once every predetermined time in an AC signal targeted for gain adjustment.
By generating gain control data, such as gain from the amplifier is increased by a predetermined amount, and supplies it to the programmable gain control amplifier, when a predetermined amount of writing digital data in the memory is completed, or memory 1 when writing digital data to
The gain control data is generated at such a rate that the gain from the programmable gain control amplifier is increased by a predetermined amount, and is supplied to the programmable gain control amplifier.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a gain adjusting apparatus according to the present invention. FIG. 1 is a block diagram of a signal processing device including the gain adjusting device of the present invention, FIG. 2 is a block diagram showing a configuration example of a programmable gain control amplifier, and FIG. 3 is a write clock signal and a read address clock. FIG. 4 is a diagram illustrating a waveform example illustrating a timing relationship with a signal, and FIG. 4 is a diagram illustrating a relationship between a writing period and a reading period in a sequential signal block section. In the signal processing device including the gain adjustment device of the present invention shown in FIG. 1, 1 is an input terminal of an AC signal to be subjected to signal processing, 2 is an output terminal of the signal processing device, Reference numeral 3 denotes a programmable gain control amplifier (a specific configuration example is shown in FIG. 2). 4 is an analog-to-digital converter, 5 is a memory, and 6 is a digital-to-analog converter.

The above-mentioned programmable gain control amplifier 3
The analog-to-digital converter changes the gain in accordance with the gain control data DT2 supplied thereto and adjusts the signal level of the AC signal supplied via the input terminal 1 which is to be processed. Give to 4. As the programmable gain control amplifier 3 described above, for example, one having a configuration as illustrated in FIG. 2 can be used. In the programmable gain control amplifier 3 shown in FIG. 2, 3a is an input terminal of an AC signal to be subjected to gain control, 3b is an output terminal of an AC signal subjected to gain control, and 3c is an input of gain control data DT2. Terminals, 21 and 22
Is a buffer amplifier, 23 to 30 are switches, 31 to 34
Is an inverter, and R, 2R, etc. are resistors.

The programmable gain control amplifier 3 illustrated in FIG. 2 has a 6-bit gain control data DT applied to an input terminal 3c of the gain control data DT2.
When 2 (Qo, Q1... Q5) is supplied, the gain is variable in 64 steps. The AC signal supplied to the input terminal 3a of the programmable gain control amplifier 3 shown in FIG. 2 and subject to gain control is passed through the buffer amplifier 21 to the movable contacts of the switches 23, 25. Has been given.
The movable contacts of the switches 23, 25... 27, 29 are connected to gain control data DT supplied as opening / closing control signals.
The gain control data DT2 is turned on and off depending on whether the signal of the specific digit 2 is in a high level state or a low level state.
Each switch 2 supplied as an open / close control signal via
The movable contacts 4, 26... 28, 30 are turned on and off depending on whether the signal of a specific digit in the gain control data DT2 is in a low level state or a high level state.

The switches 23, 25... 27, 29
, And the fixed contacts of the switches 24, 26... 28, 30 are respectively located at predetermined positions in a ladder network composed of a resistor having a resistance value of R and a resistor having a resistance value of 2R. Connected, and the switches 24,
The movable contacts 26, 28, 30 are grounded. Therefore, the programmable gain control amplifier 3 illustrated in FIG. 2 supplies the supplied 6-bit gain control data DT2 to the input terminal 3c of the gain control data DT2.
Since (Qo, Q1... Q5) the signal attenuation can be switched in 64 ways, the gain can be varied in 64 steps.

An output signal from the programmable gain control amplifier 3 is converted into a digital signal having a predetermined number of bits by an analog-to-digital converter 4, and is converted into data DT1 (8-bit data in the following description). Is written to the memory 5. The AD conversion operation in the analog-to-digital converter 4 is performed by receiving an AD conversion clock signal ADCK generated by the control unit 7 provided with a control signal generator. The memory 5 is supplied with a clock signal CS and a read / write switching signal RW of the memory generated by the control unit 7, thereby writing data DT1 to the memory 5 and reading data from the memory 5. Is performed.

The mode of the writing operation to the memory 5 is changed corresponding to the reproduction mode of the recording / reproducing apparatus. For example, when the recording / reproducing apparatus is performing the N-times speed reproducing operation, and the reproduction from the recording medium is performed. If the sound signal to be recorded is a time axis compressed sound signal in which the time axis is compressed to 1 / N of the original sound signal to be recorded, the sound signal has been written to the memory 5. The sound signal compressed on the time axis by 1 / N is read out as the original sound signal after being expanded on the time axis by N times, and the data read from the memory 5 is stored in the control unit 7. Supplies a D / A conversion clock signal DACK, and the digital / analog converter 6 performing a D / A conversion operation converts the signal into an audio signal in the form of an analog signal and sends it to the output terminal 2.

When the recording / reproducing apparatus is performing the N-times speed reproducing operation, the control unit 7 supplies the D / A conversion clock signal DACK to the digital / analog converter 6 from the analog / digital converter. 4 is used, the conversion clock signal having a cycle N times as long as the A / D conversion clock signal ADCK supplied to the memory 4 is used. The cycle of the clock signal CS is set to N times the cycle of the clock signal CS at the time of the write operation.

Now, in the signal processing device shown in FIG. 1 which is provided with the gain adjusting device of the present invention, the AC signal supplied to the input terminal 1 and subjected to the signal processing is the same as that described above. The signal level is adjusted by the programmable gain control amplifier 3 and supplied to the analog-to-digital converter 4 as described above.
6 is controlled by the gain control data DT2 output from. Then, the aforementioned gain control data DT2
Is the data DT1 output from the analog-to-digital converter 4 as described later (assuming that the data is 8-bit data as described above, and in the following description, the description is made by using the hexadecimal notation). ) Is generated by the up / down counter 16, and the specific contents are as follows.

That is, the data DT1 output from the analog-to-digital converter 4 is supplied to the minimum value detector 8 and the maximum value detector 9 in addition to being supplied to the memory 5 as described above. ing. When the minimum value detector 8 detects the minimum value 0h of the 8-bit data DT1 output from the analog-to-digital converter 4, it outputs the high-level output E (see FIG. 1) to the OR circuit 11. give. When the maximum value detector 9 detects the maximum value FFh of the 8-bit data DT1 output from the analog-to-digital converter 4, it outputs the high-level output F (see FIG. 1) to an OR circuit. Give to 11.

The minimum value 0h of the 8-bit data DT1 output from the analog-digital converter 4 is the minimum value of the analog-digital converter 4, and the minimum value 0h of the 8-bit data DT1 output from the analog-digital converter 4. The maximum value FFh is the maximum value of the analog-to-digital converter 4, and the values of 0h and FFh are limit values of conversion in the 8-bit analog-to-digital converter 4, and are output from the analog-to-digital converter 4. In a state where the 8-bit data DT1 indicates the values of 0h and FFh, it indicates that it is necessary to lower the signal level of the analog signal input to the digital converter 4. Thus, the output G of the OR circuit 11 that outputs the logical sum of the output E from the minimum value detector 8 and the output F from the maximum value detector 9 as described above is supplied to the analog-to-digital converter 4. This is used as a signal for instructing a decrease in the signal level of the analog signal.

The control unit 7 uses the clock signal CLK supplied from the oscillator 10 to generate the various signals described above and also generates the following various signals. That is, the control unit 7 generates the write clock signal WCK and sends it to the write address counter 17.
And to the read address counter 18,
In addition to supplying the read clock signal RCK, a signal CK1 consisting of one pulse each time the analog-to-digital converter 4 performs one analog-to-digital conversion operation (a signal CK1 generated every one sampling period) CK1)
The detection circuit 19 detects that the write address WAD has reached the maximum value, and the signal WMX output from the detection circuit 19
Is supplied to the control unit 7 to generate the signal CK2.

The up / down counter 16 for generating the gain control data DT2 is a presettable up / down counter (in the following description, it is assumed to be a presettable 6-bit up / down counter).
With respect to the up-count clock input terminal U,
The up / down counter 16 when the clock signal is supplied performs a counting operation as an up counter, and the up / down counter 16 when the clock signal is supplied to the down count clock input terminal D.
Performs a counting operation as a down counter. A mode change pulse MCP is supplied to the preset terminal PR of the up / down counter 16 when the operation mode is changed, whereby the up / down counter 16 is preset to a value of 3Fh when the operation mode is changed. . Therefore, when the reproduction speed is changed, the gain adjustment is automatically performed, so that the fluctuation of the reproduction signal level caused by the change in the reproduction speed is prevented.

A signal L output from the AND circuit 13 is supplied as a clock signal to a down count clock input terminal D of the up / down counter 16, and an up count clock input terminal U of the up / down counter 16 is supplied to the up count clock input terminal U. The signal K output from the circuit 12
Are supplied as clock signals. The above-mentioned signals L and K are generated as follows. First,
The input side of the AND circuit 13 is connected to the OR circuit 1 as described above.
The output signal G of 1 is supplied, and the signal CK1 generated by the control unit 7 (the signal CK1 generated one by one every sampling period) and the output signal H from the zero detector 14 are output. Since the signal is supplied, the signal L output from the AND circuit 13, that is, the down-counting clock signal supplied to the down-count clock input terminal D of the up-down counter 16 is the same as the output signal G from the OR circuit 11 described above. , And the output signal H from the zero detector 14 are both at a high level, and occur at the timing when the signal CK1 is at a high level.

On the input side of the AND circuit 12, a signal CK2 (a signal W output from the detection circuit 19 when the write address WAD reaches a maximum value) generated by the control unit 7 is provided.
Since the signal CK2 generated by the control unit 7 when MX is supplied to the control unit 7 and the output signal I from the 3F detector 15 are supplied, the signal K output from the AND circuit 12 That is, the down-counting clock signal supplied to the up-count clock input terminal U of the up-down counter 16 is such that the signal CK2 is at the high level when the output signal I from the 3F detector 15 is at the high level. Occurs at the timing of.

The up-down counter 1
6 is supplied to the zero detector 14 for preventing the counted value from becoming 0h → 3Fh when the up / down counter 16 is operating as a down counter. When the count value output from the up / down counter 16 becomes 0h, the zero detector 14 supplies the AND circuit 13 with an output H which is in a low level state. The 3F detector 15 to which the output of the up / down counter 16 is supplied prevents the count value from being 3Fh → 0h when the up / down counter 16 is operating as an up counter. When the count value output from the up / down counter 16 becomes 3Fh, the 3F detector 15 supplies the AND circuit 12 with the output I which is in a low level state.

The write address counter 17 which counts the write clock signal WCK generated by the control unit 7 to generate the write address signal WAD, and counts the read clock signal RCK generated by the control unit 7 to read the read address signal RAD From the read address counter 18 that generates the write address signal W
The AD and the read address signal RAD are supplied to the selection circuit 20. The selection circuit 20 uses the write / read switching signal RW generated by the control unit 7 as a selection control signal, selects a write address signal WAD and a read address signal RAD, and sends the address signal MAD to the memory 5.
Supply as The read operation and the write operation of the memory 5 are switched by the write / read switching signal RW supplied from the control unit 7, and the read operation and the write operation are executed at the timing of the clock signal CS. Also,
In the detection circuit 19 to which the write address signal WAD generated by the write address counter 17 is applied,
When the write address signal WAD has the maximum value, the signal WMX is generated as described above and supplied to the control unit 7.

The input signal supplied to the input terminal 1 in FIG. 1 is an output signal from a recording / reproducing device (for example, a tape recorder or a video tape recorder). When the reproduction operation is performed, the sound signal reproduced from the recording medium is 1 / N of the original sound signal to be recorded.
The time axis compressed sound signal in the state where the time axis is compressed is applied to the time axis compressed sound signal. Is performed to generate a reproduced sound signal having the same pitch as the original sound signal, for example, as illustrated in FIG. 4, the time axis divided into predetermined time lengths T on the time axis. For each compressed sound signal (block signal for each signal block section),
A write operation and a read operation are performed.

That is, in each time-axis compressed acoustic signal (block signal for each signal block section) divided into predetermined time lengths T on the time axis, the T / T
A time axis compressed acoustic signal having a time length of N seconds (T / N writing period length) is written into the memory 5 and a read operation from the memory 5 for T seconds is performed. A write clock signal WCK and a read clock signal RCK used for a write operation to the memory 5 and a read operation from the memory 5 performed on the time axis as illustrated in FIG.
Is, as exemplified in FIGS. 3A and 3B,
The period of the write clock signal WCK is 1 / N of the period of the read clock signal RCK, and the write clock signal and the read signal clock are generated at timings different from each other. FIG. 4 shows an example of a memory read / write operation when N = 5 (5 × speed reproduction), and FIG. 3 shows a case where N = 5 (5 × speed reproduction). 2 illustrates an example of a generation timing relationship between a write clock signal and a read signal clock.

Each of the signal block sections 1, 2,... In FIG.
The arrows shown by dashed lines in the figure indicate the state where information is written to the memory, and the arrows shown by the thick solid lines in the figure indicate the state where information is read from the memory. I have. In the illustrated example, the memory address (both the write address and the read address) is 0 to 7FFFFh
(However, h is a symbol representing a hexadecimal number, and in this example, a case where the address signal of the memory is 15 bits is taken as an example). Is the signal WMX from the detection circuit 19.
Are output in correspondence with the write address of 7FFFFh, and the detection circuit 19 outputs the signal WMX from each of the signal block sections 1, 2,... Will be sent. The signal block sections 1 and 2 described above
Needless to say, the time length of ... can be arbitrarily determined.

In FIG. 4, in the signal block section 1, the write address value is 7 from the point where the write address value is 0.
The write operation for the write information of the write information number S1 is continuously performed up to the point of FFFh, and the read address value is 7FFF from the point where the read address value is 0.
The read operation for the read information of the read information number S1 is continuously performed up to the point h for N times the time length of the write operation. For the signal block section 2, the write address value starts from the point where the write address value is 0. Value is 7FF
The write operation for the write information of write information number S2 is performed continuously up to the point of Fh, and the read information number continues from the point where the read address value is 0 to the point where the read address value is 7FFFh. The write operation and the read operation are performed for the sequential signal block sections such that the read operation for the read information of S2 is performed for N times the time length of the write operation. Address counter 17
At the time when the write address signal WAD corresponding to the write address of 7FFFh is generated, the detection circuit 19 outputs the signal WMX.

As described above, the gain adjusting device of the present invention is provided with the data DT 1 output from the analog-to-digital converter 4 to which the AC signal whose signal level is adjusted by the programmable gain control amplifier 3 is supplied. It has been detected by the minimum value detector 8 and the maximum value detector 9 that the data value output from the analog-to-digital converter 4 has become the conversion maximum value or the conversion minimum value in the analog-to-digital converter 4. At this time, the up / down counter 16 generates the gain control data DT2 such that the gain of the programmable gain control amplifier 3 is reduced by a predetermined amount, and supplies it to the programmable gain control amplifier 3. 1 every predetermined time in the AC signal targeted for gain adjustment
Ratio times Ide, wherein the by the gain control data DT2 as the gain of the programmable gain control amplifier 3 is increased by a predetermined amount is generated in the up-down counter 16, to supply it to the programmable gain control amplifier 3 Therefore, an AC signal having an appropriate signal level is always input to the analog-to-digital converter 4.

[0035]

As is apparent from the above description, the gain adjusting apparatus according to the present invention comprises an analog-to-digital converter to which an AC signal whose signal level is adjusted by a programmable gain control amplifier is supplied. When the output value from the analog-to-digital converter is detected by the minimum value detector and the maximum value detector to which the output value is supplied to be the conversion maximum value or the conversion minimum value, the programmable gain is set. Generating gain control data such that the gain of the control amplifier is reduced by a predetermined amount, supplying it to the programmable gain control amplifier, and controlling a predetermined amount of the AC signal that is subject to gain adjustment. and at a rate of once every predetermined time, increased by the amount the gain of said the programmable gain control amplifier is predetermined Una by generating gain control data, and supplies it to the programmable gain control amplifier,
Since the signal level of the AC signal supplied to the analog-to-digital converter is controlled, the gain adjustment for the excessive input signal is performed at high speed in the gain adjustment device of the present invention, and the signal level is adjusted. The distortion that occurs when an excessively large signal is input to the analog-to-digital converter is also suppressed in a short time, and when a recording medium on which an information signal such as an audio signal accompanying the video signal is recorded is reproduced at high speed. When the gain adjustment device of the present invention is applied to an audio signal processing device for obtaining an audio signal capable of clearly knowing the information content of the audio signal to be reproduced in the present invention, the gain adjustment device of the present invention When the playback mode is changed, the maximum signal level is set when the playback mode is changed. If the adjustment of the signal level to that signal level is completed in a short time and the signal level gradually decreases thereafter, In order to operate so as to perform adjustment with a low signal level difference, a signal level in a sequential signal section set for each predetermined time length in an AC signal to be subjected to gain adjustment. Because it does not follow the fluctuation of
An easy-to-hear sound signal can be obtained, and readjustment is performed when the playback mode is changed, so that the operation of adjusting the optimum signal level for various playback speeds can be performed quickly, and further, the gain can be improved. Even if the gain is adjusted by making the ascending adjustment be performed after the writing of the predetermined amount of digital data to the memory is completed or when the writing of the predetermined amount of digital data to the memory is started, Since the state of the change in the signal level during the adjusting operation is not written into the memory , an uncomfortable sound signal is not output. Further, since all of the control units in the gain adjustment device of the present invention can be implemented as logic circuits, they can be easily constituted by an integrated circuit, can be manufactured at low cost, and the threshold value can be set arbitrarily easily. The adjustment is not required, the operation is stable and the operation is stable. In addition, the adjustment of the optimum signal level is repeated in response to the fluctuation of the signal level during the operation. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example configuration of a signal processing device including a gain adjustment device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a programmable gain control amplifier.

FIG. 3 is a waveform diagram illustrating a relationship between a write / write clock signal and a read clock signal.

FIG. 4 is a diagram illustrating a relationship between a writing period and a reading period.

FIG. 5 is a block diagram illustrating a configuration example of a conventional acoustic signal processing device.

FIG. 6 is a diagram showing an example of an audio signal that can clearly know the information content of an audio signal reproduced when a recording medium on which an information signal such as an audio signal accompanying an image signal is recorded is reproduced at a high speed. Is a diagram for explaining the configuration principle of an acoustic signal processing device for the present invention.

FIG. 7 is a block diagram of a conventional general automatic gain control circuit.

[Explanation of symbols]

3: Programmable gain control amplifier, 4: Analog-to-digital converter, 5: Memory, 6: Digital-to-analog converter, 7: Control unit, 8: Minimum value detector, 9: Maximum value detector, 10: Oscillator, 11 ... OR circuit, 12, 13 AND circuit, 14 zero detector, 15 3F detector, 16 ...
Up / down counter, 21, 22, ... buffer amplifier,
23 to 30 switches, 31 to 34 inverters, 35
... automatic gain adjustment amplifier, 36 ... analog-digital converter, 37 ... memory, 38 ... digital-analog converter, 3
9: control circuit, 40: variable gain amplifier, 41: low-pass filter, 42: detection circuit,

Claims (2)

(57) [Claims] An analog-to-digital conversion means for performing an analog-to-digital conversion operation on an AC signal, a gain control means provided before the analog-to-digital conversion means, and an output value from the analog-to-digital conversion means Is a preset value near the maximum conversion value or the minimum conversion value.
When a preset value near the value is reached, the gain
Means for setting the gain in the gain control means so that the gain of the control means is reduced by a predetermined amount; and 1 for every predetermined time.
At a rate of times, the gain adjustment device gain is and means to ensure that the gain setting is performed in the above-mentioned gain control unit to be larger by a predetermined amount to a predetermined gain control means described above. 2. The method according to claim 1, wherein the recording information of the acoustic signal recorded on the recording medium is recorded for a time T / N shorter than a time T required for recording.
(Where N is a natural number of 2 or more) analog-to-digital conversion means for analog-to-digital conversion of a time-axis compressed sound signal obtained by reproduction, and digital data of the time-axis compressed sound signal output from the analog-to-digital conversion means And a means for reading the digital data of the time-axis compressed sound signal stored in the memory as digital data of a reproduced sound signal in a state where the time axis is expanded by N times, and the analog-to-digital conversion means The gain control means provided in advance and the output value from the analog-to-digital conversion means have a preset value near the maximum conversion value.
Or means for setting the gain in the gain control means so that the gain of the gain control means is reduced by a predetermined amount when the value becomes a preset value near the conversion minimum value. When the writing of a predetermined amount of digital data to the memory is completed or when the writing of digital data to the memory is started, the gain of the gain control means is increased by a predetermined amount at a rate of one time. Means for setting the gain in the gain control means described above.