JP3246329B2 - Sound signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention reproduces information recorded on a recording medium on which an acoustic signal is recorded in a shorter time than the time required for recording, thereby performing signal processing on the acoustic signal having a higher pitch. The present invention relates to an audio signal processing apparatus for obtaining a reproduced signal that can be heard well.

[0002]

2. Description of the Related Art To reproduce recorded information on a recording medium on which an information signal is recorded in a time shorter than the time required for recording, for example, when reproducing from a video tape recorder (VTR) or a tape recorder, etc. It is well known that it has been widely used in the past. That is, a so-called helical scan type video in which a magnetic tape wound around a part of a peripheral surface of a drum is run at a predetermined running speed and a recording and reproducing operation is performed using a rotating magnetic head.・ Tape recorder (VTR) [or video
In the cassette recorder (VCR)], the rotation locus of the rotating magnetic head is 90 degrees with respect to the reference edge of the running magnetic tape.
In a helical scan type VTR configured to perform recording / reproduction in a state of showing an inclination angle of less than or equal to one degree, a video signal for one field period is recorded on one recording trace. When the playback speed is higher than the running speed of the magnetic tape at the time, the so-called high-speed playback operation is performed, and even if a high-speed playback operation is performed, a reproduced image that can confirm the image content recorded on the magnetic tape is viewed. In order to make it possible to confirm the image content recorded on the magnetic tape within a short time compared to the time required for recording the image, a high-speed reproduction operation has been performed. .

Incidentally, the pattern of the recording trace formed on the magnetic tape according to the rotation locus of the rotary magnetic head of the helical scan type VTR as described above depends on the diameter of the drum, the number of rotations of the rotary magnetic head, the number of rotations of the rotary magnetic head. Since it is determined by various conditions such as the rotation direction, the running speed of the magnetic tape, the running direction of the magnetic tape, the track angle, the head track width, and the recording area width of the magnetic tape, the operation mode of the VTR (normal playback mode, high-speed playback mode, etc.) By changing the various trick play operation modes), for example,
When the conditions such as the running direction and the running speed of the magnetic tape change, the pattern of the rotation locus of the rotary magnetic head drawn on the magnetic tape by the rotary magnetic head changes.

Therefore, during normal recording / reproducing (normal recording / reproducing), the rotating locus of the rotating magnetic head drawn on the magnetic tape by the rotating magnetic head and the rotating magnetic head drawn on the magnetic tape by the rotating magnetic head during trick play. The rotation locus of the head intersects. Therefore, the signal level of the frequency modulated wave signal of the reproduced signal reproduced at the time of trick play changes greatly every time the rotating magnetic head crosses the recording trace, and the frequency modulated wave of the reproduced signal in one vertical scanning period is changed. Looking at the signal envelope, large undulations occur during one vertical scanning period. Therefore, as a reproduced image at the time of trick play, only a reproduced image of poor quality having noise bars in the image can be obtained. .

In order to solve the above-mentioned problem, it is only necessary to make the rotation locus of the rotary magnetic head coincide with the recording trace of the magnetic tape T. Conventionally, as an actuator in an open loop control circuit or a closed loop control circuit, A rotating magnetic head is attached to the electro-mechanical transducer used, and the rotating magnetic head is displaced by the electro-mechanical transducer so that the rotating magnetic head can be traced to the recording mark of the magnetic tape. As disclosed in JP-A-63-34126 and JP-A-61-158633, the rotating drum on which the rotating magnetic head is mounted and the lower drum are integrally inclined so that the rotating head is A magnetic tape for a drum can be traced, for example, as disclosed in JP-B-61-22376. By changing the height of guides for limiting the height in the width direction of the magnetic tape provided on the entrance side and the side where the magnetic tape is released from the drum, the rotating head can track the recording trace of the magnetic tape T. Various solutions have been proposed, such as
An upper drum having a sliding surface with respect to a magnetic tape wound around a part of the peripheral surface of the upper and lower drums, a rotating magnetic head, and an extended surface of the sliding surface of the magnetic tape on the upper drum; In addition to the magnetic tape sliding contact surface, the lower drum, which is provided coaxially with the upper drum, and the rotation track surface of the rotating magnetic head are aligned with the recording marks formed on the magnetic tape. First tilt drive means for tilting the central axes of the upper and lower drums and the rotary magnetic head by a predetermined angle; and the lower and upper drums being separate from the upper and lower drums. A guide member for regulating the position of the reference edge of the magnetic tape, the guide member for regulating the position of the reference edge of the magnetic tape, which is disposed close to the outer peripheral surface of the small diameter portion formed at the lower part of the magnetic tape, and the position of the magnetic tape Replace the regulating guide member with a magnetic Flop magnetic recording and reproducing apparatus comprising a second inclined drive means for tilting to match the reference edge position of has been proposed.

[0006] By applying the various solutions as described above, a VTR capable of obtaining a good reproduced image without bar noise even in the high-speed reproduction mode has been provided. In addition, if it is realized that the quick preview by the high-speed reproduction image of good image quality without noise is realized,
It seems that something is not enough that no sound is attached to the reproduced image, and in addition to the sound signal accompanying the video signal, the sound signal is reproduced when the magnetic tape is played at high speed. However, since it is possible to expand various uses if the information content can be clearly understood, it has been demanded that an audio signal can be reproduced even during high-speed reproduction.

On the other hand, in a tape recorder, by increasing the running speed of the magnetic tape during reproduction as compared with the running speed of the magnetic tape during recording, a long recording content can be compared with the time required during recording. Listening within a short period of time has conventionally been performed. However, since the acoustic signal reproduced from the magnetic tape when the high-speed reproduction is performed as described above is in a state where the pitch is converted to a higher frequency, the running speed of the magnetic tape is simply recorded. Digital data obtained by sampling and quantizing a time-axis compressed audio signal that has been played back from a magnetic tape at high speed with a short sampling cycle can not be grasped satisfactorily just by making it faster than usual. Is stored in a memory, and the digital data of the time-axis compressed sound signal is read out at a period longer than the sampling period to reduce the frequency and perform pitch conversion to obtain an original sound signal that can be heard well. A tape recorder and a VTR equipped with an audio signal processing device have been proposed.

In the above-described audio signal processing apparatus, for each block of the time-axis compressed audio signal divided for each predetermined time, only a short cycle of the time-axis compressed audio signal within a time shorter than the predetermined time is used. The digital data obtained by sampling and quantization is stored in a memory, and the digital data of the time-axis compressed acoustic signal is read at a period longer than the sampling period over the predetermined time, and the pitch conversion is performed. Since the sampling and quantization are performed, the sampling and quantization operation for the time axis compressed sound signal of a certain block is completed, and the time axis from the start of the sampling and quantization for the time axis compressed sound signal of the next one block is started. The compressed sound signal is discarded. The digital data obtained by sampling and quantizing the time-axis compressed audio signal of each block is usually stored as a series of signals from a minimum address to a maximum address of a memory. In some cases, the digital data stored in the memory is 1
In the time axis compressed sound signal of the block, for example, if a silent period is included, the series of signals becomes short,
There is a problem that the reproduced signal is hard to hear. Therefore, during a silent period, a device which makes it easier to hear the contents of a series of signals without writing to a memory (for example, Japanese Patent Laid-Open No.
No. 5656) has been proposed.

[0009]

According to the above-mentioned conventional apparatus, a silent sound portion is not written in a memory, and a continuous sound content is extended to obtain a reproduced sound signal which is easy to hear. That was achieved, but it was difficult to achieve both the problem of how to set the criterion for the detection of silence, and the good balance between good silence removal and audio processing suitable for image scenes. There was a problem. Next, the above problem will be specifically described. As described above, in order to delete a silent part, it is necessary to detect a silent part. As the silent portion detecting device, a device that does not make a determination based on the level of an acoustic signal with respect to a certain threshold value is used. However, the sound signal to be recorded usually contains not only the voice of conversation but also surrounding sounds and the like, and further, the signal contains noise. Therefore, the threshold value to be set in the silent portion detecting device is not set so that the silent state is determined based on the state of the signal level 0, but is set to a minute value close to 0. An acoustic signal smaller than the value is determined to be silent.

FIG. 5 is a block diagram of a conventional apparatus. FIG.
Is an input terminal of a time-axis compressed sound signal reproduced at high speed, and the time-axis compressed sound signal supplied to the input terminal 1 is supplied to an analog-to-digital converter (ADC) 3 via a low-pass filter (LPF) 2. Is entered. The time-axis compressed sound signal is sampled and quantized at high speed at a predetermined sampling period in the analog-to-digital converter 3, and digital data based on the time-axis compressed sound signal is written into the memory 10. Digital data read from the memory 10 at a predetermined period longer than the above-described sampling period is converted into a digital-to-analog converter (DA).
C) After being converted into an analog signal by 4, it is sent to an output terminal 6 via a low-pass filter (LPF) 5.

Reference numeral 9 denotes a control circuit (CTL). The control circuit 9 includes a memory write address counter (WCNT).
A signal CK serving as a reference signal for the thirteen clock signals WCK
1. A signal CK2 serving as a reference signal of a clock signal RCK of a memory read counter (RCNT) 16, a write / read selection signal RW and a memory control signal CS, a clock signal ADCK of the analog-digital converter 3, and a clock signal of the digital-analog converter 4. A signal DACK and other necessary signals are generated. In FIG. 5, WAD indicates a write address value, and RAD indicates a read address value. Reference numeral 17 denotes a comparator (CMP).
Outputs a high-level signal EQ [see (d) of FIG. 6] when the write address value WAD matches the read address value RAD.

Reference numeral 11 denotes an address selection circuit (SEL),
This address selection circuit 11 receives a write / read selection signal RW
Is at a high level, the read address value RA
D, and supplies it to the memory 10 as the address signal ADR.
Is at a low level, the write address value W
AD is selected and supplied to the memory 10 as an address signal ADR. Reference numeral 7 denotes a silence detection unit. When the input signal falls below a predetermined level, the silence detection unit 7
Silence state signal SI in a high level state (indicating a silence state)
[See FIG. 6 (b)] is output. The silence state signal S
When I becomes a low level state (indicating a sound state), the write enable signal WEN output from the inverter 8 is output.
[See (c) of FIG. 6] becomes a high level state, whereby the reference signal CK of the memory write address counter 13 is set.
1 is used as the clock signal WCK of the memory write address counter 13 via the AND circuit 12, and is input to the memory write address counter 13 to advance the address. When the silent state signal SI is at a high level, the clock signal WCK of the memory write address counter 13 is not generated.

The silent state signal SI is at a high level (silent state) and the write address value WAD
And the read address value RAD coincide with each other, and the output signal EQ of the comparator 17 is at a high level, the read enable signal REN output from the NAND circuit (NAND) 14 [see (e) of FIG. ] Is at a low level, the output signal RCK of the AND circuit 15 is at a low level, and the counting operation of the memory read counter 16 is stopped. The read enable signal REN output from the NAND circuit 14 is at a high level under other conditions. When the read enable signal REN is at the high level, the reference signal CK2 is used as the clock signal RCK of the memory read counter 16 via the AND circuit 15, whereby the memory read counter 16 advances the address.

FIG. 6 shows a change state of a memory address in a case where the conventional apparatus shown in FIG. 5 performs signal processing of a time-base compressed acoustic signal reproduced from a recording medium at twice the recording speed during recording. [(A) of FIG. 6] and a silence state signal SI of an output signal of each component of the device [FIG.
(B)], the write enable signal WEN [(c) in FIG. 6] output from the inverter 8, the output signal EQ [(d) in FIG. 6] of the comparator 17, and the read enable output from the NAND circuit 14. 7 is a time chart illustrating a change state of a signal REN [(a) of FIG. 6].

In the example shown in FIG. 6, it is assumed that the device starts a write operation and a read operation at time t1. First, during the period from time t1 to time t4, since the silent state signal SI is a sounded portion indicating a low level state, the write enable signal WEN output from the inverter 8 is at a high level state. Therefore, since the clock signal WCK of the memory write address counter is being supplied to the memory write address counter 13 via the AND circuit 12, the memory write address counter is supplied over the period from the time t1 to the time t4. The counter 13 continues the counting operation. The manner of change of the write address value WAD by the counting operation of the memory write address counter 13 over the above-mentioned sound portion period from the time t1 to the time t4 is shown in FIG. …… Is indicated by a straight line drawn by a broken line connecting points リ, ヌ, →, ヲ. In FIG. 6A, a solid line indicated by a drawing symbol RAD indicates a read address value R.
The state of the change of AD is shown, and MIN at the left end of the figure shows the start address value of the memory, and MAX shows the end address value of the memory.

Next, during a period from time t4 to time t5, a silent section in which the silent state signal SI indicates a high level state, and during this silent section, the write enable signal WEN output from the inverter 8 is supplied. It is in a low level state. Since the supply of the clock signal WCK of the memory write address counter from the AND circuit 12 to the memory write address counter 13 is stopped during the silent period, the silence period between the time t4 and the time t5 is reduced. The memory write address counter 13 does not perform a counting operation. Thus, the write address value WAD during the silent period from the time t1 to the time t4 holds the same value as shown by the straight line connecting the points ヲ → W in FIG. ing.

Next, at time t5, the silence state signal SI becomes a sounded portion indicating a low level state, so the write enable signal WE output from the inverter 8 at time t5.
N goes into a high level state, and the memory write address counter 13 restarts the counting operation. Then, the counting operation of the memory write address counter 13 is continued over a sound part period from time t6 when the silent state signal SI changes from a low level to a silent part indicated by a high level. Thus, the write address value WAD obtained by the counting operation of the memory write address counter 13 over the sound period from the time t5 to the time t6.
6 is indicated by a straight line drawn by a broken line connecting points W, F, Y, and T in FIG. 6A.

During the period from time t6 to time t8, a silent portion in which the silent state signal SI indicates a high level state. During the silent portion, the memory write address counter 13 performs the counting operation as described above. Since the writing is not performed, the write address value WAD during the silent period from the time t6 to the time t8 has the same value as shown by the straight line connecting the point to the point in FIG. Hold. In the illustrated operation example, the output signal EQ of the comparator 17 is, as shown in FIG. 6D, time t1, time t2, time t3, and time t7.
To a high level from time t8. At time t1, time t2, and time t3, since the silence state signal SI is at a low level, the read enable signal REN output from the NAND circuit 14 remains at a high level.

The memory write address counter 13 stops counting during the silent period from time t6 to time t8. However, since the silent period from time t6 to time t8 is long, the write address The value WAD and the read address value RAD have the same address value, and the output signal EQ of the comparator 17 is at a high level. Then, at time t7, the read enable signal REN output from the NAND circuit 14 goes to a low level, and at time t7, the AND condition of the AND circuit 15 is not satisfied. The clock signal RCK of the memory read counter supplied to the counter 16 is no longer supplied to the memory read counter 16, and the counting operation of the memory read counter 16 starts at time t7.
To stop.

At time t8, the silence state signal SI becomes a sounded portion indicating a low level state, the write enable signal WEN output from the inverter 8 becomes a high level state, and the clock signal of the memory write address counter is output. WCK is supplied to the memory write address counter 13 via the AND circuit 12, and the memory write address counter 13 starts counting operation from the time t8. The manner in which the write address value WAD is changed by the counting operation of the memory write address counter 13 during the sound period from the time t8 is shown in FIG.
(a) It is shown by a straight line indicated by a broken line connecting points d → d → d → d → d → d.

In the conventional apparatus described above with reference to FIGS. 5 and 6, when the input signal falls below a predetermined level, the high-level silence state signal S is output.
If the period in which the silent state is determined by the silent state determination unit 7 that outputs I is long, such as the period from time t6 to time t8 shown in FIG. 6, at time t7 in the above-mentioned period. Write address value WAD and read address value R
When AD has the same address value, the output signal EQ of the comparator 17 is at a high level, the read enable signal REN output from the NAND circuit 14 is at a low level, and at time t7, the AND circuit 15 Since the condition is no longer satisfied, the clock signal RCK of the memory read counter is no longer supplied to the memory read counter 16 at time t7, and the counting operation of the memory read counter 16 stops at time t7, so that the period shown from time t7 to time t8 In the memory 10, the operation of repeatedly writing digital data based on the time-base compressed acoustic signal sequentially output from the analog-to-digital converter 3 to the same address and reading the written digital data is performed. .

By the way, the silence judgment by the silence judging section 7 is performed by setting a certain threshold value to determine whether the input signal has fallen below a predetermined level. Even when the silent state is determined by the unit 7, since there are many cases where an acoustic signal such as an ambient sound equal to or less than the threshold is included, the silent state is determined by the silent state determining unit 7. During the period from the time t7 to the time t8 during the period from the time t6 to the time t8,
As a result of the reading operation, an acoustic signal having a very small signal level in a state where the time axis is not extended is output. Then, the sound reproduced in the above state becomes noise of unknown meaning.

The above problem is that the writing operation and the reading operation of the memory 10 are stopped during the period from the time t7 to the time t8 during the period from the time t6 to the time t8 when the silent state is judged by the silence judging section 7. However, if such a means is applied, the period from the time t7 to the time t8 becomes a completely non-signal state, giving a great sense of discomfort to the viewer. In particular, in a VTR equipped with a function that enables a quick view, a situation may occur in which a completely silent state suddenly occurs despite that there should be ambient sounds while a reproduced image is displayed. Gives a very unnatural feeling. In order to prevent such an unnatural state from occurring, for example, it is conceivable to set the threshold value in the silence determination unit 7 to a very low level. It becomes difficult to remove the unnecessary sound, and the problem is that the original purpose, that is, the efficient silence removal operation cannot be performed.

In the conventional device, if there are many silent parts,
The silence elimination operation results in a longer continuous processing time, but if there is less silence, the read address is immediately overtaken by the write address, and further writing is performed on information that has already been written and has not been read. There is a problem that the reproduced sound is difficult to hear because it is performed. Therefore, an acoustic signal processing device free from the above-mentioned various problems has been demanded.

[0025]

SUMMARY OF THE INVENTION According to the present invention, a time axis compressed audio signal reproduced from a recording medium at a speed higher than the recording speed at the time of recording is sampled and quantized at a predetermined sampling period to obtain an audio signal. Analog-to-digital conversion means for obtaining digital data of the above, a memory for writing and storing the digital data of the above-mentioned acoustic signal at the above-mentioned predetermined sampling period, and a read-out period longer than the above-mentioned sampling period, Means for reading the digital data of the acoustic signal read from the memory, and digital-to-analog converting means for converting the digital data of the acoustic signal read from the memory from digital to analog and outputting it as an audio signal in the form of an analog signal In the signal processing device, the reading of the digital data of the acoustic signal from the memory described above,
Means for performing a cyclic operation from the first address to the last address of the memory, and means for detecting a low-tone state below a predetermined signal level including a silent state Means for stopping the progress of the write address in the case where the sound level becomes lower than a predetermined signal level including a silence state, and when the progress of the write address is stopped, First write address progress resuming means for resuming the progress of the write address when a loud state of a predetermined signal level or higher occurs, and a write address of the write address in the loud state of the predetermined signal level or higher. During the process, if the write address value matches the read address value or the write address value becomes a value near the read address value, the write address And means for stopping the progression, in a state in which the progress of the writing address is stopped, or the write address value matches the read address value, if the write address value is a value in the vicinity of the read address value,
A second write address progress resuming means for resuming the progress of the write address; and a low tone state below a predetermined signal level including a silence state, wherein the write address value is stopped in a state where the progress of the write address is stopped. After the read address value has been matched or the write address value has become a value near the read address value and the progress of the write address has been resumed, a loud state exceeding the above-mentioned predetermined signal level has occurred. Means for causing a write address and a read address to match or to be close to each other when is detected.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific contents of an audio signal processing device according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a block diagram showing an embodiment of an audio signal processing apparatus according to the present invention. In the sound signal processing apparatus of the present invention shown in FIG. 1, reference numeral 1 denotes an input terminal of a time-axis compressed sound signal reproduced at high speed. The time-axis compressed sound signal supplied to the input terminal 1 is a low-pass filter (LPF) 2 Is input to an analog-to-digital converter (ADC) 3 via the. The time-axis compressed sound signal is converted by the analog-to-digital converter 3 into
High-speed sampling and quantization at a predetermined sampling period,
Digital data based on the time axis compressed sound signal is written into the memory 10. Digital data read from the memory 10 at a predetermined period longer than the above-described sampling period is converted into an analog signal by a digital-to-analog converter (DAC) 4 and then converted to a low-pass filter (L).
PF) 5 to an output terminal 6.

Reference numeral 9 denotes a control circuit (CTL), which is a memory write address counter (WCNT).
p) Signal C serving as a reference signal for clock signal WCK of 27
K1, a clock signal RCK of a memory read counter (RCNT) 28, a write / read selection signal RW, a memory control signal CS, and a clock signal A of the analog-to-digital converter 3.
It generates DCK, the clock signal DACK of the digital-to-analog converter 4, and other necessary signals. In FIG. 1, WAD indicates a write address value, and RAD indicates a read address value. The above-mentioned memory write address counter (WCNTp) 27 is a counter with a preset function. This memory write address counter 27, when the preset signal PR given to its preset terminal PRT becomes a high level state, The read address value RAD is loaded as described later.

Reference numeral 11 denotes an address selection circuit (SEL). When the write / read selection signal RW is at a high level, the address selection circuit 11 selects a read address value RAD and uses it as an address signal ADR. When the write / read select signal RW is at a low level, the write address value WAD is selected and supplied to the memory 10 as an address signal ADR. Reference numeral 29 denotes a low-pitched sound detecting section. The low-pitched sound detecting section 29 outputs a low-pitched sound signal SM in a high level state (indicating a low-pitched sound state) when the input signal falls below a predetermined level [FIG. (B) is output.

FIG. 2 is a block diagram showing an example of the configuration of the above-mentioned small sound detector 29, and FIG. 3 is a waveform diagram for explaining the operation of the small sound detector 29 shown in FIG. In the configuration example of the low-pitched sound detecting section shown in FIG. 2, reference numeral 31 denotes a rectifier circuit (RCT), which is supplied to the input terminal 29a of the low-pitched sound detecting section 29 in FIG.
(A) as shown in FIG.
Is rectified by the rectifier circuit 31 to become a signal Sb as shown in FIG. Output signal S of rectifier circuit 31
b is supplied to the voltage comparator 33. The voltage comparator 3
3 is supplied with a threshold voltage Vc generated by a reference voltage generation circuit (REF) 32.

In the voltage comparator 33, the output signal Sb of the rectifier circuit 31 shown in FIG. 3B output from the rectifier circuit 31 and the reference signal generator 32 generate the output signal Sb. The threshold value Vc is compared with the threshold voltage Vc, a pulse train Pd as shown in FIG. 3C is output, and the pulse train Pd is supplied to the retrigable monostable multivibrator 34 as a trigger signal. The retrigable monostable multivibrator 34 is retriggered when the interval between trigger signals sequentially supplied thereto is within a predetermined time, as shown in FIG. 3D. When the signal level of a sound signal falls below a predetermined level,
When the signal level becomes a low level and the signal level of the sound signal becomes higher than a predetermined level, a pulse Pe which becomes a high level state is generated and supplied to the inverter 35. Therefore, as shown in FIG. 3 (e), when the signal level of the audio signal falls below a predetermined level, the inverter 35 enters a high-level state (indicating a low-pitched sound state). When the signal level of the sound signal becomes equal to or higher than a predetermined level, a low-sound state signal SM which is in a low-level state (indicating a loud sound state) is transmitted to the output terminal 29b.

In FIG. 1, the reference signal CK1 of the memory write address counter becomes the clock WCK of the memory write address counter via the AND circuit 26, and is input to the memory write address counter 27 to advance the address. Further, the memory read counter 28 constantly performs an adding operation cyclically from the first address to the last address of the memory 10 to advance the address. The write address value WAD indicated as the count value of the memory write address counter 27 is based on the state of the change in the signal level of the original sound signal, as exemplified by the broken line WAD in FIG. , The progress of the address is stopped, or the progress of the address is restarted.

The read address value RAD indicated as the count value of the memory read counter 28 is shown in FIG.
As illustrated by a solid line RAD therein, a change such that the read address value RAD changes from the start address to the end address of the memory 10 and then changes again from the start address to the end address of the memory 10 on the time axis. The memory read counter 28 cyclically changes the read address value RAD from the first address to the last address of the memory 10 as described above. Thus, the read address value RA in the above-described variation mode is
D is obtained.

FIG. 4 shows a change in memory address when the above-described acoustic signal processing apparatus performs signal processing on a time-base compressed acoustic signal reproduced from a recording medium at twice the recording speed during recording. State [(a) of FIG. 4]
5 is a time chart illustrating a state of a change in an output signal of each component of the apparatus [(b) to (k) in FIG. 4]. In the example shown in FIG. 4, a period from time t1 to time t4, a period from time t5 to time t6, and a time
The period after 9 is a sound part period (loud part period), and the low sound state signal SM [(b) in FIG. 4] output from the low sound detector 29 indicates a low level state. The period from time t4 to time t5 and the period from time t6 to time t9 are small tone periods, and the small tone state signal SM output from the small tone detection unit 29 [FIG. (B)] shows a high level state.

When the operation start pulse PRS [(g) in FIG. 4] is input to the terminal 30 of the acoustic signal processing device at time t1, the acoustic signal processing device starts the writing operation and the reading operation at time t1. First, when the operation start pulse PRS is input to the preset terminal PRT of the memory write address counter 27 via the OR circuit 22,
The memory write address counter 27 loads the read address value RAD at that time, and writes the write address value WA.
D is made to match the read address value RAD. The operation start pulse PRS is also given to the OR circuit 21. Thus, the operation start pulse PRS is supplied from the OR circuit 21 to the set signal Ps2 [FIG.
(H)] is set to the set terminal S of the D-type flip-flop 24.
To supply. Thereby, the D-type flip-flop 2
4 is set to a set state at time t1, and outputs a high level write enable signal WEN from its Q terminal to supply it to the AND circuit 26. Therefore, the AND circuit 26 uses the reference signal CK1 of the clock signal WCK of the memory write address counter provided from the control circuit 9 as the clock signal WCK of the memory write address counter to generate the memory write address counter 2
7

As a result, the memory write address counter 27 starts counting operation from time t1. FIG. 4 (a)
In the example shown in (1), the write address value WAD and the read address value RAD at time t1 indicate an address value corresponding to the point A. As a result of the counting operation of the memory write address counter 27, the write address value WAD output from the memory write address counter 27 changes from point A to point B to point C in FIG.
→ It changes on a straight line WAD indicated by a broken line connecting each point to the point. On the other hand, the memory read address counter 28 has a read address value RAD that constantly changes between the start address value and the end address a of the memory 10 as described above.
Is output. The state of the change of the read address value RAD is indicated by the solid line indicated by the symbol RAD in FIG.

As described above, since the write address value WAD and the read address value RAD become the same at time t1, the comparator 17 outputs the high-level coincidence pulse EQ [(e in FIG. 4) at time t1. )], And supplies it to the AND circuit 20. In the example of FIG.
Is the voiced part period from time t1 to time t4 as described above.
(Loud part period), the small sound detector 29
Low-pitched sound state signal SM [(b) in FIG. 4]
Indicates a low level state. Accordingly, since the AND circuit 20 at time t1 has its gate closed, the high-level coincidence pulse EQ output from the comparator 17 at time t1 is
It is not output as W. Therefore, at time t1, the set / reset flip-flop 23 is not set. The same applies to the coincidence pulse EQ output from the comparator 17 at times t2 and t3 during the period when the low-pitched sound state signal SM is at the low level (the loud section and the sound section) in FIG. is there.

The counting operation of the memory write address counter 27 proceeds from the time t1 described above. When the write address value WAD matches the read address value RAD at the time t2, the comparator 17 outputs a coincidence pulse EQ.
It is supplied to the clock terminal of the D-type flip-flop 24 in the set state. Then, at time t2, the D-type flip-flop 24 reads the low-level data in the set state supplied from the Q bar terminal to the data terminal D and outputs it from the Q terminal at time t2. The write enable signal WEN output from the Q terminal of the flip-flop 24 changes from a high level to a low level at time t2.

As a result, the AND gate 26 at time t2
Is closed, and the clock signal WC previously supplied from the AND circuit 26 to the memory write address counter 27
K is no longer provided to the memory write address counter 27, and at time t2, the memory write address counter 27
Is stopped. D-type flip-flop 2
The Q bar terminal of No. 4 changes to the high level state at the time t2 and gives it to the data terminal D.

Since the counting operation of the memory read address counter 28 is continuously performed on the time axis without a break as described above, in the example shown in FIG. At time t3 when the read address value RAD matches the write address value WAD due to the change, the comparator 17 outputs a match pulse EQ. Then, the D-type flip-flop 24 outputs a write enable signal WEN at a high level from the Q terminal thereof at time t3. AND circuit 2 to which a high-level write enable signal WEN output from the Q terminal of D-type flip-flop 24 is applied
6 is a reference signal C of the clock signal WCK of the memory write address counter provided from the control circuit 9
K1 is supplied to the memory write address counter 27 as a clock signal WCK of the memory write address counter.

As a result, the memory write address counter 27 restarts the counting operation from time t3. FIG. 4 (a)
In the example shown in FIG. 4, the write address value WAD output from the memory write address counter 27 by the counting operation of the memory write address counter 27 becomes
(A) in FIG. 7A, point D, point D, point D,..., Point D,. On the other hand, the memory read address counter 28 always outputs the read address value RAD that changes cyclically between the start address value and the end address of the memory 10 as described above. Note that the write address value WAD at the time t3 when the memory write address counter 27 restarts the counting operation [the write address value WAD at the point in FIG.
This is the same as the write address value WAD at the time t2 when the memory write address counter 27 stops counting [the write address value WAD at the point in FIG.

Next, at time t4 shown in FIG. 4, the period changes from the loud section period to the low sound section period, and the low sound state signal SM output from the low sound detecting section 29 [(b) of FIG. ] Changes from the low level state to the high level state, at time t
At 4, the monostable multivibrator 19 is triggered, and the monostable multivibrator 19 generates a pulse SMu shown at (c) in FIG. 4 at time t4. When the pulse SMu output from the monostable multivibrator 19 at time t4 is applied to the reset terminal R of the D-type flip-flop 24, the D-type flip-flop 24
Is reset at time t4 and the D-type flip-flop 2
4, the write enable signal W output from the Q terminal
EN [(i) in FIG. 4] changes from the high level state to the low level state at time t4. As a result, the AND circuit 26 closes the gate at time t4 so that the memory write address counter 27
Is no longer supplied to the memory write address counter 27, and the counting operation of the memory write address counter 27 stops at time t4.

Next, in the loud section period starting from time t5 in FIG. 4, the low-pitched sound state signal SM [(a) in FIG. 4] output from the low-pitched sound detecting section 29 at time t5 is in a high level state. When the signal output from the inverter 8 changes from a low-level state to a high-level state when the state changes from a low-level state (loud part and a sound part) to a low-level state (loud part and a sound part), The monostable multivibrator 18 is triggered, and at time t5, the monostable multivibrator 18 generates a pulse SMd shown in FIG. 4D. The pulse SMd output from the monostable multivibrator 18 is supplied to the set terminal S of the D-type flip-flop 24 as a high-level set signal Ps2 via the OR circuit 21.
It is also provided to the reset terminal R of the flip-flop 23.

Thus, the above-mentioned D-type flip-flop 2
4 outputs a high level write enable signal WEN from its Q terminal at time t5 and supplies it to the AND circuit 26. Then, the AND circuit 26 supplies the clock signal WCK of the memory write address counter to the memory write address counter 27, whereby the memory write address counter 27 restarts the counting operation from time t5. The write address value WAD at the time t5 is an address value corresponding to the point 中 in the figure [the same as the address value corresponding to the write address value WAD at the time t4 indicated by the point nu in FIG. It is. By the counting operation of the memory write address counter 27, the write address value WAD output from the memory write address counter 27 is changed as shown in FIG.
It changes on a straight line WAD indicated by a broken line that connects each of the following points: middle point → point → point → point → point.

On the other hand, the pulse SMd output from the monostable multivibrator 18 at the time t5 is supplied to the reset terminal R, and the set / reset flip-flop 23 receives the pulse SMd at the time t5. Because the flip-flop 23 is not set, the pulse SMd supplied to the reset terminal R of the set-reset flip-flop 23 at time t5
Does not change the operation state of the set / reset flip-flop 23, and the Q-bar terminal of the set / reset flip-flop 23 is kept at the high level even at time t5.

Next, at time t6 of the small-tone portion period starting from time t6 in FIG. 4, the small-tone state signal SM output from the small-tone detection unit 29 is in a low-level state (loud portion, voiced portion). Part)
, The monostable multivibrator 19 is triggered at time t6. The monostable multivibrator 19
Generates a pulse SMu shown at (c) in FIG. 4 at time t6 and gives it to the reset terminal R of the D-type flip-flop 24. As a result, the D-type flip-flop 24 is reset at time t6 to change the write enable signal output from the Q terminal thereof from a high level state to a low level state. Accordingly, the supply of the clock signal WCK to the memory write address counter 27 is stopped because the gate of the AND circuit 26 is closed at time t6, and the counting operation of the memory write address counter 27 is stopped at time t6.

Since the address of the memory read address counter 28 has advanced even after the time t6 when the counting operation of the memory write address counter 27 has stopped, the write address value WAD and the read address value RAD Coincide with each other (see the dot Y in FIG. 4A). Accordingly, the high-level coincidence pulse EQ output from the comparator 17 is supplied to the AND circuit 20 at time t7. As described above, from time t6 to time t9
The period up to is a small tone period, and at time t7 during the above period, the small tone state signal SM [(b) in FIG. 4] output from the small tone detection unit 29 changes to a high level state. Therefore, the pulse Pw is output from the AND circuit 20. The output pulse P from the AND circuit 20
w is D as a set signal Ps2 via the OR circuit 21.
The output pulse Pw is also supplied to the set terminal S of the set / reset flip-flop 23 while being supplied to the set terminal S of the type flip-flop 24.

As described above, when the set signal Ps2 [(h) in FIG. 4] from the OR circuit 21 is given at the time t7, the D-type flip-flop 24 outputs the small tone whose time t7 starts from the time t6. Time t7
Outputs the write enable signal WEN from the Q terminal
It is supplied to the AND circuit 26. The aforementioned AND circuit 2
6 is a clock signal W of the memory write address counter.
CK is supplied to the memory write address counter 27 so that the memory write address counter 27
Restarts the counting operation. The write address value WAD at the time t7 is the address value corresponding to the point Y in the figure [the same as the address value corresponding to the write address value WAD at the time t6 indicated by the point f in FIG.
It is.

The output pulse Pw from the AND circuit 20 is supplied to the set terminal S. The set / reset flip-flop 23 is set at time t7.
A low-level signal Pwt [(j) in FIG. 4] is output from the Q bar terminal of the set / reset flip-flop 23 at time t7. By the way, at the time t7 when the write address value WAD and the read address value RAD match, the high-level match pulse EQ output from the comparator 17 is output from the clock of the D-type flip-flop 24. Since the set signal has priority in the operation of the D-type flip-flop 24, the coincidence pulse EQ also supplied to the clock terminal of the D-type flip-flop 24 at time t7 is ignored.

By the counting operation of the memory write address counter 27 restarted at the time t7, the write address value WAD output from the memory write address counter 27 is changed from point Y to point Y in FIG. Tap → dot →
It changes on a straight line WAD indicated by a broken line connecting points S, S, and S. Then, by the progress of the counting operation of the memory write address counter 27 restarted at the time t7, the write address value WAD and the read address value RA are increased.
D coincides with time t8 [refer to the dot in FIG. 4 (a)].
The high-level coincidence pulse EQ output from the comparator 17 is supplied to the AND circuit 20 at time t8. As described above, the period from the time t6 to the time t9 is a small sound part period, and at the time t8 during the period, the small sound state signal SM output from the small sound detector 29 [FIG. (B)] indicates a high level state, so that the AND circuit 20 outputs a pulse Pw.

The output pulse P from the AND circuit 20
w is D as a set signal Ps2 via the OR circuit 21.
While being supplied to the set terminal S of the type flip-flop 24, the output pulse Pw is also supplied to the set terminal S of the set / reset flip-flop 23. Since the set / reset flip-flop 23 has already been set at the time t7 before the time t8, the signal Qwt of the low level is also supplied from the Q bar terminal at the time t8 [( j)] continues to be output.
Further, the write address value WAD and the read address value RA
At the time t8 when D is matched, the high-level match pulse EQ output from the comparator 17 is output.
Is also supplied to the clock terminal of the D-type flip-flop 24 described above, but the operation of the D-type flip-flop 24 is also supplied to the clock terminal of the D-type flip-flop 24 at time t7 because the set signal has priority. The matched pulse EQ is ignored.

Therefore, as described above, the set signal Ps2 [FIG. 4 (h)] from the OR circuit 21 is supplied to the D-type flip-flop 24 at the time t8, and the D-type flip-flop 24 starts at the time t6. Even at time t8, the write enable signal WEN is output from the Q terminal at time t8 and supplied to the AND circuit 26. The AND circuit 26 supplies the clock signal WCK of the memory write address counter to the memory write address counter 27, so that the memory write address counter 27 performs the counting operation restarted at time t7 described above after time t8. continue. Therefore, the change of the write address value WAD after the above-mentioned time t8 changes on a straight line WAD indicated by a broken line connecting the points of point → point → point → point → in FIG. go.

Next, the low-pitched sound state signal SM output from the low-pitched sound detecting section 29 is changed from a high level state (small sound section and silent section) to a low level state (loud section and sound section) at time t9. ), The signal output from the inverter 8 changes from a low level state to a high level state, so that the monostable multivibrator 18 is triggered. The pulse SMd shown in FIG. And
The pulse SMd output from the monostable multivibrator 18 is applied to the set / reset flip-flop 2
3 is applied to the reset terminal R of
The reset flip-flop 23 is reset at time t9, and the pulse P output from its Q-bar terminal is reset.
As shown in FIG. 4 (j), at time t9, the state changes from the low level to the high level, and the monostable multivibrator 25 is triggered.

As a result, the pulse PRx output from the monostable multivibrator 25 at time t9 is supplied to the preset terminal PRT of the memory write address counter 27 as the preset signal PR via the OR circuit 22. Address value WAD of memory write address counter 27 at time t9
Is forcibly changed so as to coincide with the read address value RAD at time t9, as exemplified by the point m → point c in FIG. 4A.

The above-mentioned monostable multivibrator 18
Output from the OR circuit 2 at time t9.
1, the set signal Ps2 is supplied to the set terminal S of the D-type flip-flop 24. Since the D-type flip-flop 24 has been set before time t9 as described above, its Q terminal Output the write enable signal WEN in a high level state. Since the clock signal WCK of the memory write address counter is supplied from the AND circuit 26 to the memory write address counter 27 after time t9, the memory write address counter 27
The write address value WAD forcibly changed to match the read address value RAD in FIG. 9 [(a) of FIG.
From the address value corresponding to the middle dot c). By the counting operation of the memory write address counter 27 after the time t9, the write address value WAD output from the memory write address counter 27 is obtained.
Is the point in FIG. 4 (a) → point c → point no → point o → point →
It changes on a straight line WAD indicated by a dashed line connecting the points of. At the time t9 when the write address value WAD and the read address value RAD are forced to coincide with each other, the high-level coincidence pulse EQ output from the comparator 17 is output from the D-type flip-flop. Although the clock signal is also supplied to the clock terminal 24, since the set signal has priority in the operation of the D-type flip-flop 24, the coincidence pulse EQ also supplied to the clock terminal of the D-type flip-flop 24 at time t7 is ignored. .

Now, in the acoustic signal processing device of the present invention, the time t6 to the time t9 in the example shown in FIG.
If the state of the low-pitched sound (or silence) continues for a long time as in the low-pitched period until the time t7 to the time t9 during the low-pitched section, the memory 10 stores the low-pitched period during the small-pit interval. Since the time axis compressed acoustic signal of a small signal level is written, it is possible to prevent a situation in which the reproduced sound is interrupted even when the small sound period is long. If the content of the reproduced image and the content of the reproduced sound are not shifted when the period changes, the viewer may easily feel uncomfortable.

That is, in the acoustic signal processing apparatus including the acoustic signal processing apparatus of the present invention, in which the time axis compressed audio signal is extended in the time axis to obtain a reproduced audio signal, the signal processing is performed in view of the operation principle. Is performed, a sound signal having the content corresponding to the image content of the reproduced image accompanied by the sound signal subjected to the signal processing described above is obtained. However, the reproduced sound reproduced in the state where the time axis is expanded is gradually delayed from the reproduced image content in the fast forward state.

By the way, even when the audio signal is being reproduced in the above-described state, the viewer who is watching the VTR at a high speed can read the signal when the signal level of the reproduced audio continues in a uniform state. It is usual that you do not notice even if there is a slight time lag between the playback sound being played in a state where the time axis is expanded and the playback image content in the fast forward state, while watching without worrying about After the reproduction sound of the small signal level continues as described above, when the reproduction sound suddenly changes to the high signal level, if there is a difference between the contents of the reproduction sound and the contents of the reproduction image, This will make the viewer feel awkward. For example, the above point will be described as follows, taking as an example a case where a golf scene is reproduced at a high speed on a VTR. When a loud sound is generated by hitting the ball after a quiet period of time, no sound is produced even though the ball hits the golf club on the image,
If a hammering sound is heard late, the viewer will feel uncomfortable.

Therefore, in the acoustic signal processing device of the present invention,
As described above, when the time period is changed to the loud portion period after the period in which the time axis compressed acoustic signal of the small signal level during the low sound portion period is written in the memory 10 during the low sound portion period, the write address value WAD is changed. 4 is forcibly changed so as to match or be close to the read address value RAD at that time, and from time t9 onward in FIG.
The sound is changed on a straight line WAD indicated by a broken line connecting points D, D,..., And when the audio level suddenly changes from a low level to a high level, the reproduced video and the reproduced audio of the VTR are changed. Are matched to reduce the sense of discomfort.

[0059]

As is apparent from the above description, the sound signal processing apparatus of the present invention not only enables the sound to be heard during high-speed reproduction, but also causes a low-pitched sound state including silence. By interrupting the progress of the write address at the time of writing, it is possible to efficiently realize a series of long block times and easy-to-understand processing.Also, when the low sound state period including silence and the high sound state period are mixed, The sound signal in the low sound state period including silence is removed, and the time axis compressed sound signal in the high sound state period is written to the memory to realize efficient sound signal processing.
Even when a low-level sound signal continues, the time-base compressed sound signal of the low-level signal is forcibly written to the memory, and does not cause unnaturalness such as sudden complete silence,
Furthermore, as described above, when the period changes from the period in which the time axis compressed acoustic signal of the small signal level in the small sound period is written to the memory during the small sound period to the large sound period, the write address value is changed. Can be forcibly changed to match or be close to the read address value at that time, so that the start of the video and the sound can be matched by the VTR, and the sense of discomfort can be reduced. It is best because you can match
Even when a large-level sound signal continues, the next writing is prohibited until the information once written is read out, so that a series of sound signals takes a long time to reproduce an easily audible sound signal. Since it can be implemented with a simple circuit, the device can be provided at low cost, and according to the present invention, the above-mentioned problems in the conventional device can be satisfactorily solved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example configuration of an audio signal processing device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a small sound detection unit.

FIG. 3 is a waveform diagram for explaining the operation of the small sound detector.

FIG. 4 is a waveform diagram for explaining the operation of the acoustic signal processing device of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a conventional acoustic signal processing device.

FIG. 6 is a waveform diagram for explaining the operation of a conventional acoustic signal processing device.

[Explanation of symbols]

2, 5 low-pass filter, 3 analog-to-digital converter, 4 digital-analog converter, 7 silent section detector
8 ... inverter, 9 ... control circuit, 10 ... memory, 11 ...
Address selection circuit, 20, 26 ... AND circuit, 13, 2
7: memory write address counter, 16, 28: memory read counter, 17: comparator, 18, 19, 25 ...
Monostable multivibrator, 21, 22, ... OR circuit, 2
3: set / reset flip-flop; 24: D-type flip-flop; 29: small tone detection unit;

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11B 20/00-20/04 G10L 3/02

Claims (1)

(57) [Claims] 1. An analog-to-digital converter that obtains digital data of an audio signal by sampling and quantizing a time-axis compressed audio signal reproduced from a recording medium at a speed higher than a recording speed at the time of recording at a predetermined sampling period. A conversion unit, a memory for writing and storing the digital data of the audio signal at the predetermined sampling cycle, and a read cycle longer than the sampling cycle, for converting the audio signal from the memory at the read cycle longer than the sampling cycle. A sound signal processing apparatus comprising: means for reading digital data; and digital-to-analog conversion means for converting digital data of an acoustic signal read from a memory into digital-to-analog and outputting as an audio signal in the form of an analog signal. The reading of the digital data of the acoustic signal from the memory is performed from the above-mentioned first address of the memory to the last address. And a means for detecting a mute state below a predetermined signal level including a mute state, and a predetermined mute state including a mute state. Means for stopping the progress of the write address when the sound level becomes lower than the predetermined signal level; and a means for stopping the progress of the write address when the progress of the write address is stopped. First write address progress resuming means for resuming the progress of the write address when the sound state is reached; and a write address value which is changed during the progress of the write address in the loud sound state above the predetermined signal level. Means for stopping the progress of the write address when the read address value matches or the write address value becomes a value near the read address value; When the progress is stopped, when the write address value matches the read address value or when the write address value becomes a value near the read address value, the progress of the write address is restarted. In a state where the write address progress resumption means and a low tone state below a predetermined signal level including a silence state and the progress of the write address are stopped,
After the write address value matches the read address value, or the write address value becomes a value near the read address value, and the write address is resumed, a loud sound state above the predetermined signal level is returned. Means for causing the write address and the read address to be equal or close to each other when it is detected that the acoustic signal processing has been performed.