JPH07296505A - Gain controller - Google Patents

Abstract

PURPOSE:To provide a gain controller effective for signal processing at the time of high speed reproduction. CONSTITUTION:The fact that an output DT1 from an A/D converter 4 supplied with an AC signal in the state where a signal level is adjusted by a programmable gain control amplifier 3 becomes the conversion maximum value or the conversion minimum value of the A/D converter 4 is detected by a minimum value detector 8 and a maximum value detector 9. At this time, the gain control data DT2 in which an output value from the programmable gain control amplifier 3 is reduced by a prescribed amount are generated by an up-down counter 16 to be supplied to the programmable gain control amplifier 3. Further, the gain control data DT2 in which the output value from the programmable gain amplifier 3 is increased by a prescribed amount are generated by the up-down counter 16 once every prescribed time in the AC signal being an object of gain control. By supplying the data DT2 to the programmable gain control amplifier 3, the signal level of the AC signal supplied to the A/D converter 4 is controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain adjusting device for an AC signal, and more particularly to a gain adjusting device for an AC signal which includes an analog-digital converting means for performing an analog-digital conversion operation.

[0002]

2. Description of the Related Art It is known, for example, from a magnetic tape recorder or a video tape recorder to reproduce and listen to recorded information on a recording medium on which an acoustic signal is recorded, in a time shorter than the time required for recording. It is well known that the conventional method is used for the reproduction of. Then, for example, in reproducing recorded information from a recording medium on which a video signal and an information signal such as an audio signal accompanying the video signal are recorded, a recording medium faster than the recording medium speed during the recording operation is performed. By looking at the playback image obtained when performing a playback operation of playing at a high speed, that is, a so-called high-speed playback operation, the content of the image recorded on the recording medium is confirmed within a shorter time than the time required for recording the image. The confirmation has been conventionally performed in, for example, a helical scan type VTR. Then, when high-speed reproduction of the image content is performed as described above, since the acoustic signal accompanying the reproduced video signal is in a state in which the pitch is converted to the higher frequency,
It is usually impossible to grasp the information content.

By the way, if the information content of an audio signal reproduced when a recording medium on which an information signal such as an audio signal accompanying a video signal is recorded is reproduced at a high speed, various applications are possible. Therefore, the applicant company also proposed a video / audio reproduction device equipped with a signal processing means for performing pitch conversion such that an audio signal reproduced at high speed is returned to an original audio signal. (Patent application No. 328 filed on Nov. 13, 1992)
No. 644 “Acoustic signal processing device”, and Japanese Patent Application No. 356217 filed on Dec. 21, 1992 “Acoustic signal processing device”.

As described above, when a high-speed reproduction of the image content is performed, the pitch conversion of the audio signal accompanying the video signal is performed so that the audio information content can be grasped. Writes an acoustic signal (acoustic signal whose time axis is compressed to 1 / N ... time axis compressed acoustic signal) reproduced at high speed in the memory in a period of T / N in synchronization with the writing clock, and A configuration in which the time-axis compressed acoustic signal written in the memory can be reproduced as a reproduction acoustic signal in a time-axis expanded state by using a read clock signal having a cycle N times as long as the write clock. 6 is used for explaining the time axis compression operation and the expansion operation of the acoustic signal in the above-mentioned device.

FIG. 6 (a) shows an acoustic signal reproduced from a recording medium, that is, an original acoustic signal to be recorded, when the recording / reproducing apparatus is performing a reproducing operation at N times speed. It is shown that only the time-axis compressed acoustic signal having the time length of T / N in the time-axis compressed acoustic signal in which the time axis is compressed to 1 / N is intermittently written in the memory every time T. Also, FIG. 6 (b) has been described as the acoustic signal of the time length of T, which is the time-axis compressed acoustic signal having the time length of T / N stored in the memory, expanded by N times. The state is being read from the memory.

As is apparent from FIGS. 6 (a) and 6 (b), in the apparatus having the above-mentioned structure, the time axis compression reproduced from the recording medium of the recording / reproducing apparatus performing the reproducing operation at N times speed. Regarding the acoustic signal, a time-axis compressed acoustic signal having a time length of T / N in the time-axis compressed acoustic signal divided into time periods T on the time axis is obtained as a reproduced acoustic signal having the same pitch as the original acoustic signal. Therefore, the time length T described above is appropriately selected, and the time T /
If there is valid acoustic information during the time period of N,
The reproduced acoustic signal having the same pitch as that of the original acoustic signal is N even if it is a discrete signal portion of the original acoustic signal.
It is considered useful for confirming the information content of the sound signal reproduced at double speed.

By the way, during a high-speed reproducing operation in which the reproducing element reproduces a recording signal from the recording medium at a relative speed larger than the relative speed between the recording element and the recording medium during the recording operation, the acoustic signal reproduced from the recording medium is Since the signal level becomes higher than that of the reproduced audio signal during the normal reproduction operation, when the high speed reproduction is performed, the pitch conversion of the audio signal accompanying the video signal can be performed to grasp the audio information content. In a device having the above-mentioned configuration, that is, a device that converts an acoustic signal into a digital signal, writes the digital signal in the memory, and then extends the time axis from the memory to read the signal, a high-speed reproduction operation is performed. When the signal level of the acoustic signal becomes higher than the input signal level specified for the analog-digital converter, the data will be clipped and distortion will occur. To. Further, it is well known that when the input signal to the analog-digital converter becomes minute, the influence of the quantization error greatly appears, so that the problem of sound quality deterioration occurs.

Therefore, an attempt has been conventionally made to solve the above problem by automatically controlling the gain of an input analog signal supplied to an analog-digital converter as shown in FIG. In FIG. 5, reference numeral 35 is an automatic gain adjustment amplifier, 36 is an analog-digital converter, and 37.
Is a memory, 38 is a digital-analog converter, and 39 is a control circuit. The automatic gain adjustment amplifier 35 in FIG. 5 is configured to include a variable gain amplifier 40, a detection circuit 42, and a low-pass filter 41 as shown in the configuration example in FIG. 7, for example. The AC signal output from the variable gain amplifier 40 used as a component of the automatic gain adjustment amplifier 35 is rectified by the detection circuit 42, smoothed by the low-pass filter 41, and converted into DC. By being supplied to the variable gain amplifier 40 as a gain control signal, the output signal from the variable gain amplifier 40 described above is output from the automatic gain adjustment amplifier 35 as a signal in a state of being held at a substantially constant signal level. Is output.

The automatic gain adjustment amplifier 35 converts the reproduced signal whose signal level has increased during high speed reproduction into an analog digital signal as a reproduced signal whose signal level has been lowered to an appropriate signal level after a predetermined time delay. Converter 36
The reproduction signal which is supplied to the analog digital converter 36 is supplied to the analog-digital converter 36 as a reproduction signal in a state where the signal level is raised to an appropriate signal level after a predetermined time delay. Since it operates, the automatic gain adjustment amplifier 35 to the analog-digital converter 36
Will be supplied with an input signal of an appropriate signal level that does not become higher than the input signal level defined for the analog-digital converter 36 and the influence of the quantization error does not matter. The digital signal output from the analog-digital converter 36 is written in the memory 37, expanded in the time axis from the memory 37, read out, converted into an analog signal by the digital-analog converter 38, and output. . The control circuit 39 controls the operations of the analog-digital converter 36, the memory 37, the digital-analog converter 38, etc. described above.

[0010]

In the conventional device described with reference to FIGS. 5 and 7 and the like, the conventional device is provided in a loop control loop in the automatic gain adjustment amplifier 35 used as a component thereof. Since the control causes a time delay due to the time constant of the low-pass filter 41, the automatic gain adjustment amplifier 35 does not perform the gain adjustment when a large amplitude signal is input momentarily. However, there is a problem that the input signal to the analog-digital converter 36 exceeds the input signal level defined for the analog-digital converter, data is clipped, and distortion occurs in the output signal. Further, in order to solve the above problems, the time constant of the low pass filter 41 provided in the control loop of the automatic gain adjustment amplifier 35 is reduced. Expediently, the gain adjustment by the automatic gain control amplifier 35 will be happened that would take place, that only hesitation sound not heard not play becomes a problem by the intonation of the speech.

As one of means for solving the problem of the automatic gain adjustment technique used in the conventional apparatus described with reference to FIGS. 5 and 7, it is disclosed in, for example, Japanese Patent Laid-Open No. 4-369697. It has been proposed that the automatic gain adjustment is performed after the input signal is separated into the signal components of a large number of frequency bands and the frequency analysis is performed, like the automatic gain adjustment means applied to the speech recognition apparatus. . However, if the previously proposed automatic gain adjustment means is employed, it is necessary to use an extra component for frequency analysis that is not required for automatic gain adjustment, so Has a drawback that it becomes large and expensive, and since the level is set only once, there is a problem that it cannot handle when the level of the input signal changes after setting the level. A solution without the above problems was sought.

[0012]

SUMMARY OF THE INVENTION The present invention provides an analog-digital conversion means for performing an analog-digital conversion operation on an AC signal, a gain control means provided prior to the analog-digital conversion means, and the analog described above. The output value from the gain control means is reduced by a predetermined amount when the output value from the digital conversion means becomes a value near the conversion maximum value or a value near the conversion minimum value. The output value from the above-mentioned gain control means is increased by a predetermined amount by a means for setting the gain in the gain control means and once every predetermined time. And a sound recorded on a recording medium, the gain adjusting device having a means for setting the gain in the gain control means. Analog-to-digital conversion means for analog-to-digital conversion of the time-axis compressed acoustic signal obtained by reproducing the recorded information of the signal at a time T / N (where N is a natural number of 2 or more) shorter than the time T required at the time of recording. A memory for storing digital data of the time-axis compressed acoustic signal output from the analog-digital conversion means, and a state in which the time-axis expanded digital data of the time-axis compressed acoustic signal stored in the memory is expanded by N times. Means for reading the reproduced sound signal as digital data, gain control means provided prior to the analog-to-digital conversion means, and an output value from the analog-to-digital conversion means near a conversion maximum value. Alternatively, when the value becomes close to the conversion minimum value, the output value from the gain control means is decreased by a predetermined amount. The means for allowing the setting of the gain in the control means and the above-mentioned gain at a rate of once when the writing of the predetermined amount of digital data to the memory is completed or when the writing of the digital data to the memory is started. There is provided a gain adjusting device, which comprises means for setting the gain in the gain control means so that the output value from the control means increases by a predetermined amount.

[0013]

The analog-to-digital conversion is performed by the minimum value detector and the maximum value detector to which the output value of the analog-digital converter to which the AC signal whose signal level is adjusted by the programmable gain control amplifier is supplied is supplied. When it is detected that the output value from the converter reaches the conversion maximum value or the conversion minimum value, the gain control data is generated so that the output value from the programmable gain control amplifier is reduced by a predetermined amount. And supply it to the programmable gain control amplifier. In addition, the output value from the programmable gain control control amplifier described above is increased by a predetermined amount at a rate of once per predetermined time in the AC signal that is the object of gain adjustment. Random gain control data is generated and supplied to the programmable gain control amplifier, or when writing of a predetermined amount of digital data to the memory is completed or when writing of digital data to the memory is started. To generate gain control data such that the output value from the programmable gain control control amplifier is increased by a predetermined amount so that the output value from the gain control means is increased by a predetermined amount. And supply it to the programmable gain control amplifier.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The specific contents of the gain adjusting device of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram of a signal processing device including a gain adjusting device of the present invention, FIG. 2 is a block diagram showing a configuration example of a programmable gain control amplifier, and FIG. 3 is a write clock signal and a read address clock. FIG. 4 is a waveform example diagram showing a timing relationship with a signal, and FIG. 4 is a diagram illustrating a relationship between a writing period and a reading period in a sequential signal block section. In the signal processing device including the gain adjusting device of the present invention shown in FIG. 1, 1 is an input terminal of an AC signal to be subjected to signal processing, 2 is an output terminal of the signal processing device, Reference numeral 3 is a programmable gain control amplifier (a specific configuration example is shown in FIG. 2). Reference numeral 4 is an analog-digital converter, 5 is a memory, and 6 is a digital-analog converter.

Programmable gain control amplifier 3 described above
Is an analog-to-digital converter that adjusts the signal level of an AC signal that is a target of signal processing and that is supplied through the input terminal 1 because the gain changes according to the gain control data DT2 supplied to it. Give to 4. As the programmable gain control amplifier 3 described above, it is possible to use, for example, a configuration mode as illustrated in FIG. In the programmable gain control amplifier 3 shown in FIG. 2, 3a is an input terminal for an AC signal to be subjected to gain control, 3b is an output terminal for an AC signal subjected to gain control, 3c is an input for gain control data DT2. Terminals, and 21,22
Is a buffer amplifier, 23 to 30 are switches, 31 to 34
Is an inverter, and R, 2R, etc. are resistors.

The programmable gain control amplifier 3 illustrated in FIG. 2 has 6 bits of gain control data DT for the input terminal 3c of the gain control data DT2.
When 2 (Qo, Q1 ... Q5) is supplied, the gain can be varied in 64 steps. The AC signal to be subjected to gain control, which is supplied to the input terminal 3a of the programmable gain control amplifier 3 shown in FIG. 2, passes through the buffer amplifier 21 to the movable contacts of the switches 23, 25 ... 27, 29. Has been given.
The movable contacts of each of the switches 23, 25 ... 27, 29 are the gain control data DT supplied as the opening / closing control signal.
It is turned on / off depending on whether the signal of the specific digit of 2 is in the high level state or the low level state, and the gain control data DT2 is the inverters 31-3.
Each switch 2 supplied as an opening / closing control signal via 4
The movable contacts 4, 26 ... 28, 30 are turned on / off depending on whether the signal of a specific digit in the gain control data DT2 is in the low level state or the high level state.

The switches 23, 25 ... 27, 29 described above
28, 30 and the fixed contacts of switches 24, 26 ... 28, 30 are located at predetermined positions in the ladder network composed of a resistor having a resistance value of R and a resistor having a resistance value of 2R. Connected to the switch 24,
The movable contacts 26, 28, 30 are grounded. Therefore, the programmable gain control amplifier 3 illustrated in FIG. 2 receives the 6-bit gain control data DT2 supplied to the input terminal 3c of its gain control data DT2.
By (Qo, Q1 ... Q5), the amount of signal attenuation can be switched in 64 ways, so that the gain can be varied in 64 steps.

The output signal from the programmable gain control amplifier 3 is converted into a digital signal having a predetermined number of bits by the analog-digital converter 4 and data DT1 (in the following description, it is assumed to be 8-bit data). Is written in the memory 5. The above-mentioned AD conversion operation in the analog-digital converter 4 is performed in response to the supply of the AD conversion clock signal ADCK generated by the control unit 7 provided with the control signal generator. Further, the memory 5 is supplied with the clock signal CS of the memory and the read / write switching signal RW generated by the control unit 7, so that the operation of writing the data DT1 into the memory 5 and the operation of reading from the memory 5 are performed. Is performed.

The mode of the writing operation to the memory 5 is changed according to the reproduction mode of the recording / reproducing apparatus. For example, the recording / reproducing apparatus is performing the N-times speed reproducing operation and reproducing from the recording medium. If the recorded audio signal is a time-axis compressed audio signal in which the time axis is compressed to 1 / N of the original audio signal to be recorded, it was written in the memory 5. The acoustic signal compressed on the time axis to 1 / N is read out as the acoustic signal in the original state when expanded on the time axis by N times, and the data read from the memory 5 is stored in the control unit 7. Is supplied to the D / A conversion clock signal DACK from the D / A converter, and the D / A converter 6 performing the D / A conversion operation converts the signal into an acoustic signal in the form of an analog signal and sends the acoustic signal to the output terminal 2.

As the DA conversion clock signal DACK supplied from the control section 7 to the digital-analog converter 6 when the recording / reproducing apparatus is performing the N-speed reproduction operation, the control section 7 supplies the analog-digital converter. The conversion clock signal having a cycle N times that of the AD conversion clock signal ADCK supplied to the memory 4 is used, and the cycle of the clock signal CS supplied from the control unit 7 to the memory 5 is the same as that of the read operation. The cycle of the clock signal CS is N times the cycle of the clock signal CS during the write operation.

Now, in the signal processing apparatus having the gain adjusting apparatus of the present invention shown in FIG. 1, the AC signal to be subjected to the signal processing supplied to the input terminal 1 is as described above. As described above, the signal level is adjusted by the programmable gain control amplifier 3 and then applied to the analog-to-digital converter 4, and the gain of the programmable gain control amplifier 3 is the up / down counter 1.
It is controlled by the gain control data DT2 output from the control unit 6. Then, the above-mentioned gain control data DT2
As will be described later, the data DT1 output from the analog-digital converter 4 (assuming that it is 8-bit data as described above, the hexadecimal notation will be used in the following description. Is generated by the up / down counter 16 based on the above), and its specific content is as follows.

That is, the data DT1 output from the analog-digital converter 4 is supplied to the memory 5 as described above, and is also supplied to the minimum value detector 8 and the maximum value detector 9. ing. When the minimum value detector 8 detects the minimum value 0h of the 8-bit data DT1 output from the analog-digital converter 4, it outputs the output E (see FIG. 1) in the high level state to the OR circuit 11. give. Further, when the maximum value detector 9 detects the maximum value FFh of the 8-bit data DT1 output from the analog-digital converter 4, it outputs the output F in the high level state (see FIG. 1) to the OR circuit. Give to 11.

The minimum value 0h of the 8-bit data DT1 output from the analog-digital converter 4 is the minimum value of the analog-digital converter 4, and the 8-bit data DT1 output from the analog-digital converter 4 is the minimum value 0h. The maximum value FFh is the maximum value of the analog-digital converter 4, and the values of 0h and FFh described above are the limit values of conversion in the 8-bit analog-digital converter 4 and are output from the analog-digital converter 4. Further, when the 8-bit data DT1 shows the values of 0h and FFh, it means that it is necessary to lower the signal level of the analog signal input to the digital converter 4. Therefore, as described above, the output G of the OR circuit 11 which outputs the logical sum of the output E from the minimum value detector 8 and the output F from the maximum value detector 9 is supplied to the analog-digital converter 4. It is used as a signal for instructing the reduction of the signal level of the analog signal.

By the way, the control unit 7 uses the clock signal CLK supplied from the oscillator 10 to generate the various signals described above and also generate the following various signals. That is, the control unit 7 generates the write clock signal WCK and outputs it to the write address counter 17
To the read address counter 18,
In addition to supplying the read clock signal RCK, a signal CK1 consisting of one pulse each time the analog-to-digital converter 4 performs one analog-to-digital conversion operation (one signal generated at each sampling period) CK1) is generated,
The detection circuit 19 detects that the write address WAD has reached the maximum value, and outputs the signal WMX output from the detection circuit 19.
Is supplied to the control section 7, the signal CK2 is generated.

The up / down counter 16 for generating the gain control data DT2 is a presettable up / down counter (in the following description, it is assumed to be a presettable 6-bit up / down counter).
And for the upcount clock input terminal U,
The up / down counter 16 when the clock signal is supplied performs the counting operation as the up counter, and the up / down counter 16 when the clock signal is supplied to the down count clock input terminal D.
Performs a counting operation as a down counter. Further, a mode change pulse MCP is supplied to the preset terminal PR of the up / down counter 16 when changing the operation mode, whereby the up / down counter 16 is preset to a numerical value of 3Fh when changing the operation mode. . Therefore, when the reproduction speed is changed, the gain adjustment is automatically performed so that the reproduction signal level fluctuation that occurs due to the change of the reproduction speed is prevented.

A signal L output from the AND circuit 13 is supplied as a clock signal to the down count clock input terminal D of the up / down counter 16 described above, and an AND signal is supplied to the up count clock input terminal U of the up / down counter 16. Signal K output from circuit 12
Is supplied as a clock signal, but the signals L and K described above are respectively generated as follows. First,
As described above, the OR circuit 1 is provided on the input side of the AND circuit 13.
The output signal G of 1 is supplied, and the signal CK1 generated by the control unit 7 (the signal CK1 generated one by one in each sampling period) and the output signal H from the zero detector 14 are generated. Since it is supplied, the signal L output from the AND circuit 13, that is, the down count clock signal applied to the down count clock input terminal D of the up / down counter 16 is the same as the output signal G from the OR circuit 11 described above. , The output signal H from the zero detector 14 is at a high level, the signal CK1 is at a high level.

On the input side of the AND circuit 12, the signal CK2 generated by the control section 7 (the signal W output from the detection circuit 19 when the write address WAD reaches the maximum value) is output.
Since the signal CK2) generated by the controller 7 when MX is supplied to the controller 7 and the output signal I from the 3F detector 15 are supplied, the signal K output from the AND circuit 12, That is, the down-count clock signal applied to the up-count clock input terminal U of the up-down counter 16 is such that the signal CK2 is in the high level when the output signal I from the 3F detector 15 is in the high level. It will occur at the timing when it became.

By the way, the above-mentioned up / down counter 1
The zero detector 14 supplied with the output of 6 is a zero detector for preventing the count value of the up / down counter 16 from becoming 0h → 3Fh when the up / down counter 16 operates as a down counter. In the zero detector 14, when the count value output from the up / down counter 16 becomes 0h, the AND circuit 13 is provided with an output H that is in a low level state. Further, the 3F detector 15 to which the output of the up / down counter 16 is supplied is configured so that the count value thereof does not become 3Fh → 0h when the up / down counter 16 is operating as an up counter. The 3F detector 15 is provided for providing the AND circuit 12 with the output I which is in the low level state when the count value output from the up / down counter 16 becomes 3Fh.

A write address counter 17 which counts the write clock signal WCK generated by the control unit 7 to generate a write address signal WAD, and a read address signal RAD which counts the read clock signal RCK generated by the control unit 7. From the read address counter 18 for generating the write address signal W
The AD and the read address signal RAD are supplied to the selection circuit 20. In the selection circuit 20, the write / read switching signal RW generated by the control unit 7 is used as a selection control signal to select the write address signal WAD and the read address signal RAD, and the address signal MAD is sent to the memory 5.
Supply as. The memory 5 switches between the read operation and the write operation by the write / read switching signal RW supplied from the control unit 7, and the read operation and the write operation are executed at the timing of the clock signal CS. Also,
In the detection circuit 19 to which the write address signal WAD generated by the write address counter 17 is given,
When the write address signal WAD has the maximum value, the signal WMX is generated as described above and is supplied to the control unit 7.

By the way, the input signal supplied to the input terminal 1 in FIG. 1 is an output signal from a recording / reproducing apparatus (for example, a tape recorder or a video tape recorder), and the recording / reproducing apparatus described above has N times speed. In the case of performing the reproducing operation described above, the acoustic signal reproduced from the recording medium is 1 / N of the original acoustic signal that was the recording target.
The time-axis compressed acoustic signal has a time-axis compressed, and the time-axis expanded acoustic signal is expanded N times by applying the method described above with reference to FIG. To generate a reproduced sound signal having the same pitch as the original sound signal, the time axis in a state of being divided into predetermined time lengths T on the time axis as illustrated in FIG. 4, for example. For each compressed acoustic signal (block signal for each signal block section),
Write operation and read operation are performed.

That is, in each time-axis compressed acoustic signal (block signal in each signal block section) divided into predetermined time lengths T on the time axis, T /
A time-axis compressed acoustic signal having a time length of N seconds (T / N writing period length) is written in the memory 5, and a read operation is performed from the memory 5 for T seconds. A write clock signal WCK and a read clock signal RCK used for the above-described write operation to the memory 5 and the read operation from the memory 5 performed as illustrated in FIG. 4 on the time axis.
And, as illustrated in (a) and (b) of FIG.
The cycle of the write clock signal WCK is 1 / N of the cycle of the read clock signal RCK, and the write clock signal and the read signal clock are generated in a timing relationship such that they occur at different time positions. Note that FIG. 4 illustrates an example of the read / write operation of the memory in the case of N = 5 (in the case of 5 × speed reproduction), and in FIG. 3, in the case of N = 5 (in the case of 5 × speed reproduction). 3 illustrates the generation timing relationship between the write clock signal and the read signal clock in FIG.

Each signal block section 1, 2, ... In FIG.
The arrow indicated by the alternate long and short dash line in the figure indicates the state in which information is being written to the memory, and the arrow in the thick solid line in the figure indicates the state in which information is being read from the memory. There is. In the illustrated example, the memory address (both the write address and the read address) is 0 to 7FFFh.
(However, h is a symbol indicating that it is a hexadecimal number, and in this example, the case where the address signal of the memory is 15 bits is taken as an example). Is the signal WMX from the detection circuit 19.
The write address signal WAD generated by the write address counter 17 is output in correspondence with the write address of 7FFFh, and the detection circuit 19 outputs the signal WMX for each signal block section 1, 2 ,. Will be sent. The signal block sections 1 and 2 described above
It goes without saying that the time length of ... can be set arbitrarily.

In FIG. 4, in the signal block section 1, the write address value is 0 from the point where the write address value is 0.
The write operation for the write information of the write information number S1 is continuously performed up to the point of FFFh, and the read address value is 7FFF from the point of the read address value of 0.
Continuously up to the point h, the read operation for the read information of the read information number S1 is performed for a time length N times as long as the write operation, and for the signal block section 2, the write address value starts from 0. Value is 7FF
The write operation for the write information of the write information number S2 is continuously performed up to the point of Fh, and the read information number is continuously changed from the point where the read address value is 0 to the point where the read address value is 7FFFh. The read operation for the read information in S2 is performed for a time length N times as long as the write operation, so that the write operation and the read operation are performed for the successive signal block sections, and the write operation is performed for each successive signal block section. Address counter 17
When the write address signal WAD corresponding to the write address of 7FFFh is generated, the detection circuit 19 outputs the signal WMX.

As described above, the gain adjusting device of the present invention is supplied with the data DT1 output from the analog-digital converter 4 to which the AC signal whose signal level is adjusted by the programmable gain control amplifier 3 is supplied. It has been detected by the minimum value detector 8 and the maximum value detector 9 that the data value output from the analog-digital converter 4 has become the conversion maximum value or the conversion minimum value in the analog-digital converter 4. At this time, the up / down counter 16 generates gain control data DT2 such that the output value from the programmable gain control amplifier 3 becomes smaller by a predetermined amount, and the gain control data DT2 is supplied to the programmable gain control amplifier 3. In addition, at a rate of once every predetermined time set in advance in the AC signal that is the target of gain adjustment. Since the up / down counter 16 generates the gain control data DT2 such that the output value from the programmable gain control amplifier 3 increases by a predetermined amount and supplies it to the programmable gain control amplifier 3. , The analog-digital converter 4 always receives an AC signal having an appropriate signal level.

[0035]

As is apparent from the above detailed description, the gain adjusting device of the present invention is an analog-digital converter to which an AC signal whose signal level is adjusted by a programmable gain control amplifier is supplied. When it is detected that the output value from the analog-digital converter has reached the conversion maximum value or the conversion minimum value by the minimum value detector and the maximum value detector to which the output value is supplied, the programmable gain The gain control data is generated such that the output value from the control amplifier is reduced by a predetermined amount and is supplied to the programmable gain control amplifier, and the gain control data is previously supplied to the AC signal to be gain-adjusted. The output value from the programmable gain control amplifier described above is set to a predetermined amount once every predetermined time. The gain control data is generated so that it becomes larger, and is supplied to the programmable gain control amplifier so that the signal level of the AC signal supplied to the analog-digital converter is controlled. In the gain adjusting device of the present invention, the gain adjustment with respect to an excessive input signal is performed at high speed, and the distortion that occurs when an excessive signal level signal is input to the analog-digital converter can be suppressed in a short time. , An audio signal for obtaining an audio signal such that the information content of the audio signal reproduced when the recording medium on which the information signal such as the audio signal accompanying the video signal is recorded is reproduced at high speed When the gain adjusting device of the present invention is applied to the signal processing device, the gain adjusting device of the present invention is set to the maximum signal level when the reproduction mode is changed, and the signal level thereof is set. If the adjustment of the signal level for the signal is finished in a short time and then the signal level gradually decreases, the gain adjustment should be performed in order to operate so that the adjustment is performed slowly at the low signal level. Since it does not follow fluctuations in the signal level within a sequential signal section set for each predetermined time length in an AC signal being generated, it does not change intonation and the like, and provides an audio signal that is easy to hear. Further, since the readjustment is performed when the playback mode is changed, the optimum signal level adjusting operation for various playback speeds can be quickly performed. Further, since all the control units in the gain adjusting device of the present invention can be formed into a logic circuit, they can be easily configured by an integrated circuit, can be manufactured at low cost, and the threshold value can be arbitrarily set easily. The operation is stable and requires no adjustment, and the optimum signal level adjustment is repeated in response to fluctuations in the signal level during operation. Can be configured.

[Brief description of drawings]

FIG. 1 is a block diagram of an example configuration of a signal processing device that includes a gain adjusting device of the present invention.

FIG. 2 is a block diagram showing a configuration example of a programmable gain control amplifier.

FIG. 3 is a waveform diagram illustrating a relationship between a write write clock signal and a read clock signal.

FIG. 4 is a diagram illustrating a relationship between a writing period and a reading period.

FIG. 5 is a block diagram showing a configuration example of a conventional acoustic signal processing device.

FIG. 6 is a diagram showing an audio signal that allows the information content of an audio signal reproduced when a recording medium on which an information signal such as an audio signal accompanying a video signal is recorded to be reproduced at high speed. It is a figure for explaining the composition principle of the acoustic signal processing device for.

FIG. 7 is a block diagram of a conventional general automatic gain control circuit.

[Explanation of symbols]

3 ... Programmable gain control amplifier, 4 ... Analog-digital converter, 5 ... Memory, 6 ... Digital-analog converter, 7 ... Control part, 8 ... Minimum value detector, 9 ... Maximum value detector, 10 ... Oscillator, 11 ... OR circuit, 12, 13 ... AND circuit, 14 ... Zero detector, 15 ... 3F detector, 16 ...
Up-down counters 21, 22 ... Buffer amplifiers,
23 to 30 ... Switch, 31 to 34 ... Inverter, 35
... automatic gain adjustment amplifier, 36 ... analog-digital converter, 37 ... memory, 38 ... digital-analog converter, 3
9 ... Control circuit, 40 ... Variable gain amplifier, 41 ... Low-pass filter, 42 ... Detection circuit,

[Procedure amendment]

[Submission date] May 20, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

[0035]

As is apparent from the above detailed description, the gain adjusting device of the present invention is an analog-digital converter to which an AC signal whose signal level is adjusted by a programmable gain control amplifier is supplied. When it is detected that the output value from the analog-digital converter has reached the conversion maximum value or the conversion minimum value by the minimum value detector and the maximum value detector to which the output value is supplied, the programmable gain The gain control data is generated such that the output value from the control amplifier is reduced by a predetermined amount and is supplied to the programmable gain control amplifier, and the gain control data is previously supplied to the AC signal to be gain-adjusted. The output value from the programmable gain control amplifier described above is a predetermined amount once every predetermined time. The gain control data is generated to be large and is supplied to the programmable gain control amplifier so that the signal level of the AC signal supplied to the analog-digital converter is controlled. In the gain adjusting device of the invention, the gain adjustment for an excessive input signal is performed at high speed, and the distortion that occurs when an excessive signal level signal is input to the analog-digital converter is suppressed in a short time. An acoustic signal for obtaining an acoustic signal that allows the information content of the reproduced acoustic signal to be clearly known when the recording medium on which the information signal such as the acoustic signal accompanying the video signal is recorded is reproduced at high speed. When the gain adjusting device of the present invention is applied to the processing device, the gain adjusting device of the present invention is set to the maximum signal level when the reproduction mode is changed, and the signal level thereof is set. If the signal level adjustment to the is finished in a short time, and then the signal level gradually decreases, the gain is adjusted so that the adjustment is performed slowly with a low signal level difference. Since it does not follow fluctuations in the signal level within a sequential signal section set for each predetermined time length in an AC signal being generated, it does not change intonation and the like, and provides an audio signal that is easy to hear. Further, since the readjustment is performed when the playback mode is changed, the optimum signal level adjustment operation can be quickly performed for various playback speeds. By performing after the writing of the predetermined amount of digital data is completed or when the writing of the predetermined amount of digital data to the memory is started, Even if the gain is adjusted, the state of the change in the signal level during the gain adjusting operation is not written in memory, so that an inaudible acoustic signal is not output. The control unit in the gain adjusting device of the present invention is
Since all can be made into logic circuits, it can be easily configured by an integrated circuit, can be manufactured at low cost, and the threshold value can be set arbitrarily easily, and adjustment is not necessary and operation is stable. In addition, since the optimum signal level adjustment is repeated in response to the fluctuation of the signal level during operation, it is possible to configure a device with good performance as a small-sized and inexpensive device.

Claims (3)

[Claims] 1. An analog-digital conversion means for performing an analog-digital conversion operation on an AC signal, a gain control means provided prior to the analog-digital conversion means, and an output value from the analog-digital conversion means. Is set to a value near the conversion maximum value or a value near the conversion minimum value so that the output value from the gain control means decreases by a predetermined amount. And the gain control means for increasing the output value from the gain control means by a predetermined amount at a predetermined rate once every predetermined time. And a means for enabling the setting of the gain in the above. 2. The recording information of the acoustic signal recorded on the recording medium is recorded for a time T / N shorter than the time T required for recording.
(Where N is a natural number of 2 or more), analog-digital conversion means for analog-digital converting a time-axis compressed acoustic signal obtained by reproduction, and digital data of the time-axis compressed acoustic signal output from the analog-digital conversion means. And a means for reading the digital data of the time-axis compressed acoustic signal stored in the memory as digital data of the reproduced acoustic signal in a state expanded in the time-axis by N times, and the analog-digital conversion means. When the output value from the gain control means provided prior to the above and the analog-to-digital conversion means becomes a value near the conversion maximum value or a value near the conversion minimum value, the gain control means Means for setting the gain in the above-mentioned gain control means so that the output value of is reduced by a predetermined amount, When the writing of the predetermined amount of digital data to the memory is completed or when the writing of the digital data to the memory is started, the output value from the gain control unit is increased by a predetermined amount at a rate of once. And a means for allowing the gain control means to set the gain as described above. 3. A gain control data to be given to the gain control means for setting the gain of the gain control means provided prior to the analog-digital conversion means for performing the analog-digital conversion operation on the AC signal. An up-down counter for causing the up-down counter and a means for preventing the up-down counter from counting up when the output value of the up-down counter is greater than or equal to a first predetermined value;
3. The gain adjusting device according to claim 1, further comprising means for preventing the countdown of the up / down counter when the output value of the up / down counter is equal to or less than a second predetermined value.