JP2944069B2 - Music signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone signal generator for generating a tone signal based on waveform data stored in a waveform memory in advance.

[0002]

2. Description of the Related Art A conventional electronic musical instrument has a tone signal generator. The tone signal generator generates a tone signal based on waveform data stored in advance in a waveform memory. The waveform memory stores, for example, waveform data in the PCM format. PCM data is created by sampling a musical sound waveform at a predetermined period, quantizing it, and further encoding it. The PCM data is sequentially read from the waveform memory in accordance with the tone generation instruction, and a tone signal is generated based on the read PCM data.

In such a tone signal generating device,
In order to generate tone signals corresponding to a large number of timbres, it is necessary to store an enormous amount of PCM data in a waveform memory in advance. Therefore, in order to reduce the amount of waveform data, PC
A method has been proposed in which M data is compressed and stored in a waveform memory, and when a musical tone is generated, the compressed waveform data from the waveform memory is expanded. As such a method, for example, ADPCM (Adaptive Differential Pulse Code Modula)
Option) or DPCM (Differential Pulse Code Modul)
ation) method is known. In these methods, difference waveform data created by calculating a difference between sampling data at adjacent sample points of a musical tone waveform is stored in a waveform memory, and when a tone is generated, the difference waveform data from the waveform memory is accumulated. The tone signal is reproduced by the calculation.

In order to reduce the amount of waveform data to be stored in the waveform memory, the following method is generally employed. That is, as shown in FIG. 12, for example, only a predetermined section (attack section) at the head of the musical tone waveform and a subsequent predetermined section (repeat section) of the musical tone waveform are stored in the waveform memory. When a tone signal is generated, the attack portion is read only once from the beginning, and then the repeat portion is repeatedly read. The tone signal generator generates a tone signal based on the read waveform data.

However, conventionally, the above-mentioned ADPCM
The system and the DPCM system are rarely adopted as musical tone signal generators for electronic musical instruments. This is because the following first problem and second problem existed. The first problem is that when a method of repeatedly accumulating the waveform data of the repeat portion is adopted, a cumulative error occurs. The second problem is that since the sampled musical tone waveform is discrete, it is necessary to interpolate between two adjacent sampling points to generate a musical tone having a desired pitch. The problem is that the circuit becomes complicated.

[0006] Although having the above-mentioned problems, AD
Since the PCM method or the DPCM method can reduce the amount of waveform data, research for practical use is active. For example, Japanese Unexamined Patent Publication No.
Japanese Patent Application Publication No. 242959/1995 discloses a "tone signal generator". This device eliminates accumulated errors by always using the last data of the attack part at the head of the repeat part when decoding encoded waveform data that is repeatedly read.

However, in this tone signal generator, a comparison circuit and selectors 107 and 117 for judging whether or not it is the head of the repeat section, and a latch 106 for storing data (Δn, Sn + εn) at the time of attack end. And 118 etc. are required, so that there is a disadvantage that the circuit becomes complicated. Also, the method disclosed in Japanese Patent Application Laid-Open No. 62-242959 has a drawback that when the waveform data includes a plurality of repeat parts, the control method becomes complicated, so that the circuit becomes complicated.

[0008] The second problem has not been solved yet. For example, if the frequency number (F number) is fixed at "1", the waveform read addresses for reading the waveform data from the waveform memory are sequentially incremented by "+1", so that there is no need for interpolation. However, actual electronic musical instruments
Since a tune function (a function of shifting the pitch level in units of cents as a whole instrument), a portamento function, a glide function, and the like are required, it is necessary to perform interpolation for fine pitch control. Depending on the pitch, complicated control of generating a musical tone while accessing one sampled data a plurality of times is required. Therefore, interpolation requires a complicated control circuit.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problem, and has a simple circuit configuration, and is used when a tone signal is reproduced by the ADPCM system or the DPCM system. , The occurrence of accumulated errors due to repeated reading of waveform data can be suppressed.
It is an object of the present invention to provide a tone signal generating device capable of suppressing an accumulated error when not repeatedly reading.

[0010]

In order to achieve the above object, a musical sound signal generating apparatus according to the present invention comprises: (A) converting a musical sound waveform into sampling points P _i (where i = 0, 1, 2,...) , N
Specific sampling data D _j that is selected from the sampled data D _i obtained by sampling at -1)
(However, the specific waveform data W _j produced based on 0 ≦ j ≦ N−1) and the sampling data D _n (where n =
.., N−1, and difference waveform data ΔWD _n obtained by subtracting the sampling data D _n−1 from n ≠ j); The specific waveform data _Wj or the differential waveform data Δ
The WD _n, reading means for sequentially reading, and (C) a temporary storage unit, the (D) when said read out means reads the specific waveform data W _j to generate the sampling data YD _j, the sampling data YD _j one o'clock stored in the storage means, accumulates in the temporary storage means said difference waveform data DerutaWD _n when said read out means reads out the difference waveform data DerutaWD _n, decoding means for generating a sampled data YD _n Te following, (E )
The resulting sampled data YD _j or music signal generating means for generating a musical tone signal based on YD _n, and a city.

[0011] specific waveform data W _j and the difference waveform data is stored in the waveform storage means DerutaWD _n, for example, is produced as follows. First, as shown in FIG. 12, for example, an attack portion of a musical tone waveform and a repeat portion of a predetermined section following the attack portion are extracted. Next, the extracted attack part and repeat part are sampled at a predetermined cycle to obtain a plurality of sampled data D _i (i = 0, 1, 2,..., N−
Obtain 1). Specific sampling data D _j (0 ≦ j ≦ N
-1) is selected from among the N sampling D _i.
The contents of the specific sampling data D _j is a predetermined value.
The number of specific sampling data D _j can be 1 or more. The specific waveform data W _j is created (converted) based on the specific sampling data D _j . The specific waveform data W _j has the same format as the specific sampling data D _j ,
For example, it can be in PCM format. The contents of a particular waveform data W _j can either be the same as the contents of a particular sampling data D _j, it may be made different. Differential waveform data DerutaWD _n is obtained by subtracting the sampling data D _n-1 from the sampled data D _n (where, n = 1, 2, a · · · N-1, and n ≠
j). Differential waveform data DerutaWD _n is, DPCM format or A
It is in DPCM format.

[0012] In the musical tone signal generating apparatus of the present invention, if the difference waveform data DerutaWD _n is read from the waveform storage means by the reading means, the difference waveform data DerutaWD
_n is accumulated in the temporary storage means. That is, the read difference waveform data ΔWD _n and the sampling data YD _n−1 stored in the temporary storage unit are calculated, for example, added, and thereby the sampling data YD _n is reproduced. The resulting sampled data YD _n is used to generate the musical tone signal. By repeating this accumulation, the sampling data YD _n (n = 1, 2,.
..) are continuously updated to generate a tone signal that changes over time.

On the other hand, the specific waveform data W
_{If j} is read from the waveform storage means, decoding means for generating a sampled data YD _j. The contents of the sampling data YD _j is the same as the contents of a particular sampling data D _j. Further, the obtained sampling data YD
_j is the difference waveform data ΔWD _n (n = j + 1, j + 2,.
..) is stored in the temporary storage means as initial sampling data for accumulating (.).

According to the above configuration, it is possible to remove accumulated errors peculiar to the ADPCM system or the DPCM system. Furthermore, according to this musical tone signal generating apparatus is not limited to the case of reading by repeating the specific waveform data W _j or difference waveform data DerutaWD _n, even if the read only once a particular waveform data W _j or difference waveform data DerutaWD _n cumulative Errors can be eliminated.

In a preferred embodiment of the tone signal generating apparatus of the present invention, the reading means includes an F number generating means for generating an F number for designating a pitch, and an F number from the F number generating means. F number accumulating means for accumulating at a predetermined period, thereby generating a waveform read address consisting of an integer part and a fractional part. The read means includes: particular waveform data W _j, if the integer portion of the waveform read address is n differential waveform data ΔW
Read from the respective waveform storage means D _n, it said decoding means includes interpolation means, interpolation means, between sampling data YD n _{+ 1} and YD _n, or sampled data YD
_{j + 1} and performs interpolation according to the value of the fractional part of the waveform read address with the YD _j, than Te to obtain interpolated data, the tone signal generation means generates a musical tone signal based further on the interpolation data YD I do.

In this preferred embodiment, for example, when a key-on instruction is given, an F for designating a pitch is designated.
The number is generated by the F number generation means.

According to this preferred embodiment, it is possible to achieve a tone signal generator capable of finely adjusting the pitch.

[0018] In the musical tone signal generating apparatus of the present invention, the content of the specific sampling data D _j can be zero. The contents of a particular waveform data W _j is, for example, the minimum value "8000H" (indicating that the end "H" is a hexadecimal number. The same applies to the following.) Or a maximum value "7FF
FH "or a value near any one of these. This content can be expressed in two's complement format. Usually, the content of the difference waveform data DerutaWD _n is not a value as described above. Therefore, the specific waveform data W _j is
It can be distinguished from the difference waveform data ΔWD _n.

When the specific waveform data _Wj is read from the waveform storage means at the time of generation of the musical tone signal, the sampling data YD _n-1 reproduced by being accumulated in the temporary storage means is discarded. Sampling data YD _j
Is set in the temporary storage means as new sampling data. Thereby, the sampling data YD
Accumulation is restarted from _j .

When actually sampling a musical sound waveform, important points such as a start position (start address SA), a loop start position (loop top address LT), and a loop end position (loop end address LE) of the musical sound waveform are used. often chosen to be a specific sampling data D _j.

[0021] In the musical tone signal generating apparatus of the present invention, also, the content of the specific sampling data D _j can be within a predetermined range of spread. Such predetermined spread is:
For example, it is possible to 1/256 times the allowable maximum contents of the sampling data D _i. In this case, since the contents of a particular sampling data D _j is within a range of a predetermined spread, unlike the case where the contents of a specific sampling data D _j no spread, it is possible to easily produce a specific waveform data W _j .

In a preferred embodiment of the tone signal generating apparatus according to the present invention, the difference waveform data ΔWD _n−1 is obtained by sampling data D _M−1 (where 1 ≦ M ≦ N−3) to D _N−2.
, Where j is M <j <N
-1 is satisfied, and the reading means sets the differential waveform data ΔWD
After reading _N−1 , the difference waveform data ΔWD _M is read again. According to this preferred embodiment, the value "M"
Is the content of the loop top address LT, and the value “N”
Is the contents of the loop end address LE.

Further, in another preferred embodiment of the tone signal generating apparatus of the present invention, the specific waveform data W _j is j =
After reading the differential waveform data ΔWD _N−1 , the specific waveform data W _j (where j =
M) is read. In this preferred embodiment, the value "M" is the contents of the loop top address LT and the value "N" is the contents of the loop end address LE.

As described above, the tone signal generating apparatus of the present invention has an ADP despite its simple circuit configuration.
It is possible to suppress not only the occurrence of the accumulated error due to the repeated reading when the tone signal is generated by the CM or the DPCM method, but also the accumulated error when the reading is not the repeated reading.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a tone signal generating apparatus according to the present invention. The tone signal generator includes a tone generator circuit and a CPU for controlling the tone generator circuit. However, since the configuration and operation of the CPU are well-known, the following description focuses on the configuration and operation of the tone generator circuit.

(First Embodiment) The tone signal generator of the first embodiment generates a tone signal without performing interpolation of sampling data. In the tone signal generator of the first embodiment, the difference waveform data ΔW in the ADPCM format is used.
D _n and the specific waveform data W _{j in the} PCM format are used.

The ADPCM data has a sign (bit 15) and an exponent (bits 14 and 13) as shown in FIG.
And data of a floating-point format including a mantissa (bits 12 to 0). The ADPCM data is created as follows. As shown in FIG. 4, the musical sound waveform is sampled at a predetermined cycle at sampling points P _i (i = 0, 1, 2,.
1), quantized, and coded to obtain sampling data D _i (i = 0, 1, 2,..., N−
1) is manufactured. This sampling data _Di is PC
M format, represented in 2's complement format. Differential waveform data DerutaWD _n is obtained by subtracting the sampling data D _n-1 from the sampled data D _n. Where n = 0,
.., N−1, and n ≠ j. The difference waveform data ΔWD _n is in DPCM format, and is represented in 2's complement format. Therefore, the expression of a positive number or a negative number is possible. For example, in the example shown in FIG. 4, each sampling data D _{n at the} sampling points P _n and P _n-1 is
Differential waveform data ΔWD _n (= D representing the difference between the D _n-1 and
_n −D _n−1 ) is obtained as a positive number. Sampling point P
Difference waveform data ΔWD _{n + 1} (= D _{n + 1} −D) representing the difference between each sampling data D _{n + 1} and D _{n at n + 1} and P _n
n ) is obtained as a negative number.

The difference waveform data Δ thus obtained
WD _n (where n = 1, 2,..., N−1 and n ≠ j) is converted to floating-point format data having an exponent according to the magnitude of the absolute value. Differential waveform data DerutaWD _n obtained by this conversion is ADPCM format. Differential waveform data DerutaWD _n of ADPCM format created this way is stored in the waveform memory 208 which will be described later. The waveform memory 208 corresponds to the waveform storage unit of the present invention.

As described above, the difference waveform data ΔWD _n
In the process of creating the contents of the sampling data D _j of the PCM format specific value of the PCM format, for example, when a zero, a special processing is performed. That is, in this case, specific waveform data W _j of the PCM format is produced on the basis of a specific sampling data D _j. Specific waveform data W _j
Are stored in the waveform memory 208. Here, contents of a particular waveform data W _j is assumed to Z11.

[0030] In the following, a particular waveform data W _j and a plurality of differential waveform data _{ΔWD n (n = 1,2, ···} N-1
And a group consisting of n ≠ j) is referred to as a “waveform data group”. Further, one of a particular waveform data W _j or more differential waveform data DerutaWD _n in the waveform data group of "waveform data group of the waveform data."

As the Z11, for example, the minimum value “8”
000H "or the maximum value" 7FFFH "or a value in the vicinity thereof can be used. The contents Z11 of the specific waveform data W _j is, in most cases, completely different from the contents of the difference waveform data ΔWD _n. Therefore, the specific waveform data W _j can be distinguished from each difference waveform data ΔWD _n. Book first
In the embodiment, the minimum value “8000H” is used as an example of the content (value) Z11.

[0032] In the first embodiment, the waveform readout address for reading out the differential waveform data DerutaWD _n or specific waveform data W _j from the waveform memory 208 is composed of 32-bit data. The lower 16 bits of the waveform read address are used as a decimal address (decimal part). The upper 16 bits of the waveform read address are used as an integer address (integer part).

The loop top address LT is composed of 16-bit data. This loop top address LT corresponds to the integer part of the waveform read address. The loop end address LE is composed of 16-bit data. This loop end address LE corresponds to the integer part of the waveform read address. Loop top address LT
Is used to specify the head of the repeat part of the waveform data group. The loop end address LE is used to specify the end of the repeat part of the waveform data group.

FIG. 5 shows how the specific waveform data W _j and the difference waveform data ΔWD _n created as described above are stored in the waveform memory 208. That is, at the sampling points P ₀ and P ₁₂₈ , since the contents of the sampling data D ₀ and D ₁₂₈ are zero, the specific waveform data W _j (j = 0 and j = 128) in the PCM format is generated and the address is obtained. It is stored in the position of the waveform memory 208 specified by “0” and “128”. The content of the specific waveform data W _j (j = 0 and j = 128), that is, Z11 is “8000H” in the present embodiment. Other sampling points P _i (i = 1, 2,..., 127, 129,...)
.), The sampling data D _i (i = 1,
2, ..., 127, 129 ...) it is not a zero, the sampling data D from the sampling data D _n
By subtracting _n−1 , the difference waveform data ΔWD _{n in the} ADPCM format (i = 1, 2,..., 127, 12
9) are obtained, and the addresses “1”, “2”,.
Are stored at the positions of the waveform memory 208 designated by “127”, “129”,. The specific waveform data W is stored in the position of the waveform memory 208 specified by the address “0”.
_{When j} is not stored, the contents of the sampling data D ₀ are stored in the waveform memory 208 specified by the address “0”.
Is stored at the position of. In the first embodiment, the loop top address LT (M) is “128”. That is, the contents of the waveform memory 208 specified by the loop top address LT (M = “128”) are the specific waveform data W
_j (j = 128).

(1) Description of Decoding Circuit FIG. 1 is a block diagram showing a decoding circuit 209 (see FIG. 2) applied to a tone generator circuit of the present tone signal generating apparatus. The decoding circuit 209 corresponds to a decoding unit and a temporary storage unit.

[0036] In FIG. 1, the comparator 100 compares the specified waveform data W _j or difference waveform data DerutaWD _n value (waveform data of the waveform data group) Z21 from the waveform memory 208. Value Z21 is the same as the contents of a particular waveform data W _j. The value Z21 can be stored in, for example, a ROM or a register (not shown). As a value Z21,
For example, the minimum value “8000H” or the maximum value “7FF”
FH "or values near these can be used. As an example of the value Z21, the minimum value “8000H” is used. As a result of this comparison, if the two match, "1" is generated as a control signal by the comparator 100, otherwise, "0" is generated by the comparator 100. This control signal is supplied to the input terminal S of the selector 104.

The expansion circuit 101 receives the differential waveform data DerutaWD _n from the waveform memory 208, converts the differential waveform data DerutaWD _n from ADPCM format to DPCM format. In this conversion, the compressed quantization width is restored. Conceptually, as shown in FIG.
The value of the mantissa is shifted left according to the value of the exponent of the data. Thus, the ADPCM data is converted into DPCM data having a two's complement format in a fixed-point format.
In the case the difference waveform data DerutaWD _n stored in the waveform memory 208 of DPCM format, the expansion circuit 101
Can be removed. Expansion circuit 101, when the enter specific waveform data W _j from the waveform memory 208, the decompression circuit 101 outputs the converted specified waveform data. Differential waveform data DerutaWD _n or conversion specified waveform data is supplied to the gate 102.

The current sample memory 106 corresponds to a temporary storage. The difference waveform data is accumulated in the current sample memory 106. Here, it is assumed that the difference waveform data ΔWD _n−1 is accumulated in the current sample memory 106, and the sampling data YD _n−1 is reproduced and stored in the current sample memory 106. The tone signal generator of the present invention can simultaneously generate a plurality of tone signals. The current sample memory 106 includes a plurality of blocks corresponding to a plurality of sound channels. Current sample memory 10
Each block of 6 corresponds to each waveform data group. The number of blocks is equal to the number of time divisions. Which block is activated is determined by a timing generator 201 described later.
Is determined by the timing signal TC. Hereinafter, such a configuration is referred to as a “time division configuration”. The sampling data YD _n-1 from the current sample memory 106
Is supplied to the B input terminal of the adder 103.

The gate 102 may, if coincidence signal CF is "0", the difference waveform data DerutaWD _n from decompression circuit 101
Alternatively, the converted specific waveform data is passed as it is.
On the other hand, if the coincidence signal CF is “1”, zero is output.
This coincidence signal CF is generated by a comparator 210 (see FIG. 2) described later. The coincidence signal CF is “1” when the value of the integer part of the waveform read address is the same as the previous time, and is “0” otherwise. Whether to accumulate the difference waveform data ΔWD _n in the sampling data YD _n−1 is determined by the coincidence signal. The output of the gate 102 is supplied to the A input terminal of the adder 103.

The adder 103 adds the output of the gate 102 to the sampling data YD _n-1 from the current sample memory 106. Thus, the next sampling data YD _n obtained. Sampling data YD _n from the adder 103 is supplied to the B input terminal of the selector 104.

[0041] The selector 104 is responsive to a control signal from the comparator 100, one of the following sampling data YD _n supplied from the value Z12 or current sample memory 106 is supplied to the A input terminal to the B input terminal select. The value Z12, the contents of the specific sampling data D _j, that is equal to zero. The value Z12 can be stored in, for example, a ROM or a register (not shown). When the selector 104 receives the control signal “1” from the comparator 100, the A input terminal of the selector 104 is selected. Accordingly, the selector 104 outputs the sampling data YD _j having the same contents as the specific sampling data D _j to the clear circuit 105. On the other hand, the selector 104
When receiving the control signal “0” from 0, the B input terminal of the selector 104 is selected. Thereby, the selector 104
Outputs sampling data YD _n to the clear circuit 105.

The clear circuit 105 includes a clear signal CLRB.
, The input data is passed as it is, or zero is forcibly output. This clear circuit 105
It is used to clear the contents of the current sample memory 106 when the reading of the waveform data of the waveform data group is started. Therefore, if the waveform data group has data having a value of zero at its head, the clear circuit 105 can be removed in some cases.

Whether the clear circuit 105 is activated to output zero is determined by the control flag latch 202.
(See FIG. 2). The contents of the control flag latch 202 are set or reset by data from a CPU (not shown). The output of the clear circuit 105 is supplied to a current sample memory 106. As a result, the sampling data YD _j , YD _n or zero is stored in the current sample memory 10.
BR> 6. The output of the clear circuit 105 is also supplied to a multiplier 217.

(2) Description of Tone Generator FIG. 2 is a block diagram of a first embodiment of a tone generator applied to the present tone signal generator. In this sound source circuit,
The decoding circuit 209 described above is included. Hereinafter, the configuration and operation of the tone generator circuit will be described in detail with reference to the block diagram shown in FIG.

The reading means of the present invention comprises a current step memory 203, a selector 204, a current address memory 205, an adder 206, and a loop top address memory 2.
12, loop end address memory 213 and comparator 2
11. This reading means generates a waveform read address.

In FIG. 2, the CPU and the tone generator circuit are
They are connected to each other via a 6-bit data bus DB, 24-bit address bus AB and control data bus CNT. Latch 200 is a bidirectional tri-state latch. The latch 200 is used for controlling data transmission and reception between the CPU and the tone generator circuit. The tone generator circuit handles 32-bit data. Therefore, data transfer from the CPU to the tone generator circuit is performed twice for each 16 bits. The latch 200 sequentially takes in 16-bit data from the data bus DB, and sends out the data to the internal bus 250 when 32 bits are completed. Conversely, when data is transferred from the tone generator to the CPU, 32-bit data is set in the latch 200. The data set in the latch 200 is output to the data bus DB in 16-bit units. The latch timing and transfer direction of the latch 200 are controlled by a control signal CT from the timing generator 201.

The timing generator 201 includes a clock signal CLK from a clock generator (not shown), address data sent from the CPU via the address bus AB, and control data sent from the CPU via the control data bus CNT. To generate various control signals for controlling each part of the tone generator circuit. Specifically, the timing generator 201 includes a control signal CT for controlling the latch 200 and a control signal SEL for controlling the selector 204.
And a timing signal T specifying one time slot
Generate C. The timing signal TC is, for example, 3 when the tone generator circuit operates in a time division manner of 32 tone generation channels.
It is used to specify any one of the two time division time slots. The timing signal TC is supplied to various memories described later.

The control flag latch 202 has a time-division structure and stores data from the CPU. Clear signal CL output from a predetermined bit of control flag latch 202
RA is supplied to the clear circuit 207. The clear signal CLRB output from the other bits is
5 (see FIG. 1). The clear circuit 207 is removed as described later, and the clear circuit 1 described above is used.
In the tone signal generating device having the configuration from which 05 has been removed, the control flag latch 202 is unnecessary.

The current step memory 203 has a time-division structure and stores the F number from the CPU. Here F
The number is data that defines the pitch (frequency) of a musical tone to be generated. Specifically, when the waveform data of the waveform data group is sequentially read from the waveform memory 208,
Used as the increment value of the waveform read address. The F number from the current step memory 203 is added to the adder 20
6 A input terminal.

The selector 204 has three input ports (port 0, port 1 and port 2). Each input port is selected according to a control signal supplied to the control input terminals S0 and S1. Port 1 has 16
Bit data is supplied. Therefore, when the port 1 is selected, the selector 204 outputs 32-bit data with the lower 16 bits set to zero. The table below shows the relationship between the control signals (S0, S1) and the selected input port.

[0051]

<S1> <S0> <Selected input port> 0 0 Port 2 (next waveform read address) 0 1 Port 1 (loop top address LT) 1-Port 0 (data sent from CPU)

The port 0 is used for selecting one waveform data group from a plurality of waveform data groups.
Each waveform data group corresponds to each tone color. The CPU sends control data for generating the control signal SEL to the timing generator 201. At the same time, the CPU sends the start address (start address SA) of the waveform data group corresponding to the desired timbre to the latch 200 via the data bus DB. As a result, port 0 is selected based on the control signal SEL, and the selector 204 outputs the start address SA of the waveform data group. As a result, the initial value of the waveform read address of the waveform data group is determined. The port 1 is used for returning from the loop end address LE of the repeat part of the waveform data group to the loop top address LT. The port 2 is used for purposes other than the above, that is, for sequentially updating the waveform read address. The data selected by the selector 204 is stored in the current address memory 2
05.

The current address memory 205 has a time-division structure, and stores a current waveform read address. The current waveform read address stored in the current address memory 205 indicates the storage position of the read waveform data group. This current address memory 20
5 is supplied to the B input terminal of the adder 206 and the B input terminal of the comparator 210.

The adder 206 adds the F number from the current step memory 203 to the current waveform read address. The output of the adder 206 is the next waveform read address. The integer part of the next waveform read address indicates the storage position of the waveform data of the waveform data group read in the next cycle. The output of the adder 206 is a clear circuit 207
Supplied to

The clear circuit 207 is used to set a predetermined lower bit of the next waveform read address from the adder 206 to zero. The clear circuit 207 is necessary when invalid data is included in predetermined lower bits of a waveform read address from the CPU. Therefore, when valid data of 32 bits is sent from the CPU, the clear circuit 207 can be eliminated. This clear circuit 20
7 are the waveform memory 208 (upper 16 bits), the A input terminal of comparator 210 (upper 16 bits), the comparator 2
11 A input terminal (upper 16 bits) and port 2 (32 bits) of the selector 204 described above.

[0056] The waveform memory 208, as described above, and stores the specific waveform data W _j of the plurality of difference waveform data DerutaWD _n and PCM format ADPCM format. The contents of the waveform memory 208 are read according to the integer part of the next waveform read address from the clear circuit 207. That is, the specific waveform data W related to the integer part of the current waveform read address stored in the current address memory 205
In parallel with the musical tone signal based on the _j or differential waveform data DerutaWD _n is generated, it is read from the specific waveform data W _{j + 1} or differential waveform data ΔWD n + ₁ waveform memory 208. Specific waveform data W _{j + 1} from the waveform memory 208
Alternatively, the difference waveform data ΔWD _{n + 1} is supplied to the decoding circuit 209 in the next cycle. Sampling data YD _j or YD _n obtained by the generation or accumulation in the decoding circuit 209 is supplied to an input terminal A of the multiplier 217.

The comparator 210 compares the integer part of the current waveform read address from the current address memory 205 with the integer part of the next waveform read address from the clear circuit 207. If they match, the comparator 210 outputs “1”. If they do not match, the comparator 210 outputs “0”. The output of the comparator 210 is output as a match signal CF from the gate 1 in the decoding circuit 209.
02. The gate 102 outputs the differential waveform data Δ
It is provided to prevent WD _n from being added to sampling data YD _n redundantly. The possibility of the overlap addition occurs when the interval for reading out the waveform data of the waveform data group for reproducing the bass is shortened. In other words, it occurs when the value of the integer part does not change even if the waveform read address is incremented.

The loop top address memory 212 has a time division structure, and stores a plurality of loop top addresses LT corresponding to a plurality of waveform data groups. The loop top address LT from the loop top address memory 212
Is supplied to the port 1 of the selector 204.

The loop end address memory 213 has a time division structure and stores a plurality of loop end addresses LE corresponding to a plurality of waveform data groups. The loop end address LE from the loop end address memory 213
Is supplied to the B input terminal of the comparator 211.

Comparator 211 detects the end of the next waveform read address in the integer part (upper 16 bits) to detect the end of the repeat part.
Bit) and the loop end address LE from the loop end address memory 213 are constantly compared. Then, a signal indicating the comparison result is sent to the control input terminal S0 of the selector 204. As a result, when the integer part of the next waveform read address matches the loop end address LE, port 1 of the selector is selected. As a result, the loop top address LT and the value of zero (lower 16 bits) from the loop top address memory 212 are stored in the current address memory 205. On the other hand, when the integer part of the next waveform read address does not match the loop end address LE, port 2 of the selector 204 is selected. As a result, the next waveform read address is stored in the current address memory 205. With the above operation, the function of repeatedly reading the repeat portion of the waveform data group is achieved.

The envelope parameter memory 214 has a time-sharing configuration, and stores the current envelope target value, envelope added value, and loudness value. The contents of the envelope parameter memory 214 are read by the envelope generator 215. The current envelope memory 216 has a time division configuration, and stores a current envelope value which is an intermediate result of the envelope calculation.

The tone signal generating means of the present invention comprises an envelope generator 215 and a multiplier 217.

The envelope generator 215 adds the envelope addition value from the envelope parameter memory 214 to the current envelope value from the current envelope memory 216 in a time division manner. Then, the envelope generator 215 determines whether the calculation result has reached the envelope target value. If the operation result has not arrived, the operation result is stored in the current envelope memory 216 as a current envelope value, and is prepared for the next operation. This calculation result is further multiplied by a loudness value. Multiplication result is envelope level EL
Is output from the envelope generator 215. In this way, the envelope generator 215 generates an envelope that gradually approaches the envelope target value. The envelope level EL from the envelope generator 215 is supplied to the B input terminal of the multiplier 217.

[0064] Multiplier 217 multiplies the envelope level EL from the sampling data YD _j or YD _n and the envelope generator 215 from the decoding circuit 209. By this multiplication, a tone signal to which an envelope is added is generated. The tone signal from the multiplier 217 is supplied to the sequence adder 218.

The sequence adder 218 assigns all tone generation channels to at least one of the four tone color sequences, and adds tone signals within each tone color sequence. This sequence adder 21
The output of 8 is supplied to the digital control filter 219.

As the digital control filter 219, for example, a digital filter operating by 8 times oversampling can be used. The output of the digital control filter 219 is supplied to the D / A converter 2
20. The D / A converter 220 converts the oversampled digital signal into an analog signal for each timbre sequence described above. This analog signal is supplied to a speaker or an earphone through an amplifier (not shown).

As described above, according to the first embodiment, the specific waveform data W _j (PCM format “8000
When stored in the waveform memory 208 as H ") is read out from the waveform memory 208, it sampling data YD _n-1 obtained by the accumulation of up is discarded and accumulation is restarted from the sampling data YD _j You. As a result, it is possible to remove the accumulated error peculiar to the ADPCM or DPCM system. Further, it is possible to remove the accumulated error when the reading is not repeated.

When the musical tone waveform is sampled in a predetermined cycle, it is conceivable that the specific sampling data D _j (j = 0) does not exist at the sampling point P ₀ . In this case, the sampling start position may be slightly moved so as to obtain sampling data D _j (j = 0) whose content is zero.

The waveform memory 208 can store a plurality of waveform data groups corresponding to a plurality of timbres. Each waveform data group is composed of a particular waveform data W _j and a plurality of differential waveform data DerutaWD _n, specific sampling data D _j associated with the particular waveform data W _j of each waveform data group, each waveform data set Are preferably the same.

In the first embodiment, the specific waveform data W _j is stored in the waveform memory 2 specified by j = M = 128.
08 is stored. That is, the content of the waveform memory 208 specified by the loop top address LT is the specific waveform data _Wj . Alternatively, the difference waveform data ΔWD _n−1 is obtained by subtracting D _N−2 from the sampling data D _M−1 (where 1 ≦ M ≦ N−3), and j is M <j <N− 1 satisfied, reading means after reading the difference waveform data ΔWD _N-1, again, reads out the difference waveform data ΔWD _M. In this case, the value of “M” is the loop top address, and the value of “N” is the loop end address.

(Second Embodiment) The second embodiment is different from the first embodiment in that
1 shows a preferred embodiment of the tone signal generating device of the present invention.
The tone signal generator of the second embodiment generates a tone signal while interpolating sampling data. Book second
In the embodiment, the differential waveform data Δ
And WD _n the specific waveform data W _j of DPCM format is used. The contents of a particular sampling data D _j have a spread of a predetermined range.

The specific waveform data W _j and the difference waveform data Δ
As shown in FIG. 8A, WD _n is two-complement 16-bit data having a sign in the most significant bit (bit 15). The The specific waveform data W _j and the difference waveform data ΔWD _n, is produced in the same manner as described above with reference to FIG. In this case, if the contents of the sampling data are within a predetermined spread range, for example, within a range of ± 256, the following processing is performed. That is, if such sampling data (specific sampling data D _j ) is a positive number, the portion (bits 8 to 14) excluding the sign bit of the upper byte is set to “1” without changing the lower byte. On the other hand, when such sampling data (specific sampling data D _j ) is a negative number, the portion (bits 8 to 14) excluding the sign bit of the upper byte is cleared to “0” while leaving the lower byte as it is. This processing is performed data is a specific waveform data W _j of the PCM format.

The difference waveform data ΔWD _n (DPCM format) and the specific waveform data W _j (PCM format) obtained in the same manner as in the first embodiment are stored in a waveform memory 316 designated by an integer address described later. Is stored in

[0074] waveform memory 316 the waveform data group stored in, at the time of generation or regeneration of sampled data YD _j or YD _n, are handled as shown in FIG. 8 (B). That is, among the positive numbers, “0000H to 7EFFH (+0000)
H~ + 7EFFH)), "but it is treated as a differential waveform data ΔWD _n," 7F00H~7FFFH (+ 7F
00H + 7FFFH) "is treated as a particular waveform data W _j. Is the content of the specific waveform data W _j "7F
00H~7FFFH "in order to generate the sampling data YD _j, as shown in FIG. 8 (C) (X)," 0
000H to 00FFH (+ 0000H to + 00FF
H)). Similarly, among the negative numbers, "FFFFH to 8100H (-0001 to -7F00
H), "but are handled as difference waveform data ΔWD _n," 80FFH~8000H (-7F01H~-80
00H) "is treated as a particular waveform data W _j.
The contents of this particular waveform data W _j "80FFH~8
000H "in order to generate the sampling data YD _j, as shown in FIG. 8 (C) (Y)," FFFFH~
FF00H (-0001H to -100H) "PCM
Converted to data. In the parentheses, signed absolute values are represented in hexadecimal notation.

(1) Description of Decoding Circuit FIG. 6 is a block diagram showing a decoding circuit 317 (see FIG. 7) applied to the tone generator circuit of the tone signal generator of the present invention. This decoding circuit 317 corresponds to decoding means including interpolation means and temporary storage means. 6, the same reference numerals are given to the same or corresponding parts as the components of the decoding circuit shown in FIG.

In FIG. 6, delay latches 120, 1
Reference numerals 22, 123 and 124 are provided for pipeline control. These delay latches latch input data in synchronization with the channel clock CCK. The channel clock CCK is a clock that defines a time slot corresponding to each sounding channel, for example, as shown in FIG. The sounding channel is switched at the falling edge of the channel clock CCK. The sample clock SCK is the channel clock C
CK is a clock that generates a falling edge every time a time slot corresponding to all sounding channels is counted. Processing of each sampling data is performed in synchronization with the sample clock SCK.

The delay latch 120 is provided in the waveform memory 31
6 is stored in synchronization with the channel clock CCK. The waveform memory 316 corresponds to a waveform storage unit. The waveform data of the waveform data group from the delay latch 120 is supplied to the B input terminal of the comparator 100, the data converter 121, and the A input terminal of the adder 103.

The range value Z13 stored in the ROM or the register (not shown) is supplied to the comparator 100. The comparator 100 compares the contents of the waveform data of the waveform data group with the range value Z13. Range values Z13 has a spread in the same range as the contents of a particular waveform data W _j. That is,
Range value Z13 is 7F00H to 7FFFH and 80FFH
８8000H.

When the waveform data whose content is within the range of the range value Z13 is input to the comparator 100, the comparator 100
Detects the specific waveform data W _j and outputs the control signal C of “1”.
Output MP. When waveform data whose contents are out of the range of the range value Z13 are input to the comparator 100, the comparator 1
00 detects the difference waveform data DerutaWD _n, and outputs a control signal CMP of "0". This control signal CMP is supplied to the input terminal S of the selector 104.

The data converter 121 includes the delay latch 1
The waveform data of the waveform data group from 20 is converted by the method shown in FIG. That is, when the waveform data of the waveform data group is a positive number, the lower byte is left as it is and the upper byte is set to “00H”. In the case of a negative number, the upper byte is set to “FFH” while the lower byte remains unchanged.
As a result, the specific waveform data W _j, is restored to the PCM data to be the same as or close to the specific sampling data D _j (contents of a particular waveform data W _j having a value within the range of ± 256). The output of the data converter 121 is the selector 10
4 A input terminal. Difference waveform data ΔWD _n
Is converted to data with strange contents. However, such converted data is discarded in selector 104.

The expansion circuit 101 is optional. That is, in the second embodiment, the difference waveform data DerutaWD _n stored in the waveform memory 316 because it is DPCM format, the expansion circuit 101 is unnecessary. Waveform memory 31
When the difference waveform data DerutaWD _n of ADPCM format is stored in the 6, it may be inserted to decompression circuit 101 to the position shown in FIG. Decompression circuit 101 according to the second embodiment
Can be the same as those used in the first embodiment.

The first current sample memory 106 and the second current sample memory 128 have a time-division structure and correspond to the temporary storage means of the present invention. The first current sample memory 106 stores the sampling data YD _n−1 accumulated so far.

The sampling data YD _n-1 is supplied to the clear circuit 126. The clear circuit 126 outputs zero when a clear signal CLRB from a sound source circuit described later is activated. Otherwise, clear circuit 1
26 passes the sampling data YD _n-1 as it is. The output (zero or sampling data YD _n-1 ) of the clear circuit 126 is supplied to the second current sample memory 128 and the B input terminal of the adder 103. The clear signal CLRB is activated when reading of the waveform data of the waveform data group is started, that is, when a key-on event occurs, whereby the contents of the second current sample memory 128 are cleared to zero.

The second current sample memory 128
The sampling data YD _n−1 from the first current sample memory 106 is stored. The writing to the second current sample memory 128 is performed by the channel clock CCK unless a specific condition (described later) is satisfied.
It is performed in synchronization with. Therefore, the contents (YD _n-1 ) of the first current sample memory 106 are stored in the second current sample memory 128 after being delayed by one channel clock. The sampling data YD _n−1 from the second current sample memory 128 is supplied to the B input terminal of the subtractor 129 and the A input terminal of the adder 131.

[0085] Adder 103 specific waveform data W _j or difference waveform data DerutaWD _n from delay latch 120,
Clear circuit 1 from first current sample memory 106
26, the sampling data YD _n-1
Is added to. The output of the adder 103 is the sampling data YD _n. The function of accumulating the difference waveform data ΔWD _n is realized by the adder 103. The sampling data obtained from the adder 103 is supplied to the B input terminal of the selector 104.

[0086] The selector 104 is responsive to the control signal CMP from the comparator 100, selects one of the sampling data YD _n from the transformed data or the adder 103 from the data converter 121. More specifically, when the control signal CMP is “1”, the A input terminal side of the selector 104 is selected. Thereby, the data converter 12
1 is converted to sampling data YD _j
And the first current sample memory 106
Supplied to On the other hand, if the control signal CMP is “0”, the B input terminal side of the selector 104 is selected. Thus, data from the adder 103, sampling data YD _n of words resulting output is supplied to a first current sample memory 106.

The first current sample memory 106
Writing to is performed in synchronization with the channel clock CCK unless a specific condition (described later) is satisfied. Sampling data YD _n from the first current sample memory 106 is supplied to the clear circuit 126 and a subtracter 129.

The writing to the first and second current sample memories 106 and 128 is performed by the delay latch 1
24 and an AND gate 125. The delay latch 124 is configured by a D-type flip-flop having an inverted output. The delay latch 124 latches the coincidence signal CF in synchronization with the channel clock CCK, and supplies a signal from its inverted output terminal to the AND gate 125. Therefore, if the coincidence signal CF is “0”, the channel clock CCK is supplied to the first and second current sample memories 106 and 128 via the AND gate 125. As a result, the first current sample memory 106
With sampling data YD _n-1 is written into the second current sample memory 128 that has been held in,
The output of the selector 104 (YD _n or YD _j) is written in the first current sample memory 106. On the other hand, if the coincidence signal CF is "1", the channel clock CCK is masked by the AND gate 125, and writing to the first and second current sample memories 106 and 128 is not performed.

The coincidence signal CF is generated in a tone generator described later. This coincidence signal CF is set to "1" when a waveform read address having the same value in the integer part is output twice or more consecutively, and is cleared to "0" otherwise. Therefore, when the coincidence signal CF is set to "1", writing to the first and second current sample memories 106 and 128 is prohibited in the time slot one channel clock later.

The interpolation means of the present invention comprises a subtractor 129, a multiplier 130 and an adder 131. These are used to calculate an interpolated value between the sampling data YD _{j + 1} and YD _j or between the sampling data YD _{n + 1} and YD _n . The subtractor 129 calculates the contents of the first current sample memory 106 (YD _{j + 1} or YD _{n + 1} ).
To the contents of the second current sample memory 128 (YD
_j or YD _n ). Thus, a difference value between the two sampling data is calculated. This subtractor 12
The output of 9 is supplied to the B input terminal of the multiplier 130.

The input terminal A of the multiplier 130 is supplied with a decimal address (details will be described later) delayed by two channel clocks by the delay latches 122 and 123. The multiplier 130 multiplies the decimal address by the difference value from the subtractor 129. The output of the multiplier 130 forms an interpolated value and is supplied to the B input terminal of the adder 131. Second
Sampling data YD _n or YD _j from the current sample memory 128 is supplied to the A input terminal of the adder 131. Therefore, interpolation is performed by the adder 131 to generate interpolated sampling data YD. The output (YD) of the adder 131 is supplied to the clear circuit 132.

The clear circuit 132 outputs zero when a clear signal CLRB from the control flag latch 302 of the tone generator circuit described later is activated, and otherwise outputs the output of the adder 131 (interpolated sampling data Y
D) is passed as it is. The output of the clear circuit 132 is output to a multiplier 3 of a tone generator circuit to be described later to generate a tone signal as interpolated sampling data YD.
26. The clear signal CLRB, as described above, when the reading of differential waveform data DerutaWD _n or specific waveform data W _j is started, that is activated when the key-on event occurs, the indefinite interpolated sampling data output Is prevented.

[0093] As described above, the decoding circuit, since internal stores sampled data YD _n, unlike conventional, not always necessary to read the sampled data at two sampling points. That is, interpolation can be performed only by reading out the waveform data of one waveform data group from the waveform memory 316. Therefore, the circuit configuration is simplified. Further, for example, since the time of a time slot corresponding to one tone generation channel can be shortened, a tone signal generator capable of performing higher-speed processing can be achieved.

(2) Description of the tone generator circuit FIG. 7 is a block diagram of a second embodiment of the tone generator circuit applied to the present tone signal generator. In this sound source circuit,
The decoding circuit 317 described above is applied. Hereinafter, FIG.
The configuration and operation of the tone generator will be described in detail with reference to the block diagram shown in FIG.

The reading means of the present invention comprises:
F number accumulating means, bank memory 311, OR gate 3
12, adder 313, comparator 314 and selector 315
It consists of. The F-number generation unit includes a current step memory 303 and a clear circuit 306. The F number accumulating means includes a selector 304, a current address memory 305, an adder 307, a loop top address memory 308, a loop end address memory 309, and a comparator 310.

First, the format of the waveform read address for reading the waveform data of the waveform data group from the waveform memory 316 will be described with reference to FIG. The waveform read address is composed of 32-bit data as shown in FIG. The waveform read address has an integer part and a decimal part. Lower 16 bits of waveform read address (A
15-A0) is used as a decimal address (decimal part) and used as an interpolation address. In the second embodiment, four bits (A15-A12) are used as the interpolation address, but any value in the range of 1 to 16 bits can be used as needed.

Upper 16 waveform read addresses related to the integer part
Bit (A31-A16) and the bank address (B7-
B0) forms an address that actually specifies the position of the waveform memory 316. The waveform memory 316 is constituted by 256 banks each consisting of 64 Kbytes. The bank address is 1 out of 256 banks.
Used to select one bank. Integer address is used to specify the position of one of the differential waveform data DerutaWD _n or specific waveform data W _j in the bank.

[0098] The loop top address LT is composed of 16-bit data. This loop top address L
T corresponds to the integer part of the waveform read address. The loop end address LE is composed of 16-bit data. This loop end address LE corresponds to the integer part of the waveform read address. Loop top address LT
Is used to specify the start position of the repeat part of the waveform data group. The loop end address LE is used to specify the end position of the repeat part of the waveform data group.

In FIG. 7, the CPU and the tone generator circuit are 16
Bit data bus DB, 24-bit address bus A
B and the control data bus CNT. Latch 300 is a bidirectional tristate latch. This latch 300 is used for controlling data transmission and reception between the CPU and the tone generator circuit. The latch 300 takes in 16-bit data from the data bus DB and outputs it to the internal bus 350. Further, the latch 300 takes in 16-bit data from the internal bus 350 and outputs it to the CPU. Latch 300
Latch timing and transfer direction are determined by the timing generator 3
The control is performed based on the control signal CT sent from 01.

The timing generator 301 generates various control signals for controlling each part of the tone generator circuit, similarly to the timing generator 201 in the first embodiment. Specifically, the timing generator 301
Control signal CT for controlling the
4 and a timing signal TC for designating one tone generation channel. Each of these signals has properties similar to those of the first embodiment.

The control flag latch 302 has a time-division structure and stores data sent from the CPU. The clear signal CLRA output from a predetermined bit of the control flag latch 202 is supplied to a clear circuit 306. The clear signal CLRB output from the other bits is supplied to the clear circuits 126 and 132 (see FIG. 6).

The current step memory 303 has a time division structure and stores the F number. This current step memory 303 corresponds to the F number generation means of the present invention. The CPU generates an F number according to the key press information. The F number to be stored in the current step memory 303 is obtained from the CPU. The F number from the current step memory 303 is supplied to the clear circuit 306.

The clear circuit 306 includes a control flag latch 3
When the clear signal CLRA from 02 is activated, zero is output. Otherwise, the F number from the current step memory 303 is passed as it is. The output of the clear circuit 306 is supplied to the A input terminal of the adder 307. By the way, the clear signal CLRA is normally controlled to be active only during the first time slot when the reading of the waveform data of the waveform data group from the waveform memory 316 is started (see FIG. 9). Therefore, in the initial state, zero is supplied to the A input terminal of the adder 307. Therefore, the adder 307 outputs the content of the current address memory 305 as it is. Thus, in the initial state, the reading of the waveform data of the waveform data group is started from a specific waveform read address.

The selector 204 has four input ports (port 0, port 1, port 2 and port 3). These input ports are connected to control input terminals S0 and S1.
Is selected according to the control signal supplied to. Port 1
3, only 16-bit data is supplied. Therefore, when any one of these is selected, the lower 16
32 created by replacing bits with "0"
Bit data is output. On the other hand, port 0 has 32
Since the bit data is supplied, when this port 0 is selected, the input 32-bit data is output as it is. The table below shows the relationship between the control signals (S0, S1) and the selected input port.

[0105]

<S1> <S0> <Selected input port> 0 0 Port 0 (next waveform read address) 0 1 Port 1 (loop top address LT) 1 0 Port 2 (data sent from CPU) 1 1 Port 3 (data sent from CPU)

The ports 2 and 3 are used to select one waveform data group from a plurality of waveform data groups. That is, the CPU sends control data for generating the control signal SEL to the timing generator 301, and sets the start address (the integer part of the start address SA) of the waveform data group corresponding to the desired tone color on the data bus DB.
To the latch 300 via. Thereby, the control signal S
Port 0 is selected based on EL, and selector 304 outputs a waveform read address. The port 1 is used for returning from the loop end address LE of the repeat part of the waveform data group to the loop top address LT. When this port 1 is selected, the selector 304 outputs a 32-bit loop top address LT (integer address + decimal address (0)). The port 0 is used for the purpose other than the above, that is, for reading out the waveform data of the waveform data group while sequentially updating the waveform read address. When this port 0 is selected, the selector 304 outputs a 32-bit next waveform read address (integer address + decimal address). The data selected by the selector 304 is supplied to the current address memory 305.

The current address memory 305 has a time division structure, and stores the current waveform read address. The current waveform read address from the current address memory 305 is
It is supplied to the B input terminal of the adder 307.

Adder 307 adds the F number from clear circuit 306 to the current waveform read address. The result of this addition is used as the next waveform read address. The output of the adder 307 is supplied to the port 0 (A31
A0), the OR gate 312 (A15-A12), the B input terminal (A31-A16) of the adder 313, and the delay latch 122 (A15-A12) of the decoding circuit 317.

The interpolation address (A15-12) of the waveform read address from the adder 307 is supplied to the OR gate 312. The OR gate 312 performs a logical sum operation. Therefore, if the interpolation address is not zero, the OR gate 3
“1” is output from 12 and supplied to the A input terminal of the adder 313.

An adder 313 adds the output of the OR gate 312 to an integer address (A31-A16). The OR gate 312 and the adder 313 allow the integer address (A31-A3) when the interpolation address is not zero.
A16) is achieved with the function of incrementing ("+1"). As a result, a next waveform read address for interpolation can be obtained. The output of the adder 313 is
It is supplied to the A input terminal 14 and the B input terminal of the selector 315.

As will be described later, the loop end address memory 3
09 from the comparator 314
Is supplied to the B input terminal. Therefore, this comparator 314
Then, the integer part of the next waveform read address is compared with the loop end address LE. As a result of this comparison, if they match, “1” is output; otherwise, “0” is output.
Is output. The output of the comparator 314 is supplied to the input terminal S of the selector 315 as a control signal.

The selector 315 responds to a control signal from the comparator 314 by a loop top address LT (T31-T1) from a loop top address memory 308 described later.
6) or one of the integer parts of the next waveform read address from the adder 313 is selected. “1” is the selector 315
, The A input terminal of the selector 315 is selected to output the loop top address LT. On the other hand, when “0” is supplied to the input terminal S of the selector 315, the B input terminal of the selector 315 is selected to output the integer part of the next waveform read address. The output of the selector 315 is supplied to the waveform memory 316 as a waveform read address (A31-A16), and the A of the delay latch 318 and the comparator 319 are output.
It is supplied to the input terminal. With this configuration, the function of returning to the loop top address LT when the integer part of the next waveform read address matches the loop end address LE is achieved.

The delay latch 318 has a time division structure, and latches the bank address and the integer part of the next waveform read address from the selector 315 in synchronization with the channel clock CCK. This delay latch 318 is used to store the bank address and the integer part of the next waveform read address until one channel clock later. The output of the delay latch 318 is supplied to the B input terminal of the comparator 319.

The comparator 319 compares the output of the selector 315 with the output of the delay latch 318. Then, if they match, “1” is set; otherwise, “0” is set.
Is output. The output of the comparator 319 is the clear circuit 3
20.

The clear circuit 320 controls the control flag latch 3
It outputs zero when the clear signal CLRB from 02 is activated. Otherwise, the output of the comparator 319 is passed as it is. The output of the clear circuit 320 is supplied to the delay latch 124 of the decoding circuit 317 as a coincidence signal CF. This clear signal CLRB is
When the reading of the waveform data of the waveform data group is started, it is controlled to be active only during the first two time slots (see FIG. 9). Therefore, the match signal CF is forced to “0” during the first two time slots.
Thereby, malfunction of the tone generator circuit is avoided.

The waveform memory 316 corresponds to the waveform storage means of the present invention. The waveform memory 316, as described above, the difference waveform data DerutaWD _n or PCM in DPCM format
Storing specific waveform data W _j format. The contents of the waveform memory 316 are read according to an integer part of a waveform read address from the selector 315 and a bank address from a bank memory 311 described later. This waveform memory 20
The waveform data of the waveform data group read from 8 is supplied to the decoding circuit 317.

The sampling data YD from the decoding circuit 317 is supplied to the A input terminal of the multiplier 326.

The loop top address memory 308 has a time division structure, and stores each loop top address LT of a plurality of waveform data groups. Here, each of the plurality of waveform data groups corresponds to each tone color.
The loop top address LT from the loop top address memory 308 is stored in the current address memory 305 via the port 1 of the selector 304.

The loop end address memory 309 has a time-division structure, and stores each loop end address LE of a plurality of waveform data groups. The loop end address LE from the loop end address memory 309 is
The signal is supplied to the B input terminal of the comparator 314. Then, the loop end address LE is constantly compared with the data output from the adder 313.

The loop end address memory 309
Is supplied to the B input terminal of the comparator 310. Comparator 310 compares the integer part of the next waveform read address from adder 307 with the loop end address LE from loop end address memory 309. Then, if both match, "1" is output, otherwise "0" is output. The output of the comparator 310 is supplied to the control input terminal S0 of the selector 304. As a result, when the integer part of the next waveform read address matches the loop end address LE, the port 1 of the selector is selected, and a total of 32 bits of the loop top address LT (upper 16 bits) and zero (lower 16 bits) are set. It is stored in the current address memory 305. Otherwise, port 0 is selected, and the next waveform read address is stored in current address memory 305. As a result, a function of repeatedly reading the repeat portion of the waveform data group in the waveform memory 316 is achieved.

The bank memory 311 has a time-division structure.
A bank address for selecting one bank of the waveform memory 316 is stored. The bank address from the bank memory 311 is supplied to the waveform memory 316.

The configurations, operations, and functions of the envelope parameter memory 321 and the envelope generator 323 are the same as those of the envelope parameter memory 214 and the envelope generator 215 described in the first embodiment, respectively, and a description thereof will be omitted. The envelope level EL from the envelope generator 323 is
Supplied to

The tone signal generating means of the present invention comprises an envelope generator 323, delay latches 324 and 325, and a multiplier 326.

The delay latch 324 stores the envelope level EL from the envelope generator 323 in synchronization with the channel clock CCK. The envelope level EL delayed by one channel clock from the delay latch 324 is supplied to the delay latch 325. The delay latch 325 is a delay latch 3
24 from the channel clock C
Store in synchronization with CK. The envelope level delayed by two channel clocks from the delay latch 325 is supplied to the B input terminal of the multiplier 326. By the pipeline control achieved by these delay latches 324 and 325, sampling data YD obtained by delaying by two channel clocks,
The phase with the envelope data to be added to the sampling data YD is adjusted.

The multiplier 326 multiplies the sampling data YD from the decoding circuit 317 by data obtained by delaying the envelope level from the envelope generator 323 by two channel clocks. By this multiplication, a tone signal to which an envelope is added is generated. The output of the multiplier 326 is supplied to the sequence adder 327. The sequence adder 327, the digital control filter 328, and the D / A converter 329 have the same configurations as the sequence adder 218, the digital control filter 219, and the D / A converter 220 of the above-described first embodiment, respectively.
Their operations are the same.

Next, the operation of the second embodiment will be described with reference to FIG. 9 in order to deepen the understanding of the second embodiment. FIG. 9 shows a state in which the waveform data of the waveform data group stored in the waveform memory 316 is interpolated and the sampling data YD is output. The lower part of the figure shows the state of data change at the main points of the decoding circuit 317. Note that, for simplicity, the state of change is shown in decimal.

In FIG. 9, the points indicated by white circles are the difference waveform data ΔWD stored in the waveform memory 316.
_n , and the number surrounded by “<>” symbol indicates the range value Z13
Is shown. FIG. 9 shows how the waveform data of the waveform data group is stored at addresses 0 to 10. That is, D (j
_{= 0), ΔWD 1, ΔWD} 2, in response to the waveform data of the waveform data group that ..., "0" to address 0, "+200" to address 1, "+100" to address 2, ... are They are stored sequentially.

Further, a dotted line in FIG. 9 indicates a transition of the sampling data YD. The black circles on the dotted lines indicate the sampling data interpolated by decimal addresses, that is,
The sampling data YD obtained by the interpolation in the decoding circuit 317 is shown. FIG. 9 shows the F number =
The case of 0.75 is shown. Therefore, the integer addresses C31-C16 of the waveform read address are “0 → 1 → 2 → 3”.
→ 3 → 4 → 5 → 6 →... ”And decimal address FA
F is delayed by the two-stage delay latches 122 and 123, so that “undefined → undefined → 0 → 0.75 → 0.50
(Accumulated F-number 0.75 + 0.75 = fractional part of 1.50) → 0.25 (accumulated F-number 1.50+
0.75 = fraction of 2.25) →. The waveform data of the waveform data group read from the waveform memory 316 is delayed by one cycle by the one-stage delay latch 120 (indicated by ZD in FIG. 9).

The match signal CF is created in the tone generator circuit.
It is controlled so that it becomes "1" when the same waveform read address is output twice or more. This match signal CF is
Delayed by one channel clock by the delay latch 124. The control signal CMP indicating the comparison result is a signal output from the comparator 100 of the decoding circuit 317. When the control signal CMP is “1”, the output of the data converter 121 is selected by the selector 104 and supplied to the current sample memory 106.

In the waveform data of the waveform data group and the waveform data (ZD) of the delayed waveform data group, the data indicated by the symbol “<>” is the specific waveform in the PCM format stored in the waveform memory 316. This is the data _Wj . Other data is stored in the DPC stored in the waveform memory 316.
Which is the difference waveform data ΔWD _n of M format. With the adoption of the pipeline control method, a delay of two channel clocks is required from the output of the integer part of the waveform read address to the waveform memory 316 until the result (interpolated sampling data YD) is obtained.

As described above, according to the second embodiment, when the specific waveform data W _j is read from the waveform memory 316, the first current sample memory 106 and the second current sample memory 128 Are discarded, and the accumulation is restarted using the specific waveform data as an initial value. Therefore, ADPC
Accumulated errors unique to the M or DPCM scheme can be removed. Further, it is possible to suppress the accumulated error when the reading is not repeated.

Further, according to the second embodiment, even when the musical tone waveform is simply sampled at a predetermined period, the sampling data D within a predetermined spread range is obtained.
It is enough if _j is provided. Therefore, there is an advantage that creation of a waveform data group is facilitated.

Further, the interpolated sampling data YD
Is output, so that the tone signal generator can finely adjust the pitch. Further, unlike the related art, there is no need to always read the sampling data at two sampling points. That is, the next waveform read address of the waveform data group is read only when the value of the integer part of the accumulated F number (waveform read address) changes, so that the time slot corresponding to one sounding channel is shortened. it can. As a result, according to the tone signal generation device of the second embodiment, higher-speed processing can be achieved.

[0134]

As described above, according to the tone signal generating apparatus of the present invention, even when the tone signal is reproduced by the ADPCM method or the DPCM method, the waveform data of the waveform data is reproduced despite the simple circuit configuration. It is possible to provide a musical tone signal generator capable of suppressing the occurrence of an accumulated error due to repeated reading and also suppressing the accumulated error when the reading is not repeated.

[Brief description of the drawings]

FIG. 1 is a block diagram of a decoding circuit applied to a tone generator circuit according to a first embodiment of a tone signal generation device of the present invention.

FIG. 2 is a block diagram of a tone generator circuit according to the first embodiment of the tone signal generator of the present invention.

FIG. 3 is a diagram illustrating data used in the first embodiment of the musical tone signal generating device of the present invention.

FIG. 4 is a diagram for explaining a method of creating waveform data used in the first embodiment of the musical sound signal generator of the present invention.

FIG. 5 is a diagram showing an example of storing waveform data in a waveform memory according to the first embodiment of the tone signal generator of the present invention.

FIG. 6 is a block diagram of a decoding circuit applied to a tone generator circuit according to a second embodiment of the tone signal generation device of the present invention.

FIG. 7 is a block diagram of a tone generator circuit according to a second embodiment of the musical sound signal generator of the present invention.

FIG. 8 is a diagram illustrating data used in a second embodiment of the musical sound signal generator according to the present invention.

FIG. 9 is a diagram for explaining an example of storing waveform data in a waveform memory and a decoding operation in a second embodiment of the tone signal generator of the present invention.

FIG. 10 is a diagram for explaining a waveform read address used in a second embodiment of the musical sound signal generator of the present invention.

FIG. 11 is a timing chart showing the operation timing of the decoding circuit in the second embodiment of the musical sound signal generator of the present invention.

FIG. 12 is a diagram showing an example of storing waveform data in a waveform memory in an embodiment of a tone signal generating apparatus according to the present invention.

[Explanation of symbols]

100, 210, 211, 310, 314, 319
Comparator 101 Decompression circuit 102 Gate circuit 103, 131, 206, 307, 313 Adder 104, 204, 304, 315 Selector 105, 126, 132, 207, 320 Clear circuit 106, 128 Current sample memory 120, 122, 123, 124, 318, 324, 3
25 Delay latch 121 Data converter 125 AND gate 129 Subtractor 130, 217, 326 Multiplier 200, 300 Latch 201, 301 Timing generator 202, 302 Control flag latch 203, 303 Current step memory 205, 305 Current address memory 208, 316 Waveform memory 209, 317 Decoding circuit 212, 308 Loop top address memory 213, 309 Loop end address memory 214, 321 Envelope parameter memory 215, 323 Envelope generator 216, 322 Current envelope memory 218, 327 Sequence adder 219, 328 Digital control Filter 220, 329 D / A converter 311 Bank memory 312 OR gate

Claims (6)

(57) [Claims] (A) A musical sound waveform is sampled at a sampling point P._i(However
Sampling at i = 0,1,2, ..., N-1)
Data D obtained by performing_iChoose from
Specific sampling data D_j(However, 0 ≦ j ≦ N
Specific waveform data W created based on -1)_jAnd
Sampling data D_n(However, n = 1, 2,... N−
1 and sampling data D from n ≠ j)_n-1
Waveform data ΔWD obtained by subtracting_nAnd remember
(B) the specific waveform data W from the waveform storage means;_jOr difference
Separated waveform data ΔWD_n(C) temporary storage means, and (D) said read means.Data read by
By comparing with the specific waveform data W _j
Means for determining whether or not (E) The specific waveform data W _j Was read
Is determined, the specific waveform data W _j Based on
Sampling data YD _j Generate the sampling
Data YD _j Is stored in the temporary storage means, and the specific waveform data
W _j If it is determined that a value other than
The output data is converted to differential waveform data ΔWD _n As temporary
Storage in the storage means, and the sampling data YD _n Generate a
Decrypting means; (F) Obtained sampling data YD_jOr YD_n
And a tone signal generating means for generating a tone signal based on the following. 2. The reading means according to claim 1, wherein said reading means generates an F number for designating a pitch, and said reading means accumulates the F number from said F number generating means at a predetermined cycle. and and a F number accumulator means for generating a waveform reading address consisting of a fractional part, said read out means a specific waveform data W _j if the integer part of the waveform readout address is j, the integer of waveform read address parts read from the respective waveform storage means the difference waveform data DerutaWD _n for n, said decoding means includes interpolation means, interpolation means, between sampling data YD n _{+ 1} and YD _n, or sampled data YD _{j + 1} and performs interpolation according to the value of the fractional part of the waveform read address with the YD _j, than Te to obtain interpolated data, the tone signal generation means generates a musical tone signal based further on the interpolation data YD Features to The musical tone signal generator according to claim 1, wherein 3. The difference waveform data ΔWD _N−1 is obtained by subtracting D _N−2 from sampling data D _M−1 (1 ≦ M ≦ N−3), where j is M <J <N-
1 satisfied, the reading means after reading the difference waveform data ΔWD _N-1, again, the musical tone signal generating apparatus according to claim 1, characterized in that reading the difference waveform data ΔWD _M. 4. The specific waveform data W _j is stored at a position in the waveform storage means designated by j = M, and the reading means reads out the differential waveform data ΔWD _N-1 and then specifies again. 2. The tone signal generating apparatus according to claim 1, wherein waveform data W _j (j = M) is read. 5. A musical tone signal generating apparatus according to claim 1, wherein the content of the specific sampling data D _j is zero. Wherein said contents of a specific sampling data D _j is musical tone signal generating apparatus according to claim 1, characterized in that within a predetermined spread.