JPS58200297A - Envelope signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an envelope signal generating device that generates various envelope signals of musical tone signals used in electronic musical instruments as digital data, and in particular, it is capable of generating signals of a wide range of shapes with a small amount of data. This is how it was done.

FIG. 1 is a block diagram of an electronic musical instrument employing the frequency control device of the present invention. 1 is a keyboard section, 2 is an operation section consisting of a tone tablet switch, a vibrato effect on/off switch, a volume control for setting the depth of the vibrato effect, etc., and a 31d central processing unit (CPU), which is used in conbeaters, etc. 4 is a read/write storage device (random access memory, usually called RAM), and 6 is a read-only storage device (read-only memory, usually called ROM) in which the program that determines the operation of the CPU 3 is stored. 7 is a ROM that stores envelope parameters among the parameters for timbre synthesis; 6 is a frequency control device of the present invention for frequencies among the parameters for timbre synthesis; 66-165189, 1o is an envelope signal generator, 11 is a multiplier that multiplies envelope data representing the sine wave and the envelope signal, and 12 is a time-division multiplexed multiplier. A time slot control device that adds the results to a predetermined value or replaces them with the order of time division multiplexing; 13 is a time division multiplexed phase modulator;
14 is a digital-to-analog converter, and 15.16 is an aeroacoustic transducer.

Keyboard section 1. Operation unit 2, CPU3, RAM4, RO
M6, ROM6, ROM7, frequency control device 8° envelope signal generator 10i1: are coupled by a data bus, an address bus, and a control line. This method of connecting the Kf-ta bus, address bus, and control line is a well-known method for configuring minicomputers and microcomputers.As a data bus, 8 to 16 Standard usage) 1-,
Data is transmitted and received over this bus line 2 in a time-division manner, not in one direction, but in both directions.

A plurality of address buses, for example 16, are prepared, and normally the CPU 3 outputs the address code, and other parts receive and receive the address code. The control line is usually the memory φ request line (MREQ).

The I10 request line (IσRQ) and the lead line MREQ indicate that the memory is to be read and written, l0RQ indicates that the contents of the input/output device (Ilo) are to be retrieved, and the RD
indicates the timing to read data from the memory or Ilo, and WR indicates the timing to write data to the memory or Ilo.

An example of a microprocessor using such a control line is the microprocessor Z8o manufactured by Zilog.

Next, the operation of the electronic musical instrument shown in FIG. 1 will be described.

The keyboard section 1 is configured to divide a plurality of key switches into a plurality of groups, and to collectively send the ON-FF states of the key switches in the group to the data bus. For example, 6
For an octave keyboard, 6167, 10 groups of 6 keys (half octave) each and 1 with only 1 key.
Divide into 11 groups and assign one address code to each group. When an address code indicating one of the above groups arrives on the address line and l0RQ and RD are applied, the keyboard section 1 decodes the address code and selects the key switch 0N in the corresponding group. - Outputs 6-bit or 1-bit data indicating OFF to the data bus. These can be constructed using decoders, bus drivers and some gate circuits. Of the operation section 2, the tablet switch can have the same configuration as the keyboard section 1. For the volume setting status,
The voltage output from the volume is converted into a digital code by an analog-to-digital converter, and this is read out using the address code and control lines 10RQ and RD0.The CPU 3 reads the address of the ROM 5 corresponding to the code of the internal program counter. Read the instruction code from , decode it, and perform arithmetic operations.

7. - Performs operations such as logical operations, reading and writing data, and jumping instructions by changing the contents of the program counter. Procedures for these operations are written in the ROM 5. First, the CPU 3 reads a command for importing the data of the keyboard section 1 from the ROM 6, and reads the 0N-
A code indicating OFF is imported for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generator.

Next, the CPU 3 sequentially reads a group of instructions from the ROM 5 to read data from the operation section 2, decodes them, outputs the address code control number I0RQ and RD corresponding to the operation section 2, and outputs the address code control number I0RQ and RD corresponding to the operation section 2. The CPU 5 outputs codes representing the states of the switches and volume of the operating section 2, and reads them into the CPU 5. Then, the CPU 3 knows which timbre of musical tone signals should be synthesized.

Now that it is clear which tone with which frequency should be generated in which channel of the musical tone generator,
The CPU 3 receives an address code and a control signal MREQ that store frequency parameters of a desired tone from a ROM 6 that stores data regarding the frequency of each tone.
and RD, the desired frequency parameters are read out onto the data bus, taken into the CPUa, and written into the frequency control device 8. 11, the CPUa outputs the address code corresponding to the data register provided inside the frequency control device 8, and at the same time outputs l0RQ and WR, which is output on the data bus at the rising edge of the WR times signal. Data representing the frequency parameter is written to the data register marked -.

Next, tone parameters representing the contents of the tone to be output are read from the ROM 7 and written into a register inside the envelope generator 10. Next, when a sound output command is given to both the frequency control device 8 and the envelope generator 1o, the frequency control device 8 gives the jump number 1' to the sine wave generator 9, and the envelope signal generator 10 outputs the envelope data. occurs.

The sine wave data having a frequency of 9 pages proportional to the jump number output from the sine wave generator 9 and the envelope data are multiplied, and an envelope is given to the sine wave. The sine wave data and envelope data are generated by being time-division multiplexed, respectively. The time division multiplexing is, for example, 160 multiplexed, with 20 sine waves assigned to each channel, providing 8 channels. Normally, one musical tone is synthesized by synthesizing 20 sine waves. Therefore, as known from the Fourier series formula, 20 sine wave data are added. Data addition between time slots for this purpose is performed by the time slot exchanger 12. The time slot converter adds predetermined data from a sine wave data string modulated with envelope data that is time-division multiplexed into 160 time slots and reduces the number of time slots. This converter exchanges time slots like the time division multiplex converter disclosed in No. 67-202790. The time division multiplexing phase modulator 13 is manufactured by patent application No. 56
-152oaa "Digital musical tone modulation 1obe 1x device", which simultaneously performs multiple types of modulation by time division multiplexing. The output signal 1 from the time division multiplexing phase modulation device 13 is converted into an analog signal by the analog-to-digital converter 14, and then output from the electroacoustic converter 1516.

Although it is not shown in Fig. 1, the time slot converter 1
2 and the time-division multiplex phase modulation device 13 are connected to the CPU 3 via the address bus, data path, control line, and are connected to the CPU 3 in response to settings of tone and modulation effects made by the operation section 2. , time slot conversion and modulation conditions can be changed and set.

In FIG. 1, the envelope signal generator 1o outputs an address and a read command signal to the ROM so that desired data can be directly read.

FIG. 2 is a block diagram of an embodiment of the envelope signal generator of the present invention. In FIG. 2, reference numeral 7 denotes the above-mentioned parameter ROM, in which data 11, which is a compressed sample value of an envelope signal, is stored. 20 is a sample calculator, 21 is a tablet interface, 22 is a key interface, and 23 is an interpolation calculator.

Tone color codes are supplied to the tablet interface 21 and the parameter ROM 7 from the CPU shown in FIG. The upper three bits of the tone color code are applied to the upper address of the parameter ROM 7 as a code specifying one of the eight types of musical instruments, and the parameters of the specified instrument sound in the parameter ROM 7 are stored. Select an area.

The lower pit of the timbre code contains data indicating whether the timbre mode, tone, envelope shape is organ type, caviano type, etc., and is supplied to the sample generator 2o via the tablet interface 21. The tablet interface 21 includes a data latch, and the CPU 3 writes a tone code in the data latch, and then the sample arithmetic unit 2o reads it out at a necessary timing. The CPU 5 connects to the key interface 22,
Note octave data that represents the pitch of the sound you are trying to generate, and key 0 that represents whether the key for that pitch is ON or OFF.
NOFF signal is supplied and written to the internal latch. The sample calculator 2o reads out the data held by the tablet interface 21 and the key interface 22 according to internal predetermined timing, outputs address data to the parameter ROM 7 based on this data, and reads the contents. Reading, samples are generated by calculation and supplied to the interpolation calculator 23.

The interpolation calculator 23 performs an interpolation operation, for example, linear interpolation, on the middle of the envelope samples supplied one after another, and outputs smoothly changing envelope samples.

FIG. 3 shows examples of envelope signals and their sample values for explaining the sample calculation applied in the present invention. FIG. 3 shows the envelope to be generated in dB scale, with the maximum value being odB and the minimum value being -aodB. This curve's second black point (So
, Sl, S2. ) represents sample values sampled 13' at time intervals Ti=T and 2T. Based on such data,
If we take the difference value on the dB scale eaves of each sample value, we get Fig. 3 f.
) of (ΔEo, ΔE1.ΔE2...). FIG. 3(C) shows the sample values indicated by the black dots in FIG. 3(b) from the dB scale to the linear scale value (LEo).

LE LE . . .) and connects each point with a dotted straight line. In the present invention, the dB difference values ΔEo, ΔE1°ΔE2 shown in FIG.
．． ... is stored in the parameter ROM7. By sequentially reading and accumulating these dB difference values, the dB scale eaves envelope sample SSS...
Get...

oI 11 21 Next, the dB scale eaves envelope sample is subjected to logarithmic-linear transformation to obtain an envelope sample LEo on the linear scale.

LE LE ...... Obtain 01 I
21 The sampling period of this envelope sample is the above-mentioned 7i=T or 2T, and this period is larger than the period Ts of the musical tone sample that is finally output. Therefore, in order to successively generate envelope samples at times corresponding to the sample period of the musical tone, linear interpolation is performed between the two adjacent samples of OL 11 21 of LE LE LE ...... Then, an envelope sample having a shape as shown by the dotted line in FIG. 3(C) is obtained every period T8.

FIG. 4 is a block diagram of an embodiment of the present invention, which implements the calculation procedure described in FIG. In FIG. 4, the readout calculation control unit 25 outputs tone code, note octave data, key 0N
Reads the OFF data, stores the timbre code and the dB difference value ΔEi representing the envelope signal corresponding to the note octave data, sequentially generates the address AD according to these data, and outputs the read command signal RD. Then, the dB difference value ΔEi is read out from the parameter ROM 7 to the output terminal DO and stored in the latch 3o.

It is assumed that the latch 31 always contains zero.

The adder/subtractor 32 adds ΔE and zero to produce ΔE, which is supplied to one input of the adder/subtractor 32.

The output of the adder/subtractor 33 is stored in a register 34 and is also supplied to a logarithm-linear converter 35.

The other input of the adder/subtractor 33 is the output 161 of the register 34.
'' is supplied. The register 34 is a 1-word latch. The adder/subtractor 33 and the register 34 function as an accumulator that accumulates ΔE and generates and outputs the logarithm-to-linear converter. 35 is a read-only memory (ROM) that generates a linearized output code LEn for the input code Sn.If the input is 8 bits and the output is 16 bits, then 25
The 0-envelope interconnection sample LEnU, which becomes 6×16=4096 bits of ROM, is added to register 36 and delayed by one sample time.

Then, in the subtracter 37, ΔLE:LEn-L
En-1 is calculated. The output ΔLEn of the subtracter 37 is
The signal is shifted downward by a predetermined bit in the bit shift register 38 and supplied to one input of the adder/subtractor 39 . The output of the adder/subtractor 3'9 is delayed by a musical tone period T11 in a shift register 40 and is supplied to the other input of the adder/subtractor 39.

The bit shift register 38 is a kind of divider, and the bit shift register 38 is a kind of divider.
T, En-LEn, )/(Tn-, /T8)
(2) ('n=2, 3, 4,...) is executed.

If it is a power of 2, such as Tn,/T8=2P(3), shifting by P bits corresponds to the division η.

When δ is multiplied 2P times, ΔLEn=LEn-T, En-1 (n=2.3, 4.
...) (4). Therefore, LEn, to LE
Linear interpolation can be performed between n in time Tn-1. The interpolated envelope samples are LEn, , = (, li:n-1(LEn-LEn-
1)/(Tn-1/TB) (5)(i-1,...
..., Tn-4/T8).

Sn, LEn, ΔLEn, δ. The generation of is executed in the T4 cycle. Therefore, latch 30. register 34
, 36, the memory of the bit shift register 38 is updated by outputting one latch puff every T. from the read operation control section 25. The number of shift bits P of the bit shift register 38 is an output code ΔLEn that is shifted in multiple ways using a code representing P corresponding to T and /T output from the read operation control unit 25172,
ΔLEn/2. A signal is selected from ΔLEn/2, . . . and its output is latched. Since the contents of the register 40 are updated every cycle Ts, a latch pulse is supplied from the read operation control unit 25 every cycle T8.

Figure 5 shows simplified envelope data (ΔE, 1(i
=1.2,3. . . . is an example of N). The dB difference value ΔEi is placed at addresses 1 to N in the parameter ROM. The first address 0 is the release address R.
AD is stored. For the sake of simplicity, we will now explain the case where all T's (i=1.2, 3, . . . ) in FIG. 3(b) are equal. When the key 0NOFF signal input to the read calculation control unit 25 becomes '1' and the key is pressed,
First, the address AD indicating address 0 is output to the ROM 7, RD becomes 'o', and the release address RAD stored at address O is read out and stored in an internal register. Increase AD by 1 and 18
The page RD is set to 0'' and ΔE1 at address 1 is written to the latch 3o.Registers 30 and 34 are set as an initial state.

If zero is stored at 36.38.40, then 5
1=O, LE1=O, ΔLE1=o, δ1−o. Therefore, the output of the adder/subtractor 33 becomes 82=ΔE1. After this, calculations are performed according to the procedure described above.

Each time i advances by one, the address AD increases by one.

If you keep pressing the key, T will advance rapidly, but Ti2T1
Just before 6, increase the address AD by 7----
If the bit shift register is stopped, the bit shift register is set to zero, and the previous accumulated value is held, the envelope signal will remain I:LP01.

After that, when the key ONOFF signal becomes 60'' and it is known that the key has been turned off, ΔE1 corresponds to Ti2T15.
5 is read out to enter the decay process of 816 to S16. ”15 is the release start point, and the address where ΔE15 corresponding to this is stored is the release address RA.
Let it be D.

Before 'r,='r16, the key ONOFF signal is O''
Then, instead of incrementing address AD by 1, it is rewritten to RAD and output, and ΔE15 is read out. And after that, RAD+1, RAD+2.・・・・・・
and proceed with the release process.

If you do this, 1. No matter what time the key is turned off, the R
It can jump to AD, and after turning the key OFF, it immediately goes into release. Moreover, since the dB difference value is used,
The connections become smooth. For example, from S12 to “15
There is a discontinuity of about sdB when jumping from ΔE11 to Δ
E1. If the data jumps to 816 to S28 after S12, the data will be lowered by sdB compared to the original data and will be connected smoothly. Therefore, the connection before and after the flight does not cause discontinuity, no matter what the envelope shape. Furthermore, since the dB scale is on the eave, the dB change per unit time in the release process (dB scale eave change) is maintained. Therefore, the way you hear the time change in the decay of musical tones depends on when you turn off the key.
However, it will be the same thing.

The read operation control unit 25 that realizes the operations described above includes a register that controls the address AD, a register that stores the RAD, an arithmetic unit that increases, decreases, or changes the address,
Using the elemental circuits used in microconbeaters, such as the so-called ALu, ROM containing the program that controls these, and its decoder,
This can be achieved using a method similar to the order control of microcombinators.

FIG. 5 shows envelope data consisting of one type of dB difference value. This group of data can be stored separately for each different octave of the keyboard, or even separately for each different note within one octave. By having separate data like this, you can use the optimal envelope for each key in each range, allowing you to create excellent tones in any range. For this purpose, the note octave data shown in FIG. 4 is received, the address AD of the parameter ROM is changed according to this data, and the data in the same type of format is stored at addresses different from the addresses 0 to N in FIG. 6. You can also select.

In the data format shown in Figure 5, T is constant, but since the envelope generally changes rapidly at the rise of a musical tone, it is better to reduce T and increase the number of sample points. In order to be able to change the size of Ti depending on i, the data format should be as shown in Figure 6. In Figure 6, the release address RAD is at address 0, the slope data 5LOPE is at address 1, the point interval PI and point number PN are at address 2, and then ΔE, ~ΔE5 are at addresses 3 to 7.
is stored. Next, PI and PN, then ΔE
6 to ΔE14 are stored, and as the last group, RA
PI and PN are stored at address D, followed by ΔE16 to ΔE19. RAD is as described in Figure 5, 5LOP
E is data indicating the average increment of the rising part, and is ΔE1 to Δ
This is commonly added to E5. PI is a code indicating the interval Ti between sample points, and PN is a code indicating how many points the sample point interval Ti lasts. Third
For the envelope shown in Figure (b), the PI at address 2 specifies T, and the PN is 5. At number 8, P I it, T6 (
= 2T1), the PN is 9, and there are 22 pages. In the release address RAD, PI specifies T1 and PN is 6.

The procedure for reading out the parameter ROM in the data format shown in FIG. 6 in the embodiment shown in FIG. 4 will be explained. When the key is turned on, first the RAD at address 0 is stored in the RAD register. Next, read the slope data 5LOPE from the register 31.
(Fig. 4).

After that, PI and PN are read out and stored in the PI register and PN register. Next, ΔE1 is read from address 3 and stored in the register 30. Then, PN is subtracted by 1 and a bit shift code corresponding to Ti/T8 determined according to PI is supplied to the bit shift register 38. In this way, the envelope sample LEi1. during the section T1.
is calculated. Immediately before the end of T1, ΔE2 total 2 is written from address 4 and stored in the register 30, and PN is decremented by 1. In this way, when the address reaches address 7, PN=O, so it can be seen that PI and PN are stored next.

Therefore, address 8 is read and stored in the PI register and PN register. Thereafter, ΔE6 is read and stored in the output register 3o, and the register 31 is cleared. Furthermore, PN-1 is obtained, and a bit shift code corresponding to T6 (=2T1) is supplied to the bit shift register 38 according to the code of PI. RAD-
Since PN becomes zero when it reaches address 1, it can be seen that PI and PN are stored next. Therefore, by performing the same operation as at address 8, it can be determined that 0RAD is in the release process by comparing the data in the RAD register with the current address, so if ΔE19'' is read, then the same ΔE19 If the key continues to be ON, it can be stopped before the RAD address.If the key is turned OFF before the RAD, the contents of the AD register can be read out from the RA.
Just change it to D and start the release process.

If 5L6PE7”-Y is provided as shown in Figure 6, ΔE1
The data length of the rising edge portion of ~ΔE6 can be reduced, and the data can be compressed. 5LOPE data is shown in Figure 3(b)
represents the average slope of the envelope shape, and ΔE1 to ΔE6 are deviations from the slope. Even if a reverse slope, that is, negative slope data is provided to RAD during the release process, no.

The readout arithmetic control device 26 that reads out the parameter ROM in the data format shown in FIG.
It is equipped with an I register, a PN register, an AD register, a RAD register, etc., and is constructed using well-known circuits used in microcomputers, such as an ALU (arithmetic logic unit), a ROM that instructs these operating procedures, a program counter, and an instruction decoder. can do. Furthermore, it is also possible to construct the system using the microcomputer itself.

In the above explanation, the case where one type of envelope signal is generated has been explained. Since musical tones generally consist of multiple frequency components, multiple envelope signals are required. Furthermore, when producing not only a single melody but also multiple notes, a separate envelope signal is required for each note. To this end, in the embodiment of FIG.
0 is provided with a plurality of registers, an adder/subtracter 33.26, a subtracter 39, and a subtracter 37. Log-linear converter 36. The bit shift register 38 may be used in a time-division multiplexed manner. The registers 34, 36, and 40 may be shift registers having the same number of stages as the number of multiplexers. Read calculation control section 2
The operation procedure No. 6 may also be configured to perform time-division operation in accordance with the number of multiplexing operations.

FIG. 8 shows that the sample arithmetic unit of the envelope signal generator of the present invention explained in FIG. This is an embodiment in which the information is transmitted and the calculation procedure is executed under program control.

In FIG. 8, 6o is an address controller which receives the address code ADR from the CPU 3 in FIG.

Data DB, input/output command signal l0RQ, write command signal W
Upon receiving R, the address AD is sent to the parameter ROM 7, and data specified by the address AD is read from the parameter ROM 7 via the data bus RDB. A timing pulse generator (TPG) 61 generates a pulse signal necessary for the internal operation of page 26 from the master clock frequency. TPG61 is
It can be constructed using a clock oscillator, counter, and gate. Reference numeral 62 denotes a sequencer, which is a ROM that stores procedures for outputting addresses, write command signals, read command signals, etc., which will be described later, according to calculation procedures. 63 1-A command decoder inputs the command code output from the sequencer 52 and outputs an address code, an @include command, and a read command signal.

In the 54H1l-1z-E1 modulation register, the difference value of periodic fluctuation data that causes tremolo modulation is sent to the data bus R.
Reception is input from DB and stored at the rising edge of WRl. When OCl is n111, the contents are output to the A bus. The slope register 55 receives slope data from the data bus RDB and stores it at the rising edge of WR2. When OC2 is 1, 0AD1 output to the A bus contains an address code that specifies one of the 120 registers in the slope register 55. 56゛ is a dB difference register consisting of 120 data registers, AD12
One of them is specified by 77. Then, at the rising edge of WRa, the dB difference data is received from the data bus RDB and stored, and when OC3 is 1", the contents are output to the B bus. 57 is an envelope register consisting of 120 data registers. One of them is designated by the address code AD2, and data Sn supplied from the C bus is stored at the rising edge of WR4. When OC4 is 1'', envelope sample data Sn on the dB scale is output to the A bus. 58 is a logarithmic-linear converter which latches the data Sn supplied from the C bus at the rising edge of WRs, and converts it into a logarithmic-linear converted envelope sample LEn.

Outputs to the A bus when OC5 is °°1”.59 is
The envelope sample register consists of 120 registers, one of which is specified by the address code AD3, and the envelope sample LEn supplied from the C bus is sent to WRe.
It is latched at the rising edge of OC6, and is output to the B bus when OC6 is 1". 6o is a working register (WREG) and is output to the B bus.
Consists of word registers, address code AD
One of them is selected by 0C7, and the data supplied from the C bus is stored internally by 0C7.
When A is 1'', output the contents to A path, 0C7B
When is "1", the contents are output to the B path. 61
calculates each input data of the A bus and B bus with an adder/subtracter and outputs it to the C bus.

The addition/subtraction switching selection is specified by the instruction decoder 63.

62-stroke V Store ΔEn in the differential envelope data register. It consists of 20 registers, one of which is selected by address code AD4 and is WRl.

ΔLEn output from the adder/subtractor 61 at the rising edge of is stored internally. 63 is the difference envelope data register and 120
It consists of data registers, one of which is designated by address data AD5, and input data is stored when WRa rises and is output when OC8 is n1u. 64 is designated by a shift gate IFT signal for shifting input data by a predetermined number of bits. The shifted signal 29 is data δ. corresponds to 66 is an adder/subtracter for accumulation. A register 66 receives and stores the output of the adder/subtractor 65, and is made up of 120 registers. One of them is designated by address data AD5, stored at the rising edge of WRe, and output when OC9 is II 111.

In the embodiment shown in FIG. 8, 2.2.times.2 is generated so that 20 envelope signals corresponding to the 20th frequency component per note are simultaneously generated for 8 channels, that is, 8 notes.

X8=160 160 time division multiplex operations are performed. The number of the 8 tones is represented by -1 to 8, and the number of the 20 tones is represented by I=1 to 2o.

The calculation procedure will be explained below. Instead of the subscript n used earlier, i is used here.

WREG 4- SLOPE (K, I) + ΔEi (
K, I) (6) WREG 4- WREG
+ 3, (K, I) (force S. (K, I
) ←WREG +ΔAM, (K, I
) (a) 1+1 LOG/LIN 4- WREG +ΔAM,
(K, I) (9) ΔLE. 1(K,I)←L5
G/LIN -LE, (K, I) (1o) 30 pages LE,, +, I (K, I) ← L / LIN
(11)1 By equation (6), S LOP E
(K, I) is read from the slope register 56, dB
Difference data ΔEi (K, I) is stored in dB difference register 5
6 is read out, added, and stored in the working register 6o. Next, as in equation (7), working register 6o
and the contents of the envelope register 67 Si(K,
I) are read out, added, and stored in the working register 60. Next, according to equation (8), the contents of the working register 60 and the contents ΔA of the tremolo modulation register 54 are determined.
M(K, I) is read out and added to obtain a new envelope register Si+1(K, I), which is stored in the envelope register 67 at address (K, I). Also, the same answer is written to the input latch of the logarithmic-linear converter 68 using equation (9). Next, according to equation (1q), the output of the logarithm-linear converter 68 and the envelope sample register 69
Read the output of , take the difference ΔLE, , (K, I), and store it at address (I) of the differential envelope data register 62.
Get into it. Next, according to equation (11), the output of the logarithm-linear converter 68, LEi+131 ・' ゛(K, I), is converted to (K, I) of the envelope sample register 69.
Write in the address. In the above description and equations (6)-(11), (K, I) points to one of the 8×20-160 word registers. i [is a positive integer and is a sample number that increases sequentially starting from 1 after detecting the key ON.

To execute the above calculation procedure, the address codes AD1 to AD4. Write command signals WR4 to 7, 10. Read command signals QC1~e, 7A, 7B (6)~(1
1) The equations should be output in the order of the equations0 (6) to (11), first with =1, then ■=1 to
2o, then =2. . . . , 8, then in - order, and then back to the beginning, so that i can be incremented one by one.

The differential envelope data register 62' has ■=1 to 2°14
′ consists of 2o word registers. Therefore, ■=1
~20 new ΔLEi+1(K, ■) is found, then this new ΔLEi, (K, I)Fi
, , the corresponding 2 inside the differential envelope data register 63
Transferred to register at address 0. The speed of this transfer must match the read speed of the differential envelope data register 63, that is, the update speed of the address code ADs.
Don't give up. Moreover, this speed is finally determined by the envelope data LEi2. corresponds to the period in which is output. The address ADs of the differential envelope data register 63 is always 160.
ΔLE, (K, I
) are output one after another according to (K, I) determined by address code AD5. Shift gate 6 constant beep!・Shift by the number l−, δ, (K, I
) is output and accumulated by the adder/subtractor 66 and the register 66.

FIG. 9 shows an example of data in the parameter ROM 7 used in the embodiment shown in FIG. Address 0 indicates the basic nature of the sound, such as percussive or normal envelope. MOD E:
It consists of a harmonic limit code that specifies the maximum number of envelopes to output out of the 20 envelopes of ■=1 to 20. Address 1 is the release address mentioned above. Addresses 2 to 21 are a table of data that specifies the number of envelope data to be used in each time slot corresponding to the 20 envelope signals. Addresses 22 to 41 are 20 envelope data tables. This is the slope data. Address 42 is the point interval PI and point number PN of the rising part. 43 to 62.63
~82,...

Addresses 103 to 122 have 20 PNN groups d each.
B is differential data. These are the PI and PN at address 12323. 124-143, 144-163, 16
4～183,...

are 20 dB difference data each. From then on, the arrangement is the same. Multiple sets of parameters with such a configuration are prepared. Each set is provided corresponding to a specific range of a specific tone.

Address code, data, control signals IORQ, W from address controller 50KCPU3 (FIG. 1) in FIG.
When R is supplied, and tone code, note octave data, and key ONOFF data are supplied, based on these data, it corresponds to the note octave in the specified tone area in Para 34 Vane meter ROM. ．． You can find the start address of the area containing the parameter set. (This start address can also be given directly from the CPU 3.) This start address is supplied to the parameter ROM via the address bus AD, and the data is read from RDB.
It is stored in a register inside the address controller 60. The address is advanced one after another and the data from addresses 0 to 21 are taken in. Next, the slope data is read from addresses 22 to 41 and stored in the slope data register 56. Next, I and PN at address 42 are stored in a predetermined register in the address controller 6o.

Next, the dB difference data ΔE1(K,
I), is stored in the dB difference register 56.

Since the above data has been read, the calculations of equations (6) to (11) can be performed using the procedure described above. Since the mode, harmonic limit code, release address, time slot/envelope number table, PI, PM, etc. are necessary for each channel, registers for storing them are provided inside the address controller.

In FIG. 9, the harmonic limit code M is a number between 1 and 2 degrees, and specifies that zero is output as an envelope sample that exceeds this number M and is 20 or less. For this, (M+1
) to 20, by applying a large negative number as ΔEi, ΔLE is set to a large negative number, and by keeping the shift amount small, δ is set to a large negative number. By doing this, the cumulative value in the adder/subtractor 65 becomes a negative number. On the other hand, in general, envelope samples may typically be zero or positive values. Therefore, when the calculation result of the adder/subtractor 66 is negative, a control line 68 is provided so as to detect this and forcibly output zero.

In this way, unnecessary envelope samples can be reduced to zero.

In FIG. 9, the time slot/envelope number table is such that the dB difference data ΔEi (K, I) of the envelope of any time slot of p5 time slots with I=1 to 2o is converted to other data Δ with different I. It provides a correspondence table between I and 1' when substituting (K, I') (I' and).

By doing this, ΔEi (K, I) becomes I
It is not necessary to have all of -1 to 20, but prepare ■ = 1 to 10, and for l-11 to 2o, I- = 1 to 10.
You can select an appropriate one or one with a similar shape. For this purpose, in the word calculation of l-11 to 20, an address conversion operation such as outputting the address where ΔEi (K, I) corresponding to ■=1 to 10 is stored may be performed. Such address conversion is similar to the operation of relative addresses and indirect addresses on microcomputers and minicomputers. This can be achieved by creating.

The data supplied to the tremolo variable W1 register 64 in FIG.
If you read what is stored in ``2.''

As described above, by using the sample arithmetic unit with the microprocessor structure shown in FIG. 8, the 0(6) The procedure of equations (11) to (11) is one example, and various embodiments can be constructed by omitting some of the 37·, -1 data or changing the procedure.

Address controller 50. Timing pulse generator 51. Sequencer 52. Since the instruction decoder 53 is already known in various microprocessors, its details will be omitted.

In the above explanation, when the key remains in the ON state, a certain envelope sample is continued to be output before the release address RAD, but when it reaches RAD-1, it is skipped to an even earlier address after that. For example, referring to FIG. 3(b), 86 to S1. The address may be manipulated repeatedly. Also, 86~
S1. Instead of repeating , it may be possible to jump to an appropriate address from S1 to S6 to S16. Such address manipulation can be realized by adding or subtracting a random code output from a pseudo-random sequence generator to or from an address.

As a type of release process, musical instruments require 38 steps such as applying a damper or applying a high-speed meeting. When such a request occurs, by setting the dB difference data to a large negative value, rapid attenuation can be achieved through accumulation. For this, ΔF
All you have to do is create a procedure to write a predetermined value as .

FIG. 10 is a diagram showing the timing of the embodiment of FIG. 8. Figure 10 (8) This shows the sample arrangement of a sine wave waveform, and the sample period of one sine wave waveform is 20μ.
It is B. FIG. 10(B) is an enlarged view of 20 μs, in which there are 8×160 time slots and 160 samples. Each sample is
It is processed in 125ns increments. Channel 1 (CHl
) has 20 salepules. The same applies to CH2-8. On the other hand, in FIG. 10 (q is the timing at which the four calculations of the differential envelope samples ΔLE, . In CH31,
A manual calculation of ΔLEi (1, I) for channel 1 is performed, and calculations for the corresponding channels are performed in the following order. 1
The calculation of ΔLE for each channel is repeated at a cycle of 6oX8=1280Ils (1,25m5). FIG. 10 shows the inside of each channel time slot ()CH8, and as an example, CH31 is enlarged. CH31
In the processing time slot P, the unit is 6 μB.
There are TSs from 1 to 32. PTS(I), I=1-20
Here are the difference envelope samples ΔLE corresponding to 20 spectra (sine waveforms) in channel 1.

Calculate (K, I). And the first 2 of PTS21
．． At 5 μs, 20 calculated ΔLEi(K.

■) The value is transferred to the differential envelope register 63 (Fig. 8) in 125 ng increments as shown in Fig. 10 (j). The timing of this transfer differs for CH31 to CH8. For example, in CH35, the second half of PST24 It is executed in the 10th
(El is an i: enlarged view of the contents of each processing time slot PT31-2o. PT81-20 are instruction time slots) IT81-6, respectively.

Each is 830ns long. In these instruction time slots (ITS), the instructions in formulas (6) to (11) are executed. Between 2181 and 200, calculations centering on the adder/subtractor 61 are performed in the embodiment of FIG. Between PT821 and PT32, ΔAMi in FIG.
(K, I), S LOP E (K, I).

A new write of data centering on ΔE, (K, I) is performed via the data bus DB. In the shape of the envelope shown in Figure 3, in the case of percussive type, when attenuating with an exponential function, ΔE In the attenuation process, it is sufficient to have a constant value regardless of i, so
It is sufficient to have one kind of ΔE as a representative value in the attenuation process, and a large amount of data compression can be achieved.

As a conversion characteristic of the logarithmic-linear converter 35 in FIG. 4, when the input Sn is small, for example, for an input code corresponding to -80 dB or less, zero is output as LEn.
:Uni, ROM may be configured.

According to the present invention, the following excellent effects can be obtained.

41,,,,.

(1) Since envelope samples are stored as digital data and interpolation calculations are performed based on this, smoothly continuous envelope signal data can be obtained based on sparse envelope samples.

(2) Since the envelope samples are stored as differential PCM data and accumulated, it is not appropriate to simply read out the envelope samples continuously. Even at the point of change, a smooth envelope change can be created.

(3) Since the differential PCM data is taken on the dB display scale of the envelope sample, the exponential decay process
This can be achieved by adding and subtracting B differences and does not require a multiplier.

Although the envelope sample Si on the (+) dB scale is log-linearly transformed, the R is smaller than when using a multiplier.
Only OM is required, and then linear interpolation is performed, so that the time change of musical tones can be made into a polygonal, smooth and non-discontinuous form.

[Brief explanation of the drawing]

42 Page Figure 1 is a block diagram of an electronic musical instrument adopting the present invention, Figure 2 is a block diagram of an electronic musical instrument adopting the present invention.
3 is a block diagram showing the basic configuration of the present invention, FIG. 3 is a diagram showing the envelope signal waveform handled by the envelope signal generator of the present invention, FIG. 4 is a block diagram of the main part of the embodiment of the present invention, 6, FIG. 6 is a diagram showing an example of the data format used in the present invention, FIG. 7 is a diagram showing an address calculation register, FIG. 8 is a block diagram of another embodiment of the present invention, and FIG. is a diagram showing an example of the format of the data, and FIG. 10 is a diagram showing the timing chart. 7...Memory unit, 20...Sample calculation unit, 23...Interpolation calculator〇Name of agent Patent attorney Toshio Nakao and 1 other person No. 6
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Claims (1)

[Scope of Claims] (1) A digital storage device that stores envelope signals of musical tones, a sample calculator that sequentially reads envelope signals from the storage device and generates envelope samples, and the envelope sample and an interpolation calculator that performs an interpolation calculation between adjacent ones of the samples. An envelope signal generating device, wherein the arithmetic unit sequentially accumulates the logarithmic difference values to generate logarithmized envelope samples, and further performs logarithmic-linear conversion on the accumulated values to generate envelope samples. (2. In the statement of claim 1, the storage device stores slope data corresponding to the slope in at least one of the rising and falling sections of the envelope signal, and the sample arithmetic unit stores the slope data corresponding to the slope in at least one of the rising and falling sections of the envelope signal. An envelope signal generator capable of generating a steep envelope signal by adding the slope value specified by the data to the envelope sample in the rising and falling sections of the chamber 2. (3) Claim 1 provides an envelope signal generating device in which the generation cycle of envelope samples is made variable and the interpolation calculation interval is made variable in accordance with the generation cycle. (4) Claim 1 (5) The envelope signal generating device according to claim 1, wherein reading of digital data stored in a memory device is made to jump to the address of the release process when the key is turned off. (5) The description of claim 1. An envelope signal generating device characterized in that the data Ω address changes randomly when the key is kept ON for a long time when reading the digital data stored in the memory device. (6) An envelope signal generating device according to claim 1, wherein the sample computing unit and the interpolation computing unit are time-division multiplexed to generate a plurality of envelope curves.