JP2722460B2 - Music synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention]   The present invention relates to a tone synthesizer, and in particular, synthesizes a tone.
It relates to the architecture technology of the sound source section. [Background of the Invention]   Conventional typical music synthesis systems use general-purpose microcontrollers.
The performance of the performance input device is
Controls such as detecting the state and transferring the required data to the sound source
Function, and the sound source section is based on data transferred from the CPU.
It has a synthesis function for synthesizing musical sounds. Generally, sound source
The parameters required for waveform generation (envelope and position)
Tone control signal generator for generating tone control signals such as phase data)
Performance of musical tone waveform using parameters from generator and generator
It has a waveform generator for performing the calculation. The sound waveform is audible
Considering the frequency range, at least 40KH_zDegree of sa
Requires sampling speed. Also polyphonic
In the case of Ip, one musical sound waveform at twice the polyphonic speed
Sample must be generated. For example, 8 sound po
For phononics, the sampling rate per note is about
320KH_z, Which is about 30 μsec in terms of time. Further
If one sound is synthesized from multiple components,
Each component must be calculated in microseconds. About this
Is not possible with today's general-purpose circuit technology
It is. For this reason, in the prior art, the waveform generation circuit
And a circuit that generates the tone control signal.
It is realized by a plurality of individual memories and individual dedicated circuits. An example
For example, for envelope generation,
Envelope level (target value), rate (slope), etc.
Individual memory for storing the envelope data of
Data provided from the CPU as rope data change data
Data for each memory and envelope data
Dedicated circuit for changing by envelope change data,
Envelope using the modified envelope data
Dedicated circuit for updating, see the updated envelope
Check the update condition of the envelope step by comparing with the standard value.
A dedicated circuit for the output is required. Generally this
These dedicated circuits operate in parallel or in pipeline form
This achieves the required speed. But
However, many dedicated internal memories and dedicated circuits are required
Traditional architectures necessarily come at the expense of circuit size
Holds. And to enhance the sound synthesis function
Is a general issue for musical sound synthesizers,
Increasing the scale is inevitable.   An example of a conventional tone synthesizer is shown in JP-B-60-42955.
Have been. In the device of this publication, a tone control signal generation unit
Dedicated to remember the length of each envelope step
Memory, dedicated for measuring step length completion
Stores the envelope plate data of the circuit and each step
Dedicated memory and envelope plate data
A dedicated circuit and envelope for calculating the envelope
Dedicated memory to store the phase data rate
Dedicated memory for accumulating the phase data rate and phase data
Dedicated circuit for calculating data and storing phase data
The dedicated circuit is composed of
They operate in parallel at the same time. One pronunciation channel
The time per file is 1 microsecond.   In the future, the need for more powerful music synthesis
Above, it is necessary to solve the problem of increasing the circuit scale,
In that case, the problem of processing speed must be overcome.
No. [Object of the invention]   Therefore, the object of the present invention is to
A new arche that can be small and has no speed issues
An object of the present invention is to provide a musical sound synthesizer having a texture. [The gist of the invention]   According to the present invention, the performance state of the performance input device (1, 2) is changed.
Controlled by the CPU (3) to monitor
Therefore, the memory (7) and the upper
Write data transferred from the CPU to the above memory.
An interface buffer (11) and the above memory
Tone control signal generator that generates tone control signals using
Generated by the circuit (12) and the tone control signal generation circuit.
To generate a musical tone waveform in accordance with the generated musical tone control signal
A tone synthesizer comprising a shaping circuit (15); (A) The operation speed of the tone control signal generation circuit is
It is slower than the operation speed of the shape generation circuit, (B) The tone control signal generation circuit and the waveform generation circuit
A speed adjustment circuit is provided between the
The above musical tone given at a low speed cycle from the sound control signal generation circuit
The control signal is transmitted at high speed in synchronization with the operation of the waveform generation circuit.
To the tone control signal of the (C) The tone control signal generation circuit performs a common operation
Circuit (308) and the operation of the shared arithmetic circuit, and
And read from the above memory as an operation buffer
/ Control circuit for controlling write access (301 to 30
5,307), and the common operation circuit is
Under the control of the control circuit, a series of operation sequences (20A
Figure) is repeatedly executed and included in the operation sequence.
In each operation step, each different operation is executed sequentially, and
At a certain step (14P, 0). Generates the above tone control signal
Configured to power The above speed adjustment circuit, (B1) At least higher than the operation speed of the waveform generation circuit
A pulse that generates an alternating pulse signal at the corresponding cycle
A signal generation circuit; (B2) the tone generated by the tone control signal generation circuit
A temporary storage memory for temporarily storing control signals, (B3) The tone control signal from the tone control signal generation circuit is
Accept and write this to the temporary storage memory
Circuit and (B4) when the pulse signal is in the first state,
Writing of the tone control signal by the
When the pulse signal is in the second state, the waveform shaping circuit
Reading of the tone control signal by the
Is provided (claim 1)
Section).   In one configuration example, the common operation circuit means
Is the generation of the envelope to be sent to the waveform generation circuit means.
for, (A) Enhancement using envelope plate change data (ERCj)
Change of Numbello plate (ERij (s)), (B) Envelope with modified envelope plate
Calculation of loop values, (C) Envelope based on envelope level change data (ELCj)
Change of the standard value (ELij (s)), (D) Whether the calculated envelope value has reached the target value
Determination of whether or not (E) When the calculated envelope value reaches the target value
Update of the envelope step (S) in case of   (2).   In one configuration example, the common operation circuit means
Generates a composite key code to be sent to the waveform generation circuit means.
for, (A) Pitch envelope data (ERpj (s), (EL
pj (s)) to calculate the pitch envelope (PEj), (B) Calculated pitching rope and key code (KC
j) Calculation of the composite key code with (3).   In one configuration example, the interface circuit means
The tone control signal generating circuit means and the waveform generating circuit means
Is formed on the sound source circuit chip means, and the memory
The memory is formed on the sound source circuit chip means, and the memory
External RAM provided outside the source circuit chip means
(Section 4).   In one configuration example, the waveform generation circuit means includes a plurality of
Multiple tone waveforms for each channel in the pronunciation channel
Is generated by the time-sharing operation of the module
Output from the musical tone control signal generation circuit means.
Key codes and envelopes for each channel and module
(Section 5).   In one configuration example, the arithmetic circuit means includes a series of operation sequences.
Sequence (Fig. 20A) by dividing the number of channels x the number of modules
Repeat all times for all channels on all channels
Sample envelope and keycode for the module
Is generated (Section 6).   Further, according to the present invention, the performance of the performance input device (1, 2) is improved.
The performance is controlled by the CPU (3) that monitors the playing state.
Memory for synthesizing musical sounds according to the playing state
(7) and transferring the data transferred from the CPU to the memory
Interface circuit (11) that writes to
A musical tone control signal is generated using the arithmetic buffer.
A sound control signal generation circuit (12);
Tone waveform according to the tone control signal generated by the path
Tone synthesizer provided with a waveform generation circuit (15) for generating a tone
At (A) The operation speed of the tone control signal generation circuit is
It is slower than the operation speed of the shape generation circuit, (B) The tone control signal generation circuit and the waveform generation circuit
A speed adjustment circuit is provided between the
The above-mentioned musical tone given at a low speed cycle from the musical tone control signal generation circuit.
A high-speed sound control signal synchronized with the operation of the waveform generation circuit
Is converted into a periodic tone control signal, (C) The tone control signal generation circuit includes:   A common operation circuit (308),   The operation of the common operation circuit and the operation
Read / write access to the memory
Control circuits (301 to 305, 307) for controlling the
And   The control circuit comprises a counter (303), an operation address
The generation circuit (301) and the operation control signal generation circuit (30
5,307,304), (A) The counter counts a predetermined basic clock (CKQ)
Counts to generate a counter output signal, (B) the operation control signal generating circuit outputs the signal from the counter;
At least part of the counter output signal of
Operation flag signal (F ', EO, MO 0, AE) from the arithmetic circuit
Generates an operation control signal, (C) The operation address generation circuit is configured to operate the counter
Of the counter output signal from the road and the above operation control
When a part of the operation control signal from the signal generation circuit is received,
Generates address signals (BA0 to BA11) for the memory, (D) the operation circuit is provided from the operation control signal generation circuit
Receiving at least a part of the control signal
Generating and outputting the tone control signal by sequentially executing;   The above speed adjustment circuit, (B1) At least higher than the operation speed of the waveform generation circuit
Generate alternating pulse signals at the corresponding predetermined cycle
A pulse signal generation circuit; (B2) the tone generated by the tone control signal generation circuit
A temporary storage memory for temporarily storing control signals, (B3) The tone control signal from the tone control signal generation circuit is
Accept and write this to the temporary storage memory
Circuit and (B4) When the pulse signal is in the first state, the write
Writing of the tone control signal by the
When the pulse signal is in the second state, the waveform shaping circuit
Reading of the tone control signal by the
A musical tone synthesizer is provided (Section 7).   In one configuration example, the musical tone control signal generation circuit means
(12) generates a series of operation sequences (Fig. 20A).
It is to repeat as many times as the number of channels x the number of modules
Musical sounds for all modules of all pronunciation channels
Generate control signal samples in a time-sharing manner,   The waveform generating circuit means includes a tone waveform of each sounding channel.
From the tone control signal generation circuit means.
Based on the tone control signal of each module belonging to the channel,
Time-division generation (section 8).   In one configuration example, the counter means includes: (A) The first counter output part representing the module number is
First counter means (311 in FIG. 18) which is generated,   A second counter output portion representing a sounding channel number
Second counter means (310) for generating   Operation step number in the above series of operation sequence
A third counter for generating a third counter output portion representing
Data means (309)   (Section 9).   Here, the module from the first and second counter means is provided.
The first counter output part (BC8-BC1
1) and the second counter output part representing the channel number
(BC5-BC7) is the address generation circuit means for operation (30
1) Input the relevant module and channel data
For address generation for reading / writing to the above memory
Used (Section 10). In addition, the third counter means
A third counter output part representing the operation step numbers
(BC0 to BC4) are the operation control signal generation circuit means (305)
Of the operation control signal in the operation step
Used for generation (Section 11).   In one configuration example, the arithmetic circuit means performs a series of operations.
In the first operation step of the sequence (Fig. 20A)
Generates the operation flag signal and generates the operation control signal
The road means is configured to perform a second operation after the first operation step.
This second operation is performed by using the operation flag signal in a step.
Generating an operation control signal for the step;
The means includes an operation control signal for the second operation step.
Therefore, the calculation operation of this second operation step is executed,
The operation control signal for the second operation step precedes.
The state of the operation flag generated in the first operation step
Occurs in different patterns depending on the state,
The arithmetic operation in the second operation step of the arithmetic circuit means
The above operation generated in the first operation step preceding the aspect
Differs depending on the status of the flag (Section 12)   In one configuration example, the operation flag signal includes a plurality of operations.
The arithmetic circuit means comprises a flag signal.
The flag signal according to the data from the memory, or
Occurs according to the result of the data operation (Section 13). [Action and Development of the Invention]   Music control signals such as envelope signals and phase signals
Changes by its very nature only at relatively low speeds. This departure
Akira focuses on this point and generates a tone control signal.
The tone control signal generation circuit means for performing
Arithmetic circuit that commonizes various operations required for signal generation
It is executed in stages. The tone control signal generation circuit means
It is composed of common operation circuit means and control circuit means.
In the present invention, the arithmetic circuit means controls the control circuit means.
Basically, one process is executed at a time under your control. This
The sequential processing method uses separate dedicated memories and dedicated circuits.
Compared with the parallel processing method or pipeline method
Low in speed. However, as mentioned above, the envelope
The tone control signal of the loop has the property that it does not change at high speed.
So there is basically no speed problem. This is
It is a basic principle of the present invention.   In the case of the architecture of the present invention,
Hardware configuration is greatly reduced because stages are shared
This has the effect of being performed.   In claim 1, the tone control signal generating means
The provided common operation circuit means is a series of operation sequences.
Sequence is executed repeatedly and included in this operation sequence.
In each operation step, execute different operations sequentially and operate
A tone control signal (e.g.,
Key code, envelope).   In an embodiment described later, a series of operation sequences
It is shown in Figure 20A.   Typically, the control circuit means operates the arithmetic circuit means.
It is equipped with a means for controlling with the microprogram method.
The microprogram is stored on a kind of ROM. Arithmetic
At each timing, each microcode is read from ROM
This microcode controls the gates of each part of the circuit.
Control, control the state in the arithmetic circuit means,
Forming memory address signals or reading memory
/ Used to define the write control signal. See below
In some embodiments, this microprogram ROM is
It is located in the timing signal generator 305.   The arithmetic circuit means is not necessarily used to generate a tone control signal.
The configuration does not need to execute all necessary operations.
If required, for example, required to generate the first tone control signal
All operations are performed by the first general-purpose arithmetic circuit means
However, all the operations required to generate the second tone control signal are
It may be performed by a second general-purpose arithmetic circuit means.
In this case, one common operation circuit means
Multiple types of operations required for control signal generation
Means means to execute it in a targeted manner.   The arithmetic circuit means according to claim 2 includes a tone control signal.
Each of the signals required to generate at least the envelope signal
Means for executing a seed operation;
Is at least the phase signal (synthetic key
Means for sequentially executing various operations required for generating the code
It is.   However, in order to eliminate the hardware configuration to the maximum extent
Contains all the performances required to generate all the tone control signals.
It is desirable that the arithmetic be performed by a single arithmetic circuit means,
In the embodiment described, both the envelope signal and the phase signal are used.
It is generated by one common arithmetic circuit 308.   Furthermore, the hardware configuration implemented on the sound source circuit chip
In order to reduce the
Is desirably provided. Claimed configuration for this
The range is shown in the fourth section. First, transfer data from CPU
By using external RAM as the memory for the calculation, the chip
You can make the most of the space above.   In the fifth term, the waveform generating circuit means is provided for each sound channel.
Time division operation of a musical tone waveform by a plurality of modules
FIG. 52 of the embodiment shows the time division operation of the waveform generation circuit (8 channels).
A schematic time chart of
Waveform generating circuit means.
Each channel provided from the musical tone control signal generation circuit means.
Tone control signals (key code and
The sound waveform of each channel is synthesized based on the envelope
Is what you do.   In this context, item 6 contains multiple channels x multiple modes.
Joule's time division operation type waveform generation circuit means.
2 shows the configuration of the arithmetic circuit means. In paragraph 6,
A series of operation sequences are channel-specific and module-specific.
Be executed. This series of operation sequence is
× The time required to repeat as many times as the number of modules is
Calculation cycle of sound control signal set (music sound control signal generation circuit
(Sampling period of the stage).
In the embodiment, the time is 1.2288 msec (FIG. 5, FIG. 19).
See figure).   Claim 7 describes the operation of the common operation circuit means.
Operation and a common operation buffer (work memo
Control circuit for read / write access control
The preferred configuration of the road means is described. This control circuit hand
The stage is a counter means (303), an address generation circuit for operation.
Means (301) and operation control signal generating circuit means (305, 30)
7, 304), and (a) the counter means has a predetermined basic
Counts clock (CKQ) and generates counter output signal
(B) the operation control signal generation circuit means
At least a part of the counter output signal from the
Operation signals from the operation circuit means (F ', EO, MOO, AE)
Generates an operation control signal in response to the
Address generation circuit means outputs the counter output from the counter means.
Part of the force signal and the operation control signal generation circuit means.
Receiving at least a part of the operation control signal to the memory
Address signals (BA0 to BA11), and (d)
The operation circuit means operates from the operation control signal generation circuit means.
Receiving at least a part of the control signal, a series of arithmetic operations are sequentially performed.
Next, the tone generation control signal is generated and output.   By configuring the control circuit means in this way, the operation
Add flexibility to the operation of circuit means
Can be. In particular, the operation flag signal from the operation circuit means
(Computation results of the computation circuit means (for example, data comparison
Result) and a signal indicating the state of the data read from the operation buffer.
Operation circuit again via the operation control signal generation circuit means.
Feedback to the means (by forming an operation control signal)
Therefore, the arithmetic circuit means performs the operation of the current operation step.
A calculation bar that reads the operation mode in the past operation steps
Data on the buffer (data from the CPU or data being calculated).
Data) and the operation results of past operation steps
It can be changed, and a branching process or the like is realized.   Item 8 is the configuration of item 7, wherein the waveform generating circuit means
Time division operation method of multiple sound channels x multiple modules
It shows the configuration applied when
You.   The ninth, tenth, and eleventh terms are, respectively, counter means
Of the preferred configuration of the
Mode of using the counter output), the counter means and the operation control signal.
Relationship with signal generation means (in operation control signal generation means
(Utilization of counter output).   The twelfth term (subordinate to the seventh term) relates to the operation flag signal.
Between the arithmetic circuit means and the operation control signal generating means.
It describes the action configuration. This interface
-According to the action configuration, the current operation of the arithmetic circuit means
The mode of the calculation operation in the step is based on the past operation steps.
Control depending on the state of the operation flag generated in the
Will be done.   Clause 13 (subordinate to clause 7) is how the operation flag signal is generated.
It is a formula.   The inventions of the fourteenth and fifteenth aspects are the same as in the first aspect,
The speed adjustment function is added to the configuration of the seventh item. That is, the tone control signal generation circuit means and the waveform generation circuit
Speed adjusting means between the road means and the speed adjusting means;
At a low-speed cycle from the tone control signal generation circuit means.
Operation of the waveform generating circuit means
To a high-speed musical tone control signal synchronized with   In an embodiment to be described later, the arithmetic circuit means (musical tone control signal generation)
The ratio of the operation cycle of the waveform generation circuit means to the calculation cycle
The ratio is 48 to 1 (see FIG. 5). Exponential conversion / phase
The speed adjustment function is included in the generation circuit 13 (FIGS. 2 and 45).
(Especially the envelope resist as a speed buffer)
1002, frequency information register 1004).   A tone control signal (key code,
Each time an envelope sample is generated and output,
Is written to registers 1002 and 1004, and each register
From the sampling rate synchronized with the waveform generation circuit means 15.
The tone control signal sample is taken out by the
Sent to 13. [Example]   FIG. 1 is a functional diagram of an electronic musical instrument according to the present invention. CPU3
Is a general-purpose microcomputer.
Operate switch 2 to detect key press, tone selection, etc.
Tone data and pronunciation using ROM4, RAM5, etc. located above
Control data is generated to control the sound generation of the sound source LSI. Sound source L
SI6 uses an external RAM7 for musical tone generation
Generates musical tones by using it as an arithmetic buffer, DAC (digital
To a digital-to-analog converter 8. Music signal is DAC8
It is converted to an analog signal, amplified by the amplifier 9 and
Sound is emitted by mosquito 10.   FIG. 2 illustrates the operation of the sound source LSI 6 to which the present invention is applied.
FIG. Sound source LSI6 has amplitude envelope
For generating key codes etc. that include loop and pitch fluctuations
RAM7 is used for memory for tone data or data for calculation progress
Use as memory. In addition, as shown in FIG.
Interface / control unit 11 (interface
Occupancy time) and envelope / key code generation circuit (calculation
Circuit occupied time) and data written from CPU
Address access for operations such as embedding and envelope
I do.   First, the operation of the interface / control unit 11 will be described.
Tone data or tone control data from the CPU 3 to the tone generator LSI 6
Data is transferred, but in the sound source LSI 6, the data buses DB0 to DB7
The rising edge of ▲ ▼ when ▲ ▼ is LOW
Capture at the edge. At this time, if / D is LOW, data bus D
Instruction of B0 ~ DB7 data, / D
If it is taken as data attached to the instruction
(See FIG. 4). The instruction will continue
This indicates the type of data to be transferred. interface
/ Control unit 11 is the instruction and data from CPU3
Received the instruction of RAM7 corresponding to the instruction.
Generates dress AA0 ~ 11 and write signal ▲ ▼, external RAM
Data transferred to external RAM 7 via interface 16
Is stored. However, the data transferred from CPU3 is special
If not, store it in the internal memory. For example transferred
The operation data (control for waveform generation)
Control data), writing to external RAM7 is prohibited.
And a write signal WO to the OC register 14 is generated.
Is written to the OC register.   The envelope / key code generation circuit 12 is connected to the external RAM 7
Address BA0 to BA1 to access the written data
1 and write signal of envelope calculation progress data, etc.
Generates ▼. As a result, the tone data in the external RAM 7
(Envelope plate / level, etc.)
Control data (key code, modulation, etc.)
Key code including amplitude envelope or pitch fluctuation
(Hereinafter referred to as a composite key code), and the bus L2
Through 14 to the exponential conversion / phase angle generation circuit 13
Send.   The exponential conversion / phase angle generation circuit 13 is an envelope / key
The amplitude envelope from the code generation circuit 12
By sharing one exponential converter in a time-sharing manner.
To exponential conversion. Exponentially transformed amplitude envelope (finger
Number envelope) and exponentially converted composite key code
(Frequency information) are the envelope register and frequency
It is temporarily stored in the number information register. These are external RAM7
To generate amplitude envelopes and composite key codes.
And the exponential conversion is performed at low speed.
An interface for performing subsequent arithmetic processing at high speed
Used as a source buffer. FIG. 5 shows two arithmetic operations.
The low-speed operation cycle is the same as the high-speed operation cycle.
48 times. This is an audible change rate of the output waveform
Waveform computation is expensive because it must be at least twice the frequency
Speed (approximately 40 KHz in this embodiment).
Calculation is performed at low speed according to the access of external RAM7
It is.   Exponential envelope stored in the envelope register
Is read out in response to the high-speed operation, and
Transferred as envelopes E0-11. Frequency information register
The frequency information stored in the
The waveform generation circuit accumulates and accumulates the data as phase angle data P0 to P11.
Transferred to 15.   The waveform generation circuit 15 reads the operation read from the OC register 14.
Exponential conversion / phase angle based on the motion codes OC0-7
Envelopes E0 to E11 and phase angles transferred from the generation circuit 13
Generates tone waveforms O0-15 according to data P0-11 and sends them to DAC8
Output.   FIG. 6 is a circuit diagram of the interface / control unit 11.
First, the timing signal generation circuit 159 will be described.
The timing signal generation circuit 159 is shown in FIG. 7 and FIG.
So that the basic clock φ_M(10MHz) frequency division and required tie
Signal and an external reset signal ▲
The internal reset signal is generated from ▼. Fig. 9
An example is shown in FIG. 10MHz basic clock
Divided by flop 233 and inverter 235 to generate S0
And the flip-flop 234 generates T0.
You. Further by And 237₁Generates and flips
V by flop 239, 240₁, W₁Is generated. Also,
T1 is generated by the flip-flop 243. these
From the inverters 242, 245, and 244, 246-248
Generates W, ▲ ▼, ▲ ▼, CK1, CK2
(FIG. 7). Counter A: 249 divides clock CK2
A binary counter that changes at the rising edge of CK2. counter
Q out of the output₁~ Q_FiveIs the address signal C for reading₁~ C_Five
Envelope / key code generation circuit 12 and OC
It is output to the register 1. Also, the counter output Q₀, Q₁From
Two-phase flip-flops 250, 251, 25
2, the inverter 253, and 254-1 to 254-4
Generates imaging signals T2, T3, CKP, CKQ, CKW, CKR
(FIG. 8). In addition, inverters 255-1 to 35-2, OR 256,
CKL is generated from and257 (▲ 52)
Figure). In addition, CARRY OUT (count value 12
From 7 “1”), CKBRT is generated by AND 258.
This signal is used to sample the external reset signal.
Used as a lock. Flicker by clock CKRT
The reset signal is sampled by the flops 260 and 261 and 2
If the external reset signal is detected by AND262
A reset signal is generated. Therefore, the internal reset signal
The numbers are as shown in FIG. Then the counter B3 in Fig. 17
Since 03 is a synchronous reset counter, reset as shown in Fig. 8.
Perform the operation after the start.   Next, the external RAM 7 which is the data memory of the CPU 3 and the sound source LSI 6
Of the interface / control unit 11
Explain the work. Table 1 shows the instructions transferred from the CPU.
Shows the corresponding address of the external RAM7.
You.   Here, the sound source LSI 6 has eight sound channels and each sound source
I have 8 sine wave generation modules for each sound channel
In the envelope / key code generation circuit 12, each sound is generated.
72 amplitudes, including pitch envelope for each channel
Envelope, must generate 64 synthetic key codes
No. Therefore, data is stored for each channel (jjj =
0-7), the data of each module (0iii = 0-7) is transferred.
Must be sent. But related to the envelope
Nine data (jjjj = 0 to 8) including the pitch are transferred
You. The module that sends only one data is the module
It is common.   In Figure 6, ▲ ▼, / D, ▲ ▼, DB0 ~ 7 are CPU
The signal from 3 is input, as shown in Fig. 4.
▲ by inverter 100-103, Nand 104, 105
▼ and ▲ ▼ occur. Signal ▲ ▼ is issued
When the data is generated, the data on buses DB0 to DB7
Taken into the latches 146-153 via the rising edge of ▲ ▼
With counter 191, flip-flop 186, 192-195
Reset. The outputs of latches 149-153 are
Input to the decoder 154, thereby
A control signal is generated. Instruction decoder
As shown in Fig. 10, inverters 265-267, NANDs 269-277,
278, and each signal is as shown in Table 2.
You.   First, of the data written to the RAM 7 of each unit,
1 byte of data per module (high
Slew rate, modulation sensitivity, envelope play
Change, envelope level change, envelope play
(Envelope level, envelope level)
Refer to Figure 11), and respond to instruction writing from CPU3.
In response, the signal ▲ ▼ becomes “0”. Then the bus
Instructions for DB0-7 are inverters 106-113
After being inverted and taken into the latches 146 to 153, the cow
Counter 191, flip-flops 192 to 195, 186 are reset
It is. And the output WB of the instruction decoder 154
Becomes “0”, the output of NAND 172 always becomes “1”.
▲ ▼ is “1”, so OR 168, 170, and 169
Therefore, CK12 becomes CKQ. Next, write data from CPU3.
When the signal ▲ ▼ changes from “0” to “1”, the flip-flop
The lop 173 outputs “1” at the rise of ▲ ▼,
The output of the flip-flop 174 becomes “1”. After that,
Flip-flops 173 and 175 are reset in synchronization with CKR
In this case, it becomes "1" for only one section of CKR. Also, the instrument
The output ▲ ▼ of the fraction decoder 154, the ID is “1”,
“0” is “0”, so OR 178, 179, inverter 180, 1
81, Nando 182, signal ▲ ▼ is “1” and T2
Is "0" when is "0". At that time, instructions
Since the outputs ▲ ▼ and WB of the decoder 154 are “1” and “0”,
The output of Noah 161 indicates that ▲ ▼ is “0” and ▲ ▼ is “0”.
Only when the clock inverter 12 of the buses D0 to D7
Outputs of 2 to 129 are output. The counter 191
Since the output ▲ ▼ of the fraction decoder 154 is “1”,
When CKC is “1”, the clock CKC becomes the clock CKC,
Are incremented to 0, 1, 2,...
192-195, inverted twice with inverters 196-199
Address AA0 to AA3 representing the module number. address
AA4 to AA6 are lower order of instruction latches 146 to 153
A value representing the channel number because it is a 3-bit inversion
It becomes “jjj”. Addresses AA7 to AA11 are
No. 2 because the outputs EF and WB of the action decoder 154 are "0".
04, right input of OR 205, 207 is “0”, right of AND 209, 211
The input is “1” and the left input of OR 203 is “0”.
Inversion of the upper 5 bits of the latches 146 to 153
The upper 5 bits of the instruction
You. As described above, one module per module for each channel
When writing data to a site,
Write signal as shown in Fig. 11 for the matching address
Is generated. Here, the identification of each channel is
The lower 3 bits of the action are used to identify the module.
Is the data number after the instruction transfer
Is performed by counting
ing. Therefore, one instruction can have multiple
In a continuous transfer format followed by
Which module is the data for
Automatically identified by the interface / control unit 11, the CP
U3 does not need to send instructions for each module
Transfer efficiency is improved.   Next, each channel among the data written to the external RAM7
2 bytes of data per module (frequency ratio, key
Chord, modulation level / rate, pitch mod
(Write operation) (see FIG. 12)
See). Respond to instruction writing from CPU3,
▲ ▼ becomes 0, which causes the instruction
Counter is latched into latches 146-153,
191, flip-flop 186, 192-195 are reset
You. The output of flip-flop 176 is “0”
The input on NAND 172 is “1”, instruction deco
The output of the NAND 172 is “0” because the output WB of the leader 154 is “1”.
And the inputs of Noah 167 are both "0"
CK12 becomes CKQ due to ORs 168, 170, and 169. CP
By writing data from U3, ▲ ▼ becomes “0” →
When it becomes “1”, flip-flops 114 to 121 acquire data.
At the same time, the flip-flop 175 outputs “1”,
Flip-flop 176 is “1”, inverter 171 is “0”, NAND
The output of 172 becomes "1". At that time, input on Noah 167
Is "1", so CK12 becomes CKW. Again ▲ ▼ is “0”
→ When it becomes “1”, the flip-flops 130 to 137
Data and the flip-flops 114 to 121 collect bus data.
At the same time, the output of the flip-flop 173 becomes “1”.
As a result, the output of the flip-flop 174 also becomes “1”. But
When it becomes “1”, flip-flops 173 and 175 are reset.
Therefore, it becomes “1” only for two sections of CKR (∵CK12 = CK
W). The output ▲ ▼ of the instruction decoder 154 is
Since the ID is “1” and the ID is “0”, the output of NAND 182 ▲ ▼
Is when T2 is “0” when is “1”, ie, “0” twice
Become. Also, since WB is “1”, ▲ ▼ changes to “0”.
When T3 is “0”, ▲ ▼ is clock invert at width of “0”.
122-129 output data, ▲ ▼ is “0” and T3 is
When “1”, ▲ ▼ is the width of “0” and the clock inverter 13
8-145 output data. Here, the data is
) And the above (rate) are written from the CPU in this order.
The buses D0 to D7 are in the order of higher (rate) and lower (level)
The data is output and input to the external RAM 7. Counter 191
Is the output ▲ ▼ of the instruction decoder 154
Since it is “0”, CKW when “1” is the clock CKC
, And the module numbers are displayed in increments of 0, 1, 2, ...
Address AA0-AA3. Address AA4 ~ AA6 are in
Inversion of the lower 3 bits of the latch 146 to 153 of the structure
Therefore, the value “jjj” indicating the channel number is obtained. Ma
The addresses AA7 to AA11 are
Since EF of DA154 is “0” and WB is “1”, AA7 when T3 is “0”
Becomes the upper 5 bits of the instruction that sets
When T3 is "1", AA8 ~ 11 are the top 4 instructions
AA7 is set to “1” by the unit. In other words, the second byte data
AA7 is used to distinguish between 1 byte address and 2 byte address
It is performed by repeating. In addition, the knowledge of the channel
For channel identification, module identification
This is the same as the case of writing 1 byte of data per file. This
As is clear from the above description, according to the present embodiment,
Byte structure of transfer data in interface / control unit 11
Built-in means of identification based on instructions
Instruction from the CPU3 to the sound source LSI6.
Variable format followed by variable byte data
Data transfer in dummy format
The optimum transfer efficiency without data can be achieved.   Next, the instruction “Flag set” is extended.
(See Fig. 13). “Flag set” is stored in external RAM7.
This command sets the envelope flag. Raw signal
Until the process is the same as in the case of 1-byte data. Inn
Since the output EF of the structure decoder 154 is “1”,
Changes from “0” to “1”, the output of AND 183 changes to “1”.
It was reset when ▲ ▼ became “0”
The output of the flip-flop 186 becomes "1". Also,
The output ▲ ▼ of the instruction decoder 154 is “1”.
Therefore, while the clock CKC of the counter 191 is “1”,
Then, the counter 191 is incremented. The value of the counter 191 is 9
In this case, in sync with CKR,
Since lip flop 186 is reset,
▼-▲ ▼ is between 0-8 (9 sections of CKR) “1”
The output ▲ ▼ of NAND 182 is T2 for each count value.
It becomes “0” when it is “0”. At that time, instructions
Since the outputs ▲ ▼ and WB of the decoder 154 are “1” and “0”,
The output of Noah 161 indicates that ▲ ▼ is “0” and ▲ ▼ is “0”.
Only "1", and clocked inverters on buses D0-7
Outputs of the data 122 to 129 are output. Addresses AA0 to AA3 are
The value of the counter 191 and the addresses AA4 to AA6 are
“Jjj” and AA7 to AA11 are “0” because EF is “1” and WB is “0”.
0110 ". Therefore, the instruction"
Same set automatically for modules 0-8
Will be written to.   Next, I will talk about the instruction "Key Orphan"
(See Fig. 14). When the signal ▲ ▼ becomes “0”,
When the traction is taken into the latches 146-153
The counter 191, flip-flops 186, and 192 to 195 are
Set. Output W of instruction decoder 154
If B is “0”, “1”, the output of NOR 167 is “0”, ▲
Since ▼ is “0”, the output of OR 168 becomes “0” and therefore CK1
2 matches CKW. When ▲ ▼ changes from “0” to “1”,
When data is taken into flip-flops 114 to 121,
At the same time, the flip-flop 173 outputs “1”, and “1” is output.
Become. Becomes “1”, flip-flops 173 and 175 are reset.
Since it is set, it becomes "1" for only two sections of CKR.
Also, the output EF of the instruction decoder 154 is "1".
So the output of AND 183 becomes “1” when “1” is output
Therefore, the output of the flip-flop 186 becomes “1”. ▲
Since ▼ is “0”, the clock CKC of the counter 191 is
During "1", it matches CKW and the counter 191 is incremented. Cow
When the value of the counter 191 becomes 9, the flip-flop is synchronized with CKR.
186 is reset, so ▲ ▼ ~ ▲
▼ is “1” between 0 and 8 (18 sections of CKR), and =
Under “1”, the output of Nand 182
When T2 is “0” and T3 is “1” for each count because it is “0”
It becomes “0”. At that time, since EF is “1”, addresses AA0 to AA
A11 becomes “00110jjjiiii”, but is “1” and T3 is “0”,
When T2 is “0”, data is read from RAM7.
I have. The flip-flops 213 to 216
The 4th bit is taken in by CKP. If the value is “* 000”, “0”
0000111 ", if" 0 *** "," 00000111 "is" 1abc "
Then, if “00000abc”, T3 is “1” and T2 is “0” ▲
▼ is output to the buses D0 to D7 with the width of “0” (however, a,
b and c are arbitrary binary numbers). As will be described later, the instruction
The options “Flag Set” and “Key Off” are
Data "envelope flag".
Here, the data "envelope flag"
Indicates the current state of the step, etc., with the lower 3 bits
Step (0-7), 4th bit is sustaining or not
Is a bit. In other words, the instruction “
"Gusset" writes envelope flag directly from CPU3
In the instruction, which step depends on the lower 3 bits of data
Anyone can start the envelope.
The 4th bit is set to the sustain value “1” and the envelope
By resetting the loop flag,
The envelope can be held. Instructor
Option “key off” is the data of the current envelope flag.
Command to reset the data according to the data
Not at (0000) or at the end of the envelope (1000)
If you have not reached the sustain level,
Go to step 7 (0111) and if you are at the sustain level
(1abc), release sustain (0abc)
I have.   Next, writing to the OC register will be described (FIG. 15). book
Operation is almost the same as 1-byte data,
To the RAM7 because the output ID of the action decoder 154 becomes "1".
No final write signal ▲ ▼ is generated (see FIG. 43).
See). The OC timing is the same as when ▲ ▼ is “0”.
A write signal WO to the register is generated, and when T2 = "0"
▼ = Flip-flops 114 to 121 when "0"
Operation code passed through gates 122-129
Input to the OC register. Finally to latch 156-158
Write (mode) occurs as above, but
Since the output ID of the structure decoder 154 becomes “1”, R
Since writing to AM7 does not occur and ▲ ▼ becomes “0”
Latch signal MLT is generated at the same timing as
The data of the flip-flops 114 to 116
Data is captured (see Fig. 16).   FIG. 17 is a block diagram of the envelope / key code generation circuit 12.
FIG. Envelope / key code generation circuit 12
Generates an amplitude envelope and a composite key code.
The following calculation is performed while accessing the RAM 7 for the purpose.   Envelope plate (envelope tilt data)
Is the data corresponding to the key range or key touch
Change in the default. "   Envelope level (for each step of the envelope
Target data) to the data “d” corresponding to the key range or key touch.
Change with envelope level change ".   Modified envelope plate, envelope preve
Generate an envelope according to the   Amplitude modulation for aftertouch, LFO, etc.
Interpolation data and calculate the amplitude envelope
Generate the final amplitude envelope.   Pitch modulation for vendors, LFOs, etc.
Calculate the pitch data with the pitch envelope.   Pitch envelope with keycode and modulation
Calculate the rope and calculate the frequency ratio for each module
And calculate the final composite key code.
Generate. To achieve these, envelope / key code generation
In the circuit 12, as shown in FIG.
The circuit 308 is used to store data into the A, B, M, and S registers.
It controls data loading and addition / subtraction. However,
One of the upper outputs of the M, S and B registers
Is selected. In FIG. 17, the counter B303 is
The circuit diagram is shown in Fig. 18.
You.   Counters 1-3: 309-311 are synchronous reset counters.
Each corresponds to an operation cycle, channel, and module.
ing. Counter 1: 309 is 0 to 19 when BC11 is 0.
Hexadecimal counter, 32-bit counter from 0 to 31 when BC11 is 1,
Counter 2: 310 is incremented each time Counter 1: 309 makes one round
Octal counter, counter 3: 311 is counter 1, 2 is 1
This is a ninth-number counter that is incremented every time the vehicle goes round. In addition, Coun
The value of data 3: 311 is 0 to 7 corresponds to modules 0 to 7,
Is equivalent to the pitch. Figure 19 Envelope / Key
4 shows an operation cycle of the code generation circuit 12.   FIG. 20A shows the operation of the envelope / key code generation circuit 12.
The flow for explaining the outline of the work is shown. Where A; A
Register, A^M; A register upper, A^L; A lower register, B; B
Register, B^M; B register upper, B^L; B register lower, M; M
Register, S; S register, F1: Flip flow captured by CKF1
F2; flip-flop taken in by CKF2. Ma
Was EF_ij; Envelope flag i = 0-8 (module, pitch), j = 0-7 (ch
Channel) ER_ij(S); Envelope plate i = 0 to 8 (〃), j = 0 to 7 (〃), s = 0 to 7 (d)
Envelope step) ERC_j; Envelope plate change j = 0-7 (〃) ▲ E^M _ij▼; Envelope upper i-8 (〃), j = 0
~ 7 (〃) ▲ Ei^L _ij▼; lower envelope i = 0 to 8 (〃), j = 0 to 7 (〃) EL_ij(S); Envelope level i = 0 to 8 (〃), j = 0 to 7 (〃), s = 0 to 7
(〃) ELC_ij; Envelope level change i = 0 to 8 (〃), j = 0 to 7 (〃) ▲ AMD^M _j▼; upper amplitude modulation j = 0 to 7
(〃) ▲ AMD^L _j▼; Lower amplitude modulation j = 0-7
(〃) ▲ PMD^M _j▼; higher pitch modulation j = 0-7
(〃) ▲ PMD^L _j▼; lower pitch modulation j = 0-7
(〃) MS_ij; Modulation sensitivity i = 0 to 7 (module), j = 0 to 7 (〃) ▲ KC^M _j▼; key code upper j = 0 to 7 (〃) ▲ KC^L _j▼; key code lower j = 0 to 7 (〃) ▲ PE^M _j▼; upper pitch envelope j = 0 to 7 (〃) ▲ PE^M _j▼; Lower pitch envelope j = 0 to 7 (〃) ▲ FR^M _ij▼; high frequency ratio j = 0-7 (〃), j = 0
~ 7 (〃) ▲ FR^L _ij▼; lower frequency ratio j = 0-7 (〃), j = 0
~ 7 (〃) MR_j; Modulation rate j = 0 ~ 7 (〃) ML_j; Modulation rate j = 0 ~ 7 (〃) It corresponds as follows. In the flow of Fig.
Numbers indicate timing, and 0 to 11 are counters
For the values 1 and 1P to 19, the value of the counter 3 is 8 (pi
Other than the value of counter 1) 12 to 19, 12P
~ 19P when the value of counter 3 is 8 (calculation of pitch)
This corresponds to the value of the counter 1 of 12 to 19.   The flow of FIG. 20A will be described. First, at timing 0,
Envelope flag; EF_ijIs loaded from RAM7 to S register
I do. Here, the data structure of the envelope flag is
It has become.1) Lower 3 bits of S register (envelope step)
Envelope plate for ER_ij(S) to A Regis
2) Envelope plate change; ERC_jB cash register
Load the upper part (lower at 0 for both A and B)
3) Add them and change the envelope plate
And store it in the B register. Envelope at the same time
Load upper value of current value to upper register A (lower 0)
4) Next, the lower part is loaded into the lower part of the A register, and 5)
EF the current value of the envelope_FourEnvelope changed according to
The envelope by adding or subtracting
Newly stored in the B register. Envelope preve
L; EL_ij(S) to the upper register of A register (0 to lower register),
6) Envelope level change in M register; ELC_ijThe low
7) Add or subtract them to change the envelope level.
And store it in the A register. Note that the d set in F1
8th bit of envelope level; EL_ij(S)⁷Is sustain
This is the flag of the point. Then, the M register
Is amplitude modulation; AMD_j(Performance of modules 0-7
Calculation), or pitch modulation; PMD_j(Pitch
(When calculating). 8) Next modified envelope
Subtract the updated envelope from the rope level and
Determine whether the envelope has reached the target value (the
AMD is below the time A register_jOr PMD_jLoad the subordinate of
deep). If the envelope has not reached the target value
Becomes F '= “0”, and 9 ▲ ▼) the envelope flag
Register (S register) is not updated and is
The upper part of the stored updated envelope is stored in RAM7
Upper envelope; ▲ E^M _ijWrite to the address corresponding to ▼
No. If the envelope has reached the target value,
F ′ = “1”, and 9F ′) envelope flag 7 (S
Update the lower 3 bits representing the step
(1 + S), the bit of the “node” is set to “0” and the
Tin flag; EL_ij(S)⁷Is “hold” if is “1”
Is set to "1" and stored in the upper register A. That
When the envelope level value is changed
The value is loaded into the B register and the RAM7
Upper level of the envelope; ▲ E^M _ijWrite to the address corresponding to ▼
No. 10) Regardless of whether you arrive next or not,
The lower stage contains the envelope lower data to be stored.
The lower part of the RAM7 envelope;^L _ij
Write to address ▼. However, the bit of the node is a node
In the case of “0” indicating
By comparing the current value of the envelope with the target value.
To determine the direction in which the envelope should travel, and
Is set. Envelope as explained above
The basic operation is to advance the envelope at each node of the step.
Judge the direction, a) Changing the envelope plate level b) Updating the envelope c) Determining whether or not the target level has been reached d) Envelope current value storage It is done by.   Next, 11) The data of the M register is transferred to the upper part of the A register.
And the upper data of the A register is
Envelope flag; EF_ijIs written to the address. This and
The amplitude modulation is below the A register; AMD_jor
Is pitch modulation; PMD_jLower data, M cash register
The star contains the high-order data.   First, the operation of modules 0 to 7 (counter 3 = 0 to
Think about 7). 12) Write to RAM7 in B register
Load the loaded envelope data into the A register
And the amplitude modulation below the A register
Lower order; ▲ AM^L _jLoad the data of ▼ to the lower register of B register
You. 13) Amplitude sensitivity; MS_ijTo the S register.
14) From the envelope data in the A register,
AMD below M and B registers_jMS data_ijSubtract according to
Exponential conversion / phase angle as final envelope data
The data is transferred to the generation circuit 13. At that time, the key is
Higher code: ▲ KC^M _j▼ is loaded. 15) A cash register
Key code below the star; ▲ KC^M _jLoad ▼. 16
) B register upper rank, pitch envelope higher rank; ▲ PE
^M _j▼ 、 17） Lower ▲ PE^M _jLoad ▼. 18) Key
Add chord and pitch envelopes and store in A register
And frequency ratio higher; ▲ FR^M _ij▼ B Regis
Loaded on top 19) Lower frequency ratio; ▲ FR^L _ij▼ to B
Load to lower register. 0) 0 of the next operation cycle
Key code with pitch envelope at timing
Final key with frequency ratio added / subtracted (according to F2)
The exponential conversion / is transferred to the phase angle generation circuit 13 as a code.   Next, consider the pitch calculation (counter 3 = 8)
You. 12P) Envelope written to RAM7 of B register
Pitch modulation in data A register; PMD
_jIs added or subtracted (according to F2), and the final pitch envelope
Rope; PE_jIn the B register. Then A
Upper amplitude modulation upper register; ▲ AMD^M _j▼
Is loaded. 13P) Lower amplitude modulation;
▲ AMD^L _jLoad ▼ to the lower part of the A register. 14P) Module
Translation rate; MR_jInto the M register. Fifteen
P) AMD_jMR_jAddition and subtraction according to F2
Option level; ML_jInto the M register. 16P)
Amplitude modulation; AMD_jUpdated values and modula
Compare the level of the envelope (then the envelope of the pitch)
RAM7: PE of RAM7^M _j▼). Amplitude modulation
Is the target value; ML_jIf not, 17P ▲ ▼)
Lower pitch envelope PE^L _jWrite ▼ to RAM7
If reached, 17PF ') target value; ML_jInto the A register
Load and ▲ PE^L _jWrite ▼ to RAM7. A cash register
Amplitude modulation data that does not exceed the target value of the star
Write to 18P) upper, 19P) lower and RAM7. In addition, 20P ~ 31P
This is a NOP for adjusting the operation timing. here,
Amplitude modulation is provided by the CPU
Absolute value of the difference between the detection amount of the switch and the previous detection amount; MR_j, Mark
No .; MR⁷ _j▼ and this time detection amount; ML_jData (see Figure 21)
Is generated by interpolation based on
You.   FIG. 22 shows the envelope / key code generation circuit of FIG.
12 generates the basic signals to perform the above operations.
FIG. 3 is a detailed diagram of an operation timing signal generation circuit
You. As shown in FIG.
Has a ROMized (firmware) structure.
The operation of the envelope / key code generation
The main operation of the road 12 will be described with reference to FIG. 20B.
You. Inputs BC0-4 are the outputs of counter 1 of counter B303.
Basic timing with power. P is in counter B303
Of the counter 3 MSB, ie, the signal of “1” during the pitch calculation
And F ′ corresponds to the branch flag F ′ of the operation flow.
I have. In the figure, 0, 1, ..., 9F 'and 12P correspond to the timing.
Timing 0, timing 1,..., F ′, respectively.
= 1, timing 9; P = 1
Means twelve. In Fig. 22, `` BW₀Is an envelope
Data from the RAM 7 is written from the
Signal on the “data bus D0 to D7” in FIG. 20B.
It is "1" only when the register output is output. LSI has
The LSB of the dress is forcibly set to “1” as described later.
Timing 12, 12P, 13P, 17, 17 ▲ ▼, 17P
It becomes "1" at F ', 18P and 19P. ▲ ▼ indicates lower address
4th bit (module) is all 0s.
At the timing when the INDEX of i is not attached to the data in the figure
It becomes “1”. OA0 to OA4 are original address signals.
It corresponds to "address". However, at timing 1,
"SSS" of 5 is envelope instead of original address OA0-2
Lower 3 bits (step) of the flag (S register)
It means that it is adopted as an address. a to k
Is the output of the clock generation circuit 304 as shown in FIG.
Clocks, CKAM, CKAL,…, CKE, etc.
At the timing of “Clock” in Figure 20B
It becomes “1”. RA and RB are RA in A register and B register respectively.
This signal is set to “1” when loading data from M7.
Corresponds to "A register input" and "B register input" in the B diagram.
ing. AM, AL, BM, and BL are respectively assigned to data buses D0 to D7.
This signal becomes "1" when outputting the register output.
"Data buses D0 to D7". B0 is the B register
To always mask the output of
"1" when "B" input is the upper "M" and lower "0"
Become. A0 is used to always mask the output of the A register.
Therefore, in the flow of FIG.^M← 0 + S, 9
F '; A^M← 1 + S, 11; A^M← 0 + M, 12; A ← 0 + B, 17P
F '; A ← 0 + M, “1” corresponding to (0). M is moderate
"1" when the B input of the arithmetic unit 440 becomes the M register output
The upper side of the “adder / subtractor B input” in FIG. 20B is
It becomes "1" at the timing of "M". SU is addition and subtraction
The operation of the unit 44 is performed in a subtraction form, that is, "AB" or "AM".
20A, 14; A-M in the flow of FIG. 20A.
(B^L), 16P; A-M (0) becomes "1". SF2 is an adder / subtractor
The B input side code of 440 is the value of F2, which will be described later.
Thus, it becomes "1" at timings 0, 15P and 16P.   Next, FIG. 24 shows the operation address generation circuit 301.
I will tell. In most cases, the address signals BA0-11 are
It is configured as follows.  Further, BA0-3 are outputs BC8-11 of the counter B303, BA4
5 to 5 are BC5 to 7, BA7 to 11 are calculation timing signal generation times.
It corresponds to the address output OA0 to OA4 of the path 305. Then special
Think about the case. At timing 1, the signal is 0
It is. OA4 is also “1” from FIG. 20B. then
₇If "1" is not high release, the inverter
371, inverter 365-367, buffer 368-370
The dress is Becomes Therefore indicated by the envelope flag
Step Envelope Plate; ER_ij(S) address
Becomes The same applies to timing 5. if,₇Is “0”
In other words, if it is a high release, OR 363, and 364
The address is Becomes Here, the high release setting is installed from the CPU.
Line with action "flag set" and data "10000111"
For example, the upper 5 bits of the upper address become “00111”,
High release rate; HR_ijAddress.
Therefore, at the time of high release, normal envelope play
The high release rate is read and used, not the
become. Next, at timings 2, 14, 14P, 15, 15P,
At 16, 16P, ▲ ▼ is “1”, LSI is “0”
Inverter 385, 386, Noah 383, 384, clock Noah
By 382, the address is   OA4 OA3 OA2 OA1 OA0 BC7 BC6 BC5 0000 next
At timings 7 and 8, 7 and 8 are “1” and ▲ ▼ is
Since “1” and LSI are “0”, the mode signal / I
When “1” indicating channel independence, inverters 385 and 386
By the inverter 381, and 378-380
Is Becomes Therefore, the instruction “Pitch module
Pitch module for each channel
7 and 8 during which the calculation data is pitch calculation
And read inside the envelope / key code generation circuit 12.
Channel-independent amplitude modulation data generated by
Data is read at timings 7 and 8 during the operation of modules 0 to 7.
Will be issued. If the mode at timing 7 and 8
If the signal / I is “0” representing the common channel,
372-374, OR 375-377 address Becomes Therefore, the amplitude and pitch
Reading the simulation data. Next time
12, 12P, 13P, 17, 17P ', 17PF', 18P, 19P
In this case, ▲ ▼ and LSI are “1”, so inverter 38
5, 386, Noah 383, 384, Clock Noah 382, and 378 ~
By 380, the address is Becomes This corresponds to the address marked with “*” in Fig. 20B.
These data correspond to the top 5
And LSB. Note that “**” is added
The digit address is the data ML by setting LSB to “1”._jNo
Dress and a dummy address.
Register A at timing 12^LFrom register B^LTo day
Since the data is transferred via tabus D0-7, the write signal of RAM7
Because it will come out). As described above,
The path 301 has address signals B0 to B0 corresponding to the operation flow shown in FIG. 20A.
Generate 11   FIG. 25 shows a detailed diagram of the arithmetic control signal generation circuit 307.
You. a is a condition signal of the clock CKAM, RA is A signal from RAM7.
This is a load control signal to the register. Here from RAM7
When loading data to the upper register, register A
Nand 387 to enter all 0s in the lower order
▲ ▼ is set to “0” (for example, timing 1). As well
When loading data from RAM7 to the upper register of B
In order to input all 0s to the lower part of the B register,
▼ becomes “0”. AM, AL, BM, BL are their respective regis
Signal for outputting data of the data to the data buses D0 to D7.
Occupies the RAM 7 of the envelope / key code generation circuit 12
Available time is when T2 is “1” and the width of the data output time is
Since ▲ ▼ in Fig. 7 is the width of "0", A as shown in Fig. 26
M ', AL', BM ', and BL' are generated. Also register
Upper 7 bits for both A and B output to data bus MSBD7
Since there is no bit to perform,
When outputting to buses D0 to D7, use OR 394 and AND 393.
The S register MSB is output as the MSB. B0 'is B cash register
This is a signal that masks the output of the
B0 from the raw circuit 305 and timing 5, ie,
Addition / subtraction enable signal for addition / subtraction of bellows plate ▲
▼ (described later), amplitude modulation of timing 14
Signal MO0 whose modulation sensitivity at the time of subtraction is 0 (described later)
And 395, or OR 396 to “1”. A0 ′
Is a signal that masks the output of the A register.
A0 from timing signal generation circuit 305, and timing 5,
That is, the envelope current at the time of adding / subtracting the envelope plate
According to the signal E0 that masks the presence value, AND 397, OR 398
To "1". “▲ ▼” indicates the output of the A register
100000000000000, pitch envelope
According to the signal E0 that masks the current envelope value during operation.
It is set to “0” by NAND400.   FIG. 27 shows the envelope / key code generation circuit 12,
Load the envelope flag (timing 0) and again
Transferred from CPU before writing (timing 11)
The same module and the same module
Or pitch envelope flag has been rewritten
If the envelope / key code generation circuit 12
Prohibit writing envelope flag to
FIG. 3 is a detailed diagram of a prohibition circuit 302. Exclusive or 4
08-414, Noah 407 forms a comparison circuit, interface
/ Channel, module or
Are bits A40-6 corresponding to the pitch and the envelope /
Operation channel and module in key code generation circuit 12
Or, compare the output with BC5 to BC11 of counter 3 corresponding to the pitch.
If the values match, "1" is output. Figure 28 is write protected
6 is a time chart of a circuit 302. 27 of 406 in FIG.
Output is provided by the interface / control unit 11
-Channels and modules calculated by the code generation circuit 12
The same channel, the same module or
When writing the pitch envelope flag, it becomes “0”.
You. FIG. 28 (1) shows an envelope / key code generation circuit.
Immediately after reading the envelope flag in step 12,
Control / control unit 11 is the same channel,
This is the case when the envelope flag of the switch is written.
It becomes 0 from the latter half of the timing 1 to inhibit writing.
Even if the value is “0” before timing 0, OR 404
Flip-flop 403 becomes “1” at timing 0
Writing is not prohibited because it is set. (2) is en
Envelope / key code generation circuit 12 is the envelope flag
Immediately before writing the
Write the envelope flag of the channel, module or pitch.
And it becomes 0 in the latter half of timing 11.
To prohibit writing. Therefore, at timings 1 to 11
The same channel, same module or pitch
The envelope flag is written by the interface / control unit 11.
The envelope / key code generation circuit 12
Inhibits writing of the envelope flag.   FIG. 29 is a detailed diagram of the exponent data address generation circuit 306.
It is. Flip-flops 415-420, inverted output flip
The flop 421 is the final envelope generated by the arithmetic circuit 308.
Exponential conversion / phase angle generation circuit 13
Stores write address when writing to memory after exponential conversion
I do. Clock inverters 425 to 434 write P1 address
And the read addresses C1 to 5 are switched by the timing signal T2.
To generate address signals DA1 to DA5.
(Address DA0 is the same as the write address). Exponential conversion
Envelope and frequency information are
Generated by WEE, WEF, and addresses DA0-5
Each is written to the memory (details will be described later).   Next, the arithmetic circuit 308 will be described with reference to FIG. Above
The operation circuit 308 is controlled by the control signal shown in FIG.
The operation is performed as shown in the operation flow of FIG.   FIG. 31 is a detailed diagram of the A register. The A register is
Input to lower FF485-492, upper FF493-499 and FF
Clock NAND 454 to 461 for selection, clock inverter 46
2 to 483 and FF output clock input for output to buses D0 to D7
Output to A input of inverters 500-514 and adder / subtractor 440
It is composed of a group of changing gates 515-531. signal
RA is input to the FF from the data bus D0-7 and the operation output L0-14.
Force selection, ▲ ▼ is low to upper FF493-499 of D0-7
Signal to input all 1 to the lower FF485 to 492 when loading
It is. All 1s are loaded in the lower FF485-492
Only when ▲ is “0” and the clock CKAL is output.
You. Also, the signals AL 'and AM' are the lower register or upper register of the A register.
To control whether or not to output the data on the data buses D0 to D7.
Things. Gate group 515-531 is A input of adder / subtractor 440
This is to change the data to force, and if A0 'is "1",
If 0, ▲ ▼ is 0, 000100010 ... 0 (Fig. 20A
Update processing of envelope steps in the operation flow 9
F '; A^M← 1 + s), if ▲ ▼ is "0",
From Fig. 25, A0 'is 1, so 10 ... 0 (Pitch envelope
Start data).   FIG. 32 is a detailed diagram of the B register. The B register
Input to lower FF564-571, upper FF572-578, and FF
Clock NAND 532-539 for selection, clock inverter 54
Clock NAND for output 0 to 562 and data D0 to D57
9 to 593, and a gate 5 for changing the output to the shift circuit 438
94-616. The signal RB is
Input to FF from source D0 ~ 7 and operation output L0 ~ 14, ▲
▼ lower when loading D0-7 to upper FF572-578
This is a signal for inputting all 1 to the lower FFs 564 to 571. still,
All 1s are loaded to lower FF564-571 because ▲
▼ is “0” and the clock CKBL is output. Also,
Nos. BL 'and BM' transfer lower or upper data of the B register.
It controls whether or not to output to the data buses D0 to D7.
You. Gate groups 594 to 616 are output data to shift circuit 438
If B is "1", the upper register is output.
If "0", M or S register is higher than B register
Instead, they are output to the shift circuit 438. B0 'is "1", B is
If "1", the outputs BI0-14 are all 0, and B0 '
If “1” and B are “0”, upper 7 bits are M or S register
And the lower 8 bits of the data are all 0. And signal 5
When "1", B is "1", so if B0 is "0", the output is 1,
BO10, BO9, BO8, 0 ... 0. This is an envelope
Data conversion for expanding the range of rate data
Data shift or data converted by 11 to BO14
By performing addition and subtraction thinning, etc.,
The ascending and descending speed of the envelope has been obtained. B Regis in Table 3
Envelope plate at the top of the table; ER⁶, ER^Five…… E
R⁰This shows the conversion of  FIG. 33 is a detailed view of the M register, and has inverted outputs FF617 to 623.
Captures data on data buses D0-6 by clock CKM
No. Clock NORs 624 to 630 use N registers when signal M is "1".
Output M1 data, M is “1” and MO0 is “1”
At this time, all 0s are output.   FIG. 34 shows a shift control circuit 447. Clock inva
Data 643 to 645, clock NOR 634, 637, 640
When signal 14 is "1", that is, the operation flow in FIG.
Of the final envelope in "E ← AM"
(E ← E_ij−AND_j) "Only when the lower 3 bits of the S register
Shift control signal SH according to the signal (modulation sensitivity)
1, 2, 4, and 8 are output. Note that the shift circuit 438 is
When signals 1, 2, 4, and 8 are "1", shift left by one each
(× 1/2), 2 left shift (× 1/4), 4 left shift (× 1/1
6), 8 shifts left (× 1/256), for example, SH
If 1, 2, 4, and 8 are 1, 0, 1, 0, respectively, total
5 shifts left (× 1/32)
(Not shown). Therefore, "A ← AM (A ← E_ij−AND
_j) ”Indicates modulation sensitivity MS_ijAccording to each moji
Weighted for each module and amplitude modulation
Can be MS_ijIs 0, the output MO0 of AND 649 is
Since it becomes “1”, the operation becomes “A ← A−0” and the modulation
It does not take any action. Next, when 12P is “1”,
Fig. 20A Operation of the final pitch envelope in the operation flow
Calculation “B ← ± A + B (B ← ± PMD_j+ E_pj) ", S
H1, 2, 4, and 8 become 0, 1, 0, 0, respectively, and 2 left
It is shifted (× 1/4) (the operation explanation will be described later). Also, 15P
Is “1”, that is, the amplitude
Interpolation operation “A ← A ± M (A ← AND_j± MR_j) "
In the case of, if MT is “0”, SH1, 2, 4, 8 are 0, 0,
1, 0 shifts 4 left (× 1/16), if MT is “1”, SH1,
2, 4, and 8 become 1, 0, 1, 0 and shift left by 5 (× 1/3
2) Here, as described above, MR_jIs aftertouch
Because it is the absolute value of the difference between the detected amount of
If MT = "0", the target value ML that is the current detection amount_jTo reach
In order, MR_j16 additions and subtractions are required. That is, the first
16 × 1.2288 = 19.6608 (msec) from the time chart in Figure 9
Will be reached. This is after every 19.6608 msec.
ML calculated from detection data such as touch_j, MR_jThe CPU
Transfer the data inside the sound source LSI,
This means generating kana data. MT =
“1” for MR_jRequires 32 times of addition and subtraction of
The cycle is 39.3216 msec. Next, at timing 5
Think. Since signal 5 is "1", AND631 to 633, 635,
Since 636, 639 and 641 are valid, SH1, 2, 4, and 8 values
Is determined by ▲ ▼ ~ ▲ ▼ (Table
4) The data is shifted as shown in Table 3.
At timings other than the above, SH1, 2, 4, and 8 are always
0, 0, 0, 0, so no shift is performed.   FIG. 35 is a detailed diagram of the envelope control circuit 448.
The envelope control circuit 448 calculates the
Raise, lower, or stop the envelope
To generate enable signals ▲ ▼
You. The signal ▲ ▼ is changed to ▲ ▼
“0”, ie during hold, or “1”, ie
Envelope is at the point of step switching and should proceed
“1” when the direction is being determined, and the envelope is fixed
Let it. In addition, inverters 651 to 654, counter 655,
Lip flops 656-659, and 660-663, or 664
Envelope calculation to change the slope of the envelope
Or a circuit that generates a thinning signal.
When the output of is 0, ▲ ▼
Becomes “1”. Table 5 shows the upper 4 bits of the envelope plate.
B register output ▲ ▼ to ▲
The value of ▼ and the enable signal ▲ ▼ for operation become “0”.
FIG.   Therefore, the thinning operation as shown in the lower part of Table 3 is performed.
It is.   FIG. 36 is a detailed diagram of the data change circuit 439. Taimi
Signal 12P becomes “1” at the time of switching 12P, so the gate circuit
According to 666-677, the output BI ″ 12-14 is   BI ″ 12 = ▲ ▼, BI ″ 13 = ▲ ▼,   BI ″ 14 ＝ BI′12 Becomes The calculation of the timing 12P is based on the operation flow of FIG. 20A.
Is “B ← ± A + B (B ← ± PMD_j+ E_pj) "And B
I'0 to 14 are obtained by shifting the output of the B register 427 by two to the left.
Therefore, the outputs BI0 to BI14 of the B register are
▲ E⁰ _pj▼-▲ E¹⁴ _pj▼ Addition / subtraction decision 440
B inputs BI′0-11 and BI ″ 12-14 of Becomes This is centered on the range of the pitch envelope.
Bell 10 ... means compressed to 1/4 around 0
You. Next, at timing 18, the signal 18 becomes "1".
Output from the gate circuits 666 to 677   BI ″ 12 = BI′12, BI ″ 13 = BI′13,   BI ″ 14 ＝ ▲ ▼ Becomes The operation at timing 18 is the operation flow shown in Figure 20A.
Is "A ← A + B (A ← KC_j+ PE_pj) "
▲ PE⁰ _j▼ ~
▲ PE¹⁴ _j▼ B input BI'0-11, B of adder / subtractor 440
I ″ 12-14 is Becomes This is centered on the final pitch envelope
Positive above level, negative 2's complement below
And Ie this is the key code; KC_jWhen adding to
And the final pitch envelope around 10 ... 0
And if it is larger, add the difference.
This is equivalent to subtracting the difference, which is reflected in the key code.
Symmetrical pitch envelope around the center level
ing.   FIG. 37 is a detailed diagram of the code generation circuit 449. The signal AS
12P, ▲ ▼ is “1” in the code on the A input side of the adder / subtractor 440
At this time, it becomes “1” by the NANDs 678 and 681. That is,
In the operation flow of FIG. 20A, “B ← ± A + B (B ← ± PMD_j+
E_pj) "Is F2 (data PMD_jMSB) is “1”
If it is positive, "0" is negative. Also, 7.P
“1”, if F2 is “1”, inverter 679, NAND 680, 681
As a result, AS becomes “1”. In other words, the pitch shown in the operation flow
Calculation of target value of chain envelope “A ← A ± M (0) (A ←
EL_pj(S) ± ELC_pj)), If F2 is “1”,
Of the envelope level data
Roll to form an envelope as shown in Fig. 38 (b).
((A) does not reverse). Where F2 is the timing
▲ ERC captured in 2⁷ _j▼ is the key code
Direction of change, i.e., the position of the previous key press and the current key press
It shows the positional relationship. At this time, the LSB of the adder / subtractor is incorrect.
There may be a difference, but there is no problem because it is small enough. But
The signal ▲ ▼ is calculated by the adder / subtracter 440 as “* ← −A
It becomes “0” when ±± is performed.
At the B input side code of 0, ▲ ▼ = “0” (timing 8, 1
It is always "1" at (4, 16P). Timing 5
Or, when the signal 5.8 is "1" at the time of 8, P or ▲ ▼
If “1” and “0”, OR 687, Noah 686, Nand 68
9 makes ▲ ▼ = ▲ ▼ (Otherwise,
“1”). That is,   5.8; Envelope update or between envelope and target value
Comparison   PV ▲ ▼: When calculating pitch or other than step 0   = "0"; The direction cannot be determined at the step switching point.
Time (described later) The output ▲ ▼ of Nando 689 becomes ▲ ▼
No. BS is 5 when S4, 8 when "1" (▲ ▼ = 0
Et al.) SF2 is "1", that is, the timing
In the case of 0, 15P and 16P, the output F2 'of NAND 685 becomes F2
("1" otherwise). That is, “0;
Addition / subtraction ”,“ 15P; Modulation rate addition / subtraction ”,
For "16P; Comparison of amplitude modulation and target value"
Is F2 ', F2, and the code BS is BS. Also, timing
When P = 0 in step 7, the output of NAND 684 is 0 and BS is "1"
Becomes That is, the operation flow “A ← A ± M (0) (A
← EL_ij(S) ± ELC_ij) "When not calculating pitch
Is the code BS is "1". When P = 1, the code BS is FA14.
Become. Therefore, as indicated by the arrow in FIG. 38, the pitch
The envelope level of the inverted data is the center level.
Above; subtract when FA14 = "1" (see Fig. 39); lower; FA
When 14 = “0” (see FIG. 39), addition is performed. That's all
The code generation circuit 449 shown in FIG.
Generates input code AS and BS, and the operation flow (Fig. 20A)
Is achieved.   FIG. 39 shows an adder / subtractor 440 and an output clip circuit 441.
It is. Adder / Subtractor 440, OR 691, Exclusive
-OR 692-699 etc., constituted by adder 700, code A
A ± B or ± A + B is executed by S and BS. FA1
4, FB14, CO and S14 are A input MSB and B input M of the adder, respectively.
SB, CARRYOUT, output MSB.   FIG. 40 shows the basis of the branch flag F 'in the operation flow.
FIG. 3 is a detailed diagram of a flag generation circuit 450 that generates a signal F according to the first embodiment.
You. Clock CKF at timing 5, 8, 15P, 16P
Only occur, so consider only that case. First, is “0”
Then, at timing 5, signals 5 and 8 are "1" and
Command 714 is enabled, the output of NAND 14 is S4 ', and the output of NAND 715
Is ▲ ▼. ▲ ▼ is “1” so Nan
The lower input of C 719 is “1”, so ▲ ▼ is “1”, CO is
If “1” or ▲ ▼ is “0” and CO is “0”, FF720 is
“1” is set. This is enabled when updating the envelope.
Flag F when overflow or underflow occurs.
It is equivalent to setting. Is “0” and at timing 8
Similarly, the output of Nand 714 is ▲ ▼, Nand 7
The output of 15 becomes S4 '. At this time, ▲ ▼ is “0”
And if the flag F is set at the timing 5
Set again. When the flag F is not set
Means that S4 'is "0", CO is "0" or S4' is "1" and CO is "1".
If so, FF720 is set to "1". It was updated
When the envelope crosses the target value while rising or falling
If it reaches or exceeds, it is equivalent to setting the flag F.
You. Therefore, when the flag F is “0”, the flag F
Set when the loop reaches the target value. Next
If it is “1”, from FIG. 37, ▲ ▼ = “1”, BS = “0”
Become. Also, from FIG. 35, ▲ = “1”. Therefore
At timing 5, “B ← A + 0” is performed. That
At this time, the output of NAND 715 is “1” in FIG.
The flag is not set because “0” and ▲ ▼ are “1”.
No. At timing 8, the output of NAND 715 is "1"
Subtract the current value of the envelope from the target value to increase the target value.
If they are equal (CO = "1"), set the flag F to "1"
You. That is, F = 1 in the + direction and F = in one direction.
Set 0 and flag. Next, except for timings 5 and 8,
In other words, at timings 15P and 16P, the output of NAND 715
The power is ▲ ▼. At timing 15P, ▲
▼ = “0” and CO = “1” or ▲ ▼ = “1” and CO =
“0”, that is, while updating the amplitude modulation data,
If overflow or underflow occurs, reset flag F.
Cut. At timing 16P, ▲ ▼ = "0"
Indicates that CO = "1" or ▲ ▼ = "1" indicates that CO = "0".
While the updated amplitude modulation is rising to the target value.
Set the flag F if it reaches, exceeds, or exceeds while descending.
To As described above, the flag F is set, and the operation
-(Fig. 20A).   Fig. 41 shows overflow and unloading in adder / subtractor 440.
Monitor the occurrence of underflow and calculate the output when it occurs.
FIG. 4 is a detailed diagram of an output clip control circuit 451 for controlling to a constant value.
You. Output signals CT, MX, ▲ ▼ are “1”, “1”,
When "0", the output of the adder 700 in FIG.
.., 1, 0... 0. First, timing 18
That is, “A ← A + B (A ← KC_j+ P
E_j) ", The shift circuit 43 of FIG.
8. B input to adder / subtractor 440 by data change circuit 439
Is , The calculation at this time is the central level 10... 0
Add data in 2's complement format with the upper part being positive and the lower part being negative.
Calculation. Therefore, the signs AS and B of the adder / subtractor 440
Instead of S, the adder B input MSB: FB14 is “0” or “1”.
Sometimes you have to watch overflow, underflow
No. When 18 is “1”, AND 728 and 731 are valid
If 18 = “1”, FB14 = “1”, ▲ ▼ = “0”,
A732 output is “0”, AND738 output ▲ ▼ is “0”
(MX = "0", CT = "0"). This adds negative data.
When calculating, if underflow, set to all “0”
Is equivalent to 18 = "1", FB14 = "0", CO = "1"
The output MX of OR729 becomes “1” (▲ ▼ = “1”, CT =
“0”). This is because when adding positive data,
Equivalent to setting all "1" when low. Then, 18
= “0” and 7ΛP = “0”, the output of Noah 722
Becomes "0" when BS = "1" or AS0 = "1" ("A-
B "or" -A + B ").
When CO = “0”, the output of NOR 732 is “0”,
The output becomes “0”, and ▲ ▼ becomes “0” (MX = “0”,
CT = "0"). This is all “0” when underflow
Means to do. When BS = "0" and AS0 = "0" (A
+ B), AND 727 becomes effective, and if CO = “1”, OR 729
Is “1” (▲ = “1”, CT = “0”).
This means that all “1” should be set in case of overflow.
To taste. Finally, the case when timing 7 and P = "1" is explained.
I do. EXOR733 output when S14 ≠ FA14 or CO ≠ BS
“1”, so CT = “1”, ▲ ▼ = “0” (MX =
“0”). This changes the pitch envelope level.
When the data exceeds the central level due to changes,
The output of the adder 700 in FIG. 39 is set to the center level 10... 0.
Means that. As described above, FIG.
The output is controlled.   FIG. 42 shows an S register and an envelope flag control circuit.
446 is a detailed view of FIG. The flip-flops 739 to 746 are S
The data buses D0 to D7 are fetched by the clock CKS.
The contents of the S register are from timing 1 of P = 1 or P = 0.
When 13 is the envelope flag and its timing
Only the output of the envelope flag control circuit 446
I have ▲ ▼ is Nand which is an envelope flag
From “747”, “* 0 ** 0000”, that is, the normal mode
It is a signal that becomes 0 at the time of step 0. Is the step
A signal that becomes “1” when the direction is determined at the switching point
7, 749, OR 748, P = "1" or ▲ by inverter 753
When ▼ = “1” and ▲ ▼ = “1”,
Node flag is 0 except for step 0 of width envelope
If it is, it becomes "1". E0 is calculated at timing 5 “B ←
A ± B [B ← E_ij± (ER_ij(S) + ERC_j)] ”To input A
Is set to 0, NAND 747, NOR 752, inverter 75
9, and 760, or or 761, ▲ ▼ = ▲ ▼ =
0, that is, when the mode is mask, or ▲
▼ = 0 and ▲ = 1, that is,
It becomes "1" at first. In the normal mode, step 0
Since the A input becomes 0 first, the envelope must be 0
It will start from. F 'is the operation flow (20A
Figure) Flags for branching, OR 762, 763, Invar
7 ′ and AND 765, F ′ =
F, at timing 9 = "0" and S3 = "0"
F '= F, otherwise F' = "0". That is,
At the time of the imaging 9, during the direction determination or during the hold, F '= 0,
Otherwise, F '= F. Next, output BI8 to BI14
I will explain. These are envelopes only at timing 9.
Output from the rope flag control circuit 446. BI8 ~ 10 is S0 ~
It becomes S2. BI11 == "0" and the envelope flag
Is not "* 0 **** 111", and F = "1" and F1 = "1"
When it becomes “1”, otherwise the original value ▲ EF^Three _ij▼
You. That is, the direction of the normal mode is not being determined.
F7 (8th bit of envelope level)
= Sustain flag), the hole is reached when it reaches “1”
C flag ▲ EF^Three _ij▼ becomes “1”. BI12 = “1”
At this time, if F = "0", it becomes "1". That is, = “1”
If the judgment result is one-way, the sign bit ▲ EF^Four _ij▼
Set to “1”. In addition, when "1" and other than F = "0"
Indicates that the output of the NAND 754 is "0", that is, the sustain level
At the time of arrival, BI12 is set to “0”. Also, ▲ ▼ = 1
That is, BI12 is set to 0 when it is at the switching point of the step.
Otherwise, BI12 is the original value ▲ EF^Four _ijIt becomes ▼. BI13
= “0”, ▲ ▼ = 1, and F = 1
, Reached when not in direction judgment and not sustaining
Is set to “0”, otherwise it is set to “1” and the step
This is a flag indicating a change. RAM7 is higher than registers A and B
When writing the 8th bit, the 8th bit of the S register
Write by SMSB. As described above, FIG.
The rope flag control circuit controls the signal according to the envelope flag.
Signals ▲ ▼, F ', E0
Set the rope flag. The envelope flag is
-After turning on, usually start from step 0 (pitch
The envelope starts after the direction is determined.)
Is added to the node flag and the node flag ▲ EF^Five _ij▼ to node
The direction is determined by setting it to 0, and the sign flag ▲ EF^Four _ij▼
To start the next step. If you reach
Sactin flag (envelope level EL_ij(S)
If the MSB of "1" is "1", it will be in the hold state and the envelope will be
Fixed. Then hold if key-off comes from CPU3
Is released and the next step is started. In addition, loop model
The sustaining flag was in the final step 7
The envelope flag is 011 * 0111 → 01101111 + 1 = 0
It becomes 1010000, and the envelope returns to Step 0.
It is repeated from the beginning.   The operation circuit of FIG. 30 has been described above.
The operation circuit of FIG. 20A
Perform operations such as final envelope and synthesis keys.
-Generate code and transfer to exponential conversion / phase angle generation circuit 13
I do.   FIG. 43 is a detailed diagram of the external RAM interface 16.
You. FIG. 44 (a) shows from the interface / control unit 11,
(B) shows the RA from the envelope / key code generation circuit 12;
This is the timing of writing to M. Address signals RA0-11
Are addresses AA0 to AA1 from the interface / control unit 11.
1. Address from envelope / key code generation circuit 12
Based on each RAM occupation time (Fig. 3)
Obtained by switching with clock inverters 777-801
It is. The write enable signal ▲ ▼
Incoming signal ▲ ▼ from the source / control unit 11 becomes “0”
(However, if the signal ID indicating the use of the internal memory is “1”
Or no envelope / key code generator
When the write signal ▲ ▼ from 12 becomes “0”,
Signal becomes “0” in the width of “0”. Also output
Enable signal ▲ ▼ is both ▲ ▼ and ▲ ▼
When it is “1”, the signal CK2 becomes “0” with a width of “0”. Data RD0
7 are signals when ▲ ▼ or ▲ ▼ is “0”.
▼ is the width of “0” and is output from the sound source LSI6.   FIG. 45 is a block diagram of the exponential conversion / phase angle generation circuit 13 shown in FIG.
It is a lock figure. Envelope / key code generation circuit 12
The envelope and keycode generated by
It is taken into the flip-flop (FF) 1000 by CKE. FF100
The output of 0 is converted by the exponent ROM1001 and the envelope register
Data 1002 and the frequency information register 1004. Fig. 46
3 is a detailed diagram of the envelope register 1002. Enbero
Loop register 1002 has two RAMs (ENVERAM, ENVORA
N), FF1014 ~ 1019, etc., inverter 1027, clock input
Inverters 102-1026, 1028-1033, etc., and inverters
Consists of 1008, 1010, Nand 1009, 1011, 48th
It operates as shown in the time chart of FIG. counter
1 (FIG. 18) is the envelope / key code generation circuit 12
This shows the basic timing of FF415-421 (Fig. 29).
The data output switches from timing 0. FF415 ~ 420
Data is envelope register 1002, frequency information register
Write channel (DA0-2) to module 1004, module
(DA3 to 5), and when T2 is 0
Only data of DA1 to DA5 (DA0 always matches the value of FF415
Yes. Also, the output of FF1000 switches as shown in Fig. 48,
Since WEE becomes “1” at timing 0, when DA0 is “0”
(Even channel) Nand 1009 becomes “0”, so T2
= “0” and the timing signal W is “1” and ENVERAM1
Data is written to the specified address of 012 (inversion of FF416 to 420).
Be included. When DA0 is “1” (odd channel)
Indicates that NAND 1011 is “0” and data is written to ENVORAM 1013.
When T2 is "1", addresses DA1 to DA5 are
The outputs C1 to C5 of the imaging signal generation circuit 159 (FIG. 6)
The channel and module corresponding to the value of C1-5.
Read buffer data, buffers 1020 to 1026, 1028 to
1033 and inverter 1027 enable ENVE when T2 = “1”
When RAM1012 and T2 = "0", T2 = "1" from ENVORAM1013
Data delayed by FF1014 to 1019
The outputs are E0 to E11. Therefore, the envelope register
1002 is the timing of the envelope / key code generation circuit 12.
Data is written in the interface / control unit 11
Read out at the same time and sent to the waveform generation circuit 15 via FF1003.
Sent.   FIG. 47 is a detailed view of the frequency information register 1004.
The operation is exactly the same as that of the rope register 1002. Read
The frequency information FI0 to FI20 via the FF1005
Sent to the accumulator (adder 1006, shift register 1007)
A phase angle is generated.   FIG. 49 is a detailed diagram of the OC register 14. OC register
14 is the envelope register 1002 and frequency information register 10
As in 04, RAM for even-numbered channels (OCERAM), odd-numbered channels
It consists of channel RAM (OCORAM) and reads it alternately.
Register that can always be read and written
You. Address AA0 ~ from interface / control unit 11
2, 4 to 6 are write addresses and C1 to C5 are read addresses
Read when T2 is “1” and write when T2 is “0”
It has become. Flip-flops 1076B-1083B, 1101-
1103, shift register 1104 provides control signals C0-3
The gates 1105-1116 are controlled by control signals C5
9 is generated.   FIG. 50 is a block diagram of the waveform generation circuit 15. Waveform
The generation circuit 15 is disclosed in Japanese Patent Application No. 61-55008 of the present applicant.
It performs almost the same operation as the circuit. First, the phase angles P0 ~ 11
Is selected by the selector 1118, the FF 1119, the phase angle conversion circuit 11
20, input to sine wave ROM 1122 via shift register 1121
To be a waveform signal sinX '. The phase conversion circuit 1120
Introduces phase distortion into the sine wave according to the value of the control signal
FIG. 51 shows the corresponding waveform. Waveform signal
sinX 'is obtained by shifting the shift register 1136, adder 1137, and FF1138.
(The output of the gate circuit 1135 is set to 0)
E ″ is multiplied by the multiplier 1124 and output through the FF 1125.
It is. If this output is output as a musical tone,
Register for accumulating force (selector 1127, FF1128,
The output from the gate circuit 1129) is the selector 1130 and the gate circuit
The data passing through the path 1131 is added and subtracted by the adder / subtractor 1126.
FIG. 52 shows a time chart of the waveform generation circuit 15. C0 ~
5 is a counter output of the timing signal generating circuit 159 in FIG.
And C1 ~ 5 are the envelope register 1002, frequency in Fig. 45
The read address of the information register 1004 and the OC register 14 in FIG.
Has become. Also, the one bit delay is
The basic timing of the circuit (Fig. 50) is 6 bits.
The lower 3 bits are the channel and the upper 3 bits are the module.
Rule calculation. The signals P, X ', E',
E ″, E ″ sinX ′, R ′, R are module 0,
Performance of module 7, channel 7 from operation of channel 0
The timing of one cycle up to the calculation is shown. Corrugated
Generation is performed by selectors 1118, 1127, and 11 by control signals C0 to C9.
30, 1132, gate circuits 1129, 1131, 1135, phase angle change
By controlling the path 1120 and the adder / subtractor 1126.
You. Table 6 shows the upper 4 bits of OC data input from the CPU.
The corresponding operation is shown (see Fig. 49).   A waveform is generated by these arithmetic controls.   The following is an example of waveform generation. Where i is the module N
o and j are channel numbers. 1) E_{j + 1j}sin (E_ijsinP_ij)   The operation code is   ij ** 000000 (upper 4 bits may be 010)   i₊₁j 1001 * 0000   i₊₂j 000 **** Becomes As a result, as shown in Table 6, module i
For the waveform of channel j, P is selected as the phase angle,
Output E ″ sinX ′ is the order of module i + 1, channel j
Become a phase. Module i + 1, channel j waveform output
E ″ sinX ′ is accumulated with the musical sound output.
9 is for a waveform output with a delay of 8 bits from the phase X.
Therefore, for example, the control signal of i + 1, j is a module
i, for the waveform output of channel j
You. 2) E_{i + 2j}sin (E_ijsinP_ij−E_{i + 1j}sinP_{i + 1j})   The operation code is   ij ** 000000 (upper 4 bits may be 010)   i₊₁j 10000000   i₊₂j 111 * 0000   i₊₃j 000 **** Becomes As a result, as shown in Table 6, module i and channel
For the waveform of channel j, P is selected as the phase angle, and its output is
E ″ sinX ′ is input to the shift register 1133.
Rule i₊₁, P is selected as the phase angle for the waveform of channel j
And the waveform is subtracted from the output R of the shift register 1134.
Being a module i₊₂, Channel j.
And module i₊₂, The waveform output E ″ s of channel j
inX 'is accumulated as a tone output. Operation as above
Various waveform generations are performed depending on the
As a result, many musical tones can be generated. output
As for the waveform, the generated waveform is accumulated successively.
When the value of C0 to C5 is “9”, the waveform of a new operation cycle
Captured by FF1128 (No output waveform = phase
), The output of FF1128 at that time is the accumulation of the waveform of the previous cycle
Because it is a value, take it in latch 1139 (CKL)
Latch 1139 causes waveform final accumulation for each operation cycle
Will output a value. The gate circuit 1140 is connected to the signal OM.
Output is all 0 (center level) when is "0"
After the reset, until the mode data is set,
maintain. That is, external reset by power-on etc.
When a signal is generated, the timing signal generation circuit 159
An internal reset signal is generated, and this is the
Switch 156 to reset its output OM to “0”.
The output of the gate circuit 1140, that is, the signal output sent to DAC8
Power is placed on silence levels all zero. On the other hand, CPU3
Tones, etc. in the external RAM 7 through the interface / control unit 11
Set the required data for
Mode latches 156 to 158.
As a result, OM becomes “1” and the gate circuit 1140 is enabled.
The waveform signal calculated by the waveform generation circuit 15 is sent to the DAC 8
Will be able to In other words, after turning on the power,
When the required data settings are complete, the sound source LSI 6
Until the signal can be synthesized, the input to DAC8 is silent.
Level is maintained. [The invention's effect]   As is clear from the above description, the present invention
CPU for monitoring the playing status of the input devices (1, 2)
Controlled by (3), synthesizes musical tones according to the playing state
Memory (7) and the data transferred from the CPU.
Interface writing data to the memory (7)
Using the path means (11) and the above memory as an arithmetic buffer
Tone control signal generation circuit that generates tone control signals
Generated by the step (12) and the tone control signal generating circuit means.
Waveform generator that generates musical tone waveforms according to the generated musical tone control signal
In the tone synthesizer comprising the circuit means (15),
The arithmetic control circuit means is shared with the sound control signal generation circuit means.
And read / write access to memory (computation buffer)
A control circuit for controlling the operation of the control and common operation circuit means
And a series of stages, and a series of arithmetic operations by common operation circuit means
Tone control by executing various operations sequentially through the sequence
Since signals are generated and output, conventional individual memory and individual
Hardware compared to the dedicated arithmetic circuit architecture
The hardware configuration can be greatly reduced. In addition,
When increasing or changing the calculation function,
There is almost no need to change the route means itself.
You only have to make some changes to the columns,
The size of the hardware does not increase proportionally
Has advantages.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a block diagram of a sound source LSI, and FIG. 3 is an interface unit and an envelope / key code of the sound source LSI. 4th time chart showing allocation of external RAM occupation by generation circuit, 4th
FIG. 5 is a time chart of data and a write control signal sent from the CPU to the interface / control unit of the tone generator LSI. FIG. 5 shows a low-speed operation cycle for generating a tone control signal and a high-speed operation cycle for generating a waveform. FIG. 6 is a detailed diagram of an interface / control unit, FIG. 7 is a time chart of a part of a signal generated by a timing signal generation circuit, FIG.
FIG. 9 is a time chart of other signals generated by the timing signal generation circuit, FIG. 9 is a detailed view of the timing signal generation circuit, FIG. 10 is a detailed view of the instruction decoder,
FIG. 11 is a time chart showing the operation of the interface / control unit for the transfer instruction of 1-byte data, FIG. 12 is a time chart showing the operation of the interface / control unit for the transfer instruction of the 2-byte data, and FIG. Fig. 14 is a time chart showing the operation of the interface / control unit for the flag set instruction. Fig. 14 is a time chart showing the operation of the interface / control unit for the key-off instruction. Fig. 15 is the interface for the write instruction to the OC register. 16 is a time chart showing the operation of the interface / control unit with respect to the mode setting instruction, FIG. 17 is a block diagram of the envelope / key code generation circuit, and FIG. Detailed view of the counter B to provide an operation cycle of Beropu / key code generating circuit, the time chart of Figure 19 is the counter B, the 20A diagram flow chart of the operation according to the envelope / key code generating circuit,
FIG. 20B is a diagram summarizing the operation of the envelope / key code generation circuit, FIG. 21 is a graph showing amplitude modulation generation data given from the CPU, FIG. 22 is a detailed diagram of an operation timing signal generation circuit, and FIG. The figure is a detailed diagram of a clock generation circuit, FIG. 24 is a detailed diagram of an operation address generation circuit, FIG. 25 is a detailed diagram of an operation control signal generation circuit, FIG. 26 is a time chart of the operation control signal generation circuit, No.
FIG. 27 is a detailed diagram of the write inhibit circuit, FIG. 28 is a time chart showing the operation of the write inhibit circuit, FIG. 29 is a detailed diagram of the exponent data address generation circuit, FIG. 30 is a detailed block diagram of the arithmetic circuit, FIG. 31 is a detailed view of the A register, and FIG. 32 is B
Figure 33 is a detailed view of the register. Figure 33 is a detailed view of the M register.
The figure is a detailed view of the shift control circuit, FIG. 35 is a detailed view of the envelope control circuit, FIG. 36 is a detailed view of the data change circuit, and FIG.
FIG. 37 is a detailed diagram of a code generation circuit, FIG. 38 is a graph showing pitch envelope inversion by a flag, FIG. 39 is a detailed diagram of an adder / subtracter and an output clip circuit, FIG. 40 is a detailed diagram of a flag generator circuit, and FIG. Figure 41 is a detailed diagram of the output clip control circuit,
42 is a detailed diagram of the S register and the envelope flag control circuit, 43 is a detailed diagram of the external RAM interface, FIG. 44 is a time chart showing the operation of the external RAM interface, and FIG. 45 is an exponential conversion / phase angle generation circuit Block diagram of the
FIG. 46 is a detailed view of the envelope register, FIG. 47 is a detailed view of the frequency information register, FIG. 48 is a time chart of the exponential conversion / phase angle generation circuit, FIG. 49 is a detailed view of the OC register, and FIG. FIG. 51 is a detailed diagram of the waveform generation circuit, FIG. 51 is a waveform diagram showing a set of sine waves in which distortion is generated by a control signal in the waveform generation circuit, and FIG. 52 is a time chart of the waveform generation circuit. 1 ... keyboard, 2 ... switch, 3 ... CPU, 7 ... external R
AM, 11: Interface / control unit, 12: Envelope / key code generation circuit, 15: Waveform generation circuit, 301
… Calculation address generation circuit, 302… write-protection circuit, 303
…… Counter B, 304 …… Clock generation circuit, 305 …… Operation timing signal generation circuit, 307 …… Operation control signal generation circuit, 308 …… Operation circuit.

Claims (1)

(57) [Claims] CPU for monitoring the performance status of the performance input devices (1, 2)
The memory (7), an interface circuit (11) for writing data transferred from the CPU to the memory, and the memory as an arithmetic buffer for synthesizing musical tones according to the playing state, controlled by (3). A tone control signal generating circuit (12) for generating a tone control signal
A waveform generating circuit for generating a musical tone waveform in accordance with the musical tone control signal generated by the musical tone control signal generating circuit (15)
(A) the operation speed of the tone control signal generation circuit is lower than the operation speed of the waveform generation circuit; and (B) the tone control signal generation circuit, the waveform generation circuit, And a speed adjusting circuit for converting the tone control signal supplied from the tone control signal generating circuit at a low cycle into a high-speed tone control signal synchronized with the operation of the waveform generating circuit. (C) The tone control signal generation circuit controls the common operation circuit (308), the operation of the common operation circuit, and the read / write access to the memory as the operation buffer. Control circuit (301-30
5,307), and under the control of the control circuit, the common operation circuit performs a series of operation sequences (20A
) Is repeatedly executed, each operation is sequentially executed in each operation step included in the operation sequence, and the tone control signal is generated and output in a predetermined step (14P, O). The speed adjusting circuit comprises: (B1) a pulse signal generating circuit that generates an alternating pulse signal at a cycle corresponding to at least the operation speed of the waveform generating circuit; and (B2) the tone control signal generating circuit. (B3) a temporary storage memory for temporarily storing the generated tone control signal; and (B3) a write circuit for receiving the tone control signal from the tone control signal generation circuit and writing the received tone control signal to the temporary storage memory. When the pulse signal is in the first state, writing of the tone control signal by the writing circuit is permitted, and when the pulse signal is in the second state, the waveform shaping circuit Musical tone synthesizing apparatus characterized by reading the musical tone control signal is permitted with. 2. 2. The musical tone synthesizer according to claim 1, wherein the common operation circuit includes: (A) an envelope based on envelope plate change data (ERCj) for generating an envelope to be included in the waveform raw circuit; Change of rate (ERij (s)), (B) calculation of envelope value by changed envelope plate, (C) change of target value (ELij) (s) by envelope level change data (ELCj), (D) calculation (E) determining whether or not the calculated envelope value has reached the target value, and (E) updating the envelope step (s) when the calculated envelope value has reached the target value. Synthesizer. 3. 2. The musical tone synthesizer according to claim 1, wherein the common operation circuit includes: (A) pitch envelope data (ERpj (s)) for generating a synthesis key code to be sent to the waveform generation circuit; , ELpj
(P) calculating the pitch envelope (PEj), and (B) calculating the calculated pitch envelope and key code (KC
j) performing a calculation of a synthesized key code according to (j). 4. 2. The tone synthesizer according to claim 1, wherein said interface circuit, said tone control signal generation circuit, and said waveform generation circuit are formed on a tone generator circuit chip, and said memory is formed on said tone generator circuit chip. , The memory is an external memory provided outside the sound source circuit chip.
A tone synthesizer characterized by being a RAM. 5. 2. The musical sound synthesizer according to claim 1, wherein said waveform generation route generates a musical tone waveform of each of a plurality of sounding channels by a time-sharing operation of a plurality of modules, and receives said musical sound as an input. For each channel and module output from the control signal generation circuit,
A tone synthesizer for receiving a key code and an envelope. 6. 6. The musical sound synthesizer according to claim 5, wherein the arithmetic circuit repeats a series of operation sequences (FIG. 20A) by the number of channels × the number of modules to obtain all the modules of all the channels. A tone synthesizer for generating a sample of an envelope and a key code. 7. CPU for monitoring the performance status of the performance input devices (1, 2)
The memory (7), an interface circuit (11) for writing data transferred from the CPU to the memory, and the memory as an arithmetic buffer for synthesizing musical tones according to the playing state, controlled by (3). A tone control signal generating circuit (12) for generating a tone control signal
A waveform generating circuit for generating a musical tone waveform in accordance with the musical tone control signal generated by the musical tone control signal generating circuit (15)
(A) the operation speed of the tone control signal generation circuit is lower than the operation speed of the waveform generation circuit; and (B) the tone control signal generation circuit, the waveform generation circuit, A speed adjusting circuit is provided between the two, and the speed adjusting circuit converts the tone control signal given at a low cycle from the tone control signal generating circuit to a high-speed cycle tone controlling signal synchronized with the operation of the waveform generating circuit. (C) the tone control signal generation circuit controls the common operation circuit (308), the operation of the common operation circuit, and the read / write access to the memory as the operation buffer And a control circuit (301 to 305, 307) for performing the operation. The control circuit includes a counter (303), an operation address generation circuit (301), and an operation control signal generation circuit (305, 3).
(A) the counter counts a predetermined basic clock (CKQ) to generate a counter output signal; and (b) the operation control signal generation circuit generates a counter output signal from the counter. Receiving an operation flag signal (F ', EO, MO0, AE) from the operation circuit at least partially and generating an operation control signal; (c) the operation address generation circuit Receiving a part of the counter output signal and a part of the operation control signal from the operation control signal generation circuit to generate an address signal (BA0 to BA11) for the memory; (d) the arithmetic circuit comprises: Upon receiving at least a part of the control signal from the operation control signal generating circuit, a series of arithmetic operations are sequentially performed to generate and output the tone control signal, and the speed adjusting circuit comprises: (B1) at least a waveform generating circuit (B2) a pulse signal generating circuit for generating an alternating pulse signal at a predetermined cycle corresponding to a speed equal to or higher than the operation speed of (B2); and a temporary memory for temporarily storing the tone control signal generated by the tone control signal generating circuit. A storage memory; and (B3) a write circuit that receives the tone control signal from the tone control signal generation circuit and writes the tone control signal into the temporary storage memory. (B4) When the pulse signal is in the first state, A tone synthesizer, wherein writing of a tone control signal by the writing circuit is permitted, and reading of the tone control signal by the waveform shaping circuit is permitted when the pulse signal is in the second state. 8. The musical tone synthesizing apparatus according to claim 7, wherein the musical tone control signal generating circuit (12) repeats a series of operation sequences (FIG. 20A) by the number of sounding channels × the number of modules to thereby obtain all the signals. Samples of tone control signals for all modules of the sound channel are generated in a time-division manner, and the waveform generation circuit converts the tone waveform of each tone channel from the tone control signal generation circuit to the tone control of each module belonging to the tone channel. A tone generator which performs time division generation based on a signal. 9. 9. The tone synthesizer according to claim 8, wherein the counter comprises: (a) a first counter (311 in FIG. 18) for generating a first counter output portion representing a module number; And (c) a third counter (309) for generating a third counter output portion representing an operation step number in the series of operation sequences. ). 10. 10. The tone synthesizer according to claim 9, wherein a first counter output portion (BC8-BC11) representing a module number from said first and second counters and a second counter output representing a channel number. Part (BC5-B
C7) is input to the operation address generation circuit (301) and is used for generating addresses for reading / writing the module, channel data, and the memory. 11. 11. The musical sound synthesizer according to claim 10, wherein the third counter representing the operation step number from the third counter.
Wherein the counter output portion (BC0-BC4) is input to the operation control signal generation circuit (305) and used to generate an operation control signal in the operation step. 12. 10. The musical tone synthesizer according to claim 9, wherein said operation circuit generates said operation flag signal in a first operation step in a series of operation sequences (FIG. 20A), and said operation control signal generation circuit Generating an operation control signal for the second operation step by using the operation flag signal in a second operation step subsequent to the first operation step; The second operation step in accordance with the operation control signal for the second operation step, and the operation control signal for the second operation step depends on the state of the operation flag generated in the preceding first operation step As a result, the arithmetic operation in the second operation step of the arithmetic circuit is performed in a different pattern. A tone synthesizer characterized by being different depending on the state of the sound. 13. The musical sound synthesizer according to claim 7, wherein the operation flag signal comprises a plurality of operation flag signals,
The musical tone synthesizer according to claim 1, wherein the arithmetic circuit generates individual arithmetic flag signals in accordance with data from the memory or in accordance with the arithmetic result of the data.