JP2718039B2 - Music synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention]   The present invention relates to a tone synthesizer, and more particularly to a tone generation system.
Related to your technology. [Background of the Invention]   Conventional typical music synthesis systems use a CPU (general purpose
Detects the calculation state in the microprocessor, etc.
Control functions such as transfer of required data are provided, and the sound source section has a CP
Synthesizing function to synthesize musical sounds based on data transferred from U
It has. In this type of device, the sound control command is
Key-on and key-off commands are sent from the CPU to the tone generator.
And a key-on command is given
Sound source, the envelope starts from the first step.
Start, and when a key-off command is given,
Then, the envelope is terminated. did
At the start of the sound,
Or start the envelope while playing
You can change to a step, or
Freedom to move the envelope to the sustain state
Lacking.   For example, Japanese Patent Publication No. 60-42955 (Japanese Patent Application No. 51-158949,
Application date, December 29, 1976, name, "wave for electronic musical instruments
Generator)), the sound source from the CPU (key assigner)
Start command is given to the unit as a key-on command
When the segment number (step number) of the sound source section is zero
And the sound source section is indicated by this segment number.
Read the envelope data and start the envelope.
Let During pronunciation, increase the segment number
Data to indicate the length of each segment to detect
Used, the sound source section subtracts this data in a certain cycle
When the segment time has elapsed, the segment number
Increment the next step of the raw envelope
Move on to The above segment length data must be
Standing, data given from the CPU, changes during sounding
There is no. Some of the segment length data include sustain
The segment number that contains the lag and this flag is set
In, the subtraction of the segment length data is stopped and the envelope
The hoop is put on hold. Therefore, the envelope
The transition to the hold state occurs when the
When the time indicated by the segment length data has elapsed
Only when the sound is generated.
Does not occur. This sustaining lug itself,
It does not change even if a key-off command is sent from the CPU
However, the key-off command is used to terminate the envelope.
A control signal is generated within the sound source based on this control signal.
Measurement of segment length data and calculation of envelope
(Addition / subtraction) is resumed.   For musical sound synthesizers for electronic musical instruments,
The degree to which the playing state can be reflected in the musical tone is important
It is one of the items to be considered, and it is desirable that this
You. [Object of the invention]   Therefore, an object of the present invention is to provide a highly flexible envelope.
To provide a tone synthesizer capable of controlling rope and sound
That is. [The gist of the invention]   In order to achieve the above object, the present invention provides an envelope
Memory for envelope flags to control the progress of the
Prepare the envelope according to the contents of this envelope flag.
An envelope generation circuit for calculating a rope;
Selectively update the envelope flag as the rope progresses
Generate tone control signal with new envelope updating circuit means
Embedded in the circuit means, and furthermore, the envelope flag
Content can be freely rewritten by the CPU.
And the main point.   That is, according to the first aspect of the present invention,
The performance is controlled by the CPU (3) that monitors the playing state.
A memory (7) for synthesizing musical tones according to the playing state;
It responds to the instructions from the CPU or the instructions and their accompanying data.
In response, an input to write data to a predetermined area of the memory is made.
Interface circuit (11) and data from the above memory
Tone control signals for generating tone control signals such as envelopes
Signal generation circuit (12) and the above tone control signal generation circuit
Waves that generate musical tone waveforms according to the generated musical tone control signal
In a musical sound synthesizer provided with a shape generation circuit (15),   The memory may include (a) the interface
Generated by the CPU through the base circuit
The envelope for each step of the envelope waveform to be used
Calculation parameters (ER_ij, EL_ijEnvelope to remember)
Parameter memory for loop calculation and (b) envelope waveform
Current value of (E_ijEnvelope current value memory
And (c) an envelope including step information of the envelope waveform.
Velocity flag (EF_ijEnvelope flag to memorize)
And memory,   The tone control signal generation circuit includes: (d) the envelope
Read the envelope flag from the
An envelope flag reading circuit;
The step indicated by the step information contained in the envelope flag
Envelope calculation parameters (ER_ij(s), EL
_ij(s)) is stored in the parameter memory for envelope calculation.
A parameter reading circuit for reading data from
Reads the current envelope value from the envelope current value memory.
Between the read and read envelope calculation parameters
To update the current envelope value and update the result.
Is output as a tone control signal and the envelope
An envelope generation circuit for saving in a value memory;
(G) According to the result of the operation by the envelope generation circuit,
Therefore, the read envelope flag is appropriately updated and updated.
The new envelope flag is
Memory envelope flag update circuit
See (H) Instructions from the CPU to the interface circuit
A flag setting instruction is included in the
The base circuit responds to the flag setting instruction and
The optional envelope flag, which is the attached data, is
Write to envelope flag memory and
The envelope flag update circuit updates the envelope according to the result of the above operation.
Replace the new envelope flag with the above envelope flag
A music device configured to write to a memory.
A sound synthesizer is provided. [Action and Development of the Invention]   According to claim 1, the CPU is a flash memory.
When giving a set command, this command
A rope flag is attached, and this envelope flag
The data is written to the memory via the interface circuit means.   For example, when starting sounding, the envelope flag
Steps other than the first step
The information to be instructed is attached to
Once sent to the stage, the envelope generation circuit means
The envelope starts from this indicated step
become. In principle, the error set by this set instruction
The envelope step can take any value. Accordingly
At the beginning of the sound
Can start.   Specifically, the scans that make up the first attack
Set envelope data including vibration in the step
And selectively omit these steps depending on the key touch
Envelope starts from step without vibration
Attack by giving a flag set instruction
Tremolo is calculated by key state
It becomes possible to select.   In addition, the flag set instruction can be used to
It is possible in principle to publish it. For example, there is
For various types of performance changes, information indicating hold is included.
Envelope flag is stored in memory by flag set instruction.
If set to, the timing is independent of the key press timing
The envelope can be put into a hold state from.   If desired, the flag set instruction can be
It can also be used as an off command.   For example, a high
High release memory that stores release data (HRij)
Is provided on the memory (7), and the CPU
Interface flag by giving a
The circuit means is the data attached to this instruction. High lily
Envelope flag that indicates the data
Write to the flag memory, and the tone control signal generation circuit
When the envelope flag is read, its envelope flag is
Normal if lag indicates high release data
High release from high release memory instead of release data
Source data (claim 4)
Section). This way, the high release flag set
A musical tone can be muted at high speed by a command.   Thus, any envelope by the flag set instruction
The envelope flag setting function is an extremely flexible envelope
And a new concept of pronunciation control.
Has been brought.   The envelope flag is sent to the envelope generation circuit means.
Has the function of controlling the calculation of the envelope
Conversely, the result of the operation by the envelope generation circuit means
Is the envelope progress, select the envelope flag
It has the function of selectively updating. Typically, envelopes
When a step with a rope waveform is completed (envelope
Set the parameters for the rope calculation to the envelope as in item 5.
Envelope if configured with rate and target level
(When the current value of the lamp reaches the target level)
Included in envelope flag by rope update circuit means
The step information is updated to the next step, and the next operation cycle
From this, the envelope generation circuit means
Envelope using the envelope data of the
Is generated (claim 10). Ma
Also, the envelope flag contains the direction information of the envelope.
Otherwise, when updating the steps,
By comparing the current envelope value, the new step
Can determine the direction information of the envelope in the
Wear.   For this purpose, for example, an envelope flag updating means
Indicates that the envelope waveform
Node flag indicating that the loop waveform is at the node (E
F⁶) To change the direction of the envelope waveform for the next step.
Judgment (Claim 11).   By the way, as in the present invention, the memo of the envelope flag is used.
Re-access is performed by the envelope generation circuit means or envelope on the sound source side.
Not only the bellows flag updating circuit means but also the external CPU
In the configuration to perform, the CPU sets the envelope flag
It is desirable to have a means for ensuring rewriting. Claim
The second term in the range describes a preferred configuration of this means.
That is, the memory of the envelope flag is written by the CPU.
Envelope flag updating circuit means when replaced
Temporarily prohibits envelope flag rewriting by
Prohibition circuit means is provided. Therefore, by COU
Envelope flag rewriting is done without delay
Will be.   The flag set instruction is used when the envelope flag data is
It is an attached instruction, and this attached data is
Is written to memory later. In contrast, the claims
No data is attached to the key-off command described in box 3.
No. This key-off command uses the envelope flag data.
It is similar to the flag set instruction in that it is a rewrite instruction.
However, the changed envelope flag data is
The difference is that the data is not sent by itself. Sand
That is, the interface circuit means responds to the key-off command.
Key-off processing circuit means,
Whether the envelope flag at the time of issuing the key-off command is stored in memory
The envelope flag according to the contents.
And then put it back in memory. This is the key release
The envelope progress at the time of
It is not uncommon for rope flags to be changed
Is considered.   When the key is released, the envelope is independent of the progress of the envelope.
If there is no problem with setting the envelope flag,
It can be performed by a set instruction. For example, Envelo
Envelope hula with the last step of the loop
If you attach the tag data to the flag set instruction,
Regardless of the step at the time of issuance, the envelope
The operation can be shifted to the final step. Conversely
For example, the flag change function by the key-off command
It has the function of complementing the flag setting function by the set instruction.
ing.   In one configuration example, the waveform shaping circuit means includes a plurality of
Multiple tone waveforms for each channel in the pronunciation channel
Is generated by the time-sharing operation of the module
Provided from the musical tone control signal generation circuit means as
Key code and envelope for each
Range 6).   In this connection, the envelope flag memory and
The envelope current value memory stores the
The envelope flag and the current envelope value
Each of them is stored in the parameter
Re for sound channels, modules, and envelopes
Store envelope calculation parameters for each step
(Claim 7).   As a data structure, the envelope flag is
(I) Envelope steps (EF⁰~ EF^Two) (Ii) En
Flag indicating whether the envelope is on hold (EF^Three)
(Claim 8).   In an embodiment to be described later, the envelope flag is (i)
Envelope steps (EF⁰~ EF^Two) (Ii) Envelope
Flag (EF)^Three) (Iii)
Envelope direction (EF^Four(Iv) The envelope is
Flag indicating whether or not a node is^Five) (V)
Envelope mode (EF⁶, EF⁷) Information
(Claim 9). [Example]   FIG. 1 is a functional diagram of an electronic musical instrument according to the present invention. CPU3
Is a general-purpose microcomputer.
Scans switch 2 to detect key press, tone selection, etc.
Tone data and pronunciation using ROM4, RAM5, etc. located above
Control data is generated to control the sound generation of the sound source LSI. Sound source L
SI6 uses an external RAM7 for musical tone generation
Generates a musical tone by using it as an arithmetic buffer,
Digital-to-analog converter) 8. The tone signal is DAC8
Is converted to an analog signal, amplified by the amplifier 9 and
The sound is emitted by the speaker 10.   FIG. 2 illustrates the operation of the sound source LSI 6 to which the present invention is applied.
FIG. Sound source LSI6 has amplitude envelope
For generating key codes etc. that include loop and pitch fluctuations
RAM7 is used for memory for tone data or data for calculation progress
Use as memory. In addition, as shown in FIG.
Interface / control unit 11 (interface
Occupancy time) and envelope / key code generation circuit (calculation
Circuit occupied time) and data written from CPU
Address access for arithmetic for envelopes and envelopes
I do.   First, the operation of the interface / control unit 11 will be described.
The CPU 3 sends warm color data or sound control data to the sound source LSI 6.
Data is transferred, but in the sound source LSI 6, the data buses DB0 to DB7
When ▲ ▼ is LOW, the data in
Take in with a cartridge. At this time, if / D is LOW, data bus DB0
~ Instructions for DB7 data, if / D is HIGH
Imported as data attached to the instruction
(See FIG. 4). Instructions will continue
Indicates the type of data to be sent. interface/
The control unit 11 receives instructions and data from the CPU 3
Receiving the RAM7 address corresponding to the instruction.
Address AA0-11 and write signal ▲ ▼
Data transferred to the external RAM 7 via the interface 16
Is stored. However, the data transferred from CPU3 is special
If not, store it in the internal memory. For example transferred
The operation data (control for waveform generation)
Control data), writing to external RAM7 is prohibited.
And a write signal WO to the OC register 14 is generated.
Is written to the OC register.   The envelope / key code generation circuit 12 is connected to the external RAM 7
Address BA0 to BA1 to access the written data
1 and write signal of envelope calculation progress data, etc.
Generates ▼. As a result, the tone data in the external RAM 7
(Envelope plate / level, etc.)
Control data (key code, modulation, etc.)
Key code including amplitude envelope or pitch fluctuation
(Hereinafter referred to as a composite key code), and the bus L2
Through 14 to the exponential conversion / phase angle generation circuit 13
Send.   The exponential conversion / phase angle generation circuit 13 is an envelope / key
The amplitude envelope from the code generation circuit 12
By sharing one exponential converter in a time-sharing manner.
To exponential conversion. Exponentially transformed amplitude envelope (finger
Number envelope) and exponentially converted composite key code
(Frequency information) are the envelope register and the frequency, respectively.
Once stored in the information register. These are external RAM7
Access to generate amplitude envelope and synthetic key code
The exponential conversion operation is performed at a low speed.
Interface for high-speed arithmetic processing after
Used as a buffer for Fig. 5 shows two arithmetic processes
The low-speed operation cycle is 48 times that of the high-speed operation cycle.
Doubled. This means that the output waveform change rate is audible
Waveform calculation is fast because it must be at least twice the number of waves
(Approximately 40 KHz in this embodiment), other operations
Is performed at low speed according to the access of external RAM7
It is.   Exponential envelope stored in the envelope register
Is read out in response to the high-speed operation, and
Transferred as envelopes E0-11. Frequency information register
The frequency information stored in the
The waveform generation circuit accumulates and accumulates the data as phase angle data P0 to P11.
Transferred to 15.   The waveform generation circuit 15 reads the operation read from the OC register 14.
Exponential conversion / phase angle based on the motion codes OC0-7
Envelopes E0 to E11 and phase angles transferred from the generation circuit 13
Generates tone waveforms O0-15 according to data P0-11 and sends them to DAC8
Output.   FIG. 6 is a circuit diagram of the interface / control unit 11.
First, the timing signal generation circuit 159 will be described.
The timing signal generation circuit 159 is shown in FIG. 7 and FIG.
So that the basic clock φ_M(10MHz) divided and required time
Signal and an external reset signal ▲
The internal reset signal is generated from ▼. In FIG.
An example is shown. 10MHz basic clock flip
The frequency is divided by the flop 233 and the inverter 235 to generate S0,
Further, T0 is generated by the flip-flop 234. Change
Φ by And 237₁Is generated, flip-flop
V by 239,240₁, W₁Is generated. Also flip
T1 is generated by flop 243. These signals
By inverters 242, 245, and 244, 246-248
W, ▲ ▼, ▲ ▼, CK1, CK2 are generated (7th
Figure). Counter A: 249 is binary dividing clock CK2
The counter changes at the rising edge of CK2. Counter output
Of which Q₁~ Q_FiveIs the address signal C for reading₁~ C_FiveAs
Envelope / key code generation circuit 12 and OC register
Output to 14. Also, the counter output Q₀, Q₁From 2 sets
Lip flop 250, 251, flip flop 252, in
Timmin by Barta 253, And 254-1 to 254-4
Signal T2, T3, CKP, CKQ, CKW, CKR are generated (eighth
Figure). In addition, inverters 255-1 to 35-2, OR 256, and
From 257, a CKL is generated (FIG. 52). Ma
The counter A: CARRY OUT of 249 (when the count value is 127
CKRT is generated by AND258 from “1”), and this signal
A clock for sampling an external reset signal
Used as Flip-flop by clock CKRT
Sample the reset signal at 260, 261 and externally more than once
When the reset signal is detected by AND 262, the internal reset signal
Issue is generated. Therefore, the internal reset signal is
become that way. At that time, the counter B303 in FIG.
Operation after reset as shown in Fig. 8 because it is a set counter
Perform   Next, the external RAM 7 which is the data memory of the CPU 3 and the sound source LSI 6
Of the interface / control unit 11
Explain the work. Table 1 shows the instructions transferred from CPU3
Shows the corresponding address of the external RAM7.
You.   Here, the sound source LSI 6 has eight sound channels and each sound source
I have 8 sine wave generation modules for each sound channel
In the envelope / key code generation circuit 12, each sound is generated.
72 amplitudes, including pitch envelope for each channel
Envelope, must generate 64 synthetic key codes
No. Therefore, data is stored for each channel (jjj =
0-7), the data of each module (0iii = 0-7) is transferred.
Must be sent. But related to the envelope
Nine data (jjjj = 0 to 8) including the pitch are transferred
You. The module that sends only one data is the module
It is common.   In Figure 6, ▲ ▼, / D, ▲ ▼, DB0 ~ 7 are CPU
The signal from 3 is input, but the signal is input as shown in Fig. 4.
▲ by inverter 100-103, Nand 104, 105
▼ and ▲ ▼ occur. Signal ▲ ▼ is issued
When the data is generated, the data on buses DB0 to DB7
Taken into the latches 146-153 via the rising edge of ▲ ▼
With counter 191, flip-flop 186, 192-195
Reset. The outputs of latches 149-153 are
Input to the decoder 154, thereby
A control signal is generated. Instruction decoder
As shown in Fig. 10, inverters 265-267, NANDs 269-277,
278, and each signal is as shown in Table 2.
You.   First, of the data written to the external RAM 7,
1 byte of data per module (high
Slew rate, modulation sensitivity, envelope play
Change, envelope level change, envelope play
(Envelope level, envelope level)
Refer to Figure 11), and respond to instruction writing from CPU3.
In response, the signal ▲ ▼ becomes “0”. Then the bus
Instructions for DB0-7 are inverters 106-113
After being inverted and taken into the latches 146 to 153, the cow
Counter 191, flip-flops 192 to 195, 186 are reset
It is. And the output WB of the instruction decoder 154
Is “0”, so the output of NAND 172 is always “1”.
▲ ▼ is “1”, so OR 168, 170, and 169
Therefore, CK12 becomes CKQ. Next, write data from CPU3.
When the signal ▲ ▼ changes from “0” to “1”, the flip-flop
The lop 173 outputs “1” at the rise of ▲ ▼,
The output of the flip-flop 174 becomes “1”. After that,
Flip-flops 173 and 175 are reset in synchronization with CKR
In this case, it becomes "1" for only one section of CKR. Also, the instrument
The output ▲ ▼ of the fraction decoder 154, the ID is “1”,
“0” is “0”, so OR 178, 179, inverter 180, 1
81, Nando 182, signal ▲ ▼ is “1” and T
When "2" is "0", it becomes "0". At that time, the instruction
The output ▲ ▼ and WB of the decoder 154 are “1” and “0”.
The output of Noah 161 is “0” for ▲ ▼ and “0” for ▲ ▼
"1" only when
Data 122 to 129 are output. Counter 191
The output ▲ ▼ of the instruction decoder 154 is “1”.
Therefore, CKQ when is “1” becomes the clock CKC,
Each CKC is incremented by 0, 1, 2, ..., and the value is flipped.
Flipped twice by flip-flops 192-195 and inverters 196-199
Address AA0 to AA3 representing the module number. A
Dresses AA4-AA6 Latch Instructions 146-153
Represents the channel number because the lower 3 bits are inverted.
Is “jjj”. Addresses AA7 to AA11 are
Since the outputs EF and WB of the traction decoder 154 are "0",
The right input of NOR 204, OR 205, 207 is "0", AND 209, 21
The right input of 1 is “1” and the left input of OR 203 is “0”.
Inversion of the upper 5 bits of the latch 146 to 153 of the struct
And the upper 5 bits of the instruction
Become. As described above, one for each module for each channel
When writing byte data, instructions and
A write signal as shown in Fig. 11 is sent to the matching address.
Issue is generated. Here, the identification of each channel is
This is done with the lower 3 bits of the function,
Another is the number of data after instruction transfer.
Is done by counting with the counter 191
Have been. Therefore, one instruction
In a continuous transfer format followed by a number of data,
Which data is for which module
Since it is automatically identified by the interface / control unit 11,
CPU3 does not need to send instructions for each module
Transfer efficiency is increased.   Next, each channel among the data written to the external RAM7
2 bytes of data per module (frequency ratio, key
Chord, modulation level / rate, pitch mod
(Write operation) (see FIG. 12)
See). Respond to instruction writing from CPU3,
▲ ▼ becomes 0, which causes the instruction
Counter is latched into latches 146-153,
191, flip-flop 186, 192-195 are reset
You. The output of flip-flop 176 is “0”
The input on NAND 172 is “1”, instruction deco
The output of the NAND 172 is
It is “0”, and both inputs of Noah 167 are “0”.
Because of OR 168, 170, and 169, CK12 becomes CKQ
You. ▲ ▼ is changed by writing data from CPU3.
When the signal changes from “0” to “1”, the flip-flops 114 to 121
And the flip-flop 175 outputs “1”
The flip-flop 176 is “1” and the inverter 171 is
The output of the NAND 172 is “0” and the output of the NAND 172 is “1”. At that time,
CK12 is CKW because the upper input of A167 is "1". Again ▲
When ▼ changes from “0” to “1”, flip-flops 130-1
37 is the previous stage data, flip-flops 114 to 121 are buses
And the output of the flip-flop 173
Becomes “1”, and the output of the flip-flop 174 becomes “1”.
Becomes Becomes “1”, the flip-flops 173 and 175
Since it is reset, it becomes “1” only for 2 sections of CKR
(∵CK12 = CKW). Output of instruction decoder 154
Power ▲ ▼ is “1” and ID is “0”, so Nando 182
When the force ▲ ▼ is “1” and T2 is “0”,
It becomes "0" twice. Also, since WB becomes “1”, ▲ ▼
Is “0” and T3 is “0”.
Inverters 122 to 129 output data, and ▲ ▼ is “0”
When T3 is “1”, ▲ ▼ is clock invert at “0” width.
Data 138 to 145 output data. Where the data is lower
(Level), upper (rate) written from CPU
Therefore, buses D0 to D7 have higher (eight) and lower (level) levels.
Are output in this order and input to the external RAM 7. Coun
191 is the output of the instruction decoder 154 ▲
Since ▼ is “0”, CKW when “1” is
CKC, the module is advanced by 0, 1, 2, ...
Addresses AA0 to AA3 representing numbers are obtained. Address AA4-A
A6 is the lower 3 bits of instruction latches 146-153.
Since this is the reverse of the default, the value “jjj” indicating the channel number is
You. Addresses AA7 to AA11 are instructions
Since EF of the decoder 154 is “0” and WB is “1”, T3 is “0”.
When AA7 is set to "0", instruction upper 5 bits
AA8-11 when T3 is "1"
AA7 becomes "1" in the upper 4 bits. In other words, two-byte data
Distinction between the first byte address and the second byte address of data
Is performed by switching AA7. In addition, Chang
Channels for channel identification and module identification
Same as writing 1 byte data per module
is there. As is clear from the description so far,
According to this, the transfer of transfer data to the interface / control unit 11 is performed.
The means to identify the program configuration based on the instruction
Since it is embedded, the CPU 3
Variable byte data follows the instruction
Data can be transferred in a variable format.
Optimum transfer efficiency without mee data can be achieved.   Next, the instruction "Flag set" is described.
(See Fig. 13). “Flag set” is stored in external RAM7.
This command sets the envelope flag. Raw signal
Until the process is the same as in the case of 1-byte data. Inn
Since the output EF of the structure decoder 154 is “1”,
Changes from “0” to “1”, the output of AND 183 changes to “1”.
And reset when ▲ ▼ becomes “0”.
The output of the flip-flop 186 becomes “1”. Also,
The output ▲ ▼ of the instruction decoder 154 is “1”
Therefore, while the clock CKC of the counter 191 is “1”,
If so, the counter 191 is incremented. If the value of counter 191 is
When it reaches 9, in sync with CKR, OR 184 and NAND 185
Since the flip-flop 186 is reset,
▼-▲ ▼ is between 0-8 (9 sections of CKR) “1”
And output ▲ ▼ of NAND 182 is T2 for each count value
Is "0" when is "0". At that time, the instruction
The output ▲ ▼ and WB of the decoder 154 are “1” and “0”.
The output of Noah 161 is “0” for ▲ ▼. ▲ ▼
It becomes "1" only when it is "0", and clocks are input to buses D0-7.
Outputs of the inverters 122 to 129 are output. Address AA0-A
A3 is the value of counter 191 and addresses AA4 to AA6 are the instructions.
Action “jjj”, AA7 to AA11 have EF “1” and WB “0”
To “00110”. Therefore, the instructions
In the "flag set", the same data is stored in modules 0-8
It will be written automatically.   Next, I will explain the instruction "Key-off"
(See FIG. 14). When the signal ▲ ▼ becomes “0”,
As traction is taken into latches 146-153,
The counter 191, flip-flops 186, 192 to 195 are reset.
Is The output WB of the instruction decoder 154 is
"0" means "1", the output of NOR 167 is "0", ▲ ▼
Is “0”, the output of OR 168 becomes “0”, and therefore CK12
Matches CKW. When ▲ ▼ changes from “0” to “1”,
When data is taken into flip-flops 114 to 121,
At the same time, the flip-flop 173 outputs “1”, and “1” is output.
Become. Becomes “1”, flip-flops 173 and 175 are reset.
Since it is set, it becomes "1" for only two sections of CKR.
Also, the output EF of the instruction decoder 154 is "1".
So the output of AND 183 becomes “1” when “1” is output
Therefore, the output of the flip-flop 186 becomes “1”. ▲
Since ▼ is “0”, the clock CKC of the counter 191 is
During "1", it matches CKW and the counter 191 is incremented. Cow
When the value of the counter 191 becomes 9, the flip-flop is synchronized with CKR.
▲ ▼ ~ ▲
▼ is “1” between 0 and 8 (18 sections of CKR), and =
Under “1”, the output ▲ ▼ of Nand 182 becomes ▲ ▼
When T2 is “0” and T3 is “1” for each count because it is “0”
It becomes “0”. At that time, since EF is “1”, addresses AA0 to AA
A11 becomes “00110jjjiiii”, but “1” and T3
When “0” and T2 are “0”, data is read from RAM7.
Is coming. The flip-flops 213 to 216
The lower 4 bits are captured by CKP and the value is “* 000”.
To “00000111”, and to “0 ****” to “00000111”
If “1abc”, then “00000abc” when T3 is “1” and T2 is “0”
▲ ▼ is output to buses D0-7 with width of “0” (however,
a, b, and c are arbitrary binary numbers). As will be described later,
Actions “Flag Set” and “Key Off” are in RAM7
Data of the “envelope flag”
You. Where the data "envelope flag" is the envelope
Indicates the current state of the step, etc.
Is the step (0-7), the 4th bit is sustaining
It is a bit of whether or not. That is, instructions
“Flag set” is used to convert envelope flags directly from CPU3.
The instruction to be written depends on the lower 3 bits of the data.
You can start the envelope from the top
is there. Also, set the fourth bit to the sustain value “1” and
By resetting the envelope flag,
You can hold the envelope from. Ins
Traction "key off" is the current envelope flag
Instruction to reset the data according to the data
At 0 (0000) or at the end of the envelope (1000)
If you haven't reached the sustain level
Proceed to Step 7 (0111) and you are at the sustain level
(1abc), release sustain (0abc)
ing.   Next, writing to the OC register will be described (FIG. 15). book
Operation is almost the same as 1-byte data,
To the RAM7 because the output ID of the action decoder 154 becomes "1".
No final write signal ▲ ▼ is generated (see FIG. 43).
See). The OC timing is the same as when ▲ ▼ is “0”.
A write signal WO to the register is generated, and when T2 = "0"
▼ = Flip-flops 114 to 121 when "0"
Operation code passed through gates 122-129
Input to the OC register. Finally to latch 156-158
Write (mode) occurs as above, but
Since the output ID of the structure decoder 154 becomes “1”, R
Since writing to AM7 does not occur and ▲ ▼ becomes “0”
Latch signal MLT is generated at the same timing as
The data of the flip-flops 114 to 116
Data is captured (see Fig. 16).   FIG. 17 is a block diagram of the envelope / key code generation circuit 12.
FIG. Envelope / key code generation circuit 12
Generates an amplitude envelope and a composite key code.
The following calculation is performed while accessing the RAM 7 for the purpose.   Envelope plate (envelope tilt data)
Is the data corresponding to the key range or key touch
Change in the default. "   Envelope level (for each step of the envelope
Target data) to the data “d” corresponding to the key range or key touch.
Change with envelope level change ".   Modified envelope plate, envelope preve
Generate an envelope according to the   Amplitude modulation for aftertouch, LFO, etc.
Interpolation data and calculate the amplitude envelope
Generate the final amplitude envelope.   Pitch modulation for vendors, LFOs, etc.
Calculate the pitch data with the pitch envelope.   Pitch envelope with keycode and modulation
Calculate the rope and calculate the frequency ratio for each module
And calculate the final composite key code.
Generate. To achieve these, envelope / key code generation
In the circuit 12, as shown in FIG.
The circuit 308 is used to store data into the A, B, M, and S registers.
It controls data loading and addition / subtraction. However,
Any one of the upper outputs of the M, S and B registers
Is selected. In FIG. 17, the counter B303 is
The circuit diagram is shown in Fig. 18.
You.   Counters 1-3: 309-311 are synchronous reset counters.
Each corresponds to an operation cycle, channel, and module.
ing. Counter 1: 309 is 0 to 19 when BC11 is 0.
Hexadecimal counter, 32-bit counter from 0 to 31 when BC11 is 1,
Counter 2: 310 is incremented each time Counter 1: 309 makes one round
Octal counter, counter 3: 311 is counter 1, 2 is 1
This is a ninth-number counter that is incremented every time the vehicle goes round. In addition, Coun
The value of data 3: 311 is 0 to 7 corresponds to modules 0 to 7,
Is equivalent to the pitch. Figure 19 Envelope / Key
4 shows an operation cycle of the code generation circuit 12.   FIG. 20A shows the operation of the envelope / key code generation circuit 12.
The flow for explaining the outline of the work is shown. Where A; A
Register, A^M; A register upper, A^L; A lower register, B; B
Register, B^M; B register upper, B^L; B register lower, M; M
Register, S; S register, F1: Flip flow captured by CKF1
F2; flip-flop taken in by CKF2. Ma
Was EF_ijAn envelope flag i = 0 to 8 (module,
Switch), j = 0 to 7 (channel) ER_ij(s); Envelope plate i = 0 to 8 (〃), j =
0-7 (〃), s = 0-7 (envelope step) ERC_j; Envelope plate change j = 0-7 (〃) ▲ E^M _ij▼; Envelope upper i-8 (〃), j = 0
7 (〃) ▲ Ei^L _ij▼; envelope lower i = 0-8 (０〜), j
= 0 to 7 (〃) EL_ij(s); envelope level i = 0 to 8 (〃), j =
0 to 7 (〃), s = 0 to 7 (〃) ELC_ij; Envelope level change i = 0 to 8 (〃), j
= 0 to 7 (〃) ▲ AMD^M _j▼; upper amplitude modulation j = 0 to 7
(〃) ▲ AMD^L _j▼; 〃 Lower j = 0-7
(〃) ▲ PMD^M _j▼; higher pitch modulation j = 0-7
(〃) ▲ PMD^L _j▼; 〃 Lower j = 0-7
(〃) MS_ijModulation sensitivity i = 0 to 7 (modulation
Le), j = 0 to 7 (〃), ▲ KC^M _j▼; key code upper j = 0 to 7 (〃) ▲ KC^L _j▼; 〃 Lower j = 0-7 (〃) ▲ PE^M _j▼; upper pitch envelope j = 0 to 7 (〃) ▲ PE^L _j▼; 〃 Lower j = 0-7 (〃) ▲ FR^M _ij▼; high frequency ratio i = 0-7 (０〜), j = 0
7 (〃) ▲ FR^L _ij▼; 下 位 Lower order i = 0 ~ 7 (〃), j = 0 ~
7 (〃) MR_jModulation rate i = 0 to 7 (〃) ML_jModulation level i = 0 to 7 (〃) It corresponds as follows. In the flow of Fig.
Numbers indicate timing, and 0 to 11 are counters
The value of 1 itself, 1P to 19 are 8
Counter 1 value other than (pitch calculation) 12 to 19
12P to 19P are when the value of counter 3 is 8 (pitch calculation)
Correspond to the values 12 to 19 of the counter 1.   The flow of FIG. 20A will be described. First, at timing 0,
Envelope flag; EF_ijIs loaded from RAM7 to S register
I do. Here, the data structure of the envelope flag is
It has become. 1) Lower 3 bits of S register (envelope step)
Envelope plate for ER_ij(s) is A register
2) Envelope plate change; ERC_jThe B Regis
Data is loaded to the upper part (both A and B are loaded with 0 to the lower part),
3) Add them and change the envelope plate, B
Store in register. At the same time the envelope
Load the upper value to the A register upper (lower 0) 4)
Next, the lower part is loaded into the lower part of the A register. 5) Envelope
The current value of the loop to EF_FourModified envelope according to
Change the envelope by adding or subtracting at a rate
And store it in the B register. More envelope levels;
EL_ij(s) to upper register A (lower 0), 6) M register
Envelope level change on star; ELC_ijAnd load
7) Add or subtract them to change the envelope level,
Store in A register. The Envelope set in F1
8th bit of loop level; EL_ij(s)⁷Is a Sustain Point
Flag. At this time, the amplitude register is stored in the M register.
Simulation; AMD_j(When calculating modules 0-7)
Is pitch modulation; PMD_j(When calculating pitch)
Load it. 8) The next modified envelope preve
Calculates the updated envelope from the
To determine whether the target has reached the target value (at that time A Regis
AMD below_jOr PMD_j). D
If the envelope has not reached the target value, F '=
“0”, 9 ▲ ▼) Envelope flag (S register
Is not updated and is stored in the upper part of the A register.
The upper part of the updated envelope is the RAM7 envelope
Higher rank; ▲ E^M _ijWrite to the address corresponding to ▼. Embe
If the rope has reached the target value, F '= "1"
9F ') Envelope flag 7 (S register)
While updating the lower 3 bits representing the step, (1+
S) The “node” bit is set to “0” and the sustain flag
G; EL_ij(s)⁷Is “1”, set the “hold” bit to “1”
Is stored in the upper part of the A register. At that time, it was changed
Using the envelope level value as the envelope value
And load it on the top of the RAM7 envelope.
▲ E^M _ijWrite to the address corresponding to ▼. 10) Next
In either case, the B register has a lower rank
Contains the lower envelope data to be stored.
This is the lower envelope of RAM7;^L _ijTo the address of ▼
Write. However, if the bit of the node is “0”
In this case, the above operation is not performed, and the envelope
Envelope by comparing the current and target values of
Judge the direction to go, and set the sign bit.
You. As described above, the basic operation of the envelope is
Judgment of the traveling direction of the envelope is made for each node of the step.
Come a) Change of envelope plate level b) Updating the envelope c) Determining whether or not the target level has been reached d) Store envelope current value It is done by.   Next, 11) The data of the M register is transferred to the upper part of the A register.
And the upper data of the A register is
Envelope flag; EF_ijIs written to the address. This and
The amplitude modulation is below the A register; AMD_jor
Is pitch modulation; PMD_jLower data, M cash register
The star contains the high-order data.   First, the operation of modules 0 to 7 (counter 3 = 0 to
Think about 7). 12) Write to RAM7 in B register
Load the loaded envelope data into the A register
And the amplitude modulation below the A register
Lower order; ▲ AMD^L _jLoad the data of ▼ to the lower register of B register
You. 13) Amplitude sensitivity; MS_ijTo the S register.
14) From the envelope data in the A register,
AMD below M and B registers_jMS data_ijSubtract according to
Exponential conversion / phase angle as final envelope data
The data is transferred to the generation circuit 13. At that time, the key is
Higher code: ▲ KC^M _j▼ is loaded. 15) A cash register
Key code below the star; ▲ KC^L _jLoad ▼. 16
) B register upper rank, pitch envelope higher rank; ▲ PE
^M _j▼ 、 17） Lower ▲ PE^M _jLoad ▼. 18) Key
Add chord and pitch envelopes and store in A register
And frequency ratio higher; ▲ FR^M _ij▼ B Regis
Loaded on top 19) Lower frequency ratio; ▲ FR^L _ij▼ to B
Load to lower register. 0) 0 of the next operation cycle
Key code with pitch envelope at timing
Final key with frequency ratio added / subtracted (according to F2)
The exponential conversion / is transferred to the phase angle generation circuit 13 as a code.   Next, consider the pitch calculation (counter 3 = 8)
You. 12P) Envelope written to RAM7 of B register
Pitch modulation in data A register; PM
D_jIs added or subtracted (according to F2), and the final pitch envelope
Rope; PE_jIn the B register. then,
Amplitude modulation higher in A register higher; ▲ AMD^M _j
▼ is loaded. 13P) Under amplitude modulation
Rank; ▲ AMD^L _jLoad ▼ to the lower part of the A register. 14P)
Duration rate; MR_jTo the M register
You. 15P) AMD_jMR_jIs added and subtracted according to F2, and
Juration level; ML_jTo the M register
You. 16P) Amplitude modulation; AMD_jWith the updated value of
Compare the modulation levels (and when
▲ PE of RAM7 for higher envelope^M _j▼). Amplitude moji
Is the target value; ML_jIf not reached, 17P
▲ ▼) Lower pitch envelope ▲ PE^L _j▼ to RAM7
If writing and reaching, 17PF ') target value; ML_jTo
Load into A register and ▲ PE^L _jWrite ▼ to RAM7
Put in. Amplitude modulation that does not exceed the target value of the A register
Write the data of the option to RAM7, 18P) upper, 19P) lower.
20P to 31P are NOPs for adjusting the calculation timing.
You. Here, the amplitude modulation is given by the CPU.
The absolute difference between the detected amount of aftertouch, etc.
Value; MR_j, Sign; ▲ MR⁷ _j▼ and this time detection amount; ML_jDay of
By interpolation based on the data (see Fig. 21).
Has been established.  FIG. 22 shows the envelope / key code generation circuit of FIG.
12 generates the basic signals to perform the above operations.
FIG. 3 is a detailed diagram of an operation timing signal generation circuit
You. As shown in FIG.
Has a ROMized (firmware) structure.
The operation of the envelope / key code generation
The main operation of the road 12 will be described with reference to FIG. 20B.
You. Inputs BC0-4 are the outputs of counter 1 of counter B303.
Basic timing with power. P is in counter B303
Of the counter 3 MSB, ie, the signal of “1” during the pitch calculation
And F ′ corresponds to the branch flag F ′ of the operation flow.
I have. In the figure, 0, 1, ..., 9F 'and 12P correspond to the timing.
Timing 0, timing 1,..., F ′, respectively.
= 1, timing 9; P = 1
Means twelve. In Fig. 22, `` BW₀Is an envelope
Data from the RAM 7 is written from the
Signal on the “data bus D0 to D7” in FIG. 20B.
It is "1" only when the register output is output. LSI has
The LSB of the dress is forcibly set to “1” as described later.
Timing 12,12P, 13P, 17,17P ▲ ▼, 17P
It becomes "1" at F ', 18P and 19P. ▲ ▼ indicates lower address
4th bit (module) is all 0s.
At the timing when the INDEX of i is not attached to the data in the figure
It becomes “1”. OA0 to OA4 are original address signals.
It corresponds to "address". However, at timing 1,
"SSS" of 5 is an envelope instead of original addresses OA0-2
Lower 3 bits (step) of the flag (S register)
It means that it is adopted as an address. a to k
Is the output of the clock generation circuit 304 as shown in FIG.
Clocks, CKAM, CKAL,…, CKE, etc.
At the timing of “Clock” in Figure 20B
It becomes “1”. RA and RB are RA in A register and B register respectively.
This signal is set to “1” when loading data from M7.
Corresponds to "A register input" and "B register input" in the B diagram.
ing. AM, AL, BM, and BL are respectively assigned to data buses D0 to D7.
This signal becomes "1" when outputting the register output.
"Data buses D0 to D7". B0 is the B register
To always mask the output of
"1" when "B" input is the upper "M" and lower "0"
Become. A0 is used to always mask the output of the A register.
Therefore, in the flow of FIG.^M← 0 + S, 9
F '; A^M← 1 + S, 11; A^M← 0 + M, 12; A ← 0 + B, 17
PF '; A ← 0 + M, (0) also corresponds to “1”. M is moderate
"1" when the B input of the arithmetic unit 440 becomes the M register output
The upper side of the “adder / subtractor B input” in FIG. 20B is
It becomes "1" at the timing of "M". SU is addition and subtraction
The operation of the unit 440 is performed in a subtraction form, that is, "AB" or "A-
M ", 8; AB, 14; A- in the flow of FIG. 20A.
M (B^L), 16P; A-M (0), which is "1". SF2 is moderate
The code on the B input side of the arithmetic unit 440 is assumed to be the value of F2, which will be described later.
As described above, it becomes "1" at timings 0, 15P, and 16P.   Next, FIG. 24 shows the operation address generation circuit 301.
I will tell. In most cases, the address signals BA0-11 are
It is configured as follows. Further, BA0-3 are the outputs BC8-11 of the counter B303, BA4-
5 is a BC5-7, BA7-11 is an operation timing signal generation circuit
305 address outputs OA0 to OA4. Then special
Think about the case. At timing 1 the signal is 0
is there. OA4 is also “1” from FIG. 20B. then₇
If “1” is not high release, inverter 37
1, add by inverter 365-367, buffer 368-370
Les is OA4 OA3S ₂ S ₁ S ₀  BC7 BC6 BC5 BC11 BC10 BC9 BC8 Becomes Therefore indicated by the envelope flag
Step envelope plate; ER_ij(s) address and
Become. The same applies to timing 5. if,₇Is “0”
In other words, if it is a high release,
The dress is0  OA3 S_Two S₁ S₀ BC7 BC6 BC5 BC11 BC10 BC9 BC8 Becomes Here, the high release setting is installed from the CPU.
Row with fraction “flab set”, data “10000111”
For example, the upper 5 bits of the upper address become “00111”,
High release rate; HR_ijAddress.
Therefore, at the time of high release, normal envelope play
The high release rate is read and used, not the
become. Next, at timings 2, 14, 14P, 15, 15P,
At 16, 16P, ▲ ▼ is “1”, LSI is “0”
Inverter 385, 386, Noah 383, 384, clock Noah
By 382, the address is 0A4 OA3 OA2 OA1 OA0 BC7 BC6 BC5 0 0 0 0 Becomes Next, at timings 7 and 8, 7 and 8 are “1”,
Since ▲ ▼ is “1” and LSI is “0”, the mode signal /
When I is “1” indicating channel independence, the inverter 385,
386, clock inverter 381, and 378-380,
The address is 0A4 OA3 OA2 OA1 OA0 BC7 BC6 BC5 ▲0 0 0
▼ Becomes Therefore, the instruction “Pitch module
Pitch module for each channel
7 and 8 during which the calculation data is pitch calculation
And read inside the envelope / key code generation circuit 12.
Channel-independent amplitude modulation data generated by
Data is read at timings 7 and 8 during the operation of modules 0 to 7.
Will be issued. If the mode at timing 7 and 8
If the signal / I is “0” representing the common channel,
372-374, OR 375-377 address 0A4 OA3 OA2 OA1 OA0 ▲0 0 0 0 0 0
▼ Becomes Therefore, the amplitude and pitch
Reading the simulation data. Next time
12, 12P, 13P, 17, 17P ', 17PF', 18P, 19P
In this case, ▲ ▼ and LSI are “1”, so inverter 38
5, 386, Noah 383, 384, Clock Noah 382, and 378 ~
By 380, the address is 0A4 OA3 OA2 OA1 OA0 BC7 BC6 BC5 0 0 0 1 Becomes This corresponds to the address marked with “*” in Fig. 20B.
These data correspond to the top 5
And LSB. Note that “**” is added
The digit address is the data ML by setting LSB to “1”._jNo
Dress and a dummy address.
Register A at timing 12^LFrom register B_LTo day
Since the data is transferred via tabus D0-7, the write signal of RAM7
Because it will come out). As described above,
The path 301 has address signals B0 to B0 corresponding to the operation flow shown in FIG. 20A.
Generate 11   FIG. 25 shows a detailed diagram of the arithmetic control signal generation circuit 307.
You. a is a condition signal of the clock CKAM, RA is A signal from RAM7.
This is a load control signal to the register. Here from RAM7
When loading data to the upper register,
Nand 387 to enter all 0s in the lower order
▲ ▼ is set to “0” (for example, timing 1). As well
When loading data from RAM7 to the upper register of B
In order to input all 0s to the lower part of the B register,
▼ becomes “0”. AM, AL, BM, BL are their respective regis
Signal for outputting data of the data to the data buses D0 to D7.
Occupies the RAM 7 of the envelope / key code generation circuit 12
Available time is when T2 is “1” and the width of the data output time is
Since ▲ ▼ in Fig. 7 is the width of "0", A as shown in Fig. 26
M ', AL', BM ', and BL' are generated. Also register
Upper 7 bits for both A and B output to data bus MSBD7
Since there is no bit to perform,
When outputting to buses D0 to D7, use OR 394 and AND 393.
The S register MSB is output as the MSB. B0 'is B cash register
This is a signal that masks the output of the
B0 from the raw circuit 305 and timing 5, ie,
Addition / subtraction enable signal for addition / subtraction of bellows plate ▲
▼ (described later), amplitude modulation of timing 14
Signal MO0 whose modulation sensitivity at the time of subtraction is 0 (described later)
And 395, or OR 396 to “1”. A0 ′
Is a signal that masks the output of the A register.
A0 from timing signal generation circuit 305, and timing 5,
That is, the envelope current at the time of adding / subtracting the envelope plate
According to the signal E0 that masks the presence value, AND 397, OR 398
To "1". “▲ ▼” is the output of A register
To 1000000000000, the pitch envelope
According to the signal E0 that masks the current envelope value during
Therefore, it is set to “0” by the NAND 400.   FIG. 27 shows the envelope / key code generation circuit 12,
Load the envelope flag (timing 0) and again
Transferred from CPU before writing (timing 11)
The same module and the same module
Or pitch envelope flag has been rewritten
If the envelope / key code generation circuit 12
Prohibit writing the envelope flag to. writing
FIG. 3 is a detailed diagram of a prohibition circuit 302. Exclusive or 4
08-414, Noah 407 forms a comparison circuit, interface
/ Channel, module or
Are bits AA0 to 6 in charge of the pitch and the envelope /
Operation channel and module in key code generation circuit 12
Or, compare the output with BC5 to BC11 of counter 3 corresponding to the pitch.
If the values match, "1" is output. Figure 28 is write protected
6 is a time chart of a circuit 302. 27 of 406 in FIG.
Output is provided by the interface / control unit 11 for the envelope /
Channels and modules calculated by the key code generation circuit 12
Module or pitch, same channel, same module or pitch
Becomes “0” when the pitch envelope flag is written.
You. FIG. 28 (1) shows an envelope / key code generation circuit.
Immediately after reading the envelope flag in step 12,
Control / control unit 11 is the same channel,
This is the case when the envelope flag of the switch is written.
It becomes 0 from the latter half of the timing 1 to inhibit writing.
Even if the value is “0” before timing 0, OR 404
Flip-flop 403 becomes “1” at timing 0
Writing is not prohibited because it is set. (2) is en
Envelope / key code generation circuit 12 is the envelope flag
Immediately before writing the
Write the envelope flag of the channel, module or pitch.
And it becomes 0 in the latter half of timing 11.
To prohibit writing. Therefore, at timings 1 to 11
The same channel, same module or pitch
The envelope flag is written by the interface / control unit 11.
The envelope / key code generation circuit 12
Inhibits writing of the envelope flag.   FIG. 29 is a detailed diagram of the exponent data address generation circuit 306.
It is. Flip-flops 415-420, inverted output flip
The flop 421 is the final envelope generated by the arithmetic circuit 308.
Exponential conversion / phase angle generation circuit 13
Stores write address when writing to memory after exponential conversion
I do. Clock inverters 425 to 434 write P1 address
And the read addresses C1 to 5 are switched by the timing signal T2.
To generate address signals DA1 to DA5.
(Address DA0 is the same as the write address). Exponential conversion
Envelope and frequency information are
Generated by WEE, WEF, and addresses DA0-5
Each is written to the memory (details will be described later).   Next, the arithmetic circuit 308 will be described with reference to FIG. Above
The operation circuit 308 is controlled by the control signal shown in FIG.
The operation is performed as shown in the operation flow of FIG.   FIG. 31 is a detailed diagram of the A register. The A register is
Input to lower FF485-492, upper FF493-499 and FF
Clock NAND 454 to 461 for selection, clock inverter 46
2 to 483 and FF output clock input for output to buses D0 to D7
Output to A input of inverters 500-514 and adder / subtractor 440
It is composed of a group of changing gates 515-531. signal
RA is input to the FF from the data bus D0-7 and the operation output L0-14.
Force selection, ▲ ▼ low D0-7 to upper FF493-499
Signal to input all 1 to the lower FF485 to 492 when loading
It is. All 1s are loaded in the lower FF485-492
Only when ▲ is “0” and the clock CKAL is output.
You. Also, the signals AL 'and AM' are the lower register or upper register of the A register.
To control whether or not to output the data on the data buses D0 to D7.
Things. Gate group 515-531 is A input of adder / subtractor 440
This is to change the data to force, and if A0 'is "1",
If 0 and ▲ ▼ are 0, then 00000010 ... 0 (Fig. 20A
Update processing of envelope steps in the operation flow 9
F ': A^M← corresponds to 1 + s, If "0" is shown in FIG. 25, A0 'is 1, so 10 ... 0 (pip
H), which is equivalent to the start data of the envelope.   FIG. 32 is a detailed diagram of the B register. The B register
Input to lower FF564-571, upper FF572-578, and FF
Clock NAND 532-539 for selection, clock inverter 54
0 to 562, and clock number for output to data bus D0 to D7
Switches 579 to 593 and the output of the shift circuit 438.
594-616. The signal RB is
Input selection to FF from tabus D0 ~ 7 and operation output L0 ~ 14,
▲ ▼ indicates that D0-7 is to be loaded into upper FF572-578
Is a signal for inputting all 1s to the lower FFs 564 to 571.
All 1s are loaded in the lower FF564-571
▲ ▼ is “0” and the clock CKBL is output. Ma
Also, the signals BL 'and BM' are the lower or upper data of the B register.
To control whether data is output to the data buses D0 to D7.
It is. Gate groups 594 to 616 output to shift circuit 438
Change the data. If B is "1", B register upper
Is output. If "0", the M or S register is set to the upper B register.
Is output to the shift circuit 438 instead. B0 'is "1", B
Is "1", outputs BI0-14 are all 0, and B0 '
If “1” and B are “0”, upper 7 bits are M or S register
And the lower 8 bits of the data are all 0. And signal 5
When "1", B is "1", so if B0 is "0", the output is 1,
B010, B09, B08, 0 ... 0. This is an envelope
Data conversion for expanding the range of rate data
Data shift or data converted by 11 to BO14
By performing addition and subtraction thinning, etc.,
The ascending and descending speed of the envelope has been obtained. B Regis in Table 3
Envelope plate at the top of the table; ER⁶, ER^Five......
ER⁰This shows the conversion of  FIG. 33 is a detailed view of the M register, and has inverted outputs FF617 to 623.
Captures data on data buses D0-6 by clock CKM
No. Clock NORs 624 to 630 use N registers when signal M is "1".
Output M1 data, M is “1” and MO0 is “1”
At this time, all 0s are output.   FIG. 34 shows a shift control circuit 447. Clock inva
Data 643 to 645, clock NOR 634, 637, 640
When signal 14 is "1", that is, the operation flow in FIG.
Of the final envelope in "E ← AM"
(E ← E_ij-AMD_j) "Only when the lower 3 bits of the S register
Shift control signal SH according to the signal (modulation sensitivity)
1, 2, 4, and 8 are output. Note that the shift circuit 438 is
When signals 1, 2, 4, and 8 are "1", shift left by one each
(× 1/2), 2 left shift (× 1/4), 4 left shift (× 1/1
6) Performs 8 left shifts (× 1/256). For example, SH
If 1, 2, 4, and 8 are 1, 0, 1, 0, respectively, total
5 shifts left (× 1/32)
(Not shown). Therefore, "A ← AM (A ← E_ij-AMD
_j) ”Indicates modulation sensitivity MS_ijAccording to each moji
Weighted for each module and amplitude modulation
Can be MS_ijIs 0, the output MO0 of AND 649 is
Since it becomes “1”, the operation becomes “A ← A−0” and the modulation
It does not take any action. Next, when 12P is “1”,
Fig. 20A Operation of the final pitch envelope in the operation flow
Calculation “B ← ± A + B (B ← ± PMD_j+ E_pj) ", S
H1, 2, 4, and 8 become 0, 1, 0, 0, respectively, and 2 left
It is shifted (× 1/4) (the operation explanation will be described later). Also, 15P
Is “1”, that is, the amplitude
Interpolation operation "A ← A ± M (A ← ± AMD_j+ MR_j) "
In the case of, if MT is “0”, SH1, 2, 4, 8 are 0, 0,
1, 0 shifts 4 left (× 1/16), if MT is “1”, SH1,
2, 4, and 8 become 1, 0, 1, 0 and shift left by 5 (× 1/3
2) Here, as described above, MR_jIs aftertouch
Because it is the absolute value of the difference between the detected amount of
If MT = "0", the target value ML that is the current detection amount_jTo reach
In order, MR_j16 additions and subtractions are required. That is, the first
16 × 1.2288 = 19.6608 (msec) from the time chart in Figure 9
Will be reached. This is after every 19.6608 msec.
ML calculated from detection data such as touch_j, MR_jThe CPU
Transfer the data inside the sound source LSI,
This means generating kana data. MT =
“1” for MR_jRequires 32 times of addition and subtraction of
The cycle is 39.3216 msec. Next, at timing 5
Think. Since signal 5 is "1", AND631 to 633, 635,
Since 636, 639 and 641 are valid, SH1, 2, 4, and 8 values
Is determined by ▲ ▼ ~ ▲ ▼ (Table
4) The data is shifted as shown in Table 3.
At timings other than the above, SH1, 2, 4, and 8 are always
0, 0, 0, 0, so no shift is performed.   FIG. 35 is a detailed diagram of the envelope control circuit 448.
The envelope control circuit 448 calculates the
Raise, lower, or stop the envelope
To generate enable signals ▲ ▼
You. The signal ▲ ▼ is changed to ▲ ▼
“0”, that is, while holding or “1”
And the envelope is at the point where the step switches
It is set to “1” when the power direction is being determined, and the envelope is
Fixed. In addition, inverters 651 to 654, counter 65
5, flip-flops 656-659, and 660-663, or 6
64 is to change the envelope slope.
A circuit that generates a thinning-out signal is formed.
When the output of 664 is 0, ▲
▼ becomes “1”. Table 5 shows the top four envelope plates.
B register output which is bit data ▲ ▼ ～ ▲
The value of ▼ and the enable signal ▲ ▼ for operation are “0”
Shows the relationship between the counter values.   Therefore, the operation is thinned out as shown in the lower part of Table 3.
It is.   FIG. 36 is a detailed diagram of the data change circuit 439. Taimi
Signal 12P becomes “1” at the time of switching 12P, so the gate circuit
According to 666-677, the output BI ″ 12-14 is BI ″ 12 = ▲ ▼, BI ″ 13 = ▲ ▼, B
I ″ 14 ＝ BI ″ 12 Becomes The calculation of the timing 12P is based on the operation flow of FIG. 20A.
Is “B ← ± A + B (B ← ± PMD_j+ E_pj) "And B
I'0 to 14 are obtained by shifting the output of the B register 427 by two to the left.
Therefore, the outputs BI0 to BI14 of the B register are
▲ E⁰ _pj▼-▲ E¹⁴ _pj▼ If you add, subtractor 440
B inputs BI′0-11 and BI ″ 12-14 of Becomes This is centered on the range of the pitch envelope.
Bell 10 ... means compressed to 1/4 around 0
You. Next, at timing 18, is signal 18 "1"?
Output by the gate circuits 666 to 677 BI ″ 12 = BI ″ 12, BI ″ 13 = BI ″ 13, BI ″ 14 = ▲
▼ Becomes The operation at timing 18 is the operation flow shown in Fig. 20A.
Then, "A ← A + B (A ← KC_j+ PE_pj) "
▲ PE⁰ _j
▼-▲ PE¹⁴ _j▼ B input BI'0 ~ 1 of adder / subtractor 440
1, BI ″ 12-14, Becomes This is centered on the final pitch envelope
Positive above level, negative 2's complement below
And That is, this is the key code; KC_jAdd to
The final pitch envelope is centered around 10 ... 0
If the difference is larger, add the difference.
Is equivalent to subtracting the difference of
Symmetrical pitch envelope around center level
doing.   FIG. 37 is a detailed diagram of the code generation circuit 449. The signal AS
12P, ▲ ▼ is “1” in the code on the A input side of the adder / subtractor 440
At this time, it becomes “1” by the NANDs 678 and 681. That is,
In the operation flow of FIG. 20A, “B ← ± A + B (B ← ± PMD_j+
E_pj) "Is F2 (data PMD_jMSB) is “1”
Is positive, and “0” is negative. Also, 7.P
“1”, if F2 is “1”, inverter 679, NAND 680, 681
As a result, AS becomes “1”. In other words, the pitch shown in the operation flow
Calculation of target value of chain envelope “A ← A ± M (0) (A ←
EL_pj(s) ± ELC_pj)), If F2 is “1”, the pitch
Envelope level data is inverted with respect to the center level
Then, the envelope becomes as shown in FIG. 38 (b) ((a)
Is not inverted). Here, F2 is taken at timing 2.
▲ ERC embedded⁷ _j▼ This is the key code change
Direction, that is, the positional relationship between the previous key press and the current key press
It represents. At this time, an error of the LSB of the adder / subtracter appears.
In some cases, there is no problem because it is small enough. Therefore the signal
▲ ▼ indicates that the operation “* ← −A ± *”
It will be "0" when performed. Signal BS is input to B of adder / subtractor 440
The sign of the force value, ▲ ▼ = “0” (timing 8, 14,
16P) is always "1". Also, at timing 5 or
When the signal 5.8 is "1" at 8 and P or ▲ ▼
If “1” is “0”, or 687, Noah 686, Nando 689
Becomes ▲ ▼ = ▲ ▼ (otherwise,
“1”). That is, 5.8; Envelope update or ratio of envelope to target value
Comparison PV ▲ ▼: When calculating pitch or other than step 0 = "0"; when the direction is not determined at the step switching point
(See below) The output ▲ ▼ of Nando 689 becomes ▲ ▼
No. BS is 5 when S4, 8 when “1” (▲ ▼ = “0”
Et al.) SF2 is "1", that is, the timing
In the case of 0, 15P and 16P, the output F2 'of NAND 685 becomes F2
("1" otherwise). That is, “0;
Addition / subtraction ”,“ 15P; Modulation rate addition / subtraction ”,
For "16P; Comparison of amplitude modulation and target value"
Is F2 ', F2, and the code BS is BS. Also, timing
When P = 0 in step 7, the output of NAND 684 is 0 and BS is "1"
Becomes That is, the operation flow “A ← A ± M (0) (A
← EL_ij(S) ± ELC_ij) "When not calculating pitch
Is the code BS is "1". When P = 1, the code BS is FA14.
Become. Therefore, as indicated by the arrow in FIG. 38, the pitch
The envelope level of the inverted data is the center level.
Above; subtract when FA14 = "1" (see Fig. 39); lower; FA
When 14 = “0” (see FIG. 39), addition is performed. That's all
The code generation circuit 449 shown in FIG.
Generates input code AS and BS, and the operation flow (Fig. 20A)
Is achieved.   FIG. 39 shows an adder / subtractor 440 and an output clip circuit 441.
It is. Adder / Subtractor 440, OR 691, Exclusive
-OR 692-699 etc., constituted by adder 700, code A
A ± B or ± A + B is executed by S and BS. FA1
4, FB14, CO and S14 are A input MSB and B input M of the adder, respectively.
SB, CARRY OUT, output MSB.   FIG. 40 shows the basis of the branch flag F 'in the operation flow.
FIG. 3 is a detailed diagram of a flag generation circuit 450 that generates a signal F according to the first embodiment.
You. Clock CKF at timing 5, 8, 15P, 16P
Only occur, so consider only that case. First, is “0”
Then, at timing 5, signals 5 and 8 are "1" and
714 is enabled, the output of NAND 714 is S4 ', NAND 71
The output of 5 is ▲ ▼. ▲ ▼ is “1”, so
719 is “1”, so ▲ ▼ is “1”, CO is
If “1” or ▲ ▼ is “0” and CO is “0”, FF720 is
“1” is set. This is enabled when updating the envelope.
-Set flag F when overflow or underflow occurs.
Is equivalent to Is “0” and at timing 8
Similarly, the output of Nand 714 is ▲ ▼, Nand 7
The output of 15 becomes S4 '. At this time, ▲ ▼ is “0”
And if the flag F is set at the timing 5
Set again. When Huag F is not set
Means that S4 'is "0", CO is "0" or S4' is "1" and CO is "1".
If so, FF720 is set to "1". It was updated
When the envelope crosses the target value while rising or falling
If it reaches or exceeds, it is equivalent to setting the flag F.
You. Therefore, when the flag F is "0", the flag F
Set when the target reaches the target value. Next is “1”
Then, from Fig. 37, ▲ ▼ = "1" and BS = "0".
You. Also, from FIG. 35, ▲ = “1”. Therefore
In the imming 5, “B ← A + 0” is performed. At that time,
In FIG. 40, the output of NAND 715 is “1”, CO is “0”, ▲
Since ▼ is “1”, no flag is set. Thailand
In mining 8, the output of NAND 715 is "1", so
Subtract the current value of the envelope from the
If so (CO = “1”), the flag F is set to “1”. You
That is, F = 1 in the + direction and F = 0 in one direction.
Set the rug. Next, except for timings 5 and 8,
At timings 15P and 16P, the output of NAND 715 is
It becomes ▲ ▼. At timing 15P, ▲ ▼
= “0” and CO = “1”, or ▲ ▼ = “1” and CO = “0”,
That is, while updating the amplitude modulation data,
-Set flag F if flow or underflow
You. At timing 16P, ▲ ▼ = “0” and CO =
“1” or ▲ ▼ = “1” and CO = “0”, ie update
Amplitude modulation reaches the target value while rising
Set the flag F if it exceeds or exceeds or descends
You. The flag F is set as described above, and the operation flow
(FIG. 20A).   Fig. 41 shows overflow and unloading in adder / subtractor 440.
Monitor the occurrence of underflow and calculate the output when it occurs.
FIG. 4 is a detailed diagram of an output clip control circuit 451 for controlling to a constant value.
You. Output signals CT, MX, ▲ ▼ are “1”, “1”,
When "0", the output of the adder 700 in FIG.
.., 1, 0... 0. First, timing 18
That is, “A ← A + B (A ← KC_j+ P
E_j) ", The shift circuit 43 of FIG.
8. B input to adder / subtractor 440 by data change circuit 439
Is , The calculation at this time is the central level 10... 0
Add data in 2's complement format with the upper part being positive and the lower part being negative.
Calculation. Therefore, the signs AS and B of the adder / subtractor 440
Instead of S, adder B input MSB: FB14 is “0” or “1”
Sometimes you have to watch overflow, underflow
No. When 18 is “1”, AND 728 and 731 are valid
If 18 = “1”, FB14 = “1”, ▲ ▼ = “0”,
A732 output is “0”, AND738 output ▲ ▼ is “0”
(MX = "0", CT = "0"). This adds negative data.
When calculating, if underflow, set to all “0”
Is equivalent to 18 = "1", FB14 = "0", CO = "1"
The output MX of OR729 becomes “1” (▲ ▼ = “1”, CT =
“0”). This is because when adding positive data,
Equivalent to setting all "1" when low. Then, 18
= “0” and 7∧P = “0”, the output of Noah 722
Becomes "0" when BS = "1" or AS0 = "1" ("A-
B "or" -A + B ").
When CO = “0”, the output of NOR 732 is “0”,
The output becomes “0”, and ▲ ▼ becomes “0” (MX = “0”,
CT = "0"). This is all “0” when underflow
Means to do. When BS = "0" and AS0 = "0" (A
+ B), AND 727 becomes effective, and if CO = “1”, OR 729
Is “1” (▲ = “1”, CT = “0”).
This means that all “1” should be set in case of overflow.
To taste. Finally, the case when timing 7 and P = "1" is explained.
I do. EXOR733 output when S14 ≠ FA14 or CO ≠ BS
“1”, so CT = “1”, ▲ ▼ = “0” (MX =
“0”). This changes the pitch envelope level.
When the data exceeds the central level due to changes,
The output of the adder 700 in FIG. 39 is set to the center level 10... 0.
Means that. As described above, FIG.
The output is controlled.   FIG. 42 shows an S register and an envelope flag control circuit.
446 is a detailed view of FIG. The flip-flops 739 to 746 are S
The data buses D0 to D7 are fetched by the clock CKS.
The contents of the S register are from timing 1 of P = 1 or P = 0.
At 13 the envelope flag is
The output of the envelope flag control circuit 446 is significant.
ing. ▲ ▼ indicates that the envelope flag is Nand 74
7. From "* 0 ** 0000", that is, the normal mode
It is a signal that becomes 0 at the time of loop 0. Is a step switch
A signal that becomes “1” when the direction is determined at the intersection
7, 749, OR 748, P = "1" or ▲ by inverter 753
When ▼ = “1” and ▲ ▼ = “1”,
Node flag is 0 except for step 0 of width envelope
If it is, it becomes "1". E0 is calculated at timing 5 “B ←
A ± B [B ← E_ij± (ER_ij(s) + ERC_j] "And input A to 0
Signals, NAND 747, NOR 752, inverter 759,
760, or 761, ▲ ▼ = ▲ ▼ = 0
In other words, when the mode is the mask, ▲ ▼ = 0
And ▲ ▼ = 1, that is, “1” at the beginning of step 0
Becomes In the normal mode, A
Since the input is 0, the envelope must start from 0
Will be F 'is the operation flow (Fig. 20A)
Flag for Ki, OR 762, 763, inverter 764,
Due to AND 765, F '= F,
In the case of imming 9, F '= when "0" and S3 = "0"
F, otherwise F '= "0". That is,
In step 9, F '= 0 during direction determination or hold,
Outside, F '= F. Next, the outputs BI8 to BI14 are explained.
I will tell. These are envelopes only at timing 9.
The output of the flag control circuit 446. BI8 ~ 10 is S0 ~ S2
Become. BI11 is “0” and the envelope flag is
It is not "****** 111", and F = "1" and F1 = "1"
The original value ▲ EF^Three _ijIt becomes ▼.
In other words, the direction of the normal mode is not being determined.
F7 (envelope level 8th bit =
When the stin flag reaches “1”, the hold
Flag ▲ EF^Three _ij▼ becomes “1”. BI12 = "1"
If F = "0", it becomes "1". That is, when “1”
Sign bit ▲ EF if the judgment result is one-way^Four _ij▼ to “1”
I do. When the value is other than “1” and F = “0”,
When the output of C 754 reaches "0",
Sets BI12 to “0”. Also, ▲ ▼ = 1, that is,
BI12 is set to 0 when it is at the switching point. other than that
Then BI12 is the original value ▲ EF^Four _ijIt becomes ▼. BI13 = “0”,
When ▲ ▼ = 1 and F = 1, ie, the direction
If it is not judged and is not sustained, it reaches “0”
Otherwise, it is set to “1” to indicate step switching.
Flag. Write upper bits of registers A and B to RAM7
At the 8th bit, the 8th bit of the S register is
Write As described above, FIG.
The lag control circuit outputs a signal corresponding to the envelope flag ▲
▼, F ', E0 are output and the envelope
Set the lag. Envelope flag is key on
After that, usually start from step 0 (pitch envelope
The robot starts after the direction is determined.)
Is added, and the node flag ▲ EF^Five _ij▼ represents a node
The direction is determined by setting it to 0, and the sign flag ▲ EF^Four _ij▼
To start the next step. If you reach
Stinflag (envelope level EL_ij(S) MS
If B) is "1", the envelope is fixed and the envelope is fixed
Is done. Then, when the key-off comes from CPU3, the hold is released.
And start the next step. In addition, loop mode
If the Sustain flag is in the final step 7
The envelope flag is 011 * 0111 → 01101111 + 1 = 101010
000 and return to step 0, is the envelope first?
Will be repeated.   The operation circuit of FIG. 30 has been described above.
The operation circuit of FIG. 20A
Perform operations such as final envelope and synthesis keys.
-Generate code and transfer to exponential conversion / phase angle generation circuit 13
I do.   FIG. 43 is a detailed diagram of the external RAM interface 16.
You. FIG. 44 (a) shows from the interface / control unit 11,
(B) shows the RA from the envelope / key code generation circuit 12;
This is the timing of writing to M. Address signals RA0-11
Are addresses AA0 to AA1 from the interface / control unit 11.
1. Address from envelope / key code generation circuit 12
Based on each RAM occupation time (Fig. 3)
Obtained by switching with clock inverters 777-801
It is. The write enable signal ▲ ▼
Signal ▲ ▼ from the source / control unit 11 becomes “0”
(However, if the signal ID indicating the use of the internal memory is “1”
Or no envelope / key code generator
When the write signal ▲ ▼ from 12 becomes “0”,
Signal becomes “0” in the width of “0”. Also output
Enable signal ▲ ▼ is both ▲ ▼ and ▲ ▼
When it is “1”, the signal CK2 becomes “0” with a width of “0”. Data RD0
7 are signals when ▲ ▼ or ▲ ▼ is “0”.
▼ is the width of “0” and is output from the sound source LSI6.   FIG. 45 is a block diagram of the exponential conversion / phase angle generation circuit 13 shown in FIG.
It is a lock figure. Envelope / key code generation circuit 12
The envelope and keycode generated by
It is taken into the flip-flop (FF) 1000 by CKE. FF100
The output of 0 is converted by the exponent ROM1001 and the envelope register
Data 1002 and the frequency information register 1004. Fig. 46
3 is a detailed diagram of the envelope register 1002. Enbero
Loop register 1002 has two RAMs (ENVERAM, ENVORA
M), FF1014-1019, etc., inverter 1027, clock input
Inverters 102-1026, 1028-1033, etc., and inverters
Consists of 1008, 1010, Nand 1009, 1011, 48th
It operates as shown in the time chart of FIG. counter
1 (FIG. 18) is the envelope / key code generation circuit 12
This shows the basic timing of FF415-421 (Fig. 29).
The data output switches from timing 0. FF415 ~ 420
Data is envelope register 1002, frequency information register
Write channel (DA0-2) to module 1004, module
(DA3 to 5), and when T2 is 0
Only data of DA1 to DA5 (DA0 always matches the value of FF415
Yes. Also, the output of FF1000 switches as shown in Fig. 48,
Since WEE becomes “1” at timing 0, when DA0 is “0”
(Even channel) Nand 1009 becomes “0”, so T2
= “0” and the timing signal W is “1” and ENVERAM1
Data is stored at the specified address of 012 (inversion of FF416 to 420).
Written. When DA0 is “1” (odd channel)
The NAND 1011 becomes “0” and data is stored in the ENVORAM 1013
Written. When T2 is "1", addresses DA1-5 are
The outputs C1 to C5 of the timing signal generation circuit 159 (FIG. 6)
Channels and modes corresponding to the values of C1 to 5
Read data of Joule, buffers 1020 to 1026, 1028
~ 1033, inverter 1027 enables EN when T2 = "1"
When VERAM1012, T2 = "0", ENVORAM1013 to T2 =
Data read with "1" delayed by FF1014 to 1019
Output E0 to E11. Therefore, the envelope cash register
The star 1002 is a timer of the envelope / key code generation circuit 12.
Data is written by the interface, and the interface / control unit
It is read at the timing of 11, and the waveform is generated via FF1003.
Sent to Road 15.   FIG. 47 is a detailed view of the frequency information register 1004.
The operation is exactly the same as that of the rope register 1002. Read
The frequency information FI0 to FI20 via the FF1005
Sent to the accumulator (adder 1006, shift register 1007)
A phase angle is generated.   FIG. 49 is a detailed diagram of the OC register 14. OC register
14 is the envelope register 1002 and frequency information register 10
As in 04, RAM for even-numbered channels (OCERAM), odd-numbered channels
It consists of channel RAM (OCORAM) and reads it alternately.
Register that can always be read and written
You. Address AA0 ~ from interface / control unit 11
2, 4 to 6 are write addresses and C1 to C5 are read addresses
Read when T2 is “1” and write when T2 is “0”
It has become. Flip-flops 1076B-1083B, 1101-
1103, shift register 1104 provides control signals C0-3
The gates 1105-1116 are controlled by control signals C5
9 is produced.   FIG. 50 is a block diagram of the waveform generation circuit 15. Waveform
The generation circuit 15 is disclosed in Japanese Patent Application No. 61-55008 of the present applicant.
It performs almost the same operation as the circuit. First, the phase angles P0-11
FF1119 selected by selector 118, phase angle conversion circuit 112
0, input to sine wave ROM 1122 via shift register 1121
The result is a waveform signal sinX '. Note that the phase conversion circuit 1120 is
Introducing phase distortion into a sine wave according to the value of a control signal
The corresponding waveform is as shown in FIG. Waveform signal sin
X ′ is transmitted through shift register 1136, adder 1137, and FF1138.
(The output of the gate circuit 1135 is assumed to be 0)
E ″ is multiplied by the multiplier 1124 and output through the FF1125.
You. This output is a tone output if it is output as a tone.
Register (selector 1127, FF1128,
The output from the gate circuit 1129) is the selector 1130 and the gate 1131
The passed data is added / subtracted by an adder / subtractor 1126. Fig. 52
5 shows a time chart of the waveform generation circuit 15. C0 to 5 are
The counter output of the timing signal generation circuit 159 in FIG.
Figures 5 to 5 show the envelope register 1002 and frequency information
Register 1004, the read address of the OC register 14
ing. The one-bit delay is caused by the waveform forming circuit.
(Figure 50) The basic timing is 6 bits.
Lower 3 bits for channel, upper 3 bits for module
Is equivalent to the calculation of Signals P, X ', E', E ", E"
sinX ', R', R are module 0, channel 0, respectively
From the calculation of to the calculation of module 7 and channel 7
The timing of the cycle is shown. Control of waveform generation
The selectors 1118, 1127, 1130, 1132,
Gate circuits 1129, 1131, 1135, phase angle changing circuit, 1120,
This is performed by controlling the adder / subtractor 1126. Table 6
Corresponds to the upper 4 bits of OC data input from the CPU
This is shown by calculation (see Fig. 49). A waveform is generated by these arithmetic controls.   The following is an example of waveform generation. Where i is the module N
o and j are channel numbers. 1) E_{i + lj}sin (E_ijsinP_ij)   The operation code is ij ** 000000 (The upper 4 bits may be 0010) i₊₁j 101 * 0000 i₊₂j 000 **** Becomes As a result, as shown in Table 6, module i
For the waveform of channel j, P is selected as the phase angle,
Output E ″ sinX ′ is the order of module i + 1, channel j
Become a phase. Module i + 1, channel j waveform output
E ″ sinX ′ is accumulated with the musical sound output.
9 is for a waveform output with a delay of 8 bits from the phase X.
Therefore, for example, the control signal of i + 1, j
For the waveform output of channel i and channel j.
You. 2) E_{i + 2j}sin (E_ijsinP_ij-E_{i + 1j}sinP_{i + 1j})   The operation code is ij ** 000000 (The upper 4 bits may be 0010) i₊₁j 10000000 i₊₂j 111 * 0000 i₊₃j 000 **** Becomes As a result, as shown in Table 6, module i and channel
For the waveform of channel j, P is selected as the phase angle, and its output is
E ″ sinX ′ is input to the shift register 1133.
Rule i₊₁, P is selected as the phase angle for the waveform of channel j
And the waveform is subtracted from the output R of the shift register 1134.
Being a module i₊₂, Channel j.
And module i₊₂, The waveform output E ″ s of channel j
inX 'is accumulated with the musical sound output. Operation as above
The generation of various waveforms depends on the
And 9 can generate many musical tones. Output wave
The shape sequentially accumulates the generated waveforms.
When the value of ~ C5 is "9", the waveform of the new operation cycle is FF
Although it is taken into 1128 (the waveform that is not output =
), The output of FF1128 at that time is the accumulation of the waveform of the previous cycle
Because it is a value, take it in latch 1139 (CKL)
Latch 1139 causes waveform final accumulation for each operation cycle
Will output a value. The gate circuit 1140 is connected to the signal OM.
Output is all 0 (center level) when is "0"
After the reset, until the mode data is set,
maintain. That is, external reset by power-on etc.
When a signal is generated, the timing signal generation circuit 159
An internal reset signal is generated, and this is the
Switch 156 to reset its output OM to “0”.
The output of the gate circuit 1140, that is, the signal output sent to DAC8
Power is placed on silence levels all zero. On the other hand, CPU3
Tones, etc. in the external RAM 7 through the interface / control unit 11
Set the required data for
Mode latches 156 to 158.
As a result, OM becomes “1” and the gate circuit 1140 is enabled.
The waveform signal calculated by the waveform generation circuit 15 is sent to the DAC 8
Will be able to In other words, after turning on the power,
When the required data settings are completed, the tone generator LSI 6
Until the signal can be synthesized, the input to DAC8 is silent.
It is maintained at the level. [The invention's effect]   As described above in detail, in the present invention, the envelope
Use envelope flags to control rope progress
Freely write this envelope flag using the CPU.
That can be achieved with the prior art.
Highly flexible envelope control and sound control
Ability to make the performance of the performance input device more dynamic.
Can be reflected in the musical sound. For example, when the pronunciation starts
Different envelope depending on initial touch size
You can start playing the envelope from a step
Wear. In addition, the playing state that can occur at any time during
Envelopes stay sustained in response to changes
Or go to another step.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an overall configuration diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a block diagram of a sound source LSI, and FIG. 3 is an interface unit and an envelope / key code of the sound source LSI. 4th time chart showing allocation of external RAM occupation by generation circuit, 4th
FIG. 5 is a time chart of data and a write control signal sent from the CPU to the interface / control unit of the tone generator LSI. FIG. 5 shows a low-speed operation cycle for generating a tone control signal and a high-speed operation cycle for generating a waveform. FIG. 6 is a detailed diagram of an interface / control unit, FIG. 7 is a time chart of a part of a signal generated by a timing signal generation circuit, FIG.
FIG. 9 is a time chart of other signals generated by the timing signal generation circuit, FIG. 9 is a detailed view of the timing signal generation circuit, FIG. 10 is a detailed view of the instruction decoder,
FIG. 11 is a time chart showing the operation of the interface / control unit for the transfer instruction of 1-byte data, FIG. 12 is a time chart showing the operation of the interface / control unit for the transfer instruction of the 2-byte data, and FIG. FIG. 14 is a time chart showing the operation of the interface / control unit for the flag set instruction. FIG. 14 is a time chart showing the operation of the interface / control unit for the key-off instruction. FIG. 15 is an interface / control diagram for the write instruction to the OC register. 16 is a time chart showing the operation of the control unit, FIG. 16 is a time chart showing the operation of the interface / control unit with respect to the mode setting instruction, FIG. 17 is a block diagram of the envelope / key code generation circuit, and FIG. Detailed view of the counter B to provide an operation cycle of Beropu / key code generating circuit, the time chart of Figure 19 is the counter B, the 20A diagram flow chart of the operation according to the envelope / key code generating circuit,
FIG. 20B is a diagram summarizing the operation of the envelope / key code generation circuit, FIG. 21 is a graph showing amplitude modulation generation data given from the CPU, FIG. 22 is a detailed diagram of an operation timing signal generation circuit, and FIG. The figure is a detailed diagram of a clock generation circuit, FIG. 24 is a detailed diagram of an operation address generation circuit, FIG. 25 is a detailed diagram of an operation control signal generation circuit, FIG. 26 is a time chart of the operation control signal generation circuit, No.
FIG. 27 is a detailed diagram of the write inhibit circuit, FIG. 28 is a time chart showing the operation of the write inhibit circuit, FIG. 29 is a detailed diagram of the exponent data address generation circuit, FIG. 30 is a detailed block diagram of the arithmetic circuit, FIG. 31 is a detailed view of the A register, and FIG. 32 is B
Figure 33 is a detailed view of the register. Figure 33 is a detailed view of the M register.
The figure is a detailed view of the shift control circuit, FIG. 35 is a detailed view of the envelope control circuit, FIG. 36 is a detailed view of the data change circuit, and FIG.
FIG. 37 is a detailed diagram of a code generation circuit, FIG. 38 is a graph showing pitch envelope inversion by a flag, FIG. 39 is a detailed diagram of an adder / subtracter and an output clip circuit, FIG. 40 is a detailed diagram of a flag generator circuit, and FIG. Figure 41 is a detailed diagram of the output clip control circuit,
FIG. 42 is a detailed diagram of an S register and an envelope flag control circuit, FIG. 43 is a detailed diagram of an external RAM interface, and FIG.
The figure is a time chart showing the operation of the external RAM interface, FIG. 45 is a block diagram of the exponential conversion / phase angle generation circuit,
FIG. 46 is a detailed view of the envelope register, FIG. 47 is a detailed view of the frequency information register, FIG. 48 is a time chart of the exponential conversion / phase angle generation circuit, FIG. 49 is a detailed view of the OC register, and FIG. FIG. 51 is a detailed diagram of the waveform generation circuit, FIG. 51 is a waveform diagram showing a set of sine waves in which distortion is generated by a control signal in the waveform generation circuit, and FIG. 52 is a time chart of the waveform generation circuit. 1 ... keyboard, 2 ... switch, 3 ... CPU, 7 ... RAM,
11: Interface / control unit, 12: Envelope /
Key code generation circuit, 15: Waveform generation circuit, 436: A
Register, 437 ... B register, 442 ... M register, 44
7 shift control circuit, 438 shift circuit, 449 code generation circuit, 440 adder / subtractor, 441 output clip circuit, 451 output clip control circuit, 446 envelope flag control circuit, 302 ...... Write-inhibit circuit, 213-226
... Key-off processing unit.

Claims (1)

(57) [Claims] A memory (7), which is controlled by a CPU (3) for monitoring a playing state and synthesizes a musical tone in accordance with the playing state, responds to a command or a command from the CPU and its accompanying data in a predetermined area of the memory. An interface circuit (11) for writing data to the memory, a tone control signal generation circuit (12) for generating a tone control signal such as an envelope using data in the memory, and a tone control signal generated by the tone control signal generation circuit. And a waveform generating circuit (15) for generating a musical tone waveform in accordance with a signal. The memory includes, as a part thereof, (a) an envelope to be written, which is written by the CPU via the interface circuit. Envelope calculation parameters (ER _ij , EL _ij ) for each step of the waveform
(B) an envelope current value memory for storing the current value (E _ij ) of the envelope waveform, and (c) an envelope flag (EF _ij ) including the step information of the envelope waveform. An envelope flag memory, wherein the tone control signal generation circuit includes: (d) an envelope flag read circuit for reading an envelope flag from the envelope flag memory; and (e) a step indicated by step information included in the read envelope flag. A parameter readout circuit for reading envelope calculation parameters (ER _ij (s), EL _ij (s)) from the envelope calculation parameter memory; and (f) reading an envelope current value from the envelope current value memory and reading the read envelope. For calculation An envelope generating circuit for performing an arithmetic operation with the parameter to update the envelope current value, outputting the updated result as a tone control signal, and saving the updated result in an envelope current value memory; and (g) according to the result of the arithmetic operation by the envelope generating circuit. , Update the read envelope flag as appropriate,
An envelope flag updating circuit for saving the updated envelope flag in the envelope flag memory, (h) a flag setting instruction is included in an instruction from the CPU to the interface circuit, and (i) the interface circuit includes: In response to the flag set command, an optional envelope flag, which is data attached thereto, is written to the envelope flag memory, and the envelope flag updating circuit updates the envelope flag updated according to the result of the operation, to the envelope flag memory. A musical sound synthesizer characterized in that it is configured to write in a musical tone. 2. 2. The musical tone synthesizing device according to claim 1, wherein said musical tone control signal generating circuit is configured to execute said envelope flag by said envelope updating circuit when said envelope flag memory is rewritten by a flag setting instruction of said CPU. A tone synthesizer comprising a prohibition circuit (302) for temporarily prohibiting rewriting of a memory. 3. The musical sound synthesizer according to claim 1, wherein a key-off instruction is included in an instruction from said CPU to said interface circuit, and said interface circuit comprises:
In response to the key-off command, a musical sound synthesizer comprising a key-off processing circuit (213 to 226) for reading an envelope flag from the envelope flag memory, changing the envelope flag according to the value, and returning the envelope flag to the envelope flag memory. 4. 2. The musical sound synthesizer according to claim 1, wherein said memory further includes a high release memory for storing high release data (HR _ij ) for attenuating an envelope at a high speed. When a high release flag set instruction is given as a set instruction, the interface circuit writes an envelope flag indicating high release data, which is data accompanying the high release flag set instruction, to the envelope memory, and reads the parameter. If the circuit indicates that the read envelope flag indicates high release data,
A musical sound synthesizer for reading high release data from the high release memory in place of the envelope calculation parameter memory. 5. 2. The musical tone synthesizer according to claim 1, wherein said envelope calculation parameters comprise an envelope plate (ER _ij ) and a target level (EL _ij ). 6. 2. The musical tone synthesizer according to claim 1, wherein said waveform generating circuit generates a musical tone waveform of each of a plurality of tone generation channels by a time-division operation of a plurality of modules. A musical sound synthesizer characterized by receiving a key code and an envelope for each module provided from a signal generation circuit. 7. 7. The tone synthesizer according to claim 6, wherein the envelope flag memory and the envelope current value memory respectively store an envelope flag and an envelope current value for each sounding channel and for each module, and the envelope calculation parameter memory includes: A musical tone synthesizer characterized by storing parameters for envelope calculation for each sound channel, each module, and each envelope step. 8. In tone synthesis apparatus according to paragraph 1 the claims, the envelope flag, (i) an envelope of step (EF ⁰ ~EF ^2), and a flag indicating whether (ii) envelope hold state (EF ³ ) A tone synthesizer characterized by including the information of ³ ). 9. In tone synthesis apparatus according to paragraph 1 the claims, the envelope flag, (i) an envelope of step ^{(EF 0 ~EF 2), (} ii) an envelope a flag indicating whether the hold state (EF ³⁾ , (Iii) the direction of the envelope (EF ⁴ ), (iv) a flag indicating whether the envelope is at the node of the step (EF ⁵ ), and (v) the mode of the envelope (EF ⁶ , EF ⁷ ). A tone synthesizer characterized by the following. 10. 2. The musical tone synthesizer according to claim 1, wherein the envelope flag updating circuit is a step which is step information of the envelope flag when it is determined that a certain step of the envelope waveform is completed as a result of the calculation. A tone synthesizer comprising means for incrementing a number. 11. In tone synthesis apparatus as claimed in Claims paragraph 10 claims, the envelope flag updating circuit, upon completing step of the envelope waveform, the node flag indicating that the envelope waveform is in the node a (EF ⁵⁾ set the envelope flag Further comprising means for determining the direction of the envelope waveform in the next step.