JPH0738955Y2 - Music synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a musical sound synthesizer, and more particularly to a pitch envelope (frequency envelope) control technique.

[Background of the Invention] The pitch envelope in a musical tone synthesizer is a parameter that basically determines the time variation characteristic of the pitch of a generated musical tone.

As a recent technology, in such a pitch envelope,
There are attempts to reflect touch response and key scaling. That is, data such as touch response is used as change data for the target value of the pitch envelope. Here, the target value or pitch envelope level is represented by EL, and the level change data is EL
Expressed as C, the pitch envelope level EL after the change
(Change) is calculated by EL (change) = EL-ELC (Equation 1).

When ELC is used as touch response data, ELC takes a smaller value when the touch is stronger. Initially, assuming that the pitch is at the center level, that is, at the reference pitch assigned to the key, when EL is higher than this center level, (Equation 1)
According to, the stronger the touch, the higher the target value EL (change)
Is set, the pitch fluctuation range becomes wider as the touch becomes stronger. On the other hand, if EL is lower than the central level,
The weaker the touch, the lower the target value EL (change) is set, and the stronger the touch, the less the decrease in pitch. This is unnatural from a sensory point of view, and there is a problem that it is difficult to operate when the pitch is swung by touch.

[Object of the Invention] The present invention has been made in view of the above background, and an object thereof is to provide a musical sound synthesizer in which a touch response or the like is naturally reflected in a pitch envelope.

In order to achieve the above object, this invention increases the pitch envelope by the pitch envelope change data such as touch response when the pitch envelope level given from the CPU to the sound source side is lower than the center level. It is characterized in that level changing circuit means is provided for changing the direction to the direction, and when the pitch envelope level is higher than the center level, changing the direction in the direction to decrease the pitch envelope level by the pitch envelope level changing data.

[Operation and Development of the Invention] According to this invention, the pitch envelope level, which is the target value of the pitch, is changed toward the center level by the pitch envelope change data with the center level as the axis of symmetry. Therefore, when the pitch envelope change data is the touch response data, the pitch farther from the center level, which is the reference pitch level of the key, is set as the target value when the touch is stronger, which gives a natural feeling. Touch operation can be performed.

In the claims for utility model registration, starting from the first paragraph, reference numerals are entered in parentheses after each constituent element, which is the reference numeral of the corresponding element in the illustrated embodiment described later. ing. Of course, this does not mean that the present invention is limited to the embodiments, but merely shows the correspondence.

For example, EL _pj (S) ← EL _pj (S) + ELC in the first term
The expressions _pj and EL _pj (S) ← EL _pj (S) −ELC _pj are examples, and instead of this, for example, instead of the change data ELC _pj ,
Modified data with weighting factors may be used.

The second term describes circuit means for limiting the changed pitch envelope level to the center level when the center level is crossed. This limiting circuit means is a particularly effective means in the case of a normal performance in which the pitch is not changed.
In this case, if the central level pitch envelope level is given from the CPU, the pitch envelope after modification by the modification data will cross the central level,
By the function of the limiting circuit means, the reference pitch of the key is maintained by being fixed at the center level.

The configuration of the third term can bring about a pseudo portamento effect. That is, if the value in the key pressing direction is set to the flag described in the same paragraph, for example, when the key is pressed last time, the pitch is raised from the center level, and when the key is pressed high this time. , By raising the pitch toward the center level, the portamento effect will be applied.

[Embodiment] FIG. 1 is a functional diagram of an electronic musical instrument according to the present invention. The CPU3 is a general-purpose microcomputer, which scans the keyboard 1 and the switch 2 to detect key depression and tone color selection according to the control program, and generates tone color data and sound control data using the ROM4, RAM5, etc. arranged on the bus. And control the pronunciation of the sound source LSI. Sound source LSI
As will be described later in detail, 6 generates a musical sound by using the external RAM 7 as a calculation buffer for musical sound generation, and transfers it to a DAC (digital-analog converter) 8. The tone signal is converted into an analog signal by the DAC 8, amplified by the amplifier 9, and sounded by the speaker 10.

FIG. 2 is a block diagram for explaining the operation of the tone generator LSI 6 to which the present invention is applied. The tone generator LSI 6 uses the RAM 7 as a tone color data memory or a calculation progress data memory in order to generate a key code including an amplitude envelope and a pitch variation. In addition, RAM7, as shown in FIG.
The interface / control unit 11 (interface occupancy time) and the envelope / key code generation circuit (arithmetic circuit occupancy time) are alternately occupied every 0 nsec to deal with access from the CPU for writing data and computing envelopes and the like.

First, the operation of the interface / control unit 11 will be described. CP
U3 transfers tone color data or tone generation control data to the tone generator LSI6, and the tone generator LSI6 takes in the data on the data buses DB0 to DB7 at the rising edge of ▲ ▼ when ▼ is LOW. At that time, if / D is LOW, data bus DB0
~ DB7 data is taken as an instruction, and if / D is HIGH, it is taken in as data attached to that instruction (see Fig. 4). The instruction indicates the type of data that is subsequently transferred. interface/
The control unit 11 receives instructions and data from the CPU3, generates addresses AA0 to 11 of the RAM7 and write signals ▲ ▼ corresponding to the instructions, and stores the data transferred to the external RAM7 via the external RAM interface 16. To do. However, if the data transferred from CPU3 is special, it is stored in the internal memory. For example, when the transferred data is an operation code (control data for waveform generation), writing to the external RAM 7 is prohibited, and a write signal WO to the OC register 14 is generated, so that the data is written to the OC register. Be done.

The envelope / key code generation circuit 12 uses addresses BA0 to 11 to access the data written in the external RAM 7.
And write signal for envelope calculation progress data, etc.
Generate ▼. As a result, based on the tone color data (envelope rate / level, etc.) of the external RAM7, a key code (hereinafter called a synthetic key code) that includes amplitude envelope or pitch fluctuation is generated according to the tone generation control data (key code, modulation, etc.). And bus L2
Through 14 to the exponential conversion / phase angle generation circuit 13 in a time division manner.

The exponential conversion / phase angle generation circuit 13 exponentially converts the amplitude envelope and the composite key code from the envelope / key code generation circuit 12 by sharing one exponential converter in a time division manner. The exponentially converted amplitude envelope (exponential envelope) and the exponentially converted composite key code (frequency information) are temporarily stored in the envelope register and the frequency information register, respectively. These are used as interface buffers for accessing the external RAM 7 to generate an amplitude envelope and a synthetic key code and performing exponential conversion at low speed, and for performing subsequent arithmetic processing at high speed. Fig. 5 shows the time relationship between the two calculation processes. The low-speed calculation cycle is the high-speed calculation cycle.
Is doubled. This is because the change rate of the output waveform must be twice the audible frequency or more, so the waveform calculation is performed at high speed (about 40 KHz in this embodiment), and the other calculations are performed at low speed according to the access to the external RAM 7. Because it is.

The exponent envelope stored in the envelope register is read in correspondence with the high speed operation and transferred to the waveform synthesizing circuit 15 as envelopes E0 to E11. The frequency information stored in the frequency information register is read and accumulated in correspondence with the high-speed operation, and the waveform information is generated as the phase angle data P0 to 11 in the waveform generation circuit.
Transferred to 15.

The waveform generation circuit 15 is based on the operation codes OC0 to 7 read from the OC register 14, and in accordance with the envelopes E0 to 11 and the phase angle data P0 to 11 transferred from the exponential conversion / phase angle generation circuit 13, the tone waveforms O0 to O15. Is generated and output to DAC8.

FIG. 6 is a circuit diagram of the interface / control unit 11. First, the timing signal generation circuit 159 will be described. The timing signal generation circuit 159 divides the basic clock φ _M (10 MHz) to generate a necessary timing signal as shown in FIGS. 7 and 8, and a reset signal from the outside ▲ ▼
From the internal reset signal. FIG. 9 shows an embodiment thereof. The basic clock of 10 MHz is divided by the flip-flop 233 and the inverter 235 to generate S0, and the flip-flop 234 further generates T0. Further, AND 237 generates φ ₁ , and the flip-flop 23
V ₁ and W ₁ are generated by 9,240. Further, T1 is generated by the flip-flop 243. From these signals, inverters 242, 245, ANDs 244, 246 to 248 generate W, ▲ ▼, ▲ ▼, CK1 and CK2 (seventh example).
Figure). The counter A: 249 is a binary counter that divides the clock CK2 and changes at the rising edge of CK2. Of the counter outputs, Q _{1 to} Q ₅ are used as address signals C _{1 to} C ₅ for reading, and the envelope / key code generation circuit 12 and the OC register
It is output to 14. Also, the timing signals T2, T3, CKP, CKQ, CKW, CKR are generated from the counter outputs Q ₀ , Q ₁ by the two-phase flip-flops 250, 251, the flip-flop 252, the inverter 253, and ANDs 254-1 to 254-4. (8th
Figure). Inverters 255-1 to 3, OR 256, and
From 257, ▲ ▼ and CKL are generated (Fig. 52). Further, CKRT is generated by AND 258 from CARRY OUT (“1” when the count value is 127) of the counter A: 249, and this signal is used as a clock for sampling the reset signal from the outside. Flip-flop by clock CKRT
When the reset signal is sampled by 260 and 261 and the external reset signal is detected twice by AND 262, the internal reset signal is generated. Therefore, the internal reset signal becomes as shown in FIG. At that time, since the counter B303 in FIG. 17 is a synchronous reset counter, the operation after reset is performed as shown in FIG.

Next, the operation of the interface / control unit 11 that interfaces the CPU 3 and the external RAM 7 which is the data memory of the tone generator LSI 6 will be described. Table 1 shows the instructions and data transferred from the CPU3 and the corresponding addresses of the external RAM7.

Since the tone generator LSI 6 has eight sound generation channels and eight sine wave generation modules for each sound generation channel, the envelope / key code generation circuit 12 has 72 amplitudes including the pitch envelope for each sound generation channel. Envelope, 64 synthetic keycodes must be generated. Therefore, the data is for each channel (jjj =
Data of each module (0iii = 0 to 7) must be transferred to 0 to 7). However, 9 pieces of data (jjjj = 0 to 8) including the pitch are transferred as data related to the envelope. It is common to each module that only one data is sent.

In Fig. 6, ▲ ▼, / D, ▲ ▼, CPU0 for DB0-7
However, when the signal is input as shown in Fig. 4, the inverters 100 to 103, NAND 104, 105
▼ and ▲ ▼ occur. When the signal {circle over ()} is generated, the data on the buses DB0 to DB7 are taken into the latches 146 to 153 via the inverters 106 to 113 at the rising edge of {circle around ()}, and the counter 191 and the flip-flops 186, 192 to 195 are reset. The outputs of the latches 149 to 153 are input to the instruction decoder 154, which generates the necessary control signals. Instruction decoder is the 10th
As shown in the figure, it is composed of inverters 265 to 267, NANDs 269 to 277, and 278, and each signal is as shown in Table 2.

For example, for frequency ratio instructions, WB
And WT become logic "1" (WB = "1", ▲ ▼ = "0") First, of the data written to the external RAM7, 1 byte of data for each module of each channel (high release rate, Modulation sensitivity, envelope rate change, envelope level change, envelope rate,
The envelope level) write operation will be described (see FIG. 11). In response to the instruction write from the CPU 3, the signal ▲ ▼ becomes “0”. At that time, bus DB0
The instructions of ~ 7 are inverted by the inverters 106-113 and taken into the latches 146-153, and the counter
191, flip-flops 192-195, and 186 are reset. Then, the output WB of the instruction decoder 154 becomes "0", so the output of the NAND 172 becomes "1" at all times.
Since ▲ ▼ is "1", CK12 becomes CKQ by OR 168, 170, and 169. Next, when the signal ▲ ▼ changes from “0” to “1” by the data writing from the CPU 3, the flip-flop 173 outputs “1” at the rising of ▲ ▼, and the output of the flip-flop 174 becomes “1”. . After that, since the flip-flops 173 and 175 are reset in synchronization with CKR, only one section of CKR becomes "1". Further, the output ▲ ▼ of the instruction decoder 154, the IDs are “1”, “0”,
Is "0", so signal ▲ ▼ is "1" and T2 is "0" by OR 178, 179, inverters 180, 181, and NAND 182.
When it is, it becomes "0". At that time, the output ▲ ▼ of the instruction decoder 154 and WB are “1” and “0”, so NOR 161
Output becomes "1" only when ▲ ▼ is "0" and ▲ ▼ is "0", and clock inverters 122-129 of buses D0-7
Is output. In the counter 191, since the output ▲ ▼ of the instruction decoder 154 is "1", the CKQ when is "1" becomes the clock CKC, and the value is incremented by 0, 1, 2, ... for each CKC. Flip-flops 192 to 195 and inverters 196 to 199 invert twice to become addresses AA0 to AA3 representing module numbers. Address aa
4 to AA6 are lower 3 of instruction latches 146 to 153
Value "jj" that represents the channel number because it is a bit inversion
Also, the addresses AA7 to AA11 are the outputs EF and WB of the instruction decoder 154, and the addresses 204 to
The right input of the ORs 205 and 207 is “0”, the right input of the ANDs 209 and 211 is “1”, and the left input of the OR 203 is “0”. Therefore, the upper 5 bits of the instruction latches 146 to 153 are inverted,
It is the upper 5 bits of the instruction itself. As described above, in the case of writing 1-byte data for each module of each channel, a signal for writing as shown in FIG. 11 is generated for an address matching the instruction. Here, the identification of each channel is made by the lower 3 bits of the instruction, but the identification of the module is made by multiplying by the counter 191 what number data is after the instruction transfer. Therefore, in the continuous transfer format in which one instruction is followed by a plurality of data, which data is for which module is automatically identified by the interface / control unit 11. Therefore, the CPU 3 needs to send instructions for each module. But the transfer efficiency goes up.

Next, of the data written to the external RAM 7, the writing operation of 2-byte data (frequency ratio, key code, modulation level / rate, pitch modulation) for each module of each channel will be described (see FIG. 12).
In response to instruction writing from CPU3,
▼ becomes 0, so that the instruction is captured in the latches 146 to 153 and the counter 191,
The flip-flops 186, 192-195 are reset. Since the output of the flip-flop 176 is "0", the upper input of the NAND 172 is "1" and the instruction decoder 154
Output WB is "1", the output of NAND 172 is "0", and the inputs of Noah 167 are both "0".
CK12 becomes CKQ by 8,170, and169. When ▲ ▼ changes from “0” to “1” by writing data from the CPU3, the flip-flops 114 to 121 take in the data, the flip-flop 175 outputs “1”, and the flip-flop 176 outputs “1”. The inverter 171 becomes "0", and the output of the NAND 172 becomes "1". At that time, the upper input of Noah 167 is "1"
So CK12 becomes CKW. Again ▲ ▼ is “0” → “1”
Then, the flip-flops 130 to 137 take in the data of the previous stage, the flip-flops 114 to 121 take the data of the bus, and the output of the flip-flop 173 becomes "1" and the output of the flip-flop 174 also becomes "1". . When becomes 1, the flip-flops 173 and 175 are reset, so that becomes only 1 in two sections of CKR (∵CK12 = CKW).
The output ▲ ▼ of the instruction decoder 154 is “1” and the ID is “0”, so the output of the NAND 182 ▲ ▼
Is "1", T2 is "0", that is, "0" twice. Also, because WB is “1”, ▲ ▼ is “0” and T3
When is “0”, the width of ▲ ▼ is “0”.
122 to 129 output data, ▲ ▼ is “0” and T3 is “1”
When ▲ ▼ is “0”, the clock inverters 138 to 1
45 outputs the data. Since the data is written from the CPU in the order of lower (level) and upper (rate),
Data is output to the buses D0 to D7 in the order of higher (rate) and lower (level), and input to the external RAM 7. Counter 191
, The output ▲ ▼ of the instruction decoder 154 is "0", but the CKW when it is "1" becomes the clock CKC, and is stepped to 0, 1, 2, ... to become addresses AA0 to AA3 representing the module number. . Since the addresses AA4 to AA6 are the inversions of the lower 3 bits of the instruction latches 146 to 153, they have the value "jjj" indicating the channel number. Also,
Addresses AA7 to AA11 are instruction decoder 154
EF is “0” and WB is “1”, so when T3 is “0”, the upper 5 bits of the instruction that sets AA7 to “0” become T3.
When is "1", AA8 to 11 are the upper 4 bits of the instruction and AA7 is "1". That is, the first of 2-byte data
The distinction between the byte address and the second byte address is made by switching AA7. The channel identification and the module identification are the same as in the case of writing 1-byte data for each channel and module. As is apparent from the above description, according to the present embodiment, the interface / control unit 11 has a means for identifying the byte configuration of the transfer data based on the instruction, and therefore, the CPU 3 causes the tone generator LSI 6 to It is possible to perform data transfer in a variable format in which a variable byte-structured data follows the instruction, and optimum transfer efficiency without dummy data can be achieved.

Next, the instruction “flag set” will be described (see FIG. 13). “Flag set” is an instruction to set the envelope flag in the external RAM 7. The process up to signal generation is exactly the same as for 1-byte data. Since the output EF of the instruction decoder 154 is "1", when is changed from "0" to "1", the output of the AND 183 is changed to "1", and when the ▲ ▼ is changed to "0", the flip-flop which has been reset. The output of group 186 is "1". Further, since the output (1) of the instruction decoder 154 is "1", the clock CKC of the counter 191 coincides with CKQ while "1", and the counter 191 is incremented. The value of counter 191 is 9
Then, the flip-flop 186 is reset by the OR 184 and the NAND 185 in synchronization with CKR.
▼ to ▲ ▼ becomes “1” during 0 to 8 (9 sections of CKR), and the output ▲ ▼ of the NAND 182 becomes “0” when T2 for each count value is “0”. At that time, since the output ▲ ▼ of the instruction decoder 154 and WB are “1” and “0”,
The output of Noah 161 becomes "1" only when ▲ ▼ "0" and ▲ ▼ is "0", and the clocked inverter is connected to buses D0-7.
The output of 122 to 129 is output. The addresses AA0 to AA3 are the value of the counter 191, the addresses AA4 to AA6 are the instruction "jjj", and AA7 to AA11 are EF "1" and WB "0", so "001".
10 ". Therefore, in the instruction" flag set ", the same data is automatically written in modules 0-8.

Next, the instruction “key off” will be described (see FIG. 14). When the signal ▲ ▼ becomes “0”, the instructions are taken into the latches 146 to 153 and
The counter 191, the flip-flops 186, 192-195 are reset. The output WB of the instruction decoder 154 is "0", so it is "1", the output of the NOR 167 is "0", ▲ ▼
Is "0", the output of OR 168 is "0", therefore CK12
Matches CKW. When ▲ ▼ changes from “0” to “1”,
The data is taken into the flip-flops 114 to 121, and the flip-flop 173 outputs "1", which becomes "1". When becomes 1, the flip-flops 173 and 175 are reset, so that becomes only 1 in two sections of CKR.
Also, the output EF of the instruction decoder 154 is “1”.
Therefore, the output of the AND 183 is "1" when the output is "1", and the output of the flip-flop 186 is "1". ▲
Since ▼ is “0”, the clock CKC of the counter 191 coincides with CKW while is “1”, and the counter 191 is incremented. When the value of the counter 191 reaches 9, the flip-flop 186 is reset in synchronization with CKR.
▼ becomes "1" between 0 and 8 (18 sections of CKR), =
Under "1", the output ▲ ▼ of the NAND 182 becomes "0" when T2 is "0" and T3 is "1" because ▲ ▼ is "0". At that time, since EF is “1”, addresses AA0-A
A11 is “00110jjjiiii”, but is “1” and T3 is “0”,
When T2 is "0", the data is being read from RAM7. Flip-flops 213 to 216 take in the lower 4 bits of the data with CKP, and if the value is "* 000", "0"
If "0 ***" is set to 0000111 "," 1abc "is set to" 00000111 "
Then, "00000abc" when T3 is "1" and T2 is "0" ▲
▼ is output to buses D0 to 7 with a width of "0" (however, a,
b and c are arbitrary binary numbers). As will be described later, the instructions “flag set” and “key off” are used to rewrite the data “envelope flag” in the RAM 7.
Here, the data "envelope flag" indicates the current state of the step of the envelope and the like, and the lower 3 bits are the step (0 to 7) and the 4th bit is a bit indicating whether or not the sustain is being performed. That is, the instruction "flag set" is an instruction for directly writing the envelope flag from the CPU 3, and the envelope can be started from any step by the lower 3 bits of the data.
Also, by setting the fourth bit to the sustain value "1" and resetting the envelope flag, the envelope can be held from a desired time point. The instruction "key off" is an instruction to reset the data according to the data of the current envelope flag.
If it is (0000), or if the envelope has not reached the end (1000) and the sustain level has not been reached, proceed to the final step 7 (0111). If at the sustain level (1abc), cancel sustain (0abc). It is like this.

Next, writing to the OC register will be described (Fig. 15). The write operation is almost the same as the 1-byte data, but the output ID of the instruction decoder 154 becomes "1", so the final write signal ▲ ▼ to the RAM 7 is not generated (see FIG. 43).
The write signal WO to the OC register is generated at the same timing as when ▲ ▼ is "0", and when T2 = "0", ▲ ▼ =
When it is “0”, the operation code stored in the flip-flops 114 to 121 passes through the gates 122 to 129 and OC.
Input to register. Finally, writing to the latches 156 to 158 (mode) occurs similarly to the above, but since the output ID of the instruction decoder 154 becomes "1", the RAM7
To the flip-flops 114 to 116 is taken into the latches 156 to 158 at the falling edge of the latched signal MLT at the same timing as the writing of ▲ ▼ to "0". (See Figure 16).

FIG. 17 is a block diagram of the envelope / key code generation circuit 12. The envelope / key code generation circuit 12
To generate amplitude envelope and synthetic key code
The following operations are performed while accessing RAM7.

Envelope rate (envelope slope data)
Is changed by the data "envelope rate change" corresponding to the key range or key touch.

The envelope level (target data of each step of the envelope) is changed by the data "envelope level change" corresponding to the key range or key touch.

An envelope is generated according to the changed envelope rate and envelope level.

Amplitude modulation data corresponding to aftertouch, LFO, etc. is interpolated and calculated as an amplitude envelope to generate a final amplitude envelope.

Pitch modulation data corresponding to vendors, LFOs, etc. is calculated as a pitch envelope.

A key code and a pitch envelope with modulation are calculated, and a frequency ratio representing a frequency ratio of each module is calculated to generate a final synthesized key code.

In order to realize these, the envelope / key code generation circuit 12 uses a common arithmetic circuit 308 as shown in FIG. It controls addition and subtraction. However,
One of the upper outputs of the M, S register and B register is selected. In FIG. 17, the counter B303 forms a basic cycle of calculation, and FIG. 18 shows its circuit diagram.

Counters 1 to 3: 309 to 311 are cycle reset counters and correspond to operation cycles, channels, and modules, respectively. Counter 1: 309 is a decimal counter of 0 to 19 when BC11 is 0, 32 decimal counter of 0 to 31 when BC11 is 1, and counter 2: 310 is stepped every time counter 1: 309 makes one cycle. The octal counter, counter 3: 311, is a 9-ary counter that is incremented each time the counters 1 and 2 make one cycle. The counter
As for the value of 3: 311, 0 to 7 correspond to modules 0 to 7, and 8 corresponds to pitch. FIG. 19 shows the operation cycle of the envelope / key code generation circuit 12.

FIG. 20A shows a flow for explaining the outline of the operation of the envelope / key code generation circuit 12. Where A; A register, A ^M ; A register upper, A ^L ; A register lower, B; B register, B ^M ; B register upper, B ^L ; B register lower, M; M register, S; S register , F1; a flip-flop fetched by CKF1 and F2; a flip-flop fetched by CKF2. Further, EF _ij ; envelope flag i = 0 to 8 (module, pitch), j = 0 to 7 (channel) ER _ij (S); envelope rate i = 0 to 8 (〃), j = 0 to 7 (〃 ), S = 0 to 7 (envelope step) ERC _j ; envelope rate change j = 0 to 7 (〃) ▲ E ^M _ij ▼; envelope upper level i to 8 (〃), j = 0
~ 7 (〃) ▲ Ei ^L _ij ▼; Lower envelope i = 0 to 8 (〃), j = 0 to 7 (〃) EL _ij (s); Envelope level i = 0 to 8 (〃), j = 0 ~ 7 (〃), s = 0 to 7 (〃) ELC _ij ; envelope level change i = 0 to 8 (〃), j = 0 to 7 (〃) ▲ AMD ^M _j ▼; upper amplitude modulation j = 0 7
(〃) ▲ AMD ^L _j ▼; 〃 Lower j = 0 to 7
(〃) ▲ PMD ^M _j ▼; Higher pitch modulation j = 0 to 7
(〃) ▲ PMD ^L _j ▼; 〃 Lower j = 0 to 7
(〃) MS _ij ; Modulation sensitivity i = 0 to 7 (module), j = 0 to 7 (〃) ▲ KC ^M _j ▼; Key code higher j = 0 to 7 (〃) ▲ KC ^L _j ▼; 〃 Lower j = 0 to 7 (〃) ▲ PE ^M _j ▼; pitch envelope upper j = 0 to 7 (〃) ▲ PE ^L _j ▼; 〃 lower j = 0 to 7 (〃) ▲ FR ^M _ij ▼; frequency ratio upper i = 0 to 7 (〃), j = 0
~ 7 (〃) ▲ FR ^L _ij ▼; 〃 Lower i = 0 to 7 (〃), j = 0
-7 (〃) ▲ MR _j ▼; Modulation rate j = 0 to 7 (〃) ▲ ML _j ▼; Modulation level j = 0 to 7 (〃). In the flow of FIG. 20A, the numbers on the left side mean the timings, 0 to 11 are the values of the counter 1 itself, and 1P to 19 are the values of the counter 3 are 8.
Counter 1 values other than (pitch calculation) 12 to 19,
12P to 19P correspond to the values 12 to 19 of the counter 1 when the value of the counter 3 is 8 (pitch calculation).

The flow of FIG. 20A will be described. First, at timing 0, the envelope flag; EF _ij is loaded from the RAM 7 into the S register. Here, the data structure of the envelope flag is as follows.

1) Lower 3 bits of S register (envelope step)
Corresponding envelope rate; ER _ij (s) is loaded in the upper register A, 2) Envelope rate change; ERC _j is loaded in the upper register B (both A and B are loaded with 0),
3) Add them and change the envelope rate,
Store in register. At the same time, load the upper envelope current value into the A register upper register (lower register is 0) 4).
Next, the lower order is loaded into the lower order of the A register, and 5) the envelope is updated by adding / subtracting the current value of the envelope according to EF ₄ with the changed envelope rate, and stored in the B register. Further envelope level;
EL _ij (s) to A register upper (0 to lower), 6) M
Load envelope level change; ELC _ij into the register, 7) add and subtract them to change the envelope level, and store in A register. The eighth bit of the envelope level set in F1; EL _ij (s) ⁷ is a sustain point flag. At that time, amplitude modulation; AMD _j (when calculating modules 0 to 7) or pitch modulation; PMD _j (when calculating pitch) is loaded in the M register. 8) Next, the updated envelope is subtracted from the changed envelope level, and it is determined whether the envelope has reached the target value (at that time, the lower register of A register is loaded with lower _j of AMD _j or PMD _j ). ). If the envelope has not reached the target value, F '= "0", and the envelope flag (S register) is not updated, and the updated envelope value stored in the upper register of the A register is not updated. Write the upper address to the address corresponding to the upper envelope of RAM7; ▲ E ^M _ij ▼. If the envelope has reached the target value,
F ′ = “1”, 9F ′) The lower 3 bits representing the step of the envelope flag 7 (S register) are updated (1 + S), the “node” bit is set to “0”, and the sustain flag; EL _ij ( s) If ⁷ is "1", the "hold" bit is set to "1" and stored in the upper register A register. At that time,
The changed envelope level value is loaded into the B register as the envelope value, and is written in the address corresponding to the envelope upper level; ▲ E ^M _ij ▼ in RAM7. 1
0) then reached, in either case of non-arrival, since the B register lower containing the envelope lower data to be stored, it envelopes the lower RAM 7; writing the ▲ E ^L _ij ▼ address. However, if the bit of the node is "0" that represents the node, the above operation is not performed, but the current direction of the envelope and the target value are compared to determine the direction in which the envelope should proceed and the bit of the code Is set. As described above, in the basic envelope calculation, the traveling direction of the envelope is determined for each node of the step, and a) change of the envelope rate level b) update of the envelope c) determination of whether or not the target level is reached d) It is performed by storing the envelope current value.

Next, 11) the data of the M register is transferred to the upper register of the A register, and the upper register data of the A register is written to the address of the envelope flag; EF _ij of the RAM 7. At this time, the lower register of the A register contains the lower data of the amplitude modulation; AMD _j or the pitch modulation; PMD _j , and the upper data of the M register.

First, calculation of modules 0 to 7 (counter 3 = 0 to 7)
think about. 12) The envelope data written to the RAM 7 in the B register is loaded into the A register, and the amplitude modulation lower order under the A register; ▲ AMD ^L _j ▼ data is loaded into the B register lower order. 13) Amplitude sensitivity; MS _ij is loaded into the S register.
Next, from the envelope data of 14) A register,
The data of AMD _{j in} the lower part of the M and B registers is subtracted according to MS _ij and transferred to the exponential conversion / phase angle generation circuit 13 as the final envelope data. At that time, the key code high-order; ▲ KC ^M _j ▼ is loaded in the A-register high-order. 15) A register lower the key code subordinate; ▲ KC ^L _j ▼ loading. 16
) Upper register of pitch B, upper envelope of pitch; ▲ PE
^M _j ▼, 17) Load ▲ PE ^M _j ▼ in the lower level. 18) Add the key code and pitch envelope and store in the A register, and load the upper frequency; ▲ FR ^M _ij ▼ into the B register. 19) Lower frequency ratio; ▲ FR ^L _ij ▼ is loaded into the lower register of B register. 0) At the timing of 0 in the next operation cycle, exponential conversion / is transferred to the phase angle generation circuit 13 as a final key code obtained by adding / subtracting the frequency ratio (according to F2) to the key code with the pitch envelope.

Next, consider the pitch calculation (counter 3 = 8).
12P) Pitch modulation; PMD _j in the A register is added / subtracted (according to F2) to the envelope data written in the RAM 7 of the B register, and stored in the B register as the final pitch envelope; PE _j . At that time, the amplitude modulation upper level; ▲ AMD ^M _j ▼ is loaded in the A register upper level. 13P) Lower amplitude modulation; ▲ A
Load MD ^L _j ▼ into the lower register of the A register. 14P) Modulation rate; MR _j is loaded into the M register. 15P)
Add and subtract AMD _j from MR _j according to F2 and load modulation level; ML _j into M register. 16P) Amplitude modulation: Compare the updated value of AMD _j with the modulation level (at that time, write the upper envelope of the pitch into ▲ PE ^M _j ▼ of RAM7). If the amplitude modulation has not reached the target value; ML _j , write 17P ▲ ▼) Lower pitch envelope ▲ PE ^L _j ▼ in RAM7, and if it has reached, 17PF ') Target value; ML _j to A Load the register and write ▲ PE ^L _j ▼ to RAM7. Write the amplitude modulation data that does not exceed the target value of the A register to RAM7 at 18P) upper and 19P) lower. 20P-31P
Is a NOP for adjusting the calculation timing. here,
Amplitude modulation is the absolute value of the difference between the detected amount of aftertouch etc. given by the CPU and the detected amount of the previous time; MR _j , sign; ▲ MR ⁷ _j ▼, and the detected amount of this time; ML _j data (see Fig. 21) It is generated by interpolating based on.

MR (1) = ML (0) -ML (1), MR (1) ⁷ = 0 MR (2) = ML (1) -ML (2), MR (2) ⁷ = 0 MR (3) = ML (2) -ML (3), MR (3) ⁷ = 0 MR (4) = ML (4) -ML (3), MR (4) ⁷ = 1: 1 ::::::::: Envelope / key code generation circuit 12 in FIG.
FIG. 4 is a detailed diagram of a calculation timing signal generating circuit 305 for generating a basic signal for performing the above-described operation.
As shown, the calculation timing signal generation circuit 305 is a ROM
The operation will be described with reference to FIG. 20B in which the main operations of the envelope / key code generation circuit 12 are summarized. Input BC0
˜4 are outputs of the counter 1 in the counter B303, which are basic timings. Also, P is the counter 3 in the counter B303.
Is the signal of "1" during the calculation of the MSB, that is, the pitch, and F '
For example, it corresponds to the branch flag F'of the operation flow. In the figure, 0, 1, ..., 9F ', 12P correspond to timings, meaning timing 0, timing 1, ..., Timing 9 when F' = 1 and timing 12 when P = 1, respectively. is doing. In FIG. 22, “BW ₀ ” is the original signal for writing the data of RAM7 from the envelope / key code generation circuit 12, and only when the register output is output to “data bus D0-7” in FIG. 20B. It is “1”. Address L for LSI
SB is forcibly set to "1", and timings 12, 12P, 13P, 17, 17P ▲ ▼, 17PF ', 18P,
It becomes "1" at 19P. ▲ ▼ sets all the lower 4 bits (module) of the address to 0, and becomes "1" at the timing when the INDEX of i is not added to the data of FIG. 20B. OA0 to 4 are original address signals and correspond to "address" in FIG. 20B. However, "SS of timing 1 and 5"
S "means that the lower 3 bits (steps) of the envelope flag (S register) instead of the original addresses OA0 to 2 are adopted as addresses. A to k are clock generation as shown in FIG. Signals for generating various clocks, CKAM, CKAL, ..., CKE, etc., which are the outputs of the circuit 304, and become "1" at the timing of "clock" in Fig. 20B. RA and RB are A register and B respectively. A signal that becomes "1" when loading data from the register RAM7.
It corresponds to "register input" and "B register input".
AM, AL, BM, and BL are signals that become "1" when the respective register outputs are output to the data buses D0-7, and correspond to the "data buses D0-7" in FIG. 20B. B0 is for always masking the output of the B register, and becomes "1" when the "adder / subtractor B input" in FIG. 20B is the upper side "M" and the lower side "0". A0
Is for always masking the output of the A register.
In the flow of Fig. 20A, 9 ▲ ▼; A ^M ← 0 + S, 9F '; A ^M ←
1 + S, 11; ^AM ← 0 + M, 12; A ← 0 + B, 17PF '; A ←
It becomes “1” corresponding to 0 + M and (0). M is adder / subtractor 440
It becomes "1" when the B input of becomes the M register output, and becomes "1" at the timing when the upper side of the "adder / subtractor B input" in FIG. 20B becomes "M". SU is a signal that makes the operation of the adder / subtractor 440 a subtraction type, that is, "AB" or "AM", and is 8; AB, 14; AM in the flow of FIG. 20A.
( ^BL ), 16P; A-M (0) becomes "1". SF2 is an adder / subtractor
The code on the B input side of 440 is used as the value of F2, and becomes "1" at timings 0, 15P, and 16P as described later.

Next, FIG. 24 calculation address generation circuit 301 will be described. In most cases, the address signals BA0-11 are constructed as follows.

Further, BA0 to 3 are outputs BC8 to 11 and BA4 to BA4 of the counter B303.
5 is BC5-7, BA7-11 is a calculation timing signal generation circuit
It corresponds to the address signals OA0-4 of 305. Now consider a special case. At the timing 1, the signal is 0. OA4 is also "1" from Fig. 20B. Then ₇
Inverter 37
1, the address is OA4 OA3 S ₂ S ₁ S ₀ BC7 BC6 BC5 BC11 BC10 BC9 BC8 due to the inverters 365 to 367 and the buffers 368 and 370. Therefore, the address is the envelope rate of the step indicated by the envelope flag; ER _ij (s). Timing 5 is the same. If ₇ is “0”
In other words, for high release, the address is 0 0A3 S ₂ S ₁ S ₀ BC7 BC6 BC5 BC11 BC10 by OR 363 and AND 364.
BC9 It becomes BC8. If the high release is set from the CPU with the instruction "flag set" and data "10000111", the upper 5 bits of the upper address will be "00111".
High release rate: A unique address indicating HR _ij .
Therefore, at the time of high release, the high release rate is read and used instead of the normal envelope rate. Next, timing 2, 14, 14P, 15, 15P,
In 16 and 16P, ▲ ▼ is “1” and LSI is “0”, so inverters 385, 386, NOR 383, 384, clock NOR
According to 382, the address becomes OA4 OA3 OA2 OA1 OA0 BC7 BC6 BC5 00 00. Next, at timings 7 and 8, 7 and 8 are "1",
Since ▲ ▼ is “1” and LSI is “0”, the mode signal /
When I is "1" indicating channel independence, inverter 385,
By 386, clock inverter 381, and 378-380,
The address is OA4 OA3 OA2 OA1 OA0 BC7 BC6 BC5 0 0 0 ▲
▼ Therefore, the pitch modulation data for each channel written by the instruction “pitch modulation” is used for the timing 7 and 8 during the pitch calculation.
The channel-independent amplitude modulation data generated in the envelope / key code generation circuit 12 is read at timings 7 and 8 during the operation of modules 0 to 7. If the mode signal / I is "0" indicating that the channel is common at timings 7 and 8, then AND
The addresses are OA4 OA3 OA2 OA1 OA0 0 0 0 0 0 0 ▲ ▼ by 372 to 374 and ORs 375 to 377. Therefore, the amplitude and pitch modulation data common to all channels are read. Next, the timing 12, 12P, 13P, 17, 17P ', 17PF', 18P, 19P
, ▲ ▼, because the LSI is “1”, the inverter 385,
386, Noah 383, 384, Clock Noah 382, And 378-380
Therefore, the address becomes OA4 OA3 OA2 OA1 OA0 BC7 BC6 BC5 0 0 0 1 This corresponds to the address marked with "*" in Fig. 20B, and these data use the upper 5 bits and LSB for data identification. The address with "**" is distinguished from the address of the data ML _j by setting the LSB to "1", and the dummy address is used (at this timing 12, the data from register A ^L to register B ^L Since the data is transferred via the buses D0 to 7, the RAM7 write signal will be output). As described above, the arithmetic address generating circuit 301 is operated by the address signals B0 ...
Raise 11.

FIG. 25 shows a detailed diagram of the arithmetic control signal generation circuit 307.
a is a condition signal of the clock CKAM, and RA is a load control signal from the RAM 7 to the A register. Here, when data is loaded from RAM7 to the upper register A, all 0s are input to the lower register A by NAND 387.
Set ▼ to “0” (for example, timing 1). at the same time,
When loading data from RAM7 to the upper register of B register, input all 0s to the lower register of B register.
▼ becomes “0”. AM, AL, BM, and BL are condition signals for outputting the data of the respective registers to the data buses D0 to D7. The occupying time of RAM7 of the envelope / key code generation circuit 12 is when T2 is "1". The data output time is AM ', as shown in Fig. 26 because ▲ ▼ in Fig. 7 is "0".
AL ', BM', BL 'are generated. In addition, since the upper register is 7 bits for both A and B, there is no bit to output to MSBD7 of the data bus.
When outputting to ~ 7, MSB by OR 394, AND 393
As a result, the S register MSB is output. B0 'is a signal for masking the output of the B register, and B0 from the arithmetic timing signal generating circuit 305 and timing 5, that is, an addition / subtraction enable signal ▲ ▼ at the time of envelope rate addition / subtraction
As will be described later, the AND sensitivity is set to "1" by the AND 395 and the OR 396 according to the signal MO0 (described later) in which the modulation sensitivity at the time of amplitude modulation subtraction at timing 14 is 0. A0 'is A
A signal for masking the output of the register, which is set to "1" by the AND 397 and the OR 398 in accordance with A0 from the operation timing signal generating circuit 305 and the signal E0 for masking the envelope current value at the timing 5, that is, the envelope rate addition / subtraction. Become. “▲ ▼” indicates the output of the A register is 1000
It is set to 00000000000, and becomes "0" by the NAND 400 in accordance with the signal E0 for masking the envelope current value during the pitch envelope calculation.

FIG. 27 shows that the envelope / key code generation circuit 12 loads an envelope flag (timing 0) and writes it again (timing 11) until the instruction transferred from the CPU causes an envelope of the same module or pitch on the same channel. FIG. 6 is a detailed diagram of a write inhibit circuit 302 that inhibits the envelope / key code generation circuit 12 from writing the envelope flag in the RAM 7 when the flag is rewritten. Exclusive Or 408
~ 414, Noah 407 forms a comparison circuit, interface /
Bits AA0 to 6 corresponding to the channel, module or pitch in the address from the control unit 11 are compared with outputs BC5 to 11 of the counter 3 corresponding to the operation channel, module or pitch in the envelope / key code generation circuit 12. , If it matches, "1" is output. FIG. 28 is a time chart of the write inhibit circuit 302. The output of the NAND 406 of FIG. 27 is "0" when the interface / control unit 11 writes the channel flag calculated by the envelope / key code generation circuit 12, the same channel as the module or pitch, or the envelope flag of the same module or pitch. "It becomes.
FIG. 18 (1) shows the interface / key code generation circuit 12 immediately after the interface flag is read.
In the case where the control unit 11 writes the envelope flag of the same channel, the same module, or the pitch, in the latter half of timing 1, the writing becomes 0 and the writing is prohibited. Even if the value is "0" before the timing 0, the OR 404 sets the flip-flop 403 to "1" at the timing 0, so that writing is not prohibited. In (2), the interface / control unit 11 is on the same channel immediately before the envelope / key code generation circuit 12 writes the envelope flag,
In the case where the module or pitch envelope flag is written, becomes 0 in the latter half of timing 11 and writing is prohibited. Therefore, if the envelope flag of the same channel, the same module, or the pitch is written by the interface / control unit 11 between the timings 1 to 11, the writing of the envelope flag from the envelope / key code generation circuit 12 is prohibited.

FIG. 29 is a detailed diagram of the index data address generation circuit 306. The flip-flops 415 to 420 and the inversion output flip-flop 421 are write addresses when the final envelope and the final key code generated by the arithmetic circuit 308 are exponentially converted by the instruction conversion / phase angle generation circuit 13 and written in the memory. Remember. The clock inverters 425 to 434 generate the address signals DA1 to 5 by switching the write P1 address and the read addresses C1 to 5 by the timing signal T2 (the address DA0 is the same as the write address). The index-converted envelope and frequency information are written in the memory by WEE, WEF, and addresses DA0-5 generated by AND 422 and 423, respectively (details will be described in detail).

Next, the arithmetic circuit 308 will be described with reference to FIG. The arithmetic circuit 308 operates in accordance with the control signal of FIG. 17 as described above as in the operation flow of FIG. 20A.

FIG. 31 is a detailed diagram of the A register. The A register is a clock NAND 454 to 461 for input selection to the lower FF485 to 492, an upper FF493 to 499 and FF, a clock inverter 462.
.About.483, output clock inverters 500 to 514 for outputting the FF output to the buses D0 to 7, and output changing gate groups 515 to 531 to the A input of the adder / subtractor 440. signal
RA is the input selection to the FF from the data bus D0 to 7 and the operation output L0 to 14, and ▲ ▼ is a signal to input all 1s to the lower side FF485 to 492 when loading D0 to 7 to the upper side FF493 to 499. Is. All 1s are loaded to the lower FFs 485 to 492 when ▼ is “0” and the clock CKAL is output. Further, the signals AL 'and AM' control whether or not the lower or upper data of the A register is output to the data buses D0 to D7. The gate groups 515 to 531 change the data to the A input of the adder / subtractor 440. If A0 'is "1", all 0s. If ▲ ▼ is 0, 00000010 ...... 0 (envelope in the operation flow of FIG. 20A. Step update process 9
F ′; A ^M ← 1 + s), If is "0", A0 'is 1 from Fig. 25, so it is 10 ... 0 (corresponding to the start data of the pitch envelope).

FIG. 32 is a detailed diagram of the B register. B register is for lower side FF564 to 571, upper side FF572 to 578, and clock NANDs 532 to 539 for input selection to FF, clock inverter 540.
˜562, and output clock NANDs 579 to 593 to the data buses D0 to 7, and gates 594 to 616 for changing the output to the shift circuit 438. The signal RB is an input selection to the FF from the data buses D0 to 7 and operation outputs L0 to 14,
▲ ▼ is a signal for inputting all 1s to the lower FFs 564-571 when loading D0-7 to the upper FFs 572-578.
In addition, all 1 is loaded to the lower FF564-571,
It is when ▲ ▼ is “0” and the clock CKBL appears. Further, the signals BL 'and BM' control whether to output the lower or upper data of the B register to the data buses D0 to D7. The gate groups 594 to 616 change the output data to the shift circuit 438. When B is "1", the upper register of the B register is output, and when "0", the M or S register is shifted to the shift circuit 438 instead of the upper register of the B register. If B0 'is "1" and B is "1", the outputs BI0-14 are all 0. If B0' is "1" and B is "0", the upper 7 bits are M or S register. The output and lower 8 bits are all 0s. When the signal 5 is "1", B is "1", so if B0 is "0", the output is 1.
BO10, BO9, BO8, 0 ... 0. This is a data conversion for expanding the range of envelope rate data.
The rising and falling speeds of the envelope in the desired range are obtained by shifting the data converted by 11 to BO14 or thinning out the data addition / subtraction. Third, the envelope rate in the upper register of B register; ER ⁶ , ER ⁵ ......
Indicates conversion of ER ⁰ .

FIG. 33 is a detailed view of the M register. The inverted outputs FF617-623 take in the data on the data buses D0-6 by the clock CKM. The clock NORs 624 to 630 output the data of the N register when the signal M is "1" and output all 0s when M is "1" and MO0 is "1".

FIG. 34 shows the shift control circuit 447. When the signal 14 is "1" by the control inputs of the clock inverters 643 to 645 and the clock NORs 664, 637, and 640, that is, the final envelope calculation process in the operation flow of FIG.
← E _ij −AMD _j ) ”only, the shift control signal SH corresponding to the lower 3 bits (modulation sensitivity) of the S register
Outputs 1, 2, 4, and 8. The shift circuit 438 is SH
When the signals of 1, 2, 4, and 8 are "1", 1 left shift (× 1/2), 2 left shift (× 1/4), and 4 left hyft (× 1/1)
6), 8 left shift (x 1/256), for example SH
If 1, 2, 4, and 8 are 1, 0, 1, and 0, respectively, a total of 5 left shifts (× 1/32) are performed (not shown). Therefore, “A ← A−M (A ← E _ij −AMD
_j ) ”, each module is weighted according to the modulation sensitivity MS _ij and amplitude modulation is applied. When MS _ij is 0, the output MO0 of AND 649 is“ 1 ”, so the calculation is performed. "A ← A-0" and no modulation is applied.Next, when 12P is "1", that is, the calculation of the final pitch envelope in the operation flow of Fig. 20A "B ← ± A + B (B ← ± PMD _j + E _pj )" When S
H1, 2, 4, and 8 become 0, 1, 0, and 0, respectively, and are shifted to the left by 2 (× 1/4) (calculation description will be given later). Further, when 15P is “1”, that is, when the interpolation calculation of amplitude modulation in the operation flow is “A ← A ± M (A ← AMD _j ± MR _j )”, if MT is “0”, SH1, 2, 4 , 8 is 0, 0,
4 left shift (× 1/16) with 1, 0, SH1 if MT is “1”,
2, 4, 8 becomes 1, 0, 1, 0 and 5 left shift (× 1/3
2) Here, as described above, MR _j is the absolute value of the difference between the detected amount of aftertouch etc. and the previous detected amount,
If MT = “0”, addition / subtraction of MR _j is required 16 times to reach the target value ML _j which is the detected amount this time. That is, the first
16 × 1.2288 = 19.6608 (msec) from the time chart of 9 figures
Will be reached by. This is ML _j , MR _j calculated from the detected data such as aftertouch for every min19.6608msec to CPU
Means that the data is interpolated inside the sound source LSI to generate smooth data. Also, MT =
If it is "1", addition and subtraction of MR _j are required 32 times, and the cycle of interpolation calculation is 39.3216 msec. Next, consider the timing 5. Since signal 5 is "1", AND631-633, 635,
Since 636, 639, and 641 are valid, the values of SH1, 2, 4, and 8 are determined by ▲ ▼ to ▲ ▼ (Table 4), and the data shift shown in Table 3 is performed.
At timings other than the above, SH1, 2, 4, and 8 are always 0, 0, 0, 0, and therefore no shift is performed.

FIG. 35 is a detailed diagram of the envelope control circuit 448. The envelope control circuit 448 produces an enable signal ▲ ▼ for controlling whether the envelope is raised, lowered, or stopped in the calculation of timing 5. The signal ▲ ▼ indicates that ▲ ▼ is “0”, that is, is being held, or is “1”, that is,
When the envelope is at the step switching point and the direction in which to proceed is being determined, the value is "1" and the envelope is fixed. Further, the inverters 651 to 654, the counter 655, the flip-flops 656 to 659, the ANDs 660 to 663, and the OR 664 form a circuit that generates a thinning signal of the envelope operation in order to change the inclination of the envelope.
When the output of is 0, the calculation is thinned out.
Becomes “1”. Table 5 shows the B register output, which is the data of the upper 4 bits of the envelope rate.
The relationship between the value of ▼ and the counter value at which the operation enable signal ▲ ▼ becomes “0” is shown.

Therefore, the thinning-out of the operations shown in the lower part of Table 3 is performed.

FIG. 37 is a detailed diagram of the data change circuit 439 of FIG. 36. At timing 12P, the signal 12P becomes “1”, so the gate circuit 66
From 6 to 677, the outputs BI ″ 12 to 14 are BI ″ 12 = ▲ ▼, BI ″ 13 = ▲ ▼, BI ″ 14 = BI′12. The operation of timing 12P is "B ← ± A + B (B ← ± PMD _j + E _pj )" in the operation flow of FIG. 20A, and B
Since I'0 to 14 are obtained by shifting the output of the B register 427 by 2 to the left, if the outputs BI0 to 14 of the B register are made to correspond to the data, ▲ E ⁰ _pj ▼ to ▲ E ¹⁴ _pj ▼, Adder / subtractor 440
B input BI'0-11, BI ″ 12-14 of Becomes This means that the range of the pitch envelope is compressed 1/4 around the center level 10 ... 0. Next, at the timing 18, the signal 18 becomes "1", so that the outputs BI12-12 are BI "12 = BI'12, BI" 13 = BI'13, BI "14 = ▲ ▼ by the gate circuits 666-677. The operation at timing 18 is “A ← A + B (A ← KC _j + PE _pj )” in the operation flow of FIG.
Correspond the output BI0 to 14 of the register to the data ▲ PE ⁰ _j ▼
~ ▲ PE ¹⁴ _j ▼ B input BI'0 to 11 of adder / subtractor 440,
BI ″ 12-14 are Becomes This means that the envelope of the final pitch is displayed in two's complement, which is positive above the center level and negative below. That is, when this is added to the key code; KC _j , the envelope of the final pitch is centered at 10 ... 0, and if it is larger, the difference is added, and if it is smaller, the difference is subtracted. The pitch envelope reflected in the key code is symmetrical with respect to the center level.

FIG. 37 is a detailed diagram of the code generation circuit 449. The signal AS is a code on the A input side of the adder / subtractor 440, and becomes "1" by the NANDs 678 and 681 when 12P and ▲ ▼ are "1". That is,
“B ← ± A + B (B ← ± PMD _j +
The code on the A side of E _pj ) "is F1 (MSB of data PMD _j ) is" 1 "
If so, it means positive, and if "0", it means negative. If 7.P is "1" and F2 is "1", inverter 679, NAND 680, 681
As a result, AS becomes "1". That is, the target value calculation of the pitch envelope shown in the operation flow is "A ← A ± M (0) (A ←
In EL _pj (s) ± ELC _pj ) ”, if F2 is“ 1 ”, the pitch envelope level data is inverted with respect to the center level, resulting in an envelope as shown in FIG. 38 (b) ((a) is F2 is the ▲ ERC ⁷ _j ▼ captured at the timing 2, which indicates the direction of the key code change, that is, the positional relationship between the previous key press and the current key press. At this time, the LSB error of the adder / subtractor may occur, but it is sufficiently small, so there is no problem.
It becomes “0” when ± * is performed.
It is a code on the B input side of 0, and is always "1" when ▲ ▼ = "0" (timing 8, 14, 16P). When the signal 5.8 is “1” at timing 5 or 8, P or ▲
If ▼ is “1” and is “0”, ▲ ▼ ＝ ▲ ▼ will be obtained by OR 687, Noah 686, and Nando 689 (otherwise, “1”). 5.8; Envelope update or comparison of envelope and target value PV ▲ ▼; Pitch calculation or other than step 0 = "0"; When direction judgment is not made at step switching point (described later), NAND 689 Output ▲ ▼ becomes ▲ ▼, and when the code BS is 5, it is S4, and when it is 8, it is "1" (since ▲ ▼ = 0). Further, when SF2 is "1", that is, when the timing is 0, 15P, 16P, the output F2 'of the NAND 685 becomes F2 ("1" otherwise). That is, in the case of “0”: addition / subtraction of frequency rate ”,“ 15P: addition / subtraction with modulation rate ”, and“ 16P: comparison of amplitude modulation and target value ”, F2 ′ is F2 and the code BS is ▲ ▼. When P = 0 at timing 7, the output of NAND 684 is 0, BS
Becomes "1". That is, the operation flow “A ← A ± M
(0) (A ← EL _ij (S) ± ELC _ij ) ”, the code BS is“ 1 ”when the pitch is not calculated. When P = 1, the code is the code.
BS will be FA14. Therefore, as shown by the arrow in Fig. 38, the envelope level of the pitch is higher than the center level of the data after inversion; when FA14 = "1" (see Fig. 39), subtracted; below; FA14 = "0". When it is "(see Fig. 39), it is an addition. As described above, the code generation circuit 449 of FIG.
The codes AS and BS of each input in 40 are generated, and the operation flow (FIG. 20A) is realized.

FIG. 39 shows the adder / subtractor 440 and the output clip circuit 441. The adder / subtractor 440 is an OR 691, exclusive
Or 692 to 699 etc., composed of adder 700, code A
A ± B or ± A + B is executed by S and BS. FA1
4, FB14, CO and S14 are the A input MSB and B input M of the adder, respectively.
SB, CARRYOUT, output MSB.

FIG. 40 is a detailed diagram of the flag generation circuit 450 for generating the signal F which is the basis of the branch flag F'in the operation flow.
The clock CKF is generated only at timings 5, 8, 15P, and 16P, so only that case will be considered. First, if is "0", the signals 5 and 8 are "1" at the timing 5, so the NAND 71
4 becomes valid, the output of NAND 714 becomes S4 ′, and the output of NAND 715 becomes ▲ ▼. ▲ ▼ is "1" so it's Nando
The lower input of the 719 is “1”, so ▲ ▼ is “1” and CO is “1”.
Or if ▲ ▼ is “0” and CO is “0”, FF720 is set to “1”. This corresponds to setting the flag F when overflow or underflow occurs when updating the envelope. Is 0 and the timing is 8, similarly, the output of the NAND 714 becomes ▲ ▼ and the output of the NAND 715 becomes S4 ′. At this time, ▲ ▼ is "0", so if the flag F is set at timing 5, it is set again. If flag F is not set, S4 'is "0", CO is "0" or S4' is "1", and CO is "1".
Is set to "1". This corresponds to setting the flag F when the updated envelope exceeds or exceeds the target value while rising or falling. Therefore, when is "0", the flag F is set when the envelope reaches the target value. If the next is “1”, the 37th
From the figure, ▲ ▼ = “1” and BS = “0”. Also, the 35th
From the figure, ▲ ▼ = “1”. Therefore, at timing 5, "B ← A + 0" is performed. At that time, the output of NAND 715 is "1", CO is "0", and ▲ ▼ is "1" in FIG.
Therefore, the flag is not set. At timing 8, the output of NAND 715 is "1", so if the target value is greater than or equal to the target value by subtracting the current value of the envelope from the target value (CO
= “1”) Flag F is set to “1”. That is, the flag is set such that F = 1 in the + direction and F = 0 in the − direction. Next, except timing 5 and 8, that is, timing
In 15P and 16P, the output of NAND 715 is ▲ ▼. At timing 15P, ▲ ▼ ＝ “0” and CO ＝
If "1" or ▲ ▼ = "1" and CO = "0", that is, if the amplitude modulation data is being updated, a flag F is set if it overflows or underflows. timing
When 16P, ▲ ▼ ＝ “0” and CO ＝ “1”, or ▲
▼ = “1” and CO = “0”, that is, whether the updated amplitude modulation reaches or exceeds the target value while rising.
If it crosses during descent, set flag F. The flag F is set as described above, and the branch condition of the operation flow (FIG. 20A) is set.

FIG. 41 is a detailed diagram of the output clip control circuit 451 which monitors the occurrence of overflow or underflow in the adder / subtractor 440 and controls the arithmetic output to a predetermined value when the overflow or underflow occurs. Output signals CT, MX, ▲ ▼ are "1", "1",
When it is "0", the output of the adder 700 shown in FIG.
... 1, 0 ... 0. First, timing 18
That is, "A ← A + B (A ← KC _j + P in the operation flow
E _j ) ”, the shift circuit 43 of FIG.
8. The B input to the adder / subtractor 440 by the data change circuit 439 is Therefore, the calculation at this time is the central level 10 …… 0.
This is equivalent to adding data in the two's complement format in which the upper part is positive and the lower part is negative at the boundary. Therefore, the codes AS and B of the adder / subtractor 440
When the adder B input MSB: FB14 is "0" or "1" instead of S, overflow and underflow must be seen. When 18 is “1”, AND 728 and 731 are valid, and if 18 = “1”, FB14 = “1”, ▲ ▼ = “0”, the output of NOR 732 is “0”, and the output of AND 738 is ▲ ▼ becomes "0" (MX = "0", CT = "0"). This is equivalent to setting all "0" if underflow occurs when adding negative data. If 18 = "1", FB14 = "0", CO = "1"
Output MX of OR729 becomes “1” (▲ ▼ ＝ “1”, CT ＝
"0"). This is equivalent to setting all "1" if an overflow occurs when positive data is added. Then 18
When “=“ 0 ”and 7∧P =“ 0 ”, the output of NOR 722 becomes“ 0 ”when BS =“ 1 ”or AS0 =“ 1 ”(“ A-
B "or" -A + B ") At that time, AND 730 becomes valid, and when CO =" 0 ", the output of NOR 732 becomes" 0 ", the output of AND 738 becomes" 0 ", and ▲ ▼ =" 0 ". (MX = "0",
CT = "0"). This means that all underflows are set to "0". When BS = "0" and AS0 = "0" (A
+ B), AND 727 become valid, and CO = “1”, OR 729
Output MX is “1” (▲ ▼ ＝ “1”, CT ＝ “0”).
This means to set all "1" s in case of overflow. Finally, the case of timing 7 and P = “1” will be described. When S14 ≠ FA14 or CO ≠ BS, the output of EXOR733 is “1”, therefore CT ＝ “1”, ▲ ▼ ＝ “0” (MX ＝
"0"). This is because when the pitch envelope level is changed and the change causes the data to exceed the center level,
This means setting the output of the adder 700 in FIG. 39 to the center level 10 ... 0. The output of the adder 700 shown in FIG. 39 is controlled as described above.

FIG. 42 shows an S register and envelope flag control circuit 44.
It is a detailed view of 6. The flip-flops 739 to 746 are S registers and take in the data buses D0 to D7 with the clock CKS. S
The register contents are timing 1 to 13 when P = 1 or P = 0.
Is the envelope flag, and the output of the envelope flag control circuit 446 is meaningful only at that timing. ▲ ▼ has an envelope flag of 74
7 indicates "* 0 ** 0000", that is, a signal which becomes 0 when step 0 in the normal mode. Is a signal that becomes “1” when determining the direction at the step switching point.
7, 749, OR 748, Inverter 753 P = "1" or ▲
When ▼ = “1” and ▲ ▼ = “1”, that is, when the node flag is 0 except at step 0 of the amplitude envelope, it becomes “1”. E0 is the operation of timing 5 "5 ←
A ± B [B ← E _ij ± (ER _ij (s) + ERC _j )] ”is a signal that sets the A input to 0. NAND 747, NOR 752, inverter 75
9, AND 760, OR 761, ▲ ▼ ＝ ▲ ▼ ＝
0, that is, when the mode is mask, or ▲
▼ = 0 and ▲ ▼ = 1, that is, "1" is set at the beginning of step 0. In the normal mode, since the A input becomes 0 at the beginning of step 0, the envelope always starts from 0. F'is the operation flow (20A
The flag for branching in the figure), F '= other than timing 9 by OR 762, 763, inverter 764, and 765.
At F, timing 9 = “0”, and S3 = “0”, F ′ = F, and otherwise F ′ = “0”. That is, at timing 9, the direction is being determined or the hold is in progress F ′ = 0,
Otherwise, F '= F. Next, the outputs BI8 to BI14 will be described. These are outputs of the envelope flag control circuit 446 only at timing 9. BI8-10 is S0
~ S2. BI11 == "0", the envelope flag is not "* 0 *** 111", and F = "1" and F1 = "1".
In case of, it becomes "1", otherwise it becomes the original value ▲ EF ³ _ij ▼. That is, when the direction is not being determined and the step 1 in the normal mode is not performed and F1 (8th bit of the envelope level = sustain flag) reaches “1”, the hold flag ▲ EF ³ _ij ▼ is set to “1”. Become. BI12 = “1”
When F = “0”, it becomes “1”. That is, when the determination result is the-direction when = "1", the code bit ▲ EF ⁴ _ij ▼ is set to "1". When the value other than "1" and F = "0", BI12 is set to "0" when the output of the NAND 754 reaches "0", that is, the sustain level. Also, BI12 is set to 0 when ▲ ▼ = 1, that is, at the switching point of steps. Otherwise, BI12 has the original value ▲ EF ⁴ _ij ▼. BI13 =
When "0", ▲ ▼ = 1, and F = 1, that is, when the direction is not being determined and the sustain is not in progress, it will be "0", otherwise it will be "1", and step switching Is a flag indicating. RAM7 above registers A and B
When writing to, the 8th bit of the S register
Write by SMSB. As described above, the envelope flag control circuit shown in FIG. 42 outputs signals ▲ ▼, F'and E0 according to the envelope flag and sets the envelope flag. After the key is turned on, the envelope flag usually starts from step 0 (pitch envelope starts after determining the direction), and when reached, 1 is added to the step, and the node flag ▲ EF ⁵ _ij ▼ is set to 0 representing the node to determine the direction. , Sign flag ▲ EF ⁴ _ij ▼
Set and start the next step. If reached, sustain flag (envelope level EL _ij (S)
If the MSB) is “1”, the hold state is set and the envelope is fixed. Then, when the key-off comes from CPU3, the hold is released and the next step is started. If the sustain flag is in the final step 7 in loop mode, the envelope flag is 011 * 0111 ← 01101111 + 1 = 0.
Since it becomes 1010000 and returns to step 0, the envelope is repeated from the beginning.

Although the arithmetic circuit of FIG. 30 has been described above, by performing such an operation, the arithmetic circuit performs an operation as shown in the operation flow of FIG. 20A, generates a final envelope and a synthetic key code, and performs exponential conversion. / Transfer to the phase angle generation circuit 13.

FIG. 43 is a detailed diagram of the external RAM interface 16.
FIG. 44 (a) shows the interface / control unit 11
(B) RA from the envelope / key code generation circuit 12
This is the write timing to M. Address signals RA0-11
Is the address AA0-1 from the interface / control unit 11.
1. The addresses BA0 to 11 from the envelope / key code generation circuit 12 are obtained by switching the clock inverters 777 to 801 based on the RAM occupation time (FIG. 3). The write enable signal ▲ ▼ is used when the write signal ▲ ▼ from the interface / control unit 11 becomes “0” (when the signal ID indicating the use of the internal memory is not “1”) or the envelope / key. Code generation circuit
When the write signal ▲ ▼ from 12 becomes "0", the timing signal ▲ ▼ becomes "0" in the width of "0". When both ▲ ▼ and ▲ ▼ of the output enable signal ▲ ▼ are "1", the signal CK2 has a width of "0" and becomes "0". Data RD0
~ 7 is a signal when ▲ ▼ or ▲ ▼ is “0”
▼ is the width of "0", and it is the output from the sound source LSI6.

FIG. 45 is a block diagram of the exponential conversion / phase angle generation circuit 13 of FIG. The envelope and key code generated by the envelope / key code generation circuit 12 are clocked by the clock CK.
It is taken in by flip-flop (FF) 1000 at E. FF1000
Is converted by the exponent ROM 1001 and input to the envelope register 1002 and the frequency information register 1004. FIG. 46 is a detailed diagram of the envelope register 1002. The envelope register 1002 has two RAMs (ENVERAM, ENVORA
M), FF1014-1019, etc., inverter 1027, clock inverters 1020-1026, 1028-1033, etc., and inverter
1008, 1010, Nand 1009, 1011, 48th
It operates like the time chart of FIG. The counter 1 (Fig. 18) shows the basic timing of the envelope / key code generation circuit 12, and the data output of FF 415 to 421 (Fig. 29) is switched from the timing 0. The data of FF415 to 420 correspond to the address indicating the envelope register 1002, the write channel (DA0 to 2) and the module (DA3 to 5) to the frequency information register 1004, and become the data of DA1 to DA5 only when T2 is 0. (DA0 always corresponds to the value of FF415). The output of FF1000 is switched as shown in Fig. 48,
Since WEE becomes “1” at timing 0, when DA0 is “0” (even channel), NAND 1009 becomes “0”, so T2
When = "0", the timing signal W is "1" and ENVERAM1
Data is written to a predetermined address of 012 (inversion of FF416 to 420). When DA0 is "1" (odd channel), NAND 1011 becomes "0" and data is written to ENVORAM1013. When T2 is "1", the addresses DA1 to 5 are the inversions of the outputs C1 to C5 of the timing signal generation circuit 159 (Fig. 6). Read, buffer 1020-1026, 1028-
1033 and inverter 1027 enable ENVE when T2 = "1".
RAM1012, T2 = "0" from ENVORAM1013 when T2 = "0"
The data read in step FF1014 to 1019 is delayed, and the data E0 to 11 are output. Therefore, the envelope register
Data is written to 1002 at the timing of the envelope / key code generation circuit 12, read at the timing of the interface / control unit 11, and sent to the waveform generation circuit 15 via the FF 1003.

FIG. 47 is a detailed diagram of the frequency information register 1004, which operates in exactly the same way as the envelope register 1002. The read frequency information FI0-20 is sent to the accumulator (adder 1006, shift register 1007) for phase angle generation via FF1005, and the phase angle is generated.

FIG. 49 is a detailed diagram of the OC register 14. OC register 14
Are envelope register 1002 and frequency information register 1004
Similarly, the RAM for even channels (OCERAM) and the RAM for odd channels (OCORAM) consist of registers that can be written while always reading by alternately reading them. Address AA0 from interface / control unit 11
2, 4 to 6 are write addresses, C1 to C5 are read addresses, and read is possible when T2 is "1", and write is possible when T2 is "0". Flip-flops 1076B ~ 1083B, 1101 ~
1103 and shift register 1104 delay the control signals C0 to 3 in timing, and gates 1105 to 1116 control signals C5 to
It is for generating 9.

FIG. 50 is a block diagram of the waveform generation circuit 15. The waveform generation circuit 15 performs almost the same operation as the circuit shown in Japanese Patent Application No. 61-55008 relating to the present applicant. First, the phase angles P0 to 11 are selected by the selector 1118, the FF 1119, the phase angle conversion circuit 1120,
It is input to the sine wave ROM 1122 via the shift register 1121 and becomes the waveform signal sinX ′. The phase conversion circuit 1120 is
Phase distortion is introduced into the sine wave according to the value of the control signal, and the corresponding waveform is as shown in FIG. Waveform signal sin
X ′ is multiplied by the envelope E ″ through the shift register 1136, the adder 1137, and the FF 1138 (the output of the gate circuit 1135 is 0) by the multiplier 1124, and is output through the FF 1125. This output is When output as a musical sound, the output from the register (selector 1127, FF1128, gate circuit 1129) for accumulating the musical sound output is the selector 1130, gate circuit.
The data passed through 1131 is added / subtracted by an adder / subtractor 1126. First
FIG. 52 shows a time chart of the waveform generation circuit 15. C0-5
6 is the counter output of the timing signal generating circuit 159 in FIG. 6, and C1 to 5 are read addresses of the envelope register 1002, frequency information register 1004 and OC register 14 in FIG. The 1-bit delay corresponds to the basic timing of the waveform forming circuit (FIG. 50). The lower 3 bits of the 6 bits correspond to the channel and the upper 3 bits correspond to the module operation. Signals P, X ', E',
E ″, E ″ sinX ′, R ′, and R respectively indicate the timing of one cycle from the calculation of module 0 and channel 0 to the calculation of module 7 and channel 7. Waveforms are generated by selectors 1118, 1127, 11 according to control signals C0-9.
This is performed by controlling 30, 1132, gate circuits 1129, 1131, 1135, phase angle changing circuit 1120, and adder / subtractor 1126. Table 6 shows the operation corresponding to the upper 4 bits of OC data input from the CPU (see Fig. 49).

A waveform is generated by these arithmetic control.

An example of waveform generation is shown below. However, i is the module number,
j is the channel number.

_{1) E i + 1j sin (} E ij sinP ij) operation code becomes ij ** 000000 (upper 4 bits may be _{0010) i +1 j 101 * 0000} i +2 j 000 *****. As a result, as shown in Table 6, P is selected as the phase angle for the waveforms of module i and channel j, and the output E ″ sinX ′ becomes the phase of module i + 1 and channel j. Waveforms of module i + 1 and channel j The output E ″ sinX ′ is accumulated with the tone output. Control signal C6 ~
Since 9 is for the waveform output with a delay of 8 bits from phase X, for example, the control signals of i + 1, j are for the waveform output of module i, channel j.

2) E _{i + 2j} sin (E _ij sinP _ij- E _{i + 1j} sinP _{i + 1j} ) The operation code is ij ** 000000 (the upper 4 bits may be 0010) i ₊₁ j 10000000 i ₊₂ j 111 * 0000i ₊₃ j 000 ***** As a result, as shown in Table 6, P is selected as the phase angle for the waveforms of the module i and the channel j, and the output E ″ siX ′ is input to the shift register 1133. The waveforms of the module i ₊₁ and the channel j are in phase. P is selected as the angle and its waveform is subtracted from the output R of the shift register 1134 to become the phase angle of module i ₊₂ , channel j.
Then, the waveform output E ″ s of module i ₊₂ , channel j
inX 'is accumulated as a musical sound output. As described above, various waveforms are generated according to the operation code, so that many tone colors can be generated. As for the output waveform, the generated waveforms are sequentially accumulated.
When the value of C0 to C5 is "9", the waveform of the new operation cycle
It is taken into FF1128 (waveform that is not output = phase), but since the output of FF1128 at that time is the accumulated value of the waveform of the previous cycle, by latching it in (CKL), latch 1139 becomes The waveform final accumulated value for each operation cycle will be output. The gate circuit 1140 is a signal
When OM is "0", the output is all 0 (center level), and it is maintained after reset until mode data is set. That is, when an external reset signal is generated due to power-on or the like, the timing signal generation circuit 159 generates an internal reset signal, which resets the latch 156 in the mode of FIG. 6 and sets its output OM to "0". The output of the gate circuit 1140, the signal output sent to the DAC 8, is placed at a silence level, all zeros. On the other hand, CP
U3 sets required data such as a tone color in the external RAM 7 through the interface / control unit 11, and finally sends an instruction "mode" to set the mode latches 156 to 158. As a result, OM becomes “1”, the gate circuit 1140 is enabled, and the waveform signal calculated by the waveform generation circuit 15 is applied to the DAC8.
Will be sent to. In other words, after turning on the power, the external RAM7
The input to the DAC 8 is maintained at a silent level until the tone generator LSI 6 is able to synthesize a regular musical tone signal after the setting of the required data is completed.

[Advantage of Device] As described in detail above, according to this device, when the pitch envelope level which is the target value of the pitch is changed by the pitch envelope level change data such as the touch response, the pitch before the change is changed. Since the pitch envelope level is changed so that the difference between the envelope level and the center level becomes small, the degree of reflection on the pitch due to touch response etc. can be naturally controlled, and it is easy to match the user's feeling Have advantages.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a block diagram of a tone generator LSI, and FIG. 3 is an external RAM occupation by an interface unit of the tone generator LSI and an envelope / key code generation circuit. Time chart showing allocation, 4th
FIG. 5 is a time chart of data and write control signals sent from the CPU to the interface / control unit of the tone generator LSI, and FIG. 5 shows a low speed calculation cycle for generating a tone control signal and a high speed calculation cycle for generating a waveform. Time chart, FIG. 6 is a detailed view of the interface / control unit, FIG. 7 is a time chart of a part of the signals generated by the timing signal generation circuit, and FIG.
FIG. 9 is a time chart of other signals generated by the timing signal generating circuit, FIG. 9 is a detailed diagram of the timing signal generating circuit, FIG. 10 is a detailed diagram of the instruction decoder,
FIG. 11 is a time chart showing the operation of the interface / control unit for a transfer instruction of 1-byte length data, and FIG. 12 is a time chart showing the operation of the interface / control unit for a transfer instruction of 2-byte length data. Fig. 14 is a time chart showing the operation of the interface / control unit for the flag set instruction, Fig. 14 is a time chart showing the operation of the interface / control unit for the key-off instruction, and Fig. 15 is the interface for the write instruction to the OC register. 16 is a time chart showing the operation of the control unit, FIG. 16 is a time chart showing the operation of the interface / control unit with respect to mode setting instructions, FIG. 17 is a block diagram of the envelope / key code generation circuit, and FIG. Detailed view of the counter B to provide an operation cycle of Beropu / key code generating circuit, the time chart of Figure 19 is the counter B, the 20A diagram flow chart of the operation according to the envelope / key code generating circuit,
FIG. 20B is a diagram summarizing the operation of the envelope / key code generation circuit, FIG. 21 is a graph showing amplitude modulation generation data given from the CPU, FIG. 22 is a detailed diagram of the operation timing signal generation circuit, and FIG. Figure is a detailed view of the clock generation circuit, Figure 24 is a detailed view of the operation address generation circuit, Figure 25 is a detailed view of the operation control signal generation circuit, Figure 26 is a time chart in the operation control signal generation circuit, First
27 is a detailed diagram of the write inhibit circuit, FIG. 28 is a time chart showing the operation of the write inhibit circuit, FIG. 29 is a detailed diagram of the exponent data address generation circuit, FIG. 30 is a detailed block diagram of the arithmetic circuit, Figure 31 is a detailed view of the A register, and Figure 32 is B.
Detailed view of register, Fig. 33 Detailed view of M register, 34
Figure is a detailed view of the shift control circuit, Figure 35 is a detailed view of the envelope control circuit, Figure 36 is a detailed view of the data change circuit,
Fig. 37 is a detailed diagram of the code generation circuit, Fig. 38 is a graph showing the inversion of the pitch envelope by the flag, Fig. 39 is a detailed diagram of the adder / subtractor and the output clip circuit, Fig. 40 is a detailed diagram of the flag generation circuit, 41 is a detailed diagram of the output clip control circuit,
42 is a detailed view of the S register and envelope flag control circuit, FIG. 43 is a detailed view of the external RAM interface, 44
Figure is a time chart showing the operation of the external RAM interface. Figure 45 is a block diagram of the exponential conversion / phase angle generation circuit.
Fig. 46 is a detailed diagram of the envelope register, Fig. 47 is a detailed diagram of the frequency information register, Fig. 48 is a time chart of the exponential conversion / phase angle generation circuit, Fig. 49 is a detailed diagram of the OC register, and Fig. 50 is 51 is a detailed diagram of the waveform generating circuit, FIG. 51 is a waveform diagram showing a set of sinusoidal waves which are distorted by a control signal in the waveform generating circuit, and FIG. 52 is a time chart of the waveform generating circuit. 1 ... keyboard, 2 ... switch, 3 ... CPU, 7 ... external R
AM, 11 ... Interface / control section, 12 ... Envelope / key code generation circuit, 15 ... Waveform generation circuit, 436, 4
42, 440, 449, 437, 447, 450, 438, 448 ... Pitch envelope arithmetic circuit.

Claims (3)

[Scope of utility model registration request] 1. A CP for monitoring a performance state of a performance input device (1, 2) for designating at least a pitch of a musical tone to be generated.
A memory (7), which is controlled by U (3) and synthesizes a musical tone according to a playing state, interface circuit means (11) for writing data including at least a pitch transferred from the CPU to the memory, and the memory. A tone control signal generating circuit means (12) for generating a tone control signal by utilizing the above, and a waveform generating means for generating a tone waveform in accordance with the tone control signal generated by the tone control signal generating circuit means. The signal generating circuit means includes a pitch envelope generating circuit means (308) for generating a pitch envelope for giving a frequency variation to the musical tone waveform generated by the waveform generating circuit means. pitch envelope level changes data provided from CPU (ELC _pj) and pitch envelope level data (EL _pj s)) is used to change the pitch envelope level data according to the level changing circuit means (436, 442, 440, 449) and the pitch envelope level data and the pitch envelope rate data changed by the level changing circuit means. In a tone synthesizer comprising pitch envelope calculation circuit means (436, 437, 440, 449, 450, 447, 438, 448) for calculating the pitch envelope, the level changing means is provided from the CPU. When the pitch envelope level is lower than the center level which is the pitch level corresponding to the pitch designated by the performance input device, the pitch envelope level is increased by the pitch envelope level change data (EL _pj (s)
← EL _pj (s) + ELC _pj ), and when the pitch envelope level given from the CPU is higher than the center level, the pitch envelope level change data is used to decrease the pitch envelope level (EL _pj (s) ← EL
_pj (s) + ELC _pj ) is a musical sound synthesizer. 2. A tone synthesis apparatus according to claim 1, wherein the level changing circuit means changes the pitch envelope when the changed pitch envelope level data crosses the center level. A tone synthesizer having limit circuit means (451, 441) for limiting level data to the central level. 3. The musical sound synthesizer according to claim 1 of the utility model registration, wherein the memory has a portion for storing a flag (ERC _j ⁷ ) for instructing the presence or absence of inversion of the pitch envelope given from the CPU. The level changing circuit means selectively inverts the pitch envelope level data given from the CPU with respect to the center level according to the flag,
A tone synthesizer characterized in that the selectively inverted data is changed by the pitch envelope level change data.