JPS6343760B2 - - Google Patents

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone generator, and more particularly to a musical tone generator that simulates natural musical instrument sounds by manipulating the shape of a musical sound waveform and changing it over time. Structures of conventional examples and their problems Conventionally, methods using a sine wave synthesis method, methods using a frequency modulation method, methods using a subtraction method (mainly analog processing with VCO,
Those using VCF, VCA, etc. ) have been proposed, but these have had problems such as the circuit scale becoming large and making it difficult to realize, and the method having limitations. OBJECTS OF THE INVENTION It is an object of the present invention to provide a musical tone generating device that can simulate natural musical instrument sounds with a simple configuration and that can keep the musical tone rise time and waveform change time constant. Structure of the Invention The musical sound generation device of the present invention forms a composite waveform using at least two musical sound waveforms out of a plurality of musical sound waveforms from the start of musical sound generation to the end of musical sound generation and the selectively extracted musical sound waveform. a data memory section that stores multiple sets of control data used at different times;
a note clock generating section that determines a musical scale; a data reading section that reads out predetermined control data from two waveform sample data and a plurality of sets of control data from the data memory section based on the output signal of the note clock generating section; A waveform calculation section that calculates composite waveform sample data using the two waveform sample data and control data read out by the section, and a conversion section that converts the digital output signal of the waveform calculation section into an analog signal. It is configured to generate a musical sound waveform that is close to the sound of a natural instrument by changing the shape of the musical sound waveform over time, and furthermore, 1.
Even if the same waveform data within an octave is used, the rise time of a musical tone and the change time of a waveform can be made constant. DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below based on the drawings. First, the principle of the present invention will be explained. FIG. 1 shows a musical sound waveform of one period of musical tone extracted discretely. The relationship between the time elapsed from the start of pronunciation and the musical sound waveform is shown below. Musical sound waveform Time elapsed A――――――10ms B――――――25ms C――――――50ms D――――――320ms E――――――720ms As can be seen from Figure 1 As shown, the shape of the musical sound waveform changes over time. The present invention focuses on changes in the shape of musical sound waves over time, and generates musical sounds that are typical of natural musical instruments by changing the shape of the waveforms over time. Explanation of the contents stored in the data memory FIG. 2 shows an example of the envelope enveloping state of a musical sound waveform from the start of sound generation to the end of sound generation. Second
The envelope shown in the figure from the start of sound generation to the end of sound generation is divided into I (I = o, 1, ..., i,
..., I-1). Then, one period of the musical sound waveform selected and extracted from each division point is divided into N parts. FIG. 3 shows an example of selected and extracted tone waveforms. N waveform sample values obtained by dividing one period of the extracted I musical sound waveforms into N, that is, N×I waveform sample values, and control data used when generating musical tones (in the present invention, The control data for performing the insertion is stored in the data memory. Explanation of the waveform interpolation method As the waveform interpolation method, the sample wave position i to i+1 (i=0, 1, 2,
..., I-1), one cycle of the musical sound wave repeats M times, and the waveform sample (X _i,o )
The virtual sample value ^ that exists between and (X _i+1,o )
This is an attempt to obtain an approximate value by virtually calculating a waveform sample value at a virtual sample point using (X _i,n,o ) using an interpolation operation. The interpolation formula is shown below. f^(X _i,n,o )={f(X _i+1,o ) −f(X _i,o )}×m/M+f(X _i,o )...(1) i is divided into I. This is the waveform number at the sample position extracted. (i=0, 1, 2, . . . , I-1) m represents a position in the middle of a repeating transition between waveform numbers i and i+1 M times. (m=0, 1, 2, . . . M-1) n is a sample position obtained by dividing one cycle of the musical sound waveform into N, and is a waveform sample NAND. (n=0, 1, 2, . . . , N-1) FIG. 4a shows an example of interpolation using equation (1). As can be seen from the figure, discontinuities occur at the joints of the waveforms. If the level difference between these discontinuous points is large, it may cause an audible problem as an unnecessary noise component. Therefore, in this embodiment, a correction term is added to equation (1) to prevent the occurrence of discontinuous points as shown in FIG. 4b. The interpolation formula is shown by adding a correction term to formula (2). f^(X _i,n,o )={f(X _i+1,o ) −f(X _i,o )}×m+n/MN+f(X _i,o )...(2) Regarding the envelope addition method Explanation There are two types of musical sounds: organ-type envelopes and piano-type envelopes. FIG. 5 shows an example in which organ-shaped and piano-shaped envelopes are added. In the figure, a indicates an organ type, and b indicates a piano type. In this explanation, unlike the previous example, the waveform stored in the data memory is not the waveform up to the end of sound generation, but the stationary part of the musical tone or the point where the waveform shape is stable, and subsequent waveform generation is stored in the data memory. The last memorized waveform shall be used repeatedly. Explanation of organ type When the key signal turns on at point A in Figure 5,
A musical tone is synthesized by performing waveform interpolation using the waveform data in the data memory. Then, when time advances to point B, the data becomes the final waveform data, and the final waveform is generated repeatedly thereafter. After that, when the key signal is turned off at point C, the envelope signal has attenuation characteristics, and the output waveform is attenuated. Piano type explanation When the key signal turns on at point A in Figure 5,
A musical tone is synthesized by performing waveform interpolation using the waveform data in the data memory. Then, when the process reaches point B, the final waveform data becomes the final waveform data, and as the final waveform data is used repeatedly thereafter, the envelope signal enters the attenuation characteristic state, and the output waveform attenuates in accordance with the attenuation characteristic. Explanation on how to generate pitches To determine the pitch, a clock signal corresponding to a 12-tone scale is generated. Regarding octave relationships, pitches related to octaves are generated by changing the number of samples in one period of the tone waveform stored in the data memory. If the _C0 note is 512 samples, the scale clock signal will be 32.703Hz x 512 samples ≒ 16.74KHz.
Table 1 shows the scale clock frequency, and Table 2 shows the number of waveform samples and the octave relationship. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram of an electronic musical instrument employing the musical tone generator of the present invention. 601 is a keyboard section (KB), 602 is an operation section (TAB) consisting of a tone tablet switch, a vibrato effect on/off switch, a glide effect on/off switch, etc., and 603 is a central processing unit (CPU).
604 is a read/write storage device (random access memory called RAM), which is similar to that used in computers, etc.
606 is a read-only storage device (read-only memory called ROM) that stores programs that determine the operation of the CPU 603, and 606 is a storage device that stores waveform sample data for synthesizing musical tones, control data for waveform interpolation, etc. Memorized ROM
It is. Reference numeral 607 designates a musical tone generator that generates musical tones using the waveform sample data and control data stored in the ROM 606, 608 a filter that removes sampling noise, and 609 an electroacoustic transducer. Keyboard section 601, operation section 602, CPU 603,
The RAM 604, ROMs 605 and 606, and musical tone generating section 607 are connected by a data bus, an address bus, and a control line. The method of connecting the data bus, address bus, and control lines in this way is suitable for minicomputers and microcomputers.

【table】

【table】

[Table] This is a well-known configuration method centered on computers. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner. A plurality of address buses, for example 16, are also prepared, and normally the CPU 603 outputs the address code, and other parts receive the address code. Control line normal memory
A request line (), an I/O request line (), a read line (), a write line (), etc. are used. MREQ indicates reading and writing memory,
IORQ indicates retrieving the contents of an input/output device (I/O), indicates the timing to read data from memory or I/O, and indicates timing to write data to memory or I/O. Using such a control line,
An example of this is Zilog's microprocessor Z80. Next, the operation of the electronic musical instrument shown in FIG. 6 will be described.
The keyboard section 601 is configured to be able to divide a plurality of key switches into a plurality of groups and send the on/off states of the key switches in the group all at once to the data bus. For example, in the case of a 61-key keyboard, it is divided into 10 groups of 6 keys (half an octave) and 11 groups of 1 key, and one address code is assigned to each group. An address code indicating one of the above groups arrives on the address line, and the signal and signal
When RD is applied, the keyboard section 601 decodes the address code and outputs 6-bit or 1-bit data indicating on/off of the key switches in the corresponding group to the data bus. These can be constructed using decoders, bus drivers and some gate circuits. Of the operating units 602, the tablet switch is connected to the keyboard unit 60.
A configuration similar to 1 can be adopted. The CPU 603 reads the instruction code from the address of the ROM 605 that corresponds to the code of the internal program counter, decodes it, performs arithmetic operations, logical operations, reads and writes data, etc.
Performs tasks such as jumping instructions by changing the contents of the program counter. Procedures for these operations are written in the ROM 605. First, CPU6
03 reads from the ROM 605 an instruction for importing the data of the keyboard section 601, and imports codes indicating on/off of each key of the keyboard section 601 for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generating section 607, and musical tone generation data corresponding to the key code is sent out. Next, the CPU 603 sequentially reads a group of instructions from the ROM 605 for importing data from the operation unit 602, decodes them, outputs the address code and control signal corresponding to the operation unit 602, and outputs the address code and control signal corresponding to the operation unit 602 to the data bus. Output the code that expresses the status of the switch,
Load into CPU603. Based on the data read into the CPU 603, a tone color is selected and predetermined effect control data is generated, and the tone color selection data and the effect control data are sent to the ROM 606 and the musical sound generation section 607. Note that the method of allocating the pressed key code to a finite channel of the tone generator 607 is known as a generator assigner function. The musical sound generation section 607 generates musical sound synthesis data based on the musical sound generation data supplied from the CPU 603.
Predetermined waveform sample data and control data are taken in from the ROM 606 and subjected to waveform interpolation processing to generate a musical sound waveform, and the electroacoustic transducer 609 generates a musical tone via a filter 608. Note that the internal processing of the musical tone generating section 607 is as described above. FIG. 7 shows a time chart when a code is supplied from the CPU 603 to the tone generator 607.
The I/O port address is supplied to the address bus, and musical tone generation data, effect control data, etc. are supplied to the data bus. and the control signal
The contents of the data bus are latched to the channel specified by the I/O port address at the timing when the IORQ signal changes from a logic low level (hereinafter abbreviated as "O") to a logic high level (hereinafter abbreviated as "1"). . Next, various types of data supplied to musical tone generating section 607 will be explained. Table 3 shows the I/O port addresses and the contents of various data. The I/O port address is displayed in hexadecimal. The data corresponding to I/O port address (00) ₁₆ to (07) ₁₆ is musical tone generation data 8.
It is now possible to generate eight tones for each channel. I/O port address (08) ₁₆ is sustain data that specifies the attenuation characteristic of the envelope signal explained in FIG. I/O port address (09) ₁₆ is damper data that becomes valid when the envelope characteristic is piano type, and, like the sustain data, specifies the attenuation characteristic of the envelope signal. I/O port address (OA) ₁₆
is beat data, which specifies the frequency shift when two tones are generated. I/O port address (OB) ₁₆ is effect control data, vibrato on/
It consists of off signals, glide on/off signals, etc. Table 4 shows the composition of the musical tone generation data. Bit positions D0 to D3 are bits that specify the scale frequency.

【table】

[Table] This is clock specification data. Bit position D4
~D6 is waveform sample number designation data that designates the sound generation range. Bit position D7 is a key on/off signal accompanying the on/off operation of the key switch, and is "0" when off and "1" when on. Table 5 shows waveform sample number specification data SD0 to SD2.
This shows the code contents and the number of samples in one cycle of the waveform specified by the code. The waveform sample number specification data SD allows eight types of waveform sample numbers from (000) ₂ to (111) ₂ to be specified, and in this embodiment, 512 samples to 4 samples are specified. Table 6 shows notebook clock specification data ND0~
This shows the relationship between the contents of the chord represented by ND3 and the specified scale indicated by that chord. Table 7 shows the composition of the effect control data. Bit position D0 is the vibrato on/off signal VIB,
When the vibrato on/off switch in the operation unit 602 is off, the signal is "0", and when it is on, the signal is "1". Bit position D1 is for delay vibrato on/off.

【table】

【table】

[Table] The off signal DVIB is a delay vibrato effect control signal, and is "0" when the delay vibrato on/off switch in the operation section 602 is off, and "1" when it is on. Bit position D2 is the glide on/off signal GL
When the glide switch in the operation unit 602 is off, it becomes "0", and when it is on, it becomes "1". Bit position D3 is the organ type/piano type designation signal OPS, which specifies the envelope characteristics, and is “0” for organ type and “1” for piano type.
becomes. Bit position D4 is damper on/off signal DMP
This is valid only when the envelope characteristic is piano type, and is "0" when the damper is off and "1" when it is on. Bit position D5 is the generator assigner operation mode signal GAM, which allows one key to switch two musical tone generation channels.
This is the designated signal when using the GAM channel.
When the signal is “0”, one key uses one channel (eight sounds are generated), and when the signal is “1”, one key uses two channels.

[Table] (4 sounds generated). FIG. 8 is a configuration diagram of the musical tone generating section 607. In FIG. 8, 801 is a main oscillator, 802 is a sequencer that controls the operation contents of the musical tone generator 607,
803 is an input register unit that latches various data supplied from the CPU 603, 804 is a timer, 805 is a comparison register unit, and 806 is a frequency data processor (hereinafter abbreviated as FDP) that generates frequency data corresponding to the frequency to be generated. ), 807
is a waveform data processor (hereinafter abbreviated as WDP) 808 that performs the waveform interpolation process of equation (2) explained above.
809 is a data read processor (hereinafter abbreviated as DRP) that reads waveform sample data, control data, etc. from the musical tone synthesis data ROM 606, a read pulse forming unit that generates a pulse signal with a predetermined pulse width, and 810 is a WDP 807, DRP 808
811 is a digital/analog converter (hereinafter referred to as DAC) that converts a digital signal into an analog signal.
), 812 consists of two analog switches and one capacitor per channel,
An analog buffer memory section 813 that holds analog signals is an integrator. In the above configuration, 804, 805, 806,
Reference numeral 810 constitutes a note clock generating section that determines musical scales, and based on its output signal, DRP808, which is a data reading section, generates musical tone synthesis data ROM.
Predetermined data is read from 606. Also, input register section 803, comparison register section 805, FDP806, WDP807, DRP80
8. The calculation request flag generation unit 810 is the sequencer 8
02 determines the procedure for processing. When musical tone generation data is supplied from the CPPU 603 to a predetermined channel, for example channel 1, the input register section 803 outputs FDP 806 and WDP 8 at a predetermined timing determined by the sequencer 803.
07, musical tone generation data is supplied to the DRP 808. Then, the DRP 808 reads waveform sample data and control data from the musical tone synthesis data ROM 606. Then, (X _i,o ) shown in equation (2) is the data WD, and (X _i+1,o ) is the data
Supplied to WDP807 as WD. moreover,
WDP807 uses the numerator term of the interpolation coefficient shown in equation (2) based on the read control data as data MLP.
supply to. Furthermore, when the final waveform data is reached, a WEF signal indicating the final waveform data is supplied to the WDP 807. The WDP 807 uses the data WD, WD, and MLP supplied from the DRP 808 to perform waveform calculation processing according to equation (2) and supplies the processed data to the DAC 811. Then, the DAC 811 converts the digital signal supplied from the WDP 807 into an analog signal, and supplies the analog signal to the analog buffer memory section 812, where the capacitor charge corresponding to channel 1 is stored. On the other hand, in the FDP806, the input register section 80
Frequency data is generated based on the musical tone generation data supplied from 3, and is supplied to the register corresponding to channel 1 of the comparison register section 805. Then, the data supplied to the comparison register section 805 and the time data supplied from the timer 804 are compared, and if a match is detected, a matching pulse is read out and supplied to the pulse forming section 809 and the calculation request flag generator 810. do. Then, the read pulse forming section 809 generates a read signal with a predetermined pulse width, and supplies it to the analog buffer memory section 812. The charge stored in the capacitor corresponding to channel 1 in the analog buffer memory section 812 flows into the integrator 813 in response to the read signal. The calculation request flag generator 810 generates and holds a calculation request flag for determining the next waveform sample, that is, the virtual sample point ^(X _i,n,o+1 ). Thereafter, when the processing timing becomes channel 1 again, since the calculation request flag has been generated, waveform interpolation processing is performed in the same manner as described above, and charges are stored in the capacitor in the analog buffer memory section 812. Thereafter, waveform interpolation processing is performed in response to the calculation request flag, and a musical tone waveform is generated. The charge stored in the capacitor is ^(X _i,n,o-1 )
This corresponds to the difference between the waveform sample value ^(X _i,n,o ) and the waveform sample value ^(X i,n,o ) obtained this time. Then, the waveform sample value ^(X _i,n,o ) obtained this time is restored by the integrator 813. Regarding the operation around the analog buffer memory section 812 and the integrator 813, please refer to the patent application filed in 1987-
126413 “Waveform reading device”. FIG. 9 is a block diagram of a specific example of the sequencer 802. In the figure, 901 is a two-phase clock signal φ
a two-phase clock generator that generates a signal φ2 and a signal φ2;
902 is a hexadecimal counter that determines the operation sequence per channel; 903 is a counter that generates the channel code that is currently being processed; 90
4 is a ROM in which operating procedures are stored, and 905 is a decoder. FIG. 10 shows a timing chart of the sequencer 802. Master clock (MCK) from main oscillator 801
The signal is supplied to a two-phase clock generator 901.
A two-phase clock generating section 901 generates two-phase clock signals φ1 and φ2 as shown in FIG.
Signal φ1 is supplied to hexadecimal counter 902 and counter 903
is supplied to. The hexadecimal counter 902 has a 4-bit configuration, and the count-up process is performed at the timing when the signal φ1 changes from "0" to "1", the output signal becomes (1111) ₂ , and then the count-up is performed. and (0101) are set to ₂ . As a result, the output signal of the hexadecimal counter 902 becomes 11 states, that is, (0101) ₂ to (1111) ₂ . This is used as a command step signal. The counter 903 has a 3-bit configuration,
Count-up processing is performed every time the output signal of the 11 counter 902 changes from (1111) ₂ to (0101) ₂ . As a result, the output signal of the counter 903 becomes 8 states, that is, (000) ₂ to (111) ₂ . Use this as the channel code. ROM 904 reads out an instruction code based on the instruction step signal supplied from hexadecimal counter 902 and supplies it to decoder 905 . Decoder 9
05 decodes the instruction code supplied from the ROM 904 and supplies processing control signals to each section. As a result, the calculation time per channel is 2.75μs.
Therefore, each calculation process is performed in 11 instruction steps. Then, the calculation timing will be returned every 22μs. FIG. 11 shows a configuration diagram of a specific example of the analog buffer memory section 812. In the figure, 1101 is an input terminal, 1102 is an output terminal, 1103 to 1108 are analog switches, and C ₁ to C ₈ are capacitors. Analog switch 1103, 1105, 110
The signal AW1~ supplied to the gate input of 7
AW8 is supplied by WDP807. Also,
Analog switch 1104, 1106, 1108
The signals AR1 to AR supplied to the gate inputs of
8 is supplied from a read pulse forming section 809. The analog signal converted by the DAC811 is applied to the input terminal 1101 and is applied to the analog switch 110.
3,1105,1107. and,
If the data corresponds to channel 1, only analog switch 1103 is turned on, and input terminal 1 is turned on.
A charge corresponding to the analog signal applied to the capacitor _C1 is stored in the capacitor C1. Then the read pulse corresponding to channel 1
When AR1 is supplied from the read pulse generator 809 to the gate input of the analog switch 1104, the charge stored in the capacitor _C1 is supplied to the integrator 813 via the output terminal 1102. Analog switch 1103, 1105, 110
7 is synchronized with the operation timing of the WDP 807, so multiple units are not turned on at the same time. Since the analog switches 1104, 1106, and 1108 are turned on in synchronization with the scale frequency, a plurality of them can be turned on at the same time. FIG. 12 is an internal operation timing chart of the musical tone generating section 607. FIG. 12 shows the timing for four channels. Explanation of abbreviations in the figure CRF is a calculation request signal for each channel. Then, the request start point is at the comparison register section 80.
It is synchronized with the coincidence signal supplied from 5. In other words, it is synchronized with the scale frequency, and for example, in the C scale, it occurs every 59.74 μs. CLC indicates waveform calculation timing. DAC indicates the timing at which charge is stored in a capacitor in analog buffer memory 812 via DAC 811. OTC is an integrator 813 that converts the charge stored in the capacitor in the analog buffer memory 812.
It is the timing to supply to the
It occurs in synchronization with the musical scale frequency. The time chart for channel 1 will be explained. The calculation timing corresponding to channel 1 is determined by the channel code generated by the sequencer 802, and as shown in the figure,
Calculation timing occurs every 22μs. ...Signal CRF1 is generated in the middle of channel code 1. Waveform interpolation processing is not performed at the generated timing. ...Signal OTC1 is generated at the same time as signal CRF1 is generated.
is generated, and the charge of capacitor C ₁ in analog buffer memory 812 is supplied to integrator 813 . The pulse width of the signal OTC is about 2 μs. ...When the channel code becomes 1 again, reading processing of waveform sample data, waveform interpolation processing, frequency data updating processing, etc. are performed. ...When the arithmetic processing of channel 1 is completed, the signal
DAC1 is generated and charge is stored in capacitor _C1 via DAC811. ...When the arithmetic processing of channel 1 is completed, the signal
Reset CRF1 and cancel the calculation request. ...Similarly to the above, at the timing when the signal CRF1 is generated again, the charge stored in the capacitor _C1 at the above timing is transferred to the integrator 813.
is supplied to Thereafter, at the same time as described above, one virtual waveform sample value calculation process is performed every time the signal CRF is generated, and the waveform calculation result is supplied to the integrator 813 in synchronization with the generation timing of the signal CRF, that is, with the scale synchronization. Ru. Regarding the relationship between the calculation cycle and the scale period, it is sufficient that the calculation timing of the same channel can be performed twice within the minimum scale period and that the calculation result can be stored in a capacitor in the analog buffer memory section 812. That is, it is sufficient to provide calculation timing corresponding to 10 channels within the minimum scale period. Explanation of how to generate a scale period FIG. 13 shows the transition of the frequency code supplied from the FDP 806 to the comparison register section 805. The timer 804 consists of a 10-bit binary counter, and the output status is expressed in hexadecimal as follows:
Count up sequentially from (000) ₁₆ to (3FF) ₁₆ , and from (3FF) ₁₆ to (000) ₁₆ again,
(000) ₁₆ to (3FF) ₁₆ are repeated based on the signal MCK supplied from the main oscillator 801. That is, the repetition period T _R of the timer 804 is expressed by the following formula. T _R = 2 ¹⁰ × 1 / _MCK = 2 ¹⁰ × 1 / 8.00096MHz = 127.98 μs …(3) The output data transition state of the timer 804 is
It is described as timer output data in the figure. The timer 804 is used to generate the scale period.
The output signal of the FDP 806 is compared with the frequency data supplied from the FDP 806, and if a match is detected, a match pulse is sent out from the comparison register section 805.
The generation cycle of the matching pulse becomes the scale cycle of the scale to be sounded. As shown in FIG. 13, a note clock signal can be generated by updating the frequency data. In other words, the calculation process shown in the formula below is
Performed with FDP806. NFD=MOD(OFD+PD, TD _nax )...(4) NFD is new frequency data. OFD is frequency data before update. PD is scale data determined by the generated scale. TD _nax is the number of output states of the timer 804. In this embodiment, TD _nax is ²¹⁰ , or 1024. Table 8 shows scale data PD corresponding to the 12-tone scale. FIG. 14 is a configuration diagram of a specific example of the FDP 806. In FIG. 14, 1401 is a cent scale data generation unit (hereinafter abbreviated as CPD generation unit) that generates scale data (CPD) expressed in cent scale, and stores cent scale data.
Consisting of ROM, note clock specification data (ND) and waveform sample number specification data (SD)
CPD is selectively generated based on the organ type/piano type designation signal (OPS).
1402 is a beat data gate that selects beat data; 1403 is a vibrato signal generator that generates a vibrato signal; 1404 is a glide signal generator that generates a glide signal; and 1405 is a frequency value expressed in cent scale that is directly proportional to the frequency. 1406 is an arithmetic unit, 1407 is a latch (AL), 140
8 is a latch (designated as BL), 1409 is an adder (designated as FA), 1410 is a buffer, and 1411 is a gate. 1412, 1413, 1414 are bus lines, 1412 is FA bus, 1413 is bus line.
The FB bus and 1414 are the FC bus. In addition, beat data CBD, vibrato data
CVD and Glide Data CGD are also expressed in cents. Structure of various data Center pit data (CPD) Consisting of 11 bits, the upper 4 bits represent the 12-tone equal temperament scale, and the lower 7 bits represent each point of the chromatic scale divided into 128 equal parts. Beat data (CBD), vibrato data (CVD), glide data (CGD)

[Table] Each bit structure is 8 bits, uses two's complement representation, and has a resolution that divides the chromatic scale into 128 equal parts. It also represents positive and negative beat components, vibrato components, and glide components. Description of Vibrato Signal Generating Unit 1403 FIG. 22 shows a configuration diagram of a specific example of the vibrato signal generating unit 1403. In the figure, 2201 is a vibrato that stores vibrato data CVD.
ROM, 2202 is a vibrato address register that stores address data for reading vibrato data stored from the vibrato ROM 2201, 2203 is a shifter used for the delay vibrato effect, and 2204 is an output signal of the shifter 2203 (vibrato data
CVD) to the FB bus, 2205 is the signal supplied from the input register section 803
KD, signal VIB, signal DVIB and sequencer 802
2206 is a gate, 2207 is a gate, and 2208 is an AND gate. The address data stored in register 2202 is
It has a 14-bit configuration, with the lower 11 bits serving as address data for the vibrato ROM 2201 and the higher 3 bits serving as shift data for the shifter 2203. The shifter 2203 controls the amplitude of vibrato data CVD supplied from the vibrato ROM 2201 based on shift data. The relationship between shift data VSFD and output data OSFD of shifter 2203 is as follows. VSFD=(000) ₂ ...OSFD=(00) ₁₆ , VSFD=
(001) ₂ ...OSFD=(CVD/64), VSFD=(010) ₂ ...
OSFD=(CVD/32),…, VSFD=(110) ₂ …
OSFD=(CVD/2), VSFD=(111) ₂ ...OSFD=
(CVD) The condition setting unit 2205 sets the following operating conditions. Vibrato off This is a case where the vibrato on/off signal VIB is "0", and the output of the gate 2206 is forced to always be (00) ₁₆ . Then, the shift data of the shifter 2203 will always be (000) ₂ . As a result, the output data of shifter 2203 becomes (00) ₁₆ . That is, the vibrato data CVD is always (00) ₁₆ . Vibrato on Vibrato on/off signal VIB is “1”
When DVIB is "0", the vibrato is on. Address data stored in register 2202 is supplied to gate 2207 and shifter 2203 via gate 2206. Note that the upper three bits of the address data, that is, the shift data, are forcibly set to (111) ₂ . Then, gate 220
The output of the vibrato ROM 2201 (vibrato data CVD) is supplied as is to the input No. 4. Delay vibrato When the vibrato on/off signal VIB and the delay vibrato on/off signal DVIB are "1", a delay vibrato state is entered. When all of the eight channel key-on/off signals KD are turned off and any one of the key-on/off signals KD is turned on, the gate 2206 is controlled to set the address data to (000) ₁₆ . Then, in the shifter 2203, the amplitude control (0,
CVD/64, CVD/32, CVD/16, CVD/8,
CVD/4, CVD/2, CVD) are performed. Then, when the shift data becomes (111) ₂ , the shift data is forcibly set to (111) ₂ , similar to the vibrato on state. The address data stored in the register 2202 is based on the signal supplied from the sequencer 802.
RDVAD via gate 2207 to the FB bus. The address data subjected to addition processing by the arithmetic unit 1406 is stored in the register 2202 from the FC bus at the rising edge of the signal φ2 by the signal WRVAD. Also, the vibrato is controlled by the signal RDCVD.
Vibrato data stored in ROM2201
CVD is supplied to the FB bus via shifter 2203 and gate 2204. Description of glide signal generation section 1404 Similar to the vibrato signal generation section 1403, the glide signal generation section 1404 also includes a glide ROM for storing glide data, and a glide ROM for storing glide data.
It consists of a glide address register for reading out predetermined glide data from the glide address register, and a controller for controlling generation. There are two operating modes: glide-off and glide-on. Glide-off When the signal GL is “0”, the glide-off state occurs. Glide data CGD is always (00) ₁₆ . Glide on When the signal GL is “1”, the glide is on. This is similar to the well-known glide effect. In other words, 8 channel key-on/
When the key-on/off signal KD of any one channel turns on from all off signals KD, glide data CGD is read from the glide ROM. Then, after a predetermined period of time has elapsed, the glide data CGD becomes (00) ₁₆ again. Description of Exponent Converter 1405 The exponent converter 1405 has a built-in conversion ROM that stores conversion data for converting cent scale data into frequency data ED that is directly proportional to frequency. In this example, frequency data on the cent scale
EXP/ROM uses the upper 4 bits of CFD (bit positions 7 to 10) as address data, and △ uses the 11 bits from bit positions 0 to 10 as address data.
EXP and ROM are available. Then, there is a register that stores the frequency data CFD on the cent scale that has been added in the arithmetic unit 1406 using the signal WREXP, and the above-mentioned EXP・ROM and ΔEXP・ROM that use the data stored in the register as address data. ROM and signals
EXP・ROM, △ by RDEXP, RD△EXP
Data stored in EXP and ROM respectively
It consists of gates that supply the FA bus and FB bus. EXP/ROM is frequency data in 100 cent intervals
It stores 16 words, and ΔEXP・ROM divides 100 cents into ²⁷ , or 128, and stores differential frequency data of 16×128=1920 points at intervals of 0.78 cents. Figure 15 is a processing flowchart showing the data processing procedure of FDP806, in which the calculation processing shown below is performed to convert old frequency data OFD to new frequency data.
The NFD is calculated and supplied to the comparison register section 805. CPD=CPD+CVD CPD=CPD+CGD CPD=CPD+CBD PD=EXP(CPD)+ΔEXP(CPD) NED=OFD+PD Next, the operation shown in FIG. 14 will be explained.
The FDP 806 performs arithmetic processing based on processing command signals sent from the sequencer 802. Table 9 shows the flow of the arithmetic processing sequence. By sequentially executing the command steps shown in Table 9, the processing explained in FIG. 15 is realized and the new frequency data NFD is calculated. The explanations of the symbols listed in Table 9 are as follows. AL sends the data supplied to the FA bus to signal φ2.
Something that latches with a falling edge. BL sends the data supplied to the FB bus to signal φ2.
Something that latches at the falling edge of . CRAL is an instruction to clear latch AL with signal φ2 being “1”. ADD1 is a command to add “1” to the carry input of FA1409. TCA uses the results of calculation processing with FA1409.
Instructions to feed the FA bus. RDCPD is a command for supplying set pitch data CPD generated by the CPD generation unit 1401 to the FA bus. RDCBD is a command to open the beat data gate 1402 and supply beat data CBD to the FB bus. RDCVD is a command to supply vibrato data CVD generated by the vibrato signal generating section 1403 to the FB bus. RDCGD is a command for supplying glide data CGD generated by the glide signal generator 1404 to the FB bus. RDEXP was converted in the index converter 1405
Instruction to supply EXP (CPD) to the FA bus. RD△EXP is a command to supply △EXP (CPD) converted in the index converter 1405 to the FB bus. RDFD is a command to read the old frequency data OFD from the comparison register section 805 and supply it to the FB bus. RDVAD is a command to supply the contents of the vibrato counter in the vibrato signal generating section 1403 to the FB bus. RDGAD is a command for supplying the contents of the glide counter in the glide signal generator 1404 to the FB bus. WRVAD is an instruction to write the result calculated by the FA 1409 to the vibrato counter in the vibrato signal generating section 1403 at the rising edge of the signal φ2. WRGAD is an instruction to write the result calculated by the FA 1409 to the glide counter in the glide signal generating section 1404 at the rising edge of the signal φ2. WREXP is an instruction to write the result calculated by the FA 1409 to the exponent converter 1405 at the rising edge of the signal φ2. WRFD is an instruction to write the result calculated by the FA1409 into the comparison register section 805 at the rising edge of the signal φ2. Note that 11 in the sequencer 802 shown in FIG.
The state 11 occurring in advance counter 902 corresponds to instruction steps 1-11 shown in Table 9. Explanation of operation contents using signal GAM (generator assigner operation mode signal) When signal GAM="0", one key, one channel operation is performed. In this case, the beat data CBD is forced to be in the (00) ₁₆ state. In other words, no beat effect is added. When signal GAM="1", 1 key 2 channel assignment operation is performed. In this case, the 1st channel and the 5th channel, the 2nd channel and the 6th channel, the 3rd channel and the 7th channel, and the 4th channel and the 8th channel are assumed to be the same tone data. Then, force the beat data CBD used for channels 1 to 4 (00) ₁₆
By using the beat data supplied from the CPU 603 as the beat data CBD used for channels 5 to 8, a beat effect can be generated. As described above, since multiple comparators are used and the comparison data is calculated and determined, there is no need to install multiple high-speed frequency dividers (as many as the number of channels) in parallel, and the circuit scale is reduced. Can be made smaller.

【table】

[Table] Furthermore, using the signal GAM, channels 1 to 4
is beat data CBD = (00) ₁₆ , and channel 5 ~
By using the beat data CBD of 8 supplied from the CPU 603 and making channel 1 and channel 5, channel 2 and channel 6, channel 3 and channel 7, and channel 4 and channel 8 the same musical tone generation data, complex tones can be generated. Beat effects can be easily achieved without adding any peripheral circuitry. Furthermore, channel-independent glide effects can be added by simply preparing glide address counters for each channel in the glide signal generating section 1404. FIG. 16 is a block diagram showing a specific example of the comparison register section 805. In the figure, 1601, 1602,
1603 is frequency data register FDR1~FDR
8, 8 channels are available. 1604,1
605 and 1606 are gates GT1 to GT8, and 8
We have prepared channels for you. 1607, 1608,
1609 is a comparator, 1610 and 1611 are decoders, and 1612 is an AND gate. Output signals TM0-TM9 of timer 804 are commonly supplied to comparators 1607-1609. Then, the new frequency data NED calculated by FDP806 is input to registers FDR1 to FDR8.
Each is supplied from the FC bus, and the signal WRFD and signal CLRF (calculation request flag signal) are both “1”
, the new frequency data is stored in the predetermined register FDR.
NFD is written. In other words, data is written only when a calculation request is occurring. Furthermore, when the FDP 806 requires the old frequency data OFD, the signal RDFD is supplied to the decoder 1610, which opens predetermined gates of GT1 to GT8.
Supply the old frequency data OFD to the FB bus. The new frequency data NFD in the data processing means explained in FIG.
When read out through GT1 to GT8, the new frequency data NFD is supplied to the FB bus as the old frequency data OFD. On the other hand, comparators 1607 to 1609 use signals TM0 to TM9 from timer 804 and registers
Frequency data stored in FDR1 to FDR8
A comparison is made with the FD, and if a match is detected, it is output as match signals NC1 to NC8. FIG. 17 is a configuration diagram showing a specific example of the calculation request flag generator 810. In the figure, 1701-17
10 is a NAND gate, 1711 is a decoder, 1
712 to 1719 are RS flip-flops (RSFF), 1720 is a selector, and 1721 is a D-type flip-flop (DFF). Match signal supplied from comparison register section 805
NC1 to NC8 are NAND gates 1701 to 170
8 performs a logical operation with the signal MCK supplied from the main oscillator 801, and the result is
It is supplied to each input of RSFF1712 to 1719. When the match signal becomes "1" (match detected by the comparator), "0" is supplied to the input of RSFF, the output Q becomes "1", and the calculation request signal CRF explained in Fig. 12 becomes "1". becomes. The selector 1720 selects the signal CRF corresponding to the calculation timing and supplies it to the input D of the DFF 1721. Then, when the signal WRCLF in the control data supplied from the sequencer 802 becomes "1", the DFF 172 is activated at the falling edge of the signal φ2.
1, the calculation request signal selected by the selector 1720
CRF is latched and output as calculation request flag signal CLRF. If a calculation request has occurred, the flag signal CLRF is "1"; otherwise, the flag signal CLRF is "0". The signal WRCLF is generated at instruction step 1. That is, the presence or absence of a calculation request is determined at the beginning of the calculation process. Thereafter, at the timing of instruction step 11, a reset (clear) signal, which is one of the control data supplied from the sequencer 802, is activated.
CRCLF is supplied. Then the flag signal
If CLRF is “1”, NAND gate 1709
The output signal becomes “0” and the channel code
selected by decoder 1711 in CHC
Supply “0” to specified inputs of RSFF1712-1713 to reset RSFF (output Q=
“0”). This operation corresponds to the timing of resetting the calculation request signal CRF explained in FIG. Detailed Description of Data Read Processor DRP 808 First, the data format of the musical tone synthesis data ROM 606 (hereinafter referred to as data bank (DBK)) will be described. FIG. 18 is a data configuration diagram of the DBK 606.
Address (0000) The start address indicating the start position of the subsequent composite data is stored in the area from ₁₆ to 128 words. The composite data is composed of control data and waveform data. The control data consists of data specifying the number of repetitions between waveforms and final waveform flag data. The repetition number designation data will be explained.
In this embodiment, the following method is used to simplify the calculation of the interpolation coefficient Nm+n/MN shown in equation (2). (1) In equation (2), the increment value of the Nm+n term was 1, but the increment value of the numerator of the interpolation coefficient is set to α. (2) Replace interpolation coefficient Nm+n/MN with (Nm+n)α/MNα. (3) Fix the MNα term as 2 ¹⁶ . As a result, the interpolation coefficient becomes (Nm+n)α/2 ¹⁶ , and the 1/2 ¹⁶ term only needs to be shifted to the right, eliminating the need to obtain the MN term, making it easier to calculate the interpolation coefficient. Table 10 shows the relationship between the repetition designation data, the increment value α, the number of samples in one cycle of the waveform, and the number of repetitions. If the repetition number designation data is (F) ₁₆ , it is used as a final waveform flag (signal WEF) indicating the final waveform. The control data area of DBK606 is fixed at 128 words regardless of the number of waveforms. Also, one word of control data has a 16-bit structure, as shown below.
The repeat specification data is divided into four groups of 4 bits each. Bit positions 0 to 3...C, C#, D sound Bit positions 4 to 7...D#, E, F sound Bit positions 8 to 11...F#, G, G# sound Bit positions 12 to 15...A, A#, B sound Like this By doing so, the control data can be set differently depending on the scale, and even if the same waveform data within one octave is used, it is possible to keep the rise time of the musical tone and the change time of the waveform shape constant. . Waveform data is PCM with 16 bits per word.
It is data. FIG. 19 is a configuration diagram showing a specific example of the DRP 808. In the figure, 1901 is musical tone synthesis data
DBK address register stores address data for reading predetermined synthesis data from ROM (DBK) 606; 1902 is musical tone synthesis data ROM
(DBK) 1903 is a DBK input buffer that imports synthetic data from 606 into DRP808.
A reference start address gate outputs address data for reading the start address stored in the DBK 606, 1904 is a waveform data memory that stores a value in a waveform sample corresponding to (X _i,n ), and 1905 is a (X _{i+ 1,o}

[Table] 1906 is a waveform data memory that stores waveform sample values corresponding to ), 1906 is a coefficient data memory that stores (Nm+n)α corresponding to the numerator of the interpolation coefficient,
1907 is a start address register; 1908 is an increment generation unit that generates an increment value α of the (Nm+n) α term of the interpolation coefficient; 1909 is a waveform sample number memory that stores sample number n within one cycle of the waveform;
1910 is a waveform number memory that stores the waveform number i; 1910 is a wave offset data gate; 19
12 is an accumulation register (ACC); 1913 is an arithmetic unit consisting of a full adder, latch, and carry flag register; 1914 is a DA bus that supplies data to the latch AL in the arithmetic unit 1913;
15 is a DB bus that supplies data to the latch BL in the calculation unit 1913; 1916 is a DC bus that supplies the calculation results performed in the calculation unit 1913 to each register;
1917 supplies the output of the DBK input buffer 1902 to the waveform data memory 1904, etc.
It is a DBK bus. Next, the configuration of each part will be explained. Waveform data memory 1904, waveform data memory 1905
are registers R (WD) and R that temporarily store the waveform data read from the DBK 606 by signals WRWD and WRWD in the control data supplied from the sequencer 802, respectively.
(WD), and a 16-bit x 8-word memory M (WD), which stores waveform data for 8 channels.
(WD). Normally, the memory is in a read state, and the channel waveform data based on the channel code CHC supplied from the sequencer 802 is stored in the WDP800.
7. Then, the signal WRRAM in the control data from sequence 802 causes the memory to enter the write state, and the registers R(WD) and R(WD)
The waveform data stored in the channel code
Write to a given address in memory based on CHC. The coefficient data memory 1906 is connected to the calculation unit 1913.
A register R (MD) temporarily stores the result of the calculation using the signal WRMD in the control data supplied from the sequencer 802, and a 16-bit x 8-word memory M that stores coefficient data for 8 channels. (MD) and a gate that supplies the output data of the memory M (MD) to the DB bus by a signal RDMD. Normally, the memory is in a read state, and the coefficient data (M (MD)) of the address based on the channel code CHC supplied from the sequencer 802 is sent to the above-mentioned gate and WDP80.
7. Then, the memory enters a write state in response to the signal WRRAM, and the new coefficient data stored in the register R (MD) is written to a predetermined address in the memory based on the channel code CHC. The start address register 1907 is DBK60
Gate 1 supplies the start address read from 6 to the DA bus by signal TDA in the control data from sequencer 802 (the same applies hereinafter);
It consists of a register R (TAD) that temporarily stores the first address read by WRTAD, and a gate 2 that supplies the first address stored in register R (TAD) to the DB bus in response to a signal RDTAD. The increment generation unit 1908 includes a register R (REP) that temporarily stores control data read from the DBK 606 using a signal WRRFP, and an input register unit 8.
A selector selects a predetermined repetition designation data from the control data stored in the register R (REP) based on the note clock designation data ND supplied from the register R (REP), and a selector selects the repetition number designation data selected by the selector. A converter that converts the increment value α shown in the table, a detector that detects the final waveform flag and outputs the final waveform flag WEF [“1”], and a signal
It consists of a gate that supplies converter output data (increment value α) to the DA bus by RDREP. The waveform sample number memory 1909 stores the calculation result (new waveform sample number n) of the calculation unit 1913.
A register R (WSN) temporarily stores the data by the signal WRWSN, and a 16-bit x 8-word memory M that stores the waveform sample number n for 8 channels.
(WSN) and a gate that supplies the output data of the memory M (WSN) to the DB bus by a signal RDWSN. Normally, the memory M (WSN) is in a read state and supplies the channel waveform sample number n based on the channel code CHC supplied from the sequencer 802 to the above-mentioned gate. and the memory M by the signal WRRAM.
(WSN) is in write state and register R
New waveform sample number n stored in (WSN)
is written to a predetermined address in memory based on the channel code. The waveform number memory 1910 is connected to the calculation section 1913.
The calculation result (new waveform number i) is sent to the signal WRWND.
Register R (WND) temporarily stored by
, a 16-bit x 8-word memory M (WND) that stores waveform numbers i for 8 channels, and a memory M
The output data (waveform number) of (WND) is shifted (i x number of samples) based on the waveform sample number designation data SD supplied from the input register section 803, and the waveform number address WNA
a shifter section that outputs the data, a gate 1 that supplies the output data of the memory to the DB bus using the signal RDWND, a gate 2 that supplies the output data of the shifter section to the DB bus using the signal RDWNA, and a gate 2 that supplies the output data of the shifter section to the DB bus using the signal RDWNA. A sample number generator that generates sample number data corresponding to data SD, and a signal
It consists of a gate 3 which supplies the output data of the sample number generator to the DB bus by RDNWS. Normally, the memory M (WND) is in a read state and supplies the channel waveform number i based on the channel code CHC supplied from the sequencer 802 to the gate 1 and the shifter section described above. Then, by the signal WRRAM, the memory M
(WND) is in write state and register R
The new waveform number i stored in (WND) is written to a predetermined address in the memory based on the channel code. The accumulation register (ACC) 1912 is
A register R (ACC) that temporarily stores the calculation result of 913 using the signal WRACC, and a register R (ACC) that temporarily stores the calculation result of 913 using the signal WRACC.
It consists of a gate that supplies data stored in register R (ACC) to the DA bus. FIG. 23 is a configuration diagram showing a specific example of the calculation section 1913. 2301 is a latch AL that stores the contents of the DA bus at the falling edge of the signal φ2;
Cleared by signal DCRAL. 2302 is the signal φ
A latch BL stores the contents of the DB bus on the falling edge of 2; 2303 is a 16-bit adder (FA) with a carry input (CI) and a carry output (CO);
3204 is the carry output signal of FA2303.
A carry flag register stored by WRMD, 2305 is a gate that supplies the output data of FA2303 to the DA bus by signal TCA, 230
6 is the gate that supplies the output data of FA2303 to the DC bus, 2307 is the data (0000) to the DC bus ₁₆
2308 is the input register section 8
Key on/off signal KD supplied from 03
an on/off detection unit that receives the signal RDFLG and the channel code CHC, detects the timing at which the key signal changes from the off state to the on state independently for each channel, and outputs a detection signal, 2309 to 2;
313 is an AND gate, 2314, 2315, 2
316 is an OR gate. When the final waveform flag signal WEF and the signal RDNWS supplied from the increment generating section 1908 are both "1", the output signal of the AND gate 2309 becomes "1", and the latch BL 2302 is reset. When both the signal WEF and the signal WRMD are "1", the output signal of the AND gate 2312 becomes "1", and data (0000) ₁₆ from the gate 2307 is supplied to the DC bus. The offset data generated by the offset data gate 1911 is 256 in decimal notation and corresponds to the storage area for control data. Similarly to the FDP 806, the DRP 808 also performs the arithmetic processing described below based on the control signal supplied from the sequencer 802. Read the start address TAD stored in DBK. The musical tone generation data (ND, SD) supplied from the input register section 803 is sent to the sequencer 80.
By the signal RDRTA supplied from 2
Supply to DC bus. And the signal on the DC bus
ND and SD are stored in the DBK address register 1901 by the signal WRDBK and supplied to the DBK 606. The start address data TAD read from the DBK 606 is sent to the register R of the start address register 1907 by the signal WRTAD.
Store in (TAD). Loading process for specifying the number of repetitions. The arithmetic unit 1913 performs addition processing (TAD+i) between the read start address data TAD and the waveform number i stored in the waveform number memory 1910, and the addition result is stored in the DBK address register 1.
901 , reads the repetition number designation data from the DBK 606 , and stores it in the register R (REP) of the increment generation unit 1908 . Reading processing of waveform samples (X _i,o ). Addition process of the start address data TAD stored in the start address register 1907 and offset data (256) ₁₀ (WAD1=TAD+256)
is performed in the arithmetic unit 1913, and the addition result is sent to ACC.
Store in R (ACC) of 1912. ACC191
2 and the waveform sample number n stored in the waveform sample number memory 1910 (WAD1=
WAD1+n) is performed by the calculation unit 1913 and the addition result is stored in the ACC 1912. and,
Address data stored in ACC1912
Data obtained by shifting WAD1' and waveform number i based on waveform sample number specification data SD (i x number of samples; i = 0, 1, 2, ..., I-
1) is performed in the calculation unit 1913 (WAD1″=WAD1′+i×number of samples), and the addition result is sent to the ACC 1912 and the DBK address register 1.
The waveform sample data corresponding to (X _i,o ) is read from the DBK 606 and stored in the register R (WD) in the waveform memory I 1904 . Reading processing of waveform samples (X _i+1,o ). Address data stored in ACC1912
WAD1″ and the number of waveform samples NWS (generated in the waveform number memory 1910) specified by the waveform sample number specification data SD
= WAD1″+NWS) in the calculation unit 1913, store the addition result in the DBK address register 1901, read the waveform sample data corresponding to (X _i+1,o ) from the DBK 606, and register R (WD) in the waveform memory 1905. Update processing of waveform sample number n. Addition processing of waveform sample number n and signal DADD1 supplied from sequencer 802 (n
=n+1) in the calculation unit 1913 and stored in the waveform number register R (WSN) in the waveform sample number memory 1909. Update processing of interpolation coefficient (Nm+n)α. The interpolation coefficient [(Nm+n)α] stored in the coefficient data memory 1906 and the increment generation unit 190
The calculation unit 1913 performs addition processing with the increment value α generated at step 8, and the addition result is stored in the coefficient data register R in the coefficient data memory 1906.
(MD), and if the addition result overflows, the carry flag register CF in the arithmetic unit 1913 is set to "1". Update processing of waveform number i. Addition processing of the waveform number i stored in the waveform number memory 1910 and the contents of the carry flag register CF explained above (i=i+
CF) in the calculation unit 1913, and the waveform number register R in the waveform number memory 1910 is
(WND). Register R (WND), R (WSD), R (MD),
Data transfer processing for various data stored in R(WD) and R(WD) to the respective memory areas specified by channel code CHC. At the timing of instruction step 11, data transfer processing is performed based on the signal WRRAM supplied from the sequencer 802. Note that the transfer process is not performed when the calculation request flag signal CLRF is "0". This is because no new waveform samples are calculated. Table 11 shows the calculation sequence of DRP808.
By sequentially executing the instruction steps shown in Table 11, the processes described above are realized. In addition, the key on/off signal explained in Table 4
The first process when KD changes from "0" to "1" is an initial process, and the following conditions are set. A signal [“1”] instructing initial processing is generated in the on/off detection unit 2308 in the calculation unit 1913 shown in FIG. Waveform sample number n = (0) ₁₀ settings. Signal WRWSN is supplied to calculation section 1913 at the timing of instruction step 7 shown in Table 11. Then, the output signal of AND gate 2310 becomes "1", and gates 2306 and 230
"1" is supplied to the control input of 7. As a result, (0000) ₁₆ is supplied to the DC bus, and the register R in the waveform sample number memory 1909 is
Store (0000) ₁₆ in (WSN). Waveform number i = (0) ₁₀ settings. At the timing of instruction step 10 shown in Table 11, signal WRWND is supplied to calculation section 1913. Then, the output signal of AND gate 2311 becomes "1", and gates 2306 and 23
"1" is supplied to the control input of 07. As a result, (0000) ₁₆ is supplied to the DC bus, and the register R (WND) in the waveform number memory 1910 is
Store (0000) ₁₆ in. Through the above processing, the waveform number i and waveform sample number n are initialized each time the key-on/off signal KD changes from off to on. Also, the repetition specification data read from DBK606 is (F) ₁₆ , that is, the final waveform flag WEF.
If so, set the conditions as described below. Numerator term of interpolation coefficient (Nm + n) α = (0) ₁₀ settings. Signal WRMD is supplied to AND gate 2312 in arithmetic unit 1913 at the timing of instruction step 9 shown in Table 11. Then, AND
The output signal of the gate 2312 becomes "1", and "1" is supplied to the control inputs of the gates 2306 and 2307. As a result, (0000) ₁₆ is supplied to the DC bus, and (0000) ₁₆ is stored in register R (MD) in coefficient register memory 1906. Number of waveform samples NWS = (0) ₁₀ settings. Signal RDNWS is supplied to AND gate 2309 in arithmetic unit 1913 at the timing of instruction step 7 shown in Table 11. Then,
The output signal of AND gate 2309 becomes "1" and the stored state of latch BL 2302 is cleared (0000) ₁₆ . As a result, the address data of the DBK 606 for reading the waveform sample (X _i+1,o ) becomes equal to the address data for reading the waveform sample (X _i,o ). With the above settings, when it comes to the final waveform data, the final waveform data is used repeatedly without substantially performing waveform interpolation processing. Description of the signals shown in Table 11 The signals described below are supplied from the sequencer 802.

【table】

[Table] RDOSD supplies offset data (256) to the DA bus. RDACC is register R in ACC1912
An instruction to supply data stored in (ACC) to the DA bus. RDREP is an instruction for supplying the increment value α generated in the increment generation unit 1908 to the DA bus. RDWSN is waveform sample number memory 19
A command to supply the waveform sample number n read from memory M (WSN) in 09 to the DB bus. RDWND is a command to supply the waveform number i read from the memory M (WND) in the waveform number memory 1910 to the DB bus. RDWNA is the waveform number address generated in the shifter section in the waveform number memory 1910.
Instruction to supply WNA to DB bus. RDTAD is the start address stored in register R (TAD) in the start address register 1907.
Instructions to feed the DB bus. RDNWS indicates the number of samples generated by the sample number generator in the waveform number memory 1910.
Instructions to feed the DB bus. RDMD is an instruction to supply the coefficient data read from memory M (MD) in the coefficient data memory 1906 to the DB bus. RDRTA is an instruction to supply musical tone generation data (ND, SD) supplied from the input register section 803 to the DC bus. WRDBK is an instruction to store data on the DC bus in register R (DBK) in the DBK address register 1901. WRACC transfers data on the DC bus to ACC191
Instruction to store in register R (ACC) in 2. WRWSN transfers the data on the DC bus to register R (WSN) in the waveform sample number memory 1909.
Instructions to store in. WRMD is an instruction to store data on the DC bus in register R (MD) in coefficient data memory 1906. WRWND is an instruction to store data on the DC bus in register R (WND) in waveform number memory 1910. TDA is stored in the start address register 1907.
An instruction to supply the first address read from DBK to the DA bus. TCA is an instruction to supply data on the DC bus to the DA bus. DCRAL is the latch AL2 in the calculation unit 1913.
Order to clear 301. DADD1 is FA2303 in the calculation unit 1913
A command to supply a carry input signal (+1) to the RDFLG is an instruction to input a new key on/off signal KD to the on/off detection unit 2308 in the calculation unit 1913. WRRAM is the register R (WD) in the waveform data memory 1904 and the waveform data memory 19.
Register R (WD) in coefficient data memory 1906, register R (WSN) in waveform sample number memory 1909, register R (WND) in waveform number memory 1910
The data stored in each memory M
(WD), M (WD), M (MD), M (WSN), M
Instruction to write to (WND). As described above, by storing the start address of the composite data (waveform data, control data) in the data memory (DBK), different waveform data can be generated simply by manipulating the data contents in the data memory without complicating the circuit configuration. can be selected, and different musical tones can be easily generated. Furthermore, when preparing multiple sets of control data (data specifying the number of repetitions) and composing them, the predetermined control data is selected and used, so the control data can be set differently depending on the scale. Even if the same waveform data within one octave is used, the rise time of a musical tone and the change time of a waveform shape can be made constant. Furthermore, since the waveform data, control data, and start address are stored in the same database, and various data are read in a time-sharing manner, the circuit configuration of the data memory DBK can be simplified, and
Interface processing between the data memory and the DRP 808 can be simplified. Detailed Description of Waveform Data Processor WDP807 FIG. 20 is a flowchart of the arithmetic processing of WDP807. There are four types of calculations as the calculation processing of the WDP807. Virtual waveform sample values are obtained by performing waveform interpolation calculations.
Find ^(X _i,n,o ). The virtual waveform sample value ^(X _i,n,o ) is multiplied by the envelope data ED to obtain the envelope-added waveform sample value ^(X _i,n,o,q,r ). Calculate the difference between the previous envelope-added waveform sample value old^(X _i,n,o,q,r ) and the envelope-added waveform sample value new^(X _i,n,o,q,r ) found this time. Then, the difference waveform sample value D(X _i,n,o,q,r ) is obtained. Update envelope data ED. Next, envelope data ED and an envelope addition method will be explained. Envelope data ED consists of 20 bits. The upper 4 bits are EDU (Q) and the lower 16 bits are EDL (R). The method for updating the envelope data ED is the new ED =
It is obtained by performing the calculation process old ED + △ED.
The incremental envelope data △ED is the sustain data DSUS or damper data DDMP supplied from the CPU 603 to the input register section 803.
use. Sustain data and damper data are selected based on the organ-type envelope, piano-type envelope, and key-on/off signal. The formula for calculating the envelope-added waveform sample value is shown below. ^(X _i,n,o,q,r )=^(X _i,n,o )/2 ^q −1/2 ^q+1 r/R・^(X _i,n,o ) …(5) q = 0, 1, 2, ..., Q-1 (Q = 2 ⁴ ) r = 0, 1, 2, ..., R-1 (R = 2 ¹⁶ ) The envelope data ED is monotonically increased, that is,
By setting new ED = old ED + △ED (constant) and executing equation (5), an exponential characteristic damping (falling) envelope can be added. Also, by monotonically decreasing, that is, new ED = old ED - △ED (constant),
An exponential attack envelope can be added. By performing such processing, an envelope with exponential characteristics is not generated, but can be obtained only by calculation, and envelope data ED can be generated with a simple configuration. FIG. 21 is a configuration diagram showing a specific example of the WDP 807. In the figure, 2101 is a waveform data gate;
2102 is a waveform data gate, 2103 is an envelope increment generation unit (△ED generation unit) that generates an increment value of envelope data ED, and 2104 is used to store old waveform sample values ^(X _i,n,o,q,r ). old waveform data memory section, 2105 is envelope data
Envelope data memory section (ED memory section) 2106 for storing ED is a multiplication section, and 2107 is (5)
2108 is a shifter section that performs the operation of 1/2 ^q or 1/2 ^q+1 shown in the formula; 2108 is an operation section consisting of a full adder, latch, carry flag register, etc.;
109 is an output buffer register (OBR) that stores the differential waveform sample value D^(X _i,n,o,q,r )
Reference numeral 2110 denotes analog switches 1103 to 1107 (switches for storing charge in capacitors _C1 to _C8 ) (first switch) in the analog buffer memory section 812.
2111 is the latch AL in the calculation unit 2018.
2112 is the WB bus that supplies data to the latch BL in the calculation unit 2108.
A bus 2013 is a WC bus that supplies the results of the arithmetic processing performed by the arithmetic unit 2108 to each register. Next, the configuration of each part will be explained. △ED
The generation unit 2103 includes a selector for selecting either sustain data DSUS or damper data DDMP as incremental data ΔED, and an input register unit 8.
Key on/off signal supplied from 03
KD, a controller that generates a selection signal from the organ type/piano type designation signal OPS and the damper on/off signal DMP, and the signal KD, signal OPS, and signal DMP.
A virtual key signal generator generates a virtual key on/off signal from the final waveform flag signal WEF supplied from the increment generating section 1908 in the DRP 808 and outputs a virtual key signal EADG. Table 12 shows the selection contents of the incremental data ΔED and the generation state of the virtual key signal EADG. When the signal OPS shown in Table 7 is “0”, that is, the organ type is specified, the virtual key signal EADG is
This is equivalent to the on (“1”) and off (“0”) states of the key on/off signal KD. When the signal OPS is "1", that is, the piano type is specified, the virtual key signal EADG is in the state described below. When the signal WEF is “0” (a) When the signal DMP (damper on/off signal shown in Table 7) is “0”, the virtual key signal
EADG becomes “on” state. (b) When signal DMP is “1”, virtual key signal
EADG turns on the key on/off signal KD,
Equivalent to off state. When the signal WEF is "1", the virtual key signal EADG is in the off state regardless of the states of the signal DMP and the key on/off signal KD. Explanation of the function of the virtual key signal EADG When the signal WEF becomes "1" and the final waveform data is repeatedly used to generate a sustained musical tone, if the organ type is specified, the problem will occur because the musical tone characteristics will be equal to the organ type musical tone characteristics. do not. When specifying a piano type, the musical tone characteristics must be attenuation characteristics, and even if the signal WEF = "1" and a sustained tone is generated by repeatedly using the final waveform data, the virtual key signal EADG is turned off and the attenuation is performed. An envelope characteristic is added to force the musical tone characteristic to be a damping characteristic. The old waveform data memory section 2104 is
A register R (OWD) temporarily stores the calculation result of 08 by the signal WROWD supplied from the sequencer 802, and a register R (OWD) that temporarily stores the calculation result of 08 by the signal WROWD supplied from the sequencer 802, and the envelope added waveform sample value ^ (X _i,n,o,q,r ), and a gate that supplies the output data of the memory M (OWD) to the WB bus in response to a signal RDOWD. Normally, the memory M (OWD) is in a read state and supplies the envelope-added waveform sample value of the address based on the channel code CHC supplied from the sequencer 802 to the above-mentioned gate. The signal WRRAM then puts the memory M (OWD) into the write state, and the data stored in the register R (OWD) is transferred to the memory M.
(OWD). The ED memory unit 2104 includes registers R (EDL) and R (EDU) that store the calculation results of the calculation unit 2108 by signals WREDL and WREDU, respectively.
, memories M (EDL) and M (EDU) that store envelope data ED for 8 channels, and memory M
(EDL) output data by signal RDEDL
Gate L that supplies the WB bus and memory M
(EDU) output data by signal RDEDU
It consists of a gate U that supplies the WB bus.
Memory M (EDL) is 16 bits x 8 words, Memory M
(EDU) is 4 bits x 8 words. usually

[Table] Memories M (EDL) and M (EDU) are in a read state, and envelope data ED at an address based on the channel code CHC is read out and supplied to the gates L and U, respectively.
Further, the signal EDU is sent to the multiplier 2106, and the signal EDL
is supplied to the shifter section 2107. and the memory M by the signal WRRAM.
(EDL) and M (EDU) enter the write state, and the data stored in registers R (EDL) and R (EDU) are written to memories M (EDL) and M (EDU). The multiplier 2106 converts the waveform data into a signal.
Register R (MLP) temporarily stored by WRMLP
1, and temporarily stores the coefficient data MLP supplied from the DRP808 when the signal SELWE="0",
When the signal SELWE="1", the register R (MLP2) that temporarily stores the envelope data EDL supplied from the ED memory unit 2105 and the register R
A 16-bit x 16-bit = 32-bit multiplier in which the data stored in (MLP1) is the multiplicand (two's complement representation) and the data stored in register R (MLP2) is the multiplier (absolute value representation). , signal RDMLP
It consists of a gate that supplies the upper 16 bits of the multiplication result of the multiplier to the WB bus. The shifter unit 2107 has a register R (SFT) that temporarily stores the calculation result of the calculation unit 2108 in response to a signal WRSFT, and the data stored in the register R (SFT) is transferred to the envelope data EDU supplied from the ED memory unit 2105. A shifter that performs a shift operation (R(SFT)/2 ^q ; q = 0, 1, 2, ..., 2 ⁴ -1) based on the signal WRSFA, and a register R (SFA) that temporarily stores the output data of the shifter using the signal WRSFA. and a signal
A gate A that supplies data stored in register R (SFA) by RDSFA to the WA bus, and a signal
It consists of a gate B that directly supplies shifter data to the WB bus by RDSFB. FIG. 24 is a configuration diagram showing a specific example of the calculation unit 2108. 2401 is an inversion gate that inverts the data on the WA bus according to the signal INV; 2402
is a latch AL that temporarily stores the output data of the inverting gate 2401 at the falling edge of the signal φ2;
The storage state becomes (0000) ₁₆ by WCRAL,
In other words, it is reset. 2403 is a latch BL that temporarily stores the data on the WB bus at the falling edge of signal φ2; 2404 is a 16-bit adder (FA) having a carry input and a carry output; 2405 is a 16-bit adder (FA) having a carry input and a carry output;
A carry flag register ECF stores the carry output of FA2404 using the signal WREDL and resets it using the signal RDEDL; 2406 is an AND gate; 2407 is an OR gate; 2408 is a signal
WA output data of FA2404 by WTCA
Gate A, 2409, which supplies the bus, Gate B, 2410, which supplies data (FFFF) ₁₆ to the WC bus.
is the gate C that supplies the data on the WB bus to the WC bus, and 2411 is the gate C that supplies the data on the WB bus to the WC bus.
Gate D, 2412 supplies data (0000) ₁₆ to the WC bus. Gate E, 241 supplies data (0000) 16 to the WC bus.
3 is signal TBC, signal WREDU, signal WREDL,
This is a gate selector that selects any one of gates B2409 to E2412 based on the output signals (bit position 4) of signals EADG and FA2404. The gates selected by the gate selector 2413 will be explained. The gate C2410 is selected by the signal TBC supplied from the sequencer 802, and the data on the WB bus is supplied to the WC bus. When the virtual key signal EADG supplied from the △ED generation unit 2103 is in the on state, the signal
Gate E by WREDL or signal WREDU
2412 is selected and data (0000) ₁₆ is supplied on the WC bus. That is, the envelope data EDI and EDL are both set to (0000) ₁₆ . As a result, the envelope-added waveform sample value ^(X _i,n,o,q,r )=^(X _i,n,o ). Also, the output signal of FA2404 (bit position 4)
When is "1" and signal WREDU is supplied, gate B2409 is selected and data (FFFF) ₁₆ is supplied to the WC bus. That is, the envelope data EDI is always set to (F) ₁₆ . In states other than the above, gate D2411 is selected and the output data of FA2404 is supplied to the WC bus. Note that the signal WRRAN supplied to the old waveform data memory section 2105 and the ED memory section 2106
is the same as the signal WRRAM described for DRP808. WDP807 also DRP808, FDP
Similarly to 806, the following arithmetic processing is performed based on the control signal supplied from the sequencer 802,
The above-mentioned processing contents are realized. Find the virtual waveform sample value (X _i,n,o ). Signals RDWD, RDWD (instruction step 2
The waveform sample values (X _i,o ) and (X _i+1,o ) supplied from the DRP808 by
Supplied to WA bus and WB bus, calculation unit 2108
The waveform sample value is stored in the latches AL and BL at the falling edge of the signal φ2. At this time, the calculation unit 210
The data stored in the latch AL by the signal INV applied to the latch 8 becomes inverted data, that is, (X _i,o ). And Latch AL2402, Latch BL24
The calculation unit 210 uses the data stored in 03.
At step 8, addition processing [( _i,o ) + (X _i+1,o ) + 1], that is, [(X _i-1,o ) - (X _i,o )] is executed, and the calculation result is transferred to the WC bus. The multiplicand register R in the multiplier 2106 is output by the signal WRMLP.
(MLP1) at the rising edge of signal φ2, and the interpolation coefficient (Nm+n) α supplied from DRP808 is written to multiplier register R.
(MLP2). Then, multiplication of [(X _i+1,o )−(X _i,L )]×(Nm+n)α is executed in the multiplication unit 2106. It is assumed that the multiplication result becomes a correct value by the end of instruction step 4. Next, the rectangular sample value (X _i,o ) is supplied to the WA bus by the signal RDWD, the multiplication result is supplied to the WB bus by the signal RDMLP, and the respective data are sent to the latches AL and BL at the falling edge of the signal φ2. (corresponds to instruction step 5). Note that the multiplication result uses the upper 16 bits of the multiplier. This is equivalent to 1/2 ¹⁶ processing. By executing the addition process in the calculation unit 2108, the virtual waveform sample value (X _i,n,o ) expressed by equation (2) is obtained. Waveform sample value with envelope data^
Find (X _i,n,o,q,r ). The virtual waveform sample value ^(X _i,n,o ) is defined as the signal
WRMLP and signal WRSFT (corresponding to instruction step 6) are used to store the multiplicand register R (MLP1) in the multiplier section 2106 and the register R (SFT) in the shifter section 2107 at the rising edge of the signal φ2. In addition, envelope data supplied from the ED memory unit 2105 to the multiplication unit 2106
EDL signal SELWE (corresponds to instruction step 6)
The multiplier register R in the multiplier 2106 is
(MLP2) and multiplication process [^(X _i,n,o ) ×
r]. On the other hand, the register R in the shifter section 2107
Virtual waveform sample value stored in (SFT)^
(X _i,n,o ) is the envelope data supplied from the ED memory section 2105 to the shifter section 2107.
Based on EDU (Q), shift operation [^
(X _i,n,o )/2 ^q ], and by the signal WRSFB (corresponding to instruction step 7), the shifter section 2107
The data is stored in the output register R (SFB) of the internal memory. The multiplication result performed by the multiplier 2106 is then applied to the signal TBC and the signal WRSFT (instruction step 8).
), the envelope data is stored in register R (SFT) in the shifter section 2107.
Perform shift operation based on EDU (Q). The data stored in the output register R (SFB) in the shifter section 2107 is controlled by the signals RDSFA and RDSFB (corresponding to instruction step 9).
(X _i,n,o )/2 ^q ] by the latch in the calculation unit 2108
BL, the shift result data 1/2 ^q+1・r/2 ¹⁶・^(X _i,n,o )] of the shifter section 2107 is logically inverted by the signal INV, and is sent to the latch AL in the calculation section 2108. Store each. Then, the envelope added waveform sample value ^(X _i,n,o,q,r ) is obtained by executing the addition process in the arithmetic unit 2108. Find the difference waveform sample value D (X _i,n,o,q,r ). Envelope added waveform sample value^(X _i,n,o,q,r )
The old waveform memory section 21 is sent by the signal WROWD.
At the same time, the output data of the FA2404 is supplied to the WA bus by the signal TCA, and the logic is inverted by the signal INV.
Store in AL. In addition, the old envelope added waveform sample value is read out from the old waveform memory section 2104 by the signal RDOWD, and the arithmetic section 2104
Store in latch BL in 08. Then, by executing addition processing in the calculation unit 2108, the difference waveform sample value D^
(X _i,n,o,q,r ) is determined and by the signal WOBR
The differential waveform sample value is stored in register R (OBR) in the OBR 2109. Updated envelope data ED. By signals RDEDL and RD△ED (corresponding to instruction step 3), envelope data ED is transferred from the ED memory unit 2105 to the △ED generation unit 2103.
Incremental data ΔED is read out to the WA bus and WB bus, respectively, and stored in the latches AL and BL in the arithmetic unit 2108, respectively, at the falling edge of the signal φ2. Then, the calculation unit 2108 executes the addition process (EDL+△ED) to create the new envelope data ED.
Find the signal WREDL (corresponding to instruction step 4)
As a result, the new envelope data ED is stored in the register R (EDL) in the ED memory unit 2105, and the adder FA in the calculation unit 2108 is
The carry output of 2404 is stored in the flag register ECF 2405 in the calculation unit 2108. The envelope data EDU is read out by the signal RDEDU (corresponding to instruction step 6).
The calculation unit 2108 performs addition processing between the contents of the register ECF 2405 and the envelope data EDU to obtain new envelope data EDU. Signal the obtained envelope EDU
By WREDU, it is stored in register R (EDU) in the ED memory unit 2105. And, like DRP808, the signal
Register R (EDL), R by WRRAM
The various data stored in (EDU) and R (OWD) are transferred to the respective memory areas specified by the channel code CHC. Analog buffer memory section 812, DAC8
The timing of supplying data to 11 will be explained. The write pulse generated by the write pulse generator 2110 is reset by the signal CRDAS (corresponding to instruction step 9). Then, by signal WROBR (corresponding to instruction step 11), register R (OBR) in OBR2109 is
Store the difference waveform sample value D^(X _i,n,o,q,r ) in
The digital signal is supplied to the DAC811 to convert it into an analog signal, and the analog buffer memory section 8
At the same time, the write pulse generating section 2110 sets a write pulse corresponding to the channel specified by the channel code CHC, and supplies it to the analog switches AW1 to AW8 in the analog buffer memory section 812. At this time, if the signal CLRF is "0" (when no calculation request is being made), the write pulse is not set. Table 13 shows the calculation sequence of WDP807.
By sequentially executing the instruction steps shown in Table 13, the processing described above is realized. The control signals shown in Table 13 will now be explained. The signals described below are provided by sequencer 802. RDWD is a command to supply the waveform data WD supplied from the DRP808 to the WA bus. RDWD is a command to supply the waveform data WD supplied from the DRP808 to the WB bus. RDΔED is a command for supplying sustain data DSUS or damper data DDMP selected in the ΔED generation unit 2103 to the WA bus as incremental data ΔED.

[Table] RDSFA is a command to supply the output data of the shifter in the shifter unit 2107 to the WA bus. RDEDL is a command for supplying envelope data EDL read from memory M (EDL) in the ED memory unit 2105 to the WB bus. RDMLP is an instruction for supplying the output data (upper 16 bits) of the multiplier in the multiplication unit 2106 to the WB bus. RDEDU is a command for supplying envelope data EDU read from memory M (EDU) in the ED memory unit 2105 to the WB bus. RDSFB is a register R in the shifter section 2107.
Data stored in (SFB) (^(X _i,n,o )/2 ^q )
instruction to supply the WB bus. RDOWD is a command for supplying the envelope-added waveform sample value read from the memory M (OWD) in the old waveform memory section 2104 to the WB bus. WRMLP multiplies the data on the WC bus by the multiplication unit 21
Instruction to store in multiplicand register R (MLP1) in 06. WREDL is an instruction to store data on the WC bus in register R (EDL) in the ED memory unit 2105. WRSFT transfers data on the WC bus to the shifter unit 2.
Instruction to store in register R (SFT) in 107. WREDU is an instruction to store data on the WC bus in register R (EDU) in the ED memory unit 2105. WROWD is an instruction to store data on the WC bus in register R (OWD) in the old waveform data memory section 2104. WROBR transfers data on the WC bus to OBR210
Instruction to store in register R (OWR) in 9. INV inverts the logic of the data on the WA bus,
The inverted data is sent to the latch AL in the calculation unit 2108.
Instructions to supply to 2402. WADD1 is FA2404 in the calculation unit 2108
A command to supply a carry input signal (+1) to the WCRAL is the latch AL2 in the calculation unit 2108.
Command to clear 402. SELWE is a data selection instruction to be stored in the multiplier register R (MLP2) in the multiplier 2106. The selection data is coefficient data (MLP) supplied from the DRP 808 and envelope data EDL supplied from the ED memory section 2105. WRSFB transfers the output data of the shifter in the shifter unit 2107 to the register R in the shifter unit 2107.
Instruction to store in (SFB). TBC is an instruction to supply data on the WB bus to the WC bus. CRDAS is a command for resetting the write pulse supplied from the write pulse generation section 2110 to the analog buffer memory section 812. TCA is an instruction for supplying output data of the FA 2404 in the calculation unit 2108 to the WA bus. Furthermore, the virtual key signal EADG shown in Table 12
When E2412 is in the on state, gate selector 2413 in arithmetic unit 2108 selects gate E2412, and both envelope data EDL and EDU become data (0000) ₁₆ . As a result, the envelope-added waveform sample value ^(X _i,n,o,q,r ) = ^(X _i,n,o )
(q=0, γ=0). Then, when the virtual key signal EADG turns off, the envelope data ED is updated (ED=
ED+△ED) starts. As a result, arithmetic processing is performed to obtain the envelope-added waveform sample value shown in equation (5), and a musical sound waveform with a damping characteristic is obtained. Furthermore, when the envelope data ED update process progresses and the envelope data EDU becomes (1111) ₂ , the gate B2409 in the calculation unit 2108 is selected at the envelope data EDU update timing, and the envelope data EDU is always (1111). It will be in state ₂ . This state corresponds to the stop of sound generation of the musical sound waveform. As described above, the waveform interpolation method is expressed as the interpolation coefficient (Nm+n) with the correction term added, as shown in equation (2).
Since it is realized by α/HN, it is possible to prevent the generation of unnecessary noise components even if the level difference between waveforms is large. Furthermore, in areas where the waveform shape changes little, data compression becomes possible by reducing the amount of waveform data stored in the data memory section and increasing the number of repetitions. Furthermore, a converter for converting into an analog signal is installed.
Since it consists of two DACs and an analog buffer memory section, only one DAC is required, and each channel operates independently, so even if two channels of sound are played at the same time, there will be no cross-modulation distortion due to quantization distortion. will no longer occur. Furthermore, since the sampling frequency is an integral multiple of the fundamental frequency of the waveform, all folding components and sample wave components produced by quantization can be matched to harmonics of the fundamental frequency. You can create a sound without any cloudiness. Next, the interrelationships between the various parts within the musical tone generating section 607 will be explained. First, the input register section 803 will be explained. The input register unit 803 includes registers R (ADD) and R (DAT) that temporarily store I/O port address data, musical tone generation data, sustain data, etc. supplied from the CPU 603, and
A signal indicating that new data has been supplied from the CPU 603 to the input register section 803
)
A flag register (register WRCF,
When instructing, it becomes “1”) and register R.
The address stored in (ADD) is used as the write address, the channel code CHC supplied from the sequencer 802 is used as the read address, and the register file (musical sounds for 8 channels) that stores the musical tone generation data stored in register R (DAT) Stores generated data and has a volume of 8 bits x 8 words)
and an effect register section that stores sustain data, damper data, beat data, and effect control data based on the address data of register R (ADD). The timing for transferring new data stored in register R (DAT) to the register file or effect register section is when register WRCF is set to “1”.
In this state, the signal WRDAT is sent from the sequencer 802.
When supplied, the data stored in register R (DAT) is transferred to a predetermined address based on the I/O port address stored in register R (ADD). Then reset register WRCF. Signal supplied from sequencer 802
WRDAT is a data capture control signal to the register file or effect register section, and is supplied to the input register section 803 at each timing of instruction step 1 shown in Tables 9, 11, and 13. The reason why new data is imported into the register file or effect register section at the timing of instruction step 1 is that EDP806, WDP807 and DRP808
If musical tone generation data and various effect data change while various arithmetic processes are being executed within the system, correct arithmetic processes will not be performed. Therefore, it is fetched at instruction step 1, which starts arithmetic processing. Explanation of mutual relationships An explanation corresponding to channel 1 will be given. Note that it is assumed that the calculation request flag signal CCRF is generated. When the channel code CHC generated by the sequencer 802 reaches the timing of channel 1,
The musical tone generation data corresponding to channel 1 is output from the register file in the input register section 803.
Supplied to FDP806, WDP807, and DRP808. Then, as mentioned in the detailed explanation of the DRP808, the DRP808 receives the start address, control data, waveform data (X _i,o ) and (X _i+1,o ) from the DBK606 based on the musical tone generation data. The coefficient data (Nm+n) α obtained based on the read control data and the waveform data (X _i,o ) and (X _i+1,o ) read from the DBK606 are stored in the memory M in the DRP808 at the timing of instruction step 11. (MD), memory M (WD), memory M
(WD). On the other hand, in WDP807, instruction steps 1 to
During the timing of 10, the coefficient data and waveform data (X _{i,o-1) being read from the memory M (MD), memory M (WD), and memory M (WD) in the DRP808 based on the channel code CHC} .
As described in the detailed explanation of the WDP 807, waveform calculation processing is performed using and (X _i+1,o-1 ). Then, at the timing of instruction step 11, the calculation result (difference waveform sample value D^
(X _i,n,o-1,q,r ) is register R in WDP807
(OBR) and supplied to the DAC811. The processing of ~ above is performed on channel 1 of the channel code CHC generated from the sequencer 802.
Instruction steps 1 to 11 corresponding to the instruction steps 1 to 11 are executed within the same timing. Then, when the channel code CHC corresponding to channel 1 is generated again from the sequencer 802, the following processing is performed. Similar to the above explanation, the musical sound generation data corresponding to channel 1 is FDP806, WDP8
07, supplied to DRP808. Similar to the above explanation, with DRP808,
Starting address, control data, waveform data stored in DBK606 (X _i,o+1 ), (X _i+1 ),
(X _i+1,n+o ) is read and stored in memory M (MD), memory M (WD), and memory M (WD). However, the difference from the content explained above is that the control data and waveform data read from the DBK606 are data based on the waveform number i and waveform sample number n that were updated at the timing described above, that is, at the previous calculation timing of channel 1. becomes. Similarly to the above, the memory M in the DRP808
(MD), Memory M (WD), Memory M (WD)
Waveform calculation processing is performed based on the data successively output from. The data used for waveform calculation processing at this calculation timing are the coefficient data, waveform data (X i,o ), and waveform data (X _i,o ) that were read into the DRP 808 at the previous channel 1 calculation timing.
(X _i+1,o ). After that, based on the calculation request flag signal CLRF,
The above process is repeated at the calculation timing corresponding to channel 1. As described above, the data read by the DRP 808 is used for waveform calculation processing performed by the WDP 807 at the next calculation timing (when the calculation request flag signal CLRF is generated). In this way, the operation speed of the components of each section can be reduced by not performing all the readout and waveform calculation processing within the same calculation timing, but by dividing the processing timing in terms of time and performing pipeline processing. In the above explanation, data memory (DBK)
The waveform data stored in the DRP808 was stored in the form of PCM data for one cycle of the waveform, but the results of waveform symmetry, DPCM conversion, and ADPCM conversion are stored in the DBK as waveform data, and the DRP808 Data compression of waveform data becomes possible by performing restoration processing within the . Effects of the Invention As explained above, the musical tone generating device of the present invention uses at least two musical sound waveforms out of a plurality of musical sound waveforms from the start of sound generation to the end of musical sound generation and the selectively extracted musical sound waveforms. a data memory section that stores a plurality of sets of control data used when forming a synthesized waveform; a note clock generator that determines a musical tone scale;
a data reading unit that reads predetermined control data from one waveform sample data and a plurality of sets of control data; and a waveform calculation unit that calculates composite waveform sample data using the two waveform sample data and control data read by the reading unit. , and a conversion section that converts the digital output signal of the waveform calculation section into an analog signal, and is configured to generate a musical sound waveform, so that the shape of the musical sound waveform can be changed over time, and the shape can be changed naturally. It can simulate musical instrument sounds. Furthermore, since multiple sets of control data are prepared and synthesized, it is possible to select and use the control data of a predetermined (scale), and even if the same waveform data within one octave is used, it is possible to Change time can be kept constant. Furthermore, by making the sampling frequency, which is the output signal of the note clock generator, an integer multiple of the fundamental frequency of the waveform, the aliasing components that occur and the sample wave components that occur due to quantization can all be made to match the harmonics of the fundamental frequency. It has the advantage of being able to create a clear sound.

[Brief explanation of the drawing]

1 to 5 are explanatory diagrams of the operation of the present invention, FIG. 6 is a block diagram of an electronic musical instrument employing the musical tone generating device of the present invention, and FIG. 7 is a case in which data is supplied from the CPU 603 to the musical tone generating section 607. 8 is a block diagram of the musical tone generator 607, FIG. 9 is a block diagram of a specific example of the sequencer 802, FIG. 10 is an operation time chart of the sequencer 802, and FIG. 11 is a diagram of the analog buffer. Memory section 812
FIG. 12 is a configuration diagram of a specific example of the musical tone generating section 60.
7 internal operation time chart, Figure 13 is
A transition diagram of frequency data supplied from FDP806 to comparison register section 805, Fig. 14 shows FDP80
A configuration diagram of a specific example of 6, Figure 15 is FDP806
FIG. 16 is a block diagram showing a specific example of the comparison register section 805;
FIG. 17 is a configuration diagram showing a specific example of the calculation request flag generator 810, FIG. 18 is a data configuration diagram of the DBK 606, FIG. 19 is a configuration diagram showing a specific example of the DRP 808, and FIG. 20 is a calculation diagram of the WDP 807. Flowchart of processing, FIG. 21 is a configuration diagram showing a specific example of WDP807, FIG. 22 is a vibrato generation section 140
FIG. 23 is a configuration diagram showing a specific example of 3.
FIG. 24 is a configuration diagram showing a specific example of the calculation unit 2108. 601...Keyboard section, 602...Operation section, 603
...Central processing unit, 604...RAM, 605...
...ROM, 606...Musical tone synthesis data ROM, 6
07...Musical tone generator, 801...Main oscillator, 80
2...Sequencer, 803...Input register section,
804...Timer, 805...Comparison register section, 806...Frequency data processor, 807
... Waveform data processor, 808 ... Data read processor, 809 ... Read pulse forming section, 810 ... Calculation request flag generation section, 811 ...
...DAC, 812...Analog buffer memory section,
813...Integrator.

Claims (1)

[Scope of Claims] 1. Control data used when forming a composite waveform for at least two or more musical sound waveforms out of a plurality of musical sound waveforms from the start of sound generation to the end of sound generation and the selected and extracted musical sound waveforms. a data memory section that stores a plurality of sets of control data, a note clock generator that determines musical scales, and a note clock generator that generates the plural sets of control data from the data memory section based on the output signal of the note clock generator, using two waveform sample data and a pronunciation scale. a data readout unit that selectively reads out one set of control data from the readout unit; a waveform calculation unit that calculates composite waveform sample data using the two waveform sample data read out by the readout unit and the control data; and a conversion section that converts the output signal into an analog signal, and the calculation content executed by the waveform calculation section is based on the two waveform samples f read out by the data reading section.
(X _i,o ), f(X _i+1,o ), and control data in which M _i is the number of waveform transitions from f(X _i ) to f(X _i+1 ),
A virtual sample value f^(X _i,n,o ) is obtained by performing the waveform interpolation calculation shown in the following equation _, and f^(X _{i +1} )
A musical tone generating device that generates a musical sound waveform whose waveform transition time is similar to that of the musical tone generator. f^(X _i,n,o )=[f(X _i+1,o ) −f(X _i,o )]×(Nm+n)/M _i・N+f(X _i,o ) i=0,1 , 2,...I-1 Waveform number m=0, 1, 2,...M _i -1 Repetition number n=0, 1, 2,...N-1 Number of waveform samples