JPH0580770A - Bit quantity conversion device - Google Patents

Abstract

PURPOSE:To reflect the contents of digital data which are discarded at the time of conversion upon digital data after the conversion even when the digital data of multi-bit constitution are converted into the digital data of less-bit constitution. CONSTITUTION:The input digital data of L-bit constitution which are inputted one after another at a specific sampling period T are converted into the output digital data of less M-bit constitution (M=L-N), which are outputted. A data generating means generates '1' in a time slot obtained by dividing the sampling period T by (m) with probability corresponding to contents (value) that the high-order (n) bits among the low-order N bits (n<=N) of the input digital data have. An adding means 15 adds the data '1' outputted by the data generating means at the sampling period T/m to the high-order M bits of the input digital data one after another at points of time corresponding to the time slots and outputs the digital data of new M-bit constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit number converter for converting digital data having a plurality of bits into digital data having a bit number smaller than that.

[0002]

2. Description of the Related Art Electronic musical instruments have been greatly improved in their performance with the rapid development of electronic and digital technologies, and they have overcome the drawback that "electronic musical instruments lack the timbre of natural musical instruments". , Further progressing and developing. In particular, improvements in the basic performance of various digital signal processing devices have made electronic musical instruments more expressive,
It has become possible to synthesize a variety of musical sounds.
Generally, when a digital filter, a sound source, an envelope generating circuit, a reverberation effect device, and the like are configured using various digital signal processing devices, musical tone signals and the like are processed as digital data having 19 to 30 bits. In an electronic musical instrument or the like, in order to output the processed digital data as a final musical tone signal, the digital data of 19 to 30 bits is output to an analog sound system or the like through a digital-analog converter (DAC). ing.

[0003]

At this time, there is no problem if the bit configuration of the output digital data is the same as the bit configuration of the digital data that can be processed by the DAC. The bit configuration of digital data that can be processed is larger than that of the DAC. Therefore, the DAC inputs only the upper-order bit that can be processed in the digital data processed by the musical tone generator or the like and outputs it as the final musical tone signal. In such a case, even if the truncated bits of the digital data processed by the musical tone generating device or the like contain meaningful data as a musical tone signal, it is impossible to reproduce it by the DAC. It was

The present invention has been made in view of the above-mentioned points, and even when digital data having a plurality of bits is converted into digital data having a bit number having a smaller number of bits than that, the digital data is truncated at the time of the conversion. It is an object of the present invention to provide a bit number conversion device capable of reflecting the contents of the above in the converted digital data.

[0005]

A bit number conversion apparatus according to the present invention has an L-level input at a predetermined sampling period T.
The input digital data of bit structure is converted into M bit structure (M =
L-N) output digital data is converted and output, in a bit number conversion device, the sampling period T is divided into m timeslots, and the upper digit n bits of the lower digit N bits of the input digital data Data creating means for generating data "1" with a probability corresponding to the value of (n≤N), and data "1" from this data creating means are added to the upper digit M bits of the input digital data and added. And a summing means for outputting the result as output digital data of M-bit configuration.

[0006]

In the bit number conversion device according to the present invention, the input digital data of the L bit structure, which is input one after another at the predetermined sampling period T, has the M bit structure of which the number of bits is smaller than that (M = L−N). The output digit data is converted into the output digital data and output, but the contents of the upper digit n bits (n ≦ N) of the lower digit N bits are not simply truncated as in the conventional case. The (value) is reflected in the converted output digital data of M bits. For example, the lower digit N bits that are truncated are 3
In the case of bits, the lower digit N bits are “000B”,
"001B", "010B", "011B", "100"
There are eight types of digital data of "B", "101B", "110B" and "111B", and each digital data is a decimal number "0", "1", "2", "3",
It means the value of "4", "5", "6", "7".

Therefore, the digital data creating means has the content (value) of the upper digit n bits (n≤N) of the lower digit N bits of the input digital data on the time slot formed by dividing the sampling period T into m. "1" with a probability according to
To occur. For example, the lower digit N is 3 bits, m is 8, n
Is set to 3, and the rounded down lower 3 bits are "011".
B ”, which means the value“ 3 ”in decimal,
Since it shows a probability of three-eighth, "01001001" having data "1" on the first, fourth, and seventh time slots of the sampling period T / 8 divided into eight.
Generate digital data such as "B", and lower digit 3
When the bit is “110B” and means a value of “6” in decimal, it indicates a probability of 6/8, and therefore the first to third, fifth to seventh of the sampling cycle T / 8. “01110” having data “1” on the 6th time slot
111B ”and digital data is generated.

The lower digit N is 3 bits, m is 16, n
Is set to 3, and the rounded down lower 3 bits are "011".
B ”, which means the value“ 3 ”in decimal,
As in the case described above, the probability is three-eighth, so that the first, fourth, seventh, ninth, twelfth, and fifteenth time slots of the 16-divided sampling period T / 16. “01001001010 with data“ 1 ”above
When digital data such as "01001B" is generated, and the lower 3 bits are "110B", which means a value of "6" in decimal, the same as in the above case,
Since it has a probability of 6/6, the first to third, fifth to seventh, ninth to eleventh, and thirteenth to first of the sampling cycle T / 16 are shown.
Generate digital data such as "0111011101110111B" having data "1" on the fifth 12 time slots.

Further, the lower digit N is 3 bits, m is 4, n
Is set to 2 and the lower 3 bits of the truncated digits are "011".
B ”, the upper digit n is“ 01B ”, and when it means the value of“ 1 ”in decimal, it indicates a quarter probability, and therefore the sampling period T / 4 is divided into four. Generate digital data such as "0100B" having the data "1" on the third one time slot of the above, and the lower 3 bits are "110B", and the upper digit n is "11B". , Which means a value of “3” in decimal, indicates a probability of three quarters, and therefore data “1” is present on the first to third time slots of the sampling period T / 4. Generate digital data such as "0111B".

The adding means adds the data "1" from the data creating means to the upper digit M bits of the input digital data, and outputs the added result as output digital data of M bit structure. That is, the adding means successively adds the data "1" from the data creating means, which is output one after another at the sampling cycle T / m, to the upper digit M bits of the input digital data at the time corresponding to the time slot, The digital data having a new M bit structure is output.

For example, the lower digit N is 3 bits, m is 8, n
Is set to 3, and the digital data of N-bit configuration is “011
In the case of "B", the adding means sequentially adds the digital data "01001001B" as described above to the output digital data of M bit structure. That is, among the output digital data of M-bit configuration output from the adding means at the sampling cycle T / 8, the least significant bit of the output digital data corresponding to the first, fourth and seventh time slots is " 1 ”is added, and nothing is added to the other digital data. When the N-bit digital data is "110B", the adding means sequentially adds the digital data "01110111B" as described above to the M-bit digital data. That is, among the output digital data of M bit configuration output from the adding means in the sampling cycle T / 8, the least significant digit bit of the digital data corresponding to the first to third and fifth to seventh time slots is set. Is added with "1", and nothing is added to the other digital data. The same applies to the case where the lower digit N is 3 bits, m is 16 and n is 3, and the lower digit N is 3 bits, m is 4 and n is 2.

As described above, according to the present invention, when the L-bit input digital data input at the predetermined sampling period T is converted into the M-bit output digital data, the M-bit output (M = L) is converted. -N) output digital data is output at m-divided sampling periods T / m, and the upper digit n bits (n bits n) of the lower digit N bits of the input digital data are output on the time slot of the sampling period T / m at that time. Data “1” with probability according to the value of ≦ N)
Is added to the upper digit M bits of the digital data and then output, the contents of the N-bit digital data that are truncated when the number of bits is converted are output at the sampling cycle T / m. Can be reflected as a dynamic change.

[0013]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram showing a hardware configuration of an electronic musical instrument when the musical tone waveform data processing means adopting the bit number converting apparatus according to the present invention is used between a sound source and a digital-analog converter (DAC). ..

In this embodiment, the control of the entire electronic musical instrument includes a microprocessor unit (MPU) 20, a program memory (ROM) 21 for storing a system program and various parameters, and various data temporarily stored. And a working memory (RAM) 22 used as a working area. To the microcomputer system, various devices such as a key switch circuit 24, a key touch detection circuit 25, a tone color selection switch circuit 26, and a sound source 27 are connected via a data and address bus 28. Is controlled by a microcomputer.

The keyboard 23 is provided with a plurality of keys for selecting the pitch of a musical tone to be generated, and a key switch circuit 24 and a key touch detection circuit 25 are connected to each key. The key switch circuit 24 is composed of a plurality of key switches provided corresponding to each key of the keyboard 23, detects a key press or key release state of the keyboard 23, and responds to a change from a key release state to a key press state. To output the key-on event signal,
The key-off event signal is output in response to the change from the key-depressed state to the key-released state, and the key code signal indicating the key corresponding to each key event is output. This key switch circuit 2
Based on each output of 4, the microcomputer system performs a pressed key detection process and a phonetic sound allocation process for allocating a pressed key to any of a plurality of sound generation channels, and determines the key operation speed at the time of pressing down as necessary. Processing for generating initial touch data is also performed.

The key touch detection circuit 25 has a built-in after-touch sensor which detects a pressing force when the key is continuously pressed and outputs after-touch data in association with each key on the keyboard 23. The timbre selection switch circuit 26
It is provided on the operation panel including various controls for selecting, setting, and controlling pitch, effect, etc., tones and other various sounds corresponding to various natural musical instruments such as piano, organ, violin, brass instrument, guitar, etc. Is selected, and a tone color selection signal is output.

The sound source 27 comprises a musical tone waveform generating means 29 and a musical tone waveform data processing means 30. The tone waveform generating means 29 is capable of simultaneously generating tone waveform data in a plurality of channels, and is provided with a key code, a key-on signal, a key-off signal of a key assigned to each channel via the data and address bus 28. The initial touch data, the after touch data, the tone color selection signal and other data are input, and 21-bit musical tone waveform data is output based on these various data. The musical tone waveform data processing unit 30 converts the 21-bit musical tone waveform data into 18-bit musical tone waveform data, and outputs it to an external digital-analog converter (DAC) 31.

Digital-to-analog converter (DAC) 31
Converts the 18-bit musical tone waveform data output from the musical tone waveform data processing means 30 of the sound source 27 into an analog musical tone signal, and outputs the analog musical tone signal to the sound system 33 via the low pass filter (LPF) 32. The sound system 33 is composed of a speaker, an amplifier, and the like, and produces a musical sound corresponding to an analog musical sound signal input via the low-pass filter 32.

FIG. 1 shows the musical tone waveform data processing means 30 of FIG.
It is a figure which shows the detailed structure of. FIG. 3 is a timing chart for explaining the operation of the tone waveform data processing means 30. The musical tone waveform data processing means 30 is a selector circuit 1.
1, a register 12, a ROM 13, a selector circuit 14 and a half adder 15. In the selector circuit 11 and the register 12, the tone waveform generating means 29 has a cycle T = 1 / fs
The 21-bit waveform data Din to be output one after another at the timing is input, and the waveform data is subjected to oversampling processing at a frequency of 2 ^N times (2 ^N ) times the output frequency of the musical tone waveform generating means 29, one after another. Output. That is,
The cycle of the selector circuit 14 and the register 12 is T / 2 ^N = 1
The waveform data RO is output one after another at / 2 ^N fs. Here, N is the difference N = (L−M) between the number of bits L of the waveform data output by the tone waveform generating means 29 and the number of bits M of the waveform data output by the tone waveform processing means 30. In the example, L = 21 and M = 18, so N = 3. Therefore, the register 12 is provided with the musical tone waveform generating means 29.
The waveform data having a 21-bit structure is subjected to oversampling processing at a speed eight times as fast as that of the operation clock of FIG.

The selector circuit 11 inputs the waveform data RO having a 21-bit structure output from the register 12 to the input terminal A.
Then, the 21-bit waveform data Din from the tone waveform generating means 29 is input to the input terminal B. And
In the selector circuit 11, the selection signal SB has a high level “1”.
, The waveform data Din of the input terminal B is registered in the register 12
, And conversely, when the selection signal SB is low level "0", the waveform data RO of the input terminal A is output to the register 12. That is, the selector circuit 11 circulates the waveform data stored in the register 12 one after another when the selection signal SB is at the low level "0", and registers when the selection signal SB becomes the high level "1". It works to rewrite 12 contents.

The register 12 temporarily stores the waveform data Din or RO selected by the selector circuit 11 in synchronization with the rise of the clock signal φ8 input to the clock terminal CLK, and also stores the stored waveform data DAT.
A0 is output one after another. The register 12 outputs the stored 21-bit waveform data RO to the input terminal A of the selector circuit 11 as it is, and the most significant digit 18 bits (MSB18) of the 21-bit waveform data RO.
To the half adder 15 and the remaining 3 least significant bits (LSB3) are the address terminals A0, A1,
Output to A2. The cycle of the clock signal φ8 is ⅛ of the operation cycle of the tone waveform generating means 29, that is, T / 8 = 1 /
8 fs. That is, in terms of frequency, it operates at a frequency eight times that of the tone waveform generating means 29. Therefore, when the selection signal SB is low level "0", the register 12 outputs the waveform data DATA0 having the same contents eight times during the period T.

The ROM 13 and the selector circuit 14 constitute a data generating means, which inputs the least significant 3 bits (MSB3) of the 21-bit waveform data and corresponds to the numerical value designated by the 3-bit waveform data. Only the number is "1"
The 8-bit digital data D0 to D7 having the following are synchronized with the oversampling process of the register 12 and output to the half adder 15 as serial digital data.

FIG. 4 is a diagram showing an example of data stored in the ROM 13. ROM 13 has address terminal A
0, A1, A2 with the least significant digit 3 bits (LSB
The 8-bit digital data having K "1s", which is the number corresponding to the numerical value designated by 3), is stored. And
In this 8-bit digital data, "1" is distributed and stored so that the spurious moves to a high frequency band. For example, in the ROM 13, the least significant 3 bits (LSB3) is 2
When the decimal display is "000B", the high level "1" is 0 and 8-bit digital data "00000000B"
When "001B", digital data "00001000B" having one high level "1" is changed to "010".
In the case of "B", digital data "10001000B" having two high levels "1", and in the case of "011B", digital data "100 having three high levels" 1 "
10010B ", digital data" 10101010 "having four high levels" 1 "when" 100B "
"B", "101B", digital data "10110110B" having five high level "1" is "1".
In the case of "10B", digital data "11101110B" having 6 high levels "1", and in the case of "111B" digital data "1" having 7 high levels "1"
1101111B ”to each data output terminal DO0
To DO7 to data input terminal DI0 of the selector circuit 14
~ Output to DI7.

The selector circuit 14 has a pulse input terminal C.
The digital data D0 to D7 input in parallel to the data input terminals DI0 to DI7 in accordance with the pulse signals PS0, PS1 and PS2 (see FIG. 3) input to 0, C1 and C2, respectively, are serial digital data. And is output from the serial output terminal SO to the addition terminal NI of the half adder 15. That is, the serial output terminal SO
From the digital data D0 to D7 in the ROM 13 one after another in the order of DO, D1, D2, ..., D7.

The half adder 15 is the most significant digit 18 of the 21-bit waveform data RO output from the register 12.
The bit (MSB18) is input to the addition terminal MI, the serial digital data D0 to D7 from the selector circuit 14 is input to the addition terminal NI, the both are added, and waveform data Dout having a new 18-bit configuration is output to the DAC 31. ..

4 and 5 show the musical tone waveform data processing means 3.
It is a figure which shows an example of the waveform data processed by 0. First, as the waveform data Din, waveform data DATA0 to DATA7 having a 21-bit configuration as shown in FIGS.
Are taken in order. Waveform data DATA
0 is "000000H", DATA1 is "000001"
"H", DATA2 is "000002H", DATA3 is "000003H", DATA4 is "000004".
"H", DATA5 is "00000005H", DATA6 is "000006H", DATA7 is "000007H"
The absolute value gradually increases like.

When the selection signal SB0 is taken in by the selector circuit 11, the register 12 at that time the waveform data DA.
Store TA0. The register 12 synchronizes with the rising edge of the clock signal φ8 and stores the stored waveform data DATA.
0 is the output data MSB1 of the register 12 of FIGS.
8 and LSB3 one after another half adder 15 and R
Output to OM13. At this time, since the selection signal SB0 is low level "0", the register 12 has the same waveform data D
ATA0 is output eight times during the period T. Similarly, the selector circuit 11 and the register 12 output the selection signal SB.
1 to SB7 corresponding to waveform data DATA1 to DA
TA7 is output data MS of the register 12 of FIG. 5 and FIG.
8 each during period T, like B18 and LSB3
Output repeatedly.

Since the output data LSB3 from the register 12 is taken into the address terminals A0, A1 and A2 of the ROM 13, the ROM 13 outputs 8 bits corresponding to the output data LSB3.
The bit-structured digital data D0 to D7 are output from the data output terminals DO0 to DO7 to the data input terminals DI0 to DI7 of the selector circuit 14. The selector circuit 14 synchronizes the digital data D0 to D7 input to the data input terminals DI0 to DI7 with the waveform data DATA0 to DATA7 output from the register 12 and outputs the serial output terminal S.
Output from O in order.

Then, the half adder 15 sequentially adds the digital data D0 to D7 from the selector circuit 14 to the waveform data DATA0 to DATA7 to newly add 18
The waveform data Dout having a bit configuration is output. That is, the half adder 15 receives the waveform data DATA0 to D0 when the digital data D0 to D7 is at the high level "1".
The waveform data to which “1” is added is output to ATA7, and when the digital data D0 to D7 is low level “0”, the waveform data DATA0 to DATA7 from the register 12 is output.
Is output as is.

Therefore, in the case of the waveform data DATA0,
The digital data D0 output from the ROM 13 is “00
Since it is "000000B", it is "00" from the half adder 15.
The waveform data Dout of "000H" is output eight times. In the case of the waveform data DATA1, since the digital data D1 is "00010000B", the waveform data Dout of "00000H" is output from the half adder 15 four times, after that the waveform data Dout of "00001H" is output once, and again " Waveform data Do of "00000H"
ut is output three times.

In the case of the waveform data DATA2, since the digital data D2 is "00010001B", the waveform data Dout of "00001H" is output from the half adder 15.
Is output once, and then “00000H” waveform data D
out is output three times, waveform data D of "00001H" is output once, and waveform data D of "00000H" is output again.
out is output three times. Waveform data DATA3 to DA
Similarly, in the case of TA7, if the digital data D0 to D7 from the half adder 15 is at high level "1", "0" is output.
When the waveform data Dout of "0001H" is output and the digital data D0 to D7 is at the low level "0", "0" is output.
The waveform data Dout of "0000H" is output.

When the waveform data Dout newly created in this way is input to the DAC 31, the DAC 31 outputs the analog waveform DAO as shown in FIGS. 5 and 6. When this analog waveform DAO passes through the low-pass filter 32, an output value corresponding to the contents of the truncated 3-bit digital data LSB3 appears as a temporal change in the analog waveform.

In the above embodiment, the case of converting 21-bit digital data into 18-bit digital data has been described. However, the present invention is not limited to this, and digital data having a plurality of bits is used. The present invention can be applied to any conversion between bit numbers as long as the data is converted into digital data having a smaller number of bits. In the above-described embodiment, the lower digit N and the upper digit n are both 3 bits, and the number of divisions m of the sampling period is m.
Has been described by taking the case of 2 to the Nth power of 8 as an example, but the present invention is not limited to this, and the upper digit n may be smaller than the lower digit N, and the number of divisions m may be smaller than the 2nd Nth power. It may be large or small.

In the above embodiment, the selector circuit and the register constitute the oversampling means, but it goes without saying that other devices may be used. Similarly, although the ROM and the selector constitute the data generating means, it goes without saying that a device other than this may be used. For example, the data "1" may be created by a logic circuit that inputs n bits of the upper digit of N bits of the lower digit and performs a predetermined logical operation.

Further, in the above embodiment, the register 12
Although the content of is circulated, the waveform data may be continuously output to the half adder for one cycle. Also in this case, the digital data D0 to D output from the selector 14 one after another
7, the content of the new waveform data Dout changes with time as in FIGS. 5 and 6.

[0036]

According to the present invention, even when digital data having a plurality of bits is converted into digital data having a smaller number of bits than that, the contents of the digital data truncated at the time of conversion are converted to the converted digital data. Can be reflected in.

[Brief description of drawings]

FIG. 1 is a diagram showing a detailed configuration of a musical tone waveform data processing unit in FIG.

FIG. 2 is a block diagram showing a hardware configuration of an electronic musical instrument when the musical tone waveform data processing means adopting the bit number converting device according to the present invention is used between a sound source and a digital-analog converter (DAC). is there.

FIG. 3 is a timing chart for explaining the operation of the tone waveform data processing means.

FIG. 4 is a diagram showing contents of data stored in a ROM of FIG.

5 is a diagram showing an example of waveform data processed by the musical tone waveform data processing means of FIG.

6 is a diagram showing another example of the waveform data processed by the musical tone waveform data processing means of FIG.

[Explanation of symbols]

11 ... Selector circuit, 12 ... Register, 13 ... ROM,
14 ... Selector circuit, 15 ... Half adder, 20 ... Microprocessor unit, 21 ... Program memory (R
OM), 22 ... Working memory (RAM), 23 ... Keyboard, 24 ... Key switch circuit, 25 ... Key touch detection circuit,
26 ... Tone color selection switch circuit, 27 ... Sound source, 28 ... Data and address bus, 29 ... Musical tone waveform generating means, 30
... tone wave data processing means, 31 ... digital-analog converter, 32 ... low-pass filter, 33 ... sound system

Claims (1)

[Claims] 1. Input digital data of L-bit structure input at a predetermined sampling cycle T is converted into M-bit structure (M
= L-N) output digital data and outputting the converted digital data, the upper digit n of the lower digit N bits of the lower digit N of the input digital data is placed on a time slot formed by dividing the sampling period T by m. Data creating means for generating data "1" with a probability corresponding to the value of the bit (n≤N), and data "1" from this data creating means is added to the upper digit M bits of the input digital data and added. And a summing means for outputting the obtained result as output digital data of M-bit configuration.