JP2798913B2 - Musical tone waveform generating apparatus and musical tone waveform generating method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a musical tone waveform generating apparatus and a musical tone waveform generating method.

[0002]

SUMMARY OF THE INVENTION According to the present invention, by reading out waveform data having different numbers of bits and adjusting the data length, the number of bits of the stored waveform data is increased for sounds in which quantization noise is conspicuous, and the number of bits is reduced for sounds which are not so. Things.

[0003]

2. Description of the Related Art Conventionally, polyphonic musical instruments capable of simultaneously generating a plurality of musical tones have been widely implemented. In such musical instruments, a plurality of musical tone generating channels are formed by time division processing, and each channel is simultaneously operated. The musical tone corresponding to the key being assigned was assigned. The reading of the waveform data from the waveform memory for the plurality of simultaneously generated musical tones is as follows.
A shift register having the same number of stages as the number of channels is provided in a frequency number accumulator serving as a read address counter,
The frequency number accumulation value corresponding to the channel corresponding to each stage is set, and the frequency number is accumulated for each channel timing.

In this case, the number of bits of the read waveform data is the same for all the waveform data.

[0005]

However, tone waveforms include a lively sound in which quantization noise does not become a problem even if the number of quantization bits is reduced, and a sound in which quantization noise is conspicuous.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. Even if the number of quantization bits is reduced, the number of storage bits is reduced for a lively sound in which quantization noise is not so problematic. The goal is to reduce memory usage.

[0007]

In order to achieve the above object, the present invention has a configuration in which waveform data having different numbers of bits are stored, read out, and the data length is adjusted.

[0008] As a result, the number of memory bits can be reduced for a lively sound in which quantization noise does not cause a significant problem even if the number of quantization bits is reduced. , The number of storage bits can be increased.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

<Overall Circuit> FIG. 1 shows an overall circuit diagram of the present invention. Each key of a keyboard 1 and each switch of a tone switch 2 are scanned by a key assigner circuit 30 and have a pitch corresponding to an operation key. A tone of a tone corresponding to the operation tone switch is assigned to an empty channel of the 16 tone generating system. The contents of the channel assignment are stored in the assignment memory circuit 32. The key press pressure of each key of the keyboard 1 is determined by a pressure sensor 3 provided for each key.
Is converted by the A / D converter 4 into touch data TO in a digital format indicating a key press pressure, and is converted by a CPU (described later).
Sent to 300.

Further, the rhythm key 5 is used to select a rhythm such as rock or disco, and the effect key 6 is used to turn on / off each of the keys. , Honky tonk, tremolo, and the like, and the ON / OFF of each key is detected by the CPU 300. In addition, the control amounts of the volume knob 7 and the tempo knob 8 are also detected as voltage fluctuation amounts by the variable resistors, and are supplied to the CPU 300 as volume data and tempo data via the AD converters 9 and 10.

The ROM 20 stores a processing program for generating a tone signal, timbre data relating to a waveform and an envelope, and waveform data RD itself. A read address is controlled by a ROM address control circuit 31. Reading of the program or tone data and reading of the waveform data RD are switched. R
The processing program read from the OM 20 is sent to a CPU 300 (to be described later) of the key assigner circuit 30 to execute various types of processing, and the timbre data related to the waveform and the envelope read from the ROM 20 is also stored in the empty The waveform data RD itself written in an area corresponding to the channel and further read from the ROM 20 is sent to the waveform data decompression interpolation circuit 50. In the assignment memory circuit 32, the frequency number speed data F corresponding to the operation key of the keyboard 1 is stored.
S is also written in the area corresponding to the empty channel.

The frequency number speed data FS is
The frequency number accumulator 40 sequentially accumulates the data for each channel, and stores the data in the ROM 20 through the ROM address control circuit 31.
Is provided as read address data, and waveform data RD
Is read out at a speed corresponding to the frequency number speed data FS, that is, at a speed corresponding to the pitch, and is input to the waveform data expansion interpolation circuit 50. Read waveform data RD
Are stored in the ROM 20, and these selections are made by bank data read from the assignment memory circuit 32. The waveform data decompression interpolation circuit 5
In the case of 0, the differential data read from the ROM 20 in the data compressed state is expanded, and an interpolation point between the sample point points of each waveform data RD is also obtained and sent to the multiplication circuit 70. This interpolation is performed using a part of the frequency number accumulated value FA from the frequency number accumulator 40.

The data on the envelope from the assignment memory circuit 32 is stored in an envelope generator 6.
0 to generate an envelope waveform, which is sent to the multiplying circuit 70. The multiplication circuit 70 multiplies each sample value of the expanded interpolation waveform data IP by each sample value EA of the envelope waveform, shifts the data by the shift circuit 80, and accumulates the data for each sequence by the sequence accumulation circuit 90. And the sound system 11 via the DA converter 100.
Sound is output from 0.

From the envelope generator 60, the current phase value PH of the envelope waveform is sent to the assignment memory circuit 32, and acts to output envelope data for the next new phase. Further, the frequency number accumulator 40 is output from the envelope generator 60.
, An on-event signal is sent at the key-on timing, and accumulation of the frequency number speed data FS is started. Further, a data length signal D816 is sent from the envelope generator 60 to the waveform data decompression interpolation circuit 50, and selection is made whether interpolation of the waveform data RD is performed or not. The data length signal D816 indicates whether the waveform data RD consists of two 8-bit sample values or 10-bit sample values and 6-bit difference data. Is read out, interpolation of the waveform data RD is performed.

The shift circuit 80 shifts down the multiplied musical tone data in accordance with the magnitude of the envelope power data EA12 to 15 which are the upper bits of the envelope accumulated value EA, and falls when the decay and release are attenuated. This is to make the sound more exponential and closer to natural sound.

In the DA converter 100, four tone generation systems are formed in a time-division manner. In the sequence accumulating circuit 90, any one of the tone accumulating circuits 90 is provided in accordance with the sequence data GR from the assignment memory circuit 32. Is determined whether or not the musical sound data is to be sent to the generation system. This series accumulator circuit 90 includes:
The waveform folded signal FDU is also given from the frequency number accumulator 40, and the waveform folded signal FDU has generated the first half of one waveform of the waveform data and has entered the second half of the waveform. At this time, the tone accumulation data is set to a high level, so that the sequence accumulation circuit 90 takes a value obtained by inverting the tone data by plus or minus. In addition, the series accumulation circuit 90 includes:
The DA gate signal is also given from the key assigner circuit 30, and the tone data output control to the DA converter 100 is performed.

From the system clock generator 10, the respective circuits 30, 40, 50, 60, and 90 shown in FIGS. 1 and 2 are provided with a clock signal as shown in FIG. , AND, etc. are given,
Timing control of each circuit is performed.

<ROM 20> FIG. 4 shows the contents stored in the ROM 20. The ROM 20 stores "0" to "15".
Is divided into 16 bank areas, and each bank area is "0000 н (н is a symbol indicating that it is a hexadecimal value)"
To “FFFFн”, and “0000н” to “0FFFн” of the bank “0” are RA addresses of the CPU 300.
M301, an area used by the assignment memory 320, etc., where "1000" to "1FFF"
This is the area where the U latch 310 is used.
“FFFFн” stores a processing program for generating a tone signal. "0000" of bank "1"
н ”to“ 3FFF н ”store 128 tone colors for selecting and determining the contents of the waveform and the envelope.

From "4000" in bank "1" to "FFFF" in bank "15", one selected tone is read out for each bank. (A) (B) Two waveform data RD have the same address. Is stored in This waveform data RD includes a sine wave, a triangular wave, a sawtooth wave, a rectangular wave,
In addition to noise sound waveforms and the like and waveforms obtained by synthesizing them, a plurality of types of waveforms obtained by synthesizing frequency components corresponding to spectrum groups of a plurality of specific frequency bands corresponding to specific formants may be used. A PCM waveform using a loop end or the like may be used. The storage area of the timbre data is shifted from the storage area of the processing program by the MMU address data described later.
The tone data is bank data, data length signal data D8
16. Sequence data GR, initial frequency number data, loop top data, loop end data, and envelope data. The envelope data further includes phase level data PL, envelope addition / subtraction signal data EDU, thin out data TH, and envelope speed data ES. Has become.

The bank data is composed of 15 types of waveform data R
D for selecting and specifying one of D. For each tone assigned to one channel, (A)
(B) Two waveforms are selected and the data length signal D816
Indicates whether the waveform data RD is composed of two 8-bit sample values or 10-bit sample value and 6-bit difference data, as described above. The series data GR0, 1 are also described above. Thus, the tone data ST after the multiplication is assigned to any of the four tone generation systems.

The initial frequency number data, as shown in FIG. 9, indicates the frequency number accumulated value at the start time when the frequency number speed data FS is sequentially accumulated and the waveform data RD is read out. Indicates the frequency number accumulated value FA at the point where the accumulation of the frequency number speed data FS is turned from the addition direction to the subtraction direction. The loop top data indicates that the accumulation direction of the frequency number speed data FS is changed from the subtraction direction to the addition direction. A frequency number accumulated value FA at a turning point is shown. As shown in FIG. 9, the frequency number accumulated value FA is loop-changed between a loop top and a loop end, so that waveform data for a half waveform is continuous. Can be read in the state of.

The waveform return signal FDU in FIG. 9 is the most significant bit data of the frequency number accumulated value FA, and the generation of the first half of one wavelength of the waveform data is completed.
The signal is at a high level when the second half wavelength is generated. Based on the signal FDU, the frequency number accumulation value FA is switched between addition and subtraction, and the waveform data (musical sound data) sample value (amplitude value) is switched. Is switched between plus and minus.

As shown in FIG. 25, the envelope level data EL in the envelope data indicates the accumulated value of the envelope at the last point of the ack, decay, sustain, and release of the envelope waveform. It indicates whether the calculated value EA is to be added or subtracted. Envelope speed data E of the envelope data
S is data indicating the acceleration / deceleration of the envelope accumulated value EA. The larger this value is, the larger the slope of the envelope waveform becomes. The envelope speed data ES and the envelope level data EL are determined according to a key pressing speed of a key of the keyboard 1 or key touch data corresponding to a key pressing pressure.

Thin out data TH in the envelope
Is the data indicating the thinning rate of the latch for taking in the envelope accumulated value EA into the accumulation system of the envelope accumulated value EA. Once in a slot. When this data is "11", there is no thinning out, and when it is "10", it is taken once every four times,
When it is "01", it is taken once every 16 times, and when it is "00", it is taken once every 64 times. 0 and 1 are binary logic level l
It indicates an ow state and a high state. With this thin out (take-in latch thinning), the same envelope speed data can be used to double the envelope speed,
It can be changed four times, 16 times, and 64 times. This thin-out data TH may also be changed in accordance with the key pressing speed of a key of the keyboard 1 or key touch data corresponding to the key pressing pressure.

As described above, since the ROM 20 stores the processing program for generating and emitting a musical tone and the musical tone data representing the content of the musical tone, only one memory for storing the program and the data is required. The circuit configuration can be simplified accordingly.

<Key Assigner Circuit 30> FIG. 5 shows the key assigner circuit 30, in which the CPU 300 can operate only when the applied master clock signal φ (CK2) is at a high level, as shown in the lower part of FIG. And CP
When the master clock signal CK2 is at the high level “1”, data relating to the CPU 300 flows through the data bus line and the address bus line of the U300, and when the master clock signal CK2 is at the low level “0”, data unrelated to the CPU 300 flows.

<< ROM address control circuit 31 >> This CP
The address data CA0 to CA15 for accessing the ROM 20 and various memories from the U300 are 16-bit data, but the lower 11 bits CA1 to 11 excluding the least significant bit are given to the selector 313. Also, the upper 4 bits CA
12 to 15 have 4-bit data of “0000” added to the upper bits, and the lower 1 bits are input through the B input of the selector 312.
The data is supplied to the ROM 20 via the selector 313 as 19-bit address data together with the 1-bit CA1 to CA11, and the processing program is mainly read. Also C
When the PU 300 reads out tone data and other data other than the processing program, 8-bit MMU address data is output from the CPU 300 through the data bus line, and this is transmitted through the MMU latch 310 through the selector 312 and through the lower 11 bits CA1 to CA1. 11 and supplied to the ROM 20 via the selector 313.

FIG. 6 shows the switching state of the address data.
Although the address data is 9 bits, the address data of the CPU 300 is 16 bits, so that "0000" and MMU address data are added.

In this way, the MMU address is added or
By adding “0000”, it is possible to easily switch between the reading of the program and the reading of the timbre data.
Even when the read address data of 300 is smaller in the number of bits than the read address data of ROM 20, the entire area of ROM 20 can be read.

Therefore, the bank "0" of the ROM 20 is connected to the CP
Since the U300 can be directly accessed without using the MMU latch 310, a processing program dedicated to the CPU 300 is stored. Further, the CPU 300 accesses, for example, the address “3524 н” of the bank “1” by M
"13" is set in the MU latch 310, and the CPU 30
If "1524H" is set as the address data of 0, the combined address data becomes "13524H", and the address "3524H" of the bank "1" is accessed. In this case, the selector 312 cancels the most significant four bits “1н” of the address data “1524н” of the CPU 300.

The upper 4-bit data CA12 to CA15 are also supplied to a comparator 311. The comparator 311 is also supplied with 4-bit f (x) data. When the two data do not match, "0000" is output. And the top four
Bit address data CA12 to CA15 are selected. When both data match, a match signal is supplied from the comparator 311 to the selector 312, and the MMU
Latch 310 is selected. Therefore, when the upper four bits of the address data CA12 to CA15 do not match the f (x) data, the processing program of the CPU 300 is read, and when they match, the tone color data and the like are read. The f (x) data may be selected and set by the CPU 300 or may be a fixed value in advance. This f
When (x) is fixed to “1 н”, the area for the MMU latch 310 of “1000 н” to “1FFFF” of the bank “0” of the RAM 20 is accessed, and f (x) is set to “0”.
н ”,“ 00 ”of bank“ 0 ”in RAM 20
The areas from "00 н" to "0FFF н" will be accessed.

The selector 313 is also supplied with bank data read by the CPU 300 from an assignment memory 320, which will be described later, and the frequency number accumulated values FA12 to FA from the frequency number accumulator 40. The waveform data RD of the corresponding bank is read out. Data select switching in the selector 313 is performed by a clock signal CK2 from the system clock generator 10,
As shown in the lower part of FIG. 3, reading of the processing program and reading of the sample value of the waveform data RD are switched. At this time, at the timing of reading the processing program, the reading of the processing program and the reading of the tone color data are switched based on the f (x) data. These reading processes are repeatedly performed for 16 channels.

Of the data read from the ROM 20, the waveform data RD is sent to the waveform data decompression interpolation circuit 50 as it is, and the processing program and timbre data are divided into two pieces of 8-bit data each.
It is sent to the PU 300 or sent to the assignment memory 320 via the gate buffer 323. The data select switching in the selector 314 is performed by the CPU
Least significant bit CA0 of address data CA from 300
It is performed based on.

Thus, data is taken in from the ROM 20 following the processing speed of the CPU 300. Further, even if the number of bits of data read from the ROM 20 is larger than the number of bits of the data bus line of the CPU 300, data processing can be performed smoothly.

<< Assignment Memory Circuit 32 >> FIG.
Assignment memory 32 of assignment memory circuit 32
0 indicates the storage content of the assignment memory 320
Has a memory area for timbre data for 16 channels, and timbre data from the ROM 20 is set in each channel area. In this case, of the tone data to be set, the envelope data is set in each of the envelope group areas EG0 to EG15, and the other data is set separately in the respective channel areas of CH0 to CH15. The data set in CH0 to CH15 include bank data (A) (B), envelope group data (A) (B), frequency number speed data FS, key-on signal data, data length signal data D816, sequence data GR, and initials. It consists of frequency number data, loop top data, and loop end data. Of these, data other than the frequency number speed data FS, key-on signal data, and envelope group data (A) and (B) are described in the storage contents of the ROM 20. As you did.

The frequency number speed data FS is data corresponding to the pitch of the operation key of the keyboard 1 and is used as an accumulation step value of the read address data of the waveform data RD. The key-on signal data is data indicating that the key is currently on, and is "1" for key-on and "0" for key-off. Envelope group data (A)
(B) is data indicating the addresses of the envelope group areas EG0 to EG15 in which the envelope data corresponding to the tone of the channel area is stored. The tone assigned to one channel is composed of two tones. Therefore, there are two (A) and (B). Accordingly, since there are two waveform data RDs, there are two bank data (A) and (B). The envelope data set in EG0 to EG15 is also as described in the description of the storage contents of the ROM 20 described above.

The frequency number speed data FS is
(A) and (B) are shared for two musical tones, and two musical tones (A) and (B) are synthesized and output according to one operation key of the keyboard 1. These two tones (A) and (B) have different tone colors because the bank data or the envelope group data are different, and the envelope control is also performed separately. The selection of the bank data and the envelope group data can be arbitrarily switched by selecting the switches of the tone switch 2 described above. However, the size of the touch data TO from the pressure sensor 3, the volume knob 7, the tempo Switching can also be performed by changing the volume data and tempo data from the knob 8 and by selecting the rhythm key 5 and the effect key 6. In this case, the timbre may be changed by switching the initial frequency number data, the loop top data, and the loop end data in addition to the bank data and the envelope group data. In addition, the number of musical tones synthesized and output by one operation key is not limited to two (A) and (B), and may be more than two.

The data read from the assignment memory 320 is sent to the frequency number accumulator 40 and the envelope generator 60 via an AM (assignment memory) bus, or sent to the CPU via a gate buffer 322.
300. Also, the 4-bit envelope group data (A) and (B) are transmitted via the latch 324 to the phase data PA from the envelope generator 60.
Is added to the lower 2 bits, and “1” is added to the upper 1 bit to make a total of 7 bits, which are again provided to the assignment memory 320 via the selector 321 and the envelope level data EL and the thin-out data of the corresponding envelope are given. TH, envelope speed data ES, and the like are read and sent to the envelope generator 60. Read address data, which is a set of clock signals CK from the system clock generator 10, is also supplied to the assignment memory 320 via the selector 321, and the CPU 30
Access address data from 0 is also provided.

FIG. 3 is a time chart showing the switching state of these address data. The bank data (A) and (B) and the envelope group data (A) and (B) based on the clock signal group CK are shown. After that, after reading the frequency number speed data FS, reading of the envelope speed data (A) ES and the envelope level data (A) EL based on the envelope group data (A) and the phase data PA is performed.
Thereafter, access of the CPU 300 is performed. Similarly, the initial frequency number, key-on, data length signal data D816, and sequence data GR based on the clock signal group CK are read, followed by the loop top data and the loop end data. Reading of the envelope speed data (B) ES and the envelope level data (B) EL based on (B) and the phase data PA is performed, and thereafter the CPU 300 accesses. These access processes are repeated for 16 channels.

In this case, as the clock signal group CK used as read address data, CK1 to CK in FIG. 3 are used. The selection of each address data in the selector 321 is performed based on the clock signals CK1 and CK2 from the system clock generator 10, and "00""0"
1 ”, the clock signal group CK is selected,
“10” selects the envelope group data and phase data PA from the latch 324, and “11” selects CP.
The address data from U300 is selected.

A RAM 301 stores various intermediate processing data, a timer 302 gives an interrupt signal to the CPU 300 at a cycle set by the CPU 300, and a reset circuit 303 resets the CPU 300 and the output latch 304 when the power is turned on. It is. The sampling addresses of the timbre switch 2 and the keyboard 1 are temporarily set in the output latches 304 and 306, and the sampling results are input to the input buffers 305 and 307. Only one bit of the sampling data of the output latch 304 is used as a gate signal of the DA converter 100.

<Frequency Number Accumulator 40> FIG. 8 shows the frequency number accumulator 40, and the frequency number speed data FS from the assignment memory circuit 32 is shown.
Is accumulated by the adder 407 through the exclusive OR gate group 405 via the latch 404 and the accumulated frequency number FA up to that time, and the upper 8 bits FA19 to FA2 are output.
6 is the lower 19 bits FA0 through FA1 through the selector 413.
8 is again supplied to the adder 407 as the above-mentioned frequency number accumulated value FA via the exclusive OR gate group 414, the latch group 415 and the selector 416. As a result, the frequency number accumulated value FA is accumulated at a speed corresponding to the size of the frequency number speed data FS, and the accumulated value FA is transferred via the latch 418 to the 15-bit FAs 12 to 26 corresponding to the upper integer part. The waveform data RD is sent to the ROM address control circuit 31 and read out. The waveform return signal FDU of the upper three bits FA9 to FA11 of the decimal part and the most significant bit is sent to the waveform data decompression interpolation circuit 50, and is used for decompression and interpolation of the sample value of the waveform data RD.

FIG. 10 shows the contents of such a frequency number accumulated value FA. The frequency number accumulated value FA is data of 28 bits in total, and the most significant bit is a waveform folded signal FDU. The next 8-bit FAs 19 to 26 are compare bits, which are used for comparing whether or not a loop end and a loop top described later have been reached.
Bits FA12-18 are integer part, last 12 bits F
A0 to 11 are decimal parts. Such frequency number speed data FS is accumulated by the frequency number accumulator 40 for 16 channels from CH0 to CH15, and the frequency number accumulated value FA of each channel is stored in the latch group 415.
Is stored in the memory. The latch group 415 is composed of 16 latches. The latch for accumulating the frequency number speed data is switched at the timing of the clock signal CK3, and reading from the latch is performed by the clock signal CK.
3, and writing to the latch is performed at the last timing of the latter half of the clock signal CK3. Each of the latches of this latch group 415 has (A) and (B)
The same read address (the same frequency number accumulated value FA12 to FA26) is set for the two tone components. The difference in timbre is based on the difference in the bank data (A) and (B).

The 8-bit initial frequency number from the assignment memory circuit 32 is obtained by adding 1-bit “0” to the high-order and 19-bit “00... 0” to the low-order by the selector 416 via the latch 406. , Is selected as the same 28-bit data as the frequency number accumulated value FA. As the select signal in the selector 416, an on-event signal output at the key-on timing from the envelope generator 60 is used, and as shown in FIG.
From the key-on timing, the frequency number speed data FS is sequentially accumulated for this initial frequency number.

Further, the loop end data and the loop top data from the assignment memory circuit 32 are selected via the latch 402 by the selector 403 to select either the loop end or the loop top data. Is also given. In the comparator 409, the top eight of the frequency number accumulated value FA
When the frequency comparison value FA is compared with the bit comparison bits FA19 to 26, and the frequency number accumulated value FA exceeds the range between the loop end and the loop top, the selector 410 outputs an overrun signal FCP. The signals are supplied to the exclusive OR gate group 414 and the selector 413, and the loop end data or the loop top data is taken in as new data instead of the higher-order compare bits FA19 to 26 of the frequency number accumulated value FA. At this time, in the exclusive OR gate group 414, the values of the integer part and the decimal part of the frequency number accumulated value FA up to that point are inverted plus or minus, but this changes the reading direction of the waveform data RD to the loop end or the loop top. In the inversion, the fraction of the frequency number accumulated value FA is used as it is in a state of plus / minus inversion, so that the inversion readout of the waveform data RD has consistency.

The overrun signal FCP is also applied to an exclusive OR gate 412 to invert the waveform folding signal FDU, which is the most significant bit of the frequency number accumulated value FA, and thereby the exclusive OR gate group 40
The value of the frequency number speed data FS at 5 is inverted plus or minus, and the direction of accumulation of the frequency number accumulated value FA at the adder 407 is switched. FIG. 9 shows a state of loop reproduction for each half waveform by the switching of the frequency number speed data FS.

The waveform folded signal FDU is supplied to the selector 4
03 and 410 are provided as select signals. When frequency number speed data FS is added, loop end data and A <B detection signal are selected, and when subtraction, loop top data and A> B detection signal are selected. . The waveform folding signal FDU is also input to the Cin terminal of the adder 407, and when the frequency number speed data FS is subtracted, +1 processing of the frequency number accumulated value FA is performed.
Also provided to the exclusive OR gate 408. An output signal from the Cout terminal of the adder 407 is also given to the exclusive OR gate 408, and it is detected that the frequency number accumulated value FA has overflowed or underflowed.
Is output as

Further, with respect to the bank data (A) and (B) from the assignment memory circuit 32, one of the bank data (A) and (B) is selected by the selector 401 via the latch 400, and the latch 417 is selected. Is sent to the ROM address control circuit 31 together with the integer part of the frequency number accumulated value FA and the comparator bit, and the waveform data RD is read.

As a result, although the two tone components (A) and (B) assigned to one channel have different bank data, a common frequency number accumulated value FA is used, and the timing synchronization of the tone generation process is performed. Is taken.

The select signal of the selector 401 includes
Clock signal CK3 from system clock generator 10
Is used, the tone generation process for (A) is performed in the first half of the clock signal CK3, and the tone generation process for (B) is performed in the second half. The clock signal group CK from the system clock generator 10 corresponds to the latches 400, 402, 404, 406, 415, 417, 4
18 is also provided as a latch signal to synchronize the channel cycle and timing.

<Waveform Data Expansion Interpolation Circuit 50> FIG.
Indicates a waveform data decompression interpolation circuit 50, in which gates 500 to 510 and selectors 511 to 513 decompress differential data in the waveform data RD as shown in FIG. 518, 519,
With the adder 520 and the selector 521, each sample value R ₀ , R ₁ , R ₂ , R ₃ ... Of the waveform data RD as shown in FIG.
Are interpolated, and the gate groups 524 and 522 and the gate 52
6, the selector 525 and the adder 527 perform interpolation when the waveform data RD is a 10-bit sample value and 6-bit difference data (D816 = 0), and do not interpolate when two 8-bit sample values are used (D816 = 1). Done.

<< Outline of Data Processing of Waveform Data Decompression Interpolation Circuit 50 >> FIG. 14 shows a data structure of waveform data RD read from the ROM 20.
When 816 is a low level and includes a 10-bit sample value and 6-bit differential data, the upper 10 bits RD6
15 is a sample value, RD5 is difference code data, RD
2 to 4 are differential power data, and RD0 and 1 are differential mantissa data. The difference data RD0 to RD4 are stored in a compressed state, and when expanded, become 10-bit expanded difference data IE0 to IE8 and IES as shown in FIG. That is, the difference power data RD2 to RD4 are data indicating the first bit of the difference value that has “1”, and the difference mantisser data RD0, RD1 is “1”.
Indicates the data itself of 2 bits following. As described above, the data in the upper part of FIG. 15 is for adding the decompression difference data, while the data in the lower part is for subtraction. In this case, the difference power data RD2
4 is data indicating to what bit of the difference value “1” continues, and the conversion difference Mantissa data R
G0-2 correspond to difference Mantissa data RD0, RD1 in FIG.
5 is converted by the logical expression below.
As shown in FIG. 6, it is converted to a value that is inverted in the plus and minus directions.

The decompression difference data IE0 to IE8, I
ES is の of the difference between each sample value of the waveform data RD indicated by a large circle in FIG. 13, and indicates the difference between each sample value and a virtual value indicated by a cross. The virtual value in FIG. 13 overlaps with the interpolation value and is in a state where the mark “x” overlaps the mark “x”.

Each sample value R ₀ of the waveform data RD,
R ₁ , R ₂ ... Are obtained by dividing the decimal number of the frequency number accumulated value FA by 1 /.
2 (2) and FIG. 1 (1).
In order to realize a waveform connected by the X mark of 3, it is only necessary to store the sample value of the sample point G ₀ , G ₁ , G ₂ . The sample values of this intermediate point are: R ₀ = (G ₀ + G ₁ ) / 2, R ₁ = (G ₁ + G
₂ ) / 2, R ₂ = (G ₂ + G ₃ ) / 2.

As described above, instead of the sample values indicated by the crosses,
By storing the sample values at the midpoints of the crosses, FIG.
3 and FIG. 12 (2), the frequency number accumulated value F
The waveform data level can be accurately set to "0" at the start point where A is "00 ... 0". That is, ROM2
In the first address of the memory area of the waveform data RD of 0, the waveform data RD which is not the "0" level in the first step is normally stored.
Is stored, but the frequency number accumulated value FA is “0”.
In the case of "0 ... 0", the phase can be automatically adjusted by storing the sample value of the above-mentioned intermediate point even if a process for preventing the reading of the first step is not performed.
The phase shift as shown in FIG. 12 (1) does not occur.

Further, the difference data between the midpoint of the mark x and the interpolation points before and after this midpoint is the same before and after, and as a result, the difference data to be stored is only half the original difference data. . Therefore, when the sample value of the normal waveform data RD is 10 bits, the difference data is 10 bits. Even if the above-mentioned compression method is used, the number of bits of the difference power data is required to be 4 bits. 7
The difference data can be reduced to half as described above, but the difference data can be reduced to 6 bits, and can be accessed once in normal data access as a total of 16 bits.

Therefore, the waveform data RD and the program (or timbre data) are alternately read from one ROM 20, and the readout of the waveform data RD per unit time can be reduced to half. Note that the stored waveform data RD may be a waveform in which the x points are connected in a polygonal line shape.

1/4, 2/4,
If 3/4 and 4/4 are added or subtracted from the sample values as shown in FIG. 17, an interpolated value will be obtained. In this case, if the interpolated value is larger than the sample values R ₀ , R ₁ , R ₂ , R _3, ... In E ₀ , D ₁ , D ₂ , D ₃ ,. The difference data becomes an added value as shown in the upper part of FIG. 15, and when the interpolation value is smaller like D ₀ , E ₁ , E ₂ , E ₃ ..., The expanded difference data is subtracted as shown in the lower part of FIG. Value.

There are two types of data format of the waveform data RD, that is, 10-bit data format and 8-bit data format. A lively sound is 8-bit data in which quantization noise does not cause much problem even if the number of quantization bits is reduced. Sounds in which quantization noise is noticeable are selectively used as 10 bits, and the amount of memory used is reduced.

<< Circuit Configuration of Waveform Data Decompression Interpolation Circuit 50 >> In FIG. 11, the difference Mantissa data RD0 is supplied to the A-side “0” terminal and the B-side “1” terminal of the selector 511.
Is input as it is. When the most significant bit IES of the decompressed difference data is “0”, the difference mantisser data RD1 is directly input to the A-side “1” terminal and the B-side “2” terminal of the selector 511. Is "1", the AND gate 502 is opened.
Exclusive OR data RG1 of the difference mantisser data RD0 and RD1 is input. Furthermore, when the most significant bit IES is "0", the output of the NAND gate 505 becomes "1" and the exclusive OR gate 506 outputs the NOR gate to the "2" terminal on the A side and the "3" terminal on the B side of the selector 511. 509 is inverted, the logical sum of the difference power data RD2 to RD4 is input, and the most significant bit IES
Is “1”, the exclusive OR data RG2 of the inverted data of the OR of the differential mantisser data RD0 and RD1 by the OR gate 504 and the inverted data of the OR of the differential power data RD2 to RD4 is input. Then, the selector 51
The most significant bit IES is input to the A-side “3” terminal of 1, and “0” data is input to the B-side “0” terminal.

As a result, as shown in FIG. 15, data of differential mantissa data RD0, RD1 and upper one bit, or data of converted differential mantissa data RG0, RG1, RG2 is created. . The specific contents of the conversion difference mantisser data RG0 to RG2 are as shown in FIG.

The 4-bit data of the selector 511 is
The selectors 512 and 513 select whether the most significant bit IES is added by 2 bits or 4 bits at the high order, or whether the “0” data is added by 2 bits or 4 bits at the low order. Is output. Each selector 5
11, 512, 513 by appropriately selecting the select state, the difference mantissa data RD0, 1 or RG0
2 can be shifted as shown in FIG. 15, and the selection of the selection state is performed by the difference power data RD2 to RD4.
It is performed based on.

In this manner, the expanded differential data can be expanded to 10 bits, even though the differential compressed data is 6 bits, and the memory usage can be reduced.

The most significant bit IES of the expanded differential data
Are the difference code data RD5 input to the exclusive OR gate 500, the most significant bit FA11 of the decimal part of the frequency number accumulated value FA input to the NOR gate 501, and each bit RD0 to RD4 of the difference data from the NOR gate 508.
And the inverted data of the logical sum of That is, as shown in FIG. 13, when the FA 11 of D ₀ is “0”, the difference code RD 5 is “0” (addition direction), and when E ₁ and E _1
2 ... FA11 is "1" and RD5 is "1" (subtraction direction)
In this case, the most significant bit IES of the decompressed difference data becomes “1”, indicating that the difference data must be subtracted from the sample value. The above NOR gate 501
Each bit RD0, 1, 2, 3, 4, 5 of the differential data
Is input, and the difference data is “0”.
At the time of “0000”, the output of the NOR gate 501 is set to “0”, and control is performed so that the most significant bit IES of the decompressed difference data does not become “1”.

The expanded differential data IE is shifted down by one bit to become a value of と, and is input to one terminal of the adder 520 via the AND gate group 519.
The value is shifted to the lower side by 2 bits to become a value of 1/4, and is input to the other terminal of the adder 520 via the AND gate group 518. The output of the adder 520 is provided to the A side of the selector 521. On the B side of the selector 521, the decompressed difference data IE is not shifted but is given at the same magnification. Accordingly, by appropriately selecting the ratio data IM including the opening signals IM0 and IM1 of the AND gate groups 518 and 519 and the selecting signal IM2 of the selector 521, the expansion difference data IE as shown in FIG.
Can be reduced to 1/4, 2/4, 3/4, 4/4 and 0 times.

The decompression difference data I having such a multiplication factor
E is given to the adder 527 via the AND gate group 522, and the sample values RD6 to RD6 of the waveform data RD to be described later.
15 is added and subtracted, and interpolation of each sample value of the waveform data RD is performed.

Thus, one sample value RD6 to RD15
And the difference data RD0 to RD5, the waveform data R at eight points
D can be created, smooth waveform characteristics can be obtained, and the memory capacity can be reduced. In addition, such waveform data RD that can determine eight points by one data can be read out by one reading, and a sufficiently smooth waveform can be realized even if the reading time of the waveform data RD is small.
Even if the waveform data RD and other programs are read alternately, the waveform generation processing is not hindered. Even if the program and the waveform data RD are stored together in the ROM 20, the reading speed of each information is reduced. There is no need to increase

The multiplying factor data IM0 to IM2 are created by the logic gates 514 to 517 by the higher three bits FA9 to FA11 of the decimal part of the frequency number accumulated value FA. By the gate groups 514 and 517, data conversion as shown in FIG. 17 is performed, and an interpolation value of the waveform data RD is obtained. In this case, when only the most significant bit FA11 of the decimal part of the frequency number accumulated value FA is “1”, that is, when the frequency number accumulated value FA is １ ／, no interpolation is performed on the sample value. As a center, at an earlier timing, the interpolated value is a subtraction value of 1/4, 2/4, 3/4, 4/4 of the difference data,
At a later timing, the interpolated value is 1/4, 2
/ 4, 3/4.

When the waveform data RD0 to RD15 consist of a 10-bit sample value and 6-bit difference data, the sample values RD6 to RD15 are input from the A side of the selector 525 and are given to the adder 527 as they are. Then, the interpolation value is adjusted. At this time, the data length signal D8
16 becomes “0”, so that the AND gate groups 524, 5
22 is opened, the AND gate 526 is closed, and the selector 525 selects the A side. Also, the waveform data RD0
When ~ 15 consists of two 8-bit sample values,
The waveform data RD0 to RD7 are input from the B side of the selector 525, and are provided to the adder 527.
To 15 are input from the A side of the selector 525 and supplied to the adder 527. At this time, each data RD0 to RD7,
Two bits “00” are added to the lower part of 8 to 15 to form 10-bit data. At this time, the data length signal D
Since 816 is “1”, the AND gate groups 524, 5
22 is closed and no interpolation is performed. Further, at this time, since the AND gate 526 is opened, the sample value (2n = RD0 to 7, RN0 to RD7) is set in accordance with the value (1, 0) of the most significant bit FA11 of the decimal part of the frequency number accumulated value FA.
2n + 1 = RD8 to 15) are switched.

<Envelope Generator 60> FIG. 18 shows the envelope generator 60. The envelope speed data ES0 to ES0 from the assignment memory circuit 32 is shown.
5 is subjected to data expansion as shown in FIG. 23 by an envelope speed data expansion circuit 600 via a latch 641 and an adder 6 via an exclusive OR gate group 643.
At 44, the accumulated values EA0 to EA15 are accumulated to the previous accumulated values EA0 to EA15, and are supplied to the adder 644 again as the above-described envelope accumulated values EA0 to EA15 through the selector 649 and the latch group 650. ,
It is output to the multiplication circuit 70 and the shift circuit 80. The latch group 650 includes 32 latches, and a total of 32 envelope accumulated values EA for (A) and (B) two musical tones for 16 tones can be accumulated.

An envelope addition / subtraction signal EDU indicating the accumulation direction of the envelope is applied to the exclusive OR gate group 643. When the accumulation direction is subtraction, the expanded envelope speed data ESE is inverted plus or minus to add or subtract. 644 and the subtraction of the envelope accumulated value EA is performed. The upper 7 bits of the envelope accumulated value EA from the adder 644 are
45, and compared with the envelope level data EL of each phase such as attack, decay, sustain, and release of the envelope shown in FIG. 25. When the envelope accumulated value EA exceeds the envelope level data EL, the selector 646 is set. The phase step signal ECS is supplied to the selector 649 via the NOR gate 648. As a result, data in which 9-bit data having the same value as that of the envelope addition / subtraction signal EDU is added to the lower part of the envelope level data EL is switched and selected as the envelope accumulation value EA, whereby the envelope accumulation in the next envelope phase is performed. The start point of the calculation is corrected to the accurate envelope level data EL.

The select signal of the selector 646 includes
Envelope addition / subtraction signal E indicating the accumulation direction of the envelope
When DU is used and the envelope accumulation is addition, the envelope accumulated value EA is the envelope level data EL.
When the above timing is detected and the envelope accumulation is subtraction, the timing at which the envelope accumulation value becomes equal to or less than the envelope level data EL is detected. Further, the Cout output of the adder 644 and the envelope addition / subtraction signal EDU are input to an exclusive OR gate 647, which is also used as the phase step signal ECS, and is used when the envelope accumulated value overflows or underflows. Also moves to the next phase of envelope accumulation.

The phase shift is performed by the phase control circuit 630. That is, the phase control circuit 630 enters the attack phase by the key-on signal given via the latch 642, and shifts to the next phase such as decay, sustain, release, etc. every time the above-mentioned phase advance signal ECS is given. . In this phase shift, the phase control circuit 630 instructs the assignment memory circuit 32 of the key assigner circuit 30 to read the envelope data for the next phase. When the phase at that time is to be held as it is, the latch group 652 is used. Will be kept.

In the envelope speed data decompression circuit 600, the compressed envelope speed data ES
Is expanded by performing shift control with the shift coefficient data EP0 to EP3 from the shift coefficient control circuit 610. The shift coefficient data EP0 to EP3 includes the upper four bits ES2 to ES5 of the envelope speed data and the envelope accumulation data. The upper four bits EA12 to EA15 of the arithmetic value are created based on the envelope addition / subtraction signal EDU.

The thin-out data TH0, TH1 from the assignment memory circuit 32 are supplied to the thin-out circuit 620.
, The thin-out (thinning out) of the latch timing of the envelope accumulated value in the latch group 650 is controlled. This thin-out circuit 620, phase control circuit 630, latch group 652, latches 641, 642, 65
1 is supplied with a clock signal from the system clock generator 10, and a channel cycle and a timing cycle of data processing are obtained.

<< Envelope speed data expansion circuit 6
FIG. 19 shows an envelope speed data expansion circuit 6
00, the envelope speed data ES0 is input to the A side “0” terminal and the B side “1” terminal of the selector 601, and the envelope speed data ES1 is input to the A side “1” and the B side “2” terminal. A terminal “2” and B
OR gate 6 of the envelopes ES2 to ES5 on the side "3" terminal
An output via the terminal 05 is input, and data “0” is input to the “3” terminal on the A side and the “0” terminal on the B side. As a result, E in the expanded envelope speed data of FIG.
S0, 1 and its upper one bit are created.

The 4-bit data from the selector 601 is transferred to upper or lower 2 bits of “00”, 4 bits of “0000”, 4 bits of data via selectors 602, 603 and 604.
8-bit "000 ... 0" is added. At this time, if the data is input to the A side of each of the selectors 601 to 604, the data is output without being shifted to the higher order, but if input to the B side, 1 bit, 2 bits,
The data is shifted by 4 bits and 8 bits. Therefore, by appropriately selecting the selection state of each of the selectors 601 to 604, the envelope speed data ES can be shifted as shown in FIG. 24. This selection state is selected based on the shift coefficient data EP0 to EP3. Done.

Thus, although the compressed envelope speed data ES is 7 bits including the envelope addition / subtraction signal EDU, the decompression value is expanded to 16 bits, and the memory usage can be reduced.

The envelope accumulated value EA obtained by accumulating the envelope speed data ESE expanded in this way.
(A) and (B) are latched by the above-mentioned latch group 650 for two channels for each of two tone components. The envelope accumulated values EA0 to EA15 are 16 bits, of which the upper 4 bits EA12 to EA15 are power data, and the lower 12 bits EA12 to EA15 are power data.
Bits EA0 to EA11 are mantissa data.

<< Shift Coefficient Control Circuit 610 >> FIG. 20 shows the shift coefficient control circuit 610. The upper 4 bits of the compressed envelope speed data ES are directly input to the A side of the adder 611, and are passed through the AND gate group 612. 2 are output as shift coefficient data EP0 to EP3.
3, ie, the expansion of the compressed envelope speed data ES is performed. FIG. 23 shows a case where the input on the B side of the adder 611 has no effect. When the input has an effect, the data shift is corrected. The NOR gate 613 and the OR gate 614 control the envelope speed data ES2 to ES2.
When 5 is “0000”, the shift coefficient data EP is “0”.
001 ", and even when the envelope speed data is" 0000 ", the data shift position is" 000 "as shown in the uppermost row of FIG.
1 ".

The envelope addition / subtraction signal EDU indicating the accumulation direction of the envelope accumulation value EA is supplied to the inverter 617.
, And is given to the NAND gate group 615 via the AND gate 616, and the envelope addition / subtraction signal ED
At the time of decay or release when U is “1”, “1111” is input to the B input of the adder 611. The Cin terminal of the adder 611 is “1”.
Is input, the input data on the A side of the adder 611 is output as it is without any influence. When the envelope addition / subtraction signal EDU is "0", the most significant bit EA1 of the envelope accumulated value is set.
When "5" is "0", "1111" is also input to the B side, and the A input is output as it is.
When A15 is "1", the envelope power data EA
12 to 15 are inverted and given to the B side as a subtraction value.

For this reason, the envelope power data EA
12 to 15 exceed "1000" and "1001 (9
(Н is a symbol indicating that it is a hexadecimal value) "" 1010
(Aн), “1011 (Bн)”,..., The shift coefficient data EP0 to EP3 are −1, −2,
-3 ..., and as shown in FIG.
Since the data shift-up in the envelope speed data expansion circuit 600 is suppressed accordingly, the speed data becomes a value of 1/2, 1/4, 1/8 ..., and as shown in FIG. 26, the attack portion of the envelope waveform is exposed. It can be made into a sensual shape.

Thus, the attack characteristic of the envelope waveform can be made closer to a sound existing in the natural world. In this case, the envelope power data EA12-
When 15 is equal to or less than "1000 (8)", the waveform is not exponential but has a linear waveform. However, up to this stage, there is no significant difference in waveform, whether exponential or linear, and It is indistinguishable, so that the circuit configuration can be simplified.

The AND gate group 612 receives a signal from the Cout terminal of the adder 611 as an open signal, and outputs the envelope speed data ES2 to ES2.
When the subtraction value of the B input becomes larger than the value of 5, and the shift coefficient data EP0 to EP3 becomes negative,
ut terminal output becomes “0”, and the AND gate group 612 is output.
Is closed.

<< Phase Control Circuit 630 >> FIG. 21 shows the phase control circuit 630, and FIG. 29 shows the data conversion contents of the phase control circuit 630.
The phase values PH0 and PH1 are obtained by passing the phase values PB0 and PB1 through the latch group 652.
As shown in FIG. 7, the attack is represented by “00 (0)”,
1 (1) ”for the second attack or decay,“ 10
(2) ”for sustain or 2nd decay,“ 11
(3) "indicates a released or silent state.

In FIG. 21, if the key-on signal becomes "0" regardless of the phase values PH0 and PH1,
The outputs of the NAND gates NA3 and NA5 become "11", and the phase values PA0 and PA1 are made "11 (3)" as shown in the upper part of FIG. This is because if the key is turned off during sound emission, the release state is forcibly set in any phase.

When the key-on signal is "1" and the output of the NAND gate NA1 is "1", the phase values PH0, PH0,
After 1 is inverted by the NAND gates NA2 and NA4, it is again inverted by the NAND gates NA3 and NA5, and the value is maintained as shown in the lower part of FIG. This is because during key-on, the phase at that time may be maintained as it is.

Further, the phase values PH0 and PH1 are set to "11
When the key-on signal becomes "1" in the release state of "(3)", the output of the NAND gate NA1 becomes "0". Therefore, the outputs of the NAND gates NA2 and NA4 are "11", and the outputs of the NAND gates NA3 and NA5 are "00". And the phase value PA
0 and 1 are “00” as shown at the bottom of FIG.
(0) ". This is because the phase is set to “00 (0)” if the key-on state is established during the release or silence, and the next new musical tone is generated and emitted. At this time, the output of the inverter IV2 becomes "1", and an on-event signal is output. Note that the latch 63
In 1, a latch operation is performed by a clock signal from the system clock generator 10.

When the phase step signal ECS is "0", the NOR gate N of the exclusive OR gate EO1
The data from R1 becomes "0" and the phase value PA0
Is output as PB0 as it is, and AND gate AN1
Is closed, the phase value PA1 is output as it is as PB1 via the OR gate OR1, and FIG.
(2) As shown in the upper part, the value is maintained as it is.
This is because if there is no instruction to advance the phase, the phase at that time may be maintained as it is.

When the phase step signal ECS is "1", when the phase values PA0, 1 are "00", PB0,
1 becomes “01” and is advanced to the next phase. When the phase values PA0 and PA1 are “01”, PB0 and 1 become “10” and are also advanced to the next phase. ,
The result is as shown in the middle part of FIG. This is because if there is an instruction to advance the phase, the phase at that time may be advanced by one.

However, when the phase advance signal ECS is "1"
When the phase values PA0 and PA1 are "10" and "11", the phase is not advanced, and the value is maintained as shown in the lower part of FIG. 29 (2). This is because phase “10 (2)” starts with phase “11” of the next release.
The transition to (3) ”is performed only when the key-on state changes to the key-off state, and the release or silence phase“ 11 (3) ”changes to a new attack phase“ 00 ”.
The reason for shifting to (0) "is only when the state changes from the key-off state to the key-on state, and the phase only needs to be advanced by changing the key-on signal.

FIG. 28 shows such a phase value PH0,
This indicates the storage state of 1 (PB0, 1) in the latch group 652, in which (A) and (B) phase values for 16 channels are latched for two tone components.

<< Sin-out Circuit 620 >> FIG. 22 shows a thin-out circuit 620. A counter 621 is based on a clock signal CK7, as shown in FIG.
The clock signals Q0, 1,...
The clock signals Q0, 1,...
The signal is output as the latch signal TO via the OR gate group 622 and the NAND gate 623. The thin-out data TH0,1 indicating the thinning rate of the latch of the frequency number accumulated value FA from the assignment memory circuit 32 is supplied to the OR gate group 6 via the AND gate 625 and the OR gate 626.
22 and the syn-out data TH1 is directly supplied to a part of the OR gate group 622, whereby the output of the OR gate to which the "1" signal is supplied is always set to "1", and the clock signals Q0 to Q5 are output. Invalidate.

When the thin-out data TH0 and TH1 are "00", all the clock signals Q0 to Q5 are valid, so that the latch signal TO is equal to all the clock signals Q0 to Q5.
Is "0" only when is "1". As shown in the lower part of FIG. 30, this is a timing of one out of 64 times when viewed from the same clock signal CK7 as the original channel timing, that is, the original latch timing.

Further, the thin-out data TH0 and TH1 are "0"
When "1", only the clock signals Q0 to Q3 are valid, so that the latch signal TO indicates that the clock signals Q0 to Q3 are "1".
"0" only at the time of. As shown in the lower part of FIG. 30, this is a timing of 16 times when viewed from the same clock signal CK7 as the original channel timing, that is, the original latch timing.

Further, when the thin-out data TH0 and TH1 are "10", only the clock signals Q0 and 1 are valid, so that the latch signal TO becomes "0" only when the clock signals Q0 and 1 are "1". ". As shown in the lower part of FIG. 30, this is a timing of one out of four times when viewed from the same clock signal CK7 as the original channel timing, that is, the original latch timing.

Further, the syn-out data TH0, TH1
Is "11", all the clock signals Q0 to Q5 are invalidated, so that the latch signal TO
Regardless of 5, it is always "0". This is exactly the same timing as the clock signal CK7, which is the same as the original channel timing, that is, the original latch timing, as shown in the lower part of FIG.

The latch signal TO generated in this manner is
Is output from any of the 32 output lines 0 to 31 of the decoder 624, and a thin-out (decimation) latch of the envelope accumulated value EA is executed in any of the 32 latch groups 650. This is performed sequentially for each latch. 0 to 0 of the decoder 624
Selection of 31 output lines of 31 is performed by clock signals CK3 to CK7 supplied via a latch 627.

In this manner, as shown in FIG. 32, the number of bits of the envelope accumulated value EA is reduced from 20 bits conventionally required to 16 bits due to the thinning out (decimation) of the latch of the envelope accumulated value EA. It can emit musical sounds with good operability.

Incidentally, the latch 627 is latched by a clock signal from the system clock generator 10 and the timing is synchronized.

<Multiplying Circuit 70> FIG. 33 shows a multiplying circuit 70, in which the interpolation waveform data IP composed of the sample values and the interpolation values of the waveform data from the waveform data decompression interpolation circuit 50 is shown.
0 to 9 are provided to the multiplication circuit 70, and the envelope accumulated values EA0 to EA1 from the envelope generator 60 are provided.
5, the mantissa data EA3 to EA11 excluding the lower 3 bits and the upper 4 bits are also supplied to the multiplying circuit 70, and the waveform data is multiplied by the envelope.

At this time, "1" data is added to the higher order of the envelope mantisser data EA3 to EA11 to be multiplied. This is because, if the 9-bit envelope Man tipper support data EA3~11 is M, indicates that performs calculation of 1 + M / 2 ^9, so that the interpolated waveform data IP to this value is multiplied. The multiplied data MT multiplied in this way is output as 20-bit data.
5 is output to the shift circuit 80.

<Shift Circuit 80> FIG.
The multiplied data MT0 to MT15 are shifted down according to the values of the envelope power data EA12 to EA15 through the four-stage selectors 800, 801, 802, and 803, and the tone data ST0 to ST0 are output. As 15,
It is output to sequence accumulation circuit 90.

The selector 800 outputs the select signal EA12
Is "0", the data is shifted down by one bit, and when "1", the data is output without being shifted. Selector 8
01 shifts down by 2 bits when the select signal EA12 is "0", and outputs data without shifting when it is "1". The selector 802 outputs the select signal E
When A12 is "0", shift down by 4 bits to "1"
In this case, data is output without shifting. When the select signal EA12 is “0”, the selector
Bit shift down, and when "1", data is output without shifting.

Therefore, the envelope power data EA1
The smaller the value of 2 to 15, the larger the downshift amount. If the envelope power data EA12 to EA15 is P, this shift circuit 80 performs 2P ^-16 calculation. If the interpolation waveform data is R, the output of this shift circuit 80 is ^2P-16. × (1 + M / 2 ⁹ ) × R
Becomes In this case, 1 in parentheses may be omitted, and the input of the “9” terminal on the B side of the multiplication circuit 70 becomes “0”.

Due to the data shift-down, the lower the envelope level, the higher the ratio of the shift-down. As shown in FIG. 35, the envelope waveform has exponential characteristics such as decay, release, etc., as shown in FIG. Can be brought even closer to the sound that exists.

<Sequence Accumulator 90> FIG. 36 shows a sequence accumulator 90. The tone data ST0 to ST15 from the shift circuit 80 are stored in an exclusive OR gate group 90.
When the waveform return signal FDU, which indicates that the waveform data is a negative value via "0", is "1", the waveform data is inverted in the plus and minus directions. This inverted tone data GA0-15
Are added to the accumulated musical tone data GC0 to GC15 for each series up to that point in the adder 901 and are provided to the A side of the selector 906. The waveform folded signal FDU is applied to the Cin terminal of the adder 901, and when the waveform data is a negative value, +1 is corrected.

On the B side of the selector 906, 15-bit data in which each bit has the same value as the most significant bit GC15 of the accumulated musical tone data GC on the A side, and the musical tone data GA before accumulation in the adder 901 are stored. The most significant bit GA15 is given as the most significant bit, and when overflow occurs, a maximum positive value “011... 1” and when an underflow occurs, a maximum negative value “100.
06 is input from the B side and output as new accumulated musical tone data GC. The most significant bit "0" in this case
“1” is a sign bit.

The detection of the overflow and the underflow is performed as follows. That is, first, the most significant bit GA15 of the musical tone data GA and the most significant bit GC15 of the accumulated musical tone data GC up to that point are output from the inverter 903 via the exclusive OR gate 902, and the two data match, that is, "00". , It is detected that addition is being performed, and if it is determined that it is “11”, it is detected that subtraction is being performed. As a result, the AND gate 905 is opened.

Next, the most significant bit GB15 of the accumulated musical tone data GB of the accumulated value in the adder 901 and the most significant bit GA15 of the musical tone data GA are input to the exclusive OR gate 904, and when the two data do not match, That is, the most significant bit GB1 of the music data GB after accumulation during addition.
5 becomes "1" and overflow occurs, or the most significant bit GB1 of the musical tone data GB after accumulation during subtraction
5 is detected to be "0" and an underflow is detected, and this detection signal is supplied as a select signal to the selector 906 via the AND gate 905, and as described above, the positive maximum value " 01
1 ... 1 ", negative maximum value" 10
0 ... 0 "is output.

In this way, even if the cumulative value GB of the musical tone data overflows or underflows, the amplitude level of the musical tone signal can be maintained at the maximum amplitude, no special judgment bit needs to be provided, and the data processing amount is reduced. be able to.

Accumulated musical tone data GC from selector 906
0 to 15 are input to the latch buffer 910. The latch buffer 910 is composed of eight latches and eight three-state buffers having almost the same function as the selector. Of the eight latches, four latches named “group a” and “group b” are used, respectively. Are alternately switched between those for accumulating musical tone data and those for outputting this accumulated value. There are four latch buffers 910 each.
This is because there are four tone generation systems formed in the DA converter 100 and the sound system 110, and the tone data is cumulatively calculated for each of these systems.

This system includes, for example, the first system having the (A) and (B) musical tones of the channels CH0 to CH3, the second system having the (A) and (B) musical tones of the channels CH4 to CH7, and the third system having the channel CH8. To the (A) and (B) musical tones of １１11, the musical tones of (A) and (B) of the channels CH12 to 15 are assigned to the fourth system, and the musical sound data of each channel is accumulated for each stream.

The sequence is determined by the sequence data GR0,1 from the assignment memory circuit 32, and the decoder 907 converts the sequence data GR0,1 and the clock signal CK8 into the clock signal CK3 and the clock signal CK2. 37 (3)), the latch is fetched and decoded, and the latch in the latch buffer 910 to which the accumulated value is to be written is sequentially selected. This is the 35th
In the example shown in the figure, as shown in (4), each channel C
H0, 1... 15 are performed at the respective timings (A) and (B), and for each of (A) and (B) two musical tones from the shift circuit 80, four channels are accumulated and synthesized for each sequence. It will be output.

The series data GR0 and GR1 are supplied to a decoder 909 via a selector 908. The decoder 909 converts the series data GR0 and GR1 and the clock signal CK8 into a clock signal CK3 and a clock signal CK2.
Alternatively, the latch is read in at the timing of the inverted signal of the clock signal CK2, decoded, and the three-state buffer is controlled to sequentially select the latches in the latch buffer 910 from which the data being accumulated is read. This corresponds to the sequence GR0b, GR1 as shown in (5) in the example of FIG.
b, GR2b... In contrast,
The clock signal group is also supplied to the decoder 9 via the selector 908.
09, the decoder 909 captures and decodes the clock signal group and the clock signal CK8 at the timing of the clock signal CK2, controls the three-state buffer, and reads the accumulated value in the latch buffer 910. Are sequentially selected. In the example of FIG. 37, this is as shown in (5), for each channel CH0,
Sequences GR0a, GR1a, GR2a for 1 ... 15
The timing is indicated by. As a result, FIG.
As shown in (5), accumulation is performed in the latch whose write timing to the latch coincides with read timing from the latch, and accumulated tone data is read in other latches.

Music data G from latch buffer 910
C is output to the DA converter 100 via the latch 911. The latch to the latch 911 is performed as shown in FIG.
(5) are performed at the same timings as indicated by the series GR0a, GR1a, GR2a,..., And as shown in FIG.
The data is output alternately by the group latches. Note that FIG.
One shot as shown in (6) is given from the system clock generator 10 to the latch buffer 910, and the latches of group a and the latches of group b are alternately reset. The latch 911 is connected to the DA from the key assigner circuit 30.
Reset by gate signal.

The present invention is not limited to the above embodiments, but can be variously modified without departing from the spirit of the present invention. For example, the combination of the two (A) and (B) selected musical tones may be any of the 128 timbres using the numeric keypad without using the timbre switch 2. Touch data T
O may be data corresponding to the key pressing speed indicating the key pressing speed. In this case, the time from when the break contact of each key is turned on to when the make contact is turned on may be used as the touch data TO. Further, a multiplier is provided at the output end of the waveform data decompression interpolation circuit 50, and a time-varying parameter signal is given as multiplication data, and (A) and (B) the weighting of the two musical tones is changed according to the sound emission progress of the musical tones. Alternatively, the combination of (A) and (B) may be changed according to the tone length.
In this case, different parameter signals are provided in the first half and the second half of the clock signal CK3, and further, these signals are provided for 16 channels.

[A] Waveform storage means for storing a plurality of types of musical sound waveforms, waveform selection means for selecting two or more waveforms in any combination from the waveform storage means, and sound generation instruction means for instructing the generation of musical sounds In response to one instruction from the sounding instruction means, a waveform reading means for reading out each of the waveforms selected by the waveform selecting means in a common reading step by time-division processing; A musical sound waveform generating apparatus, comprising: synthesizing means for accumulating and synthesizing each waveform.

[B] Waveform storage means for storing a plurality of types of musical sound waveforms, waveform selection means for selecting two or more waveforms in any combination from the waveform storage means, and sound generation instruction means for instructing the generation of musical tones In response to one instruction from the sounding instruction means, a waveform reading means for reading out each of the waveforms selected by the waveform selecting means in a common reading step by time-division processing; A musical sound waveform generating apparatus, comprising: envelope control means for individually envelope-controlling each waveform; and synthesizing means for accumulating and synthesizing each waveform envelope-controlled by the envelope control means.

[C] The waveform selecting means selects the timbre, pitch,
The combination of the two or more waveforms is changed according to the strength or slowness of the sounding operation, the volume, the tempo, the rhythm, and the effect.
A musical sound waveform generator according to the above description.

[D] The waveform selecting means provides upper address data to the waveform storage means, and the waveform reading means provides lower address data to the waveform storage means. Or the musical sound waveform generating apparatus according to B.

[0122]

As described in detail above, according to the present invention,
Since waveform data with different numbers of bits are stored and read out to match the data length, even if the number of quantization bits is reduced, the number of stored bits is reduced for lively sounds where quantization noise is not so problematic. It is possible to reduce the amount of memory used by reducing the number of sounds, and to increase the number of storage bits for sounds that are not so effective.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of an electronic musical instrument.

FIG. 2 is a diagram illustrating an input portion of the electronic musical instrument.

FIG. 3 is a time chart of each part in FIGS. 1, 2 and 5;

FIG. 4 is a diagram showing stored contents of a ROM 20.

FIG. 5 is a circuit diagram of the key assigner circuit 30.

FIG. 6 is a diagram showing a correspondence relationship between address data of a CPU 300 and address data of a ROM 20.

FIG. 7 is a diagram showing storage contents of an assignment memory 320;

8 is a circuit diagram of a frequency number accumulator 40. FIG.

FIG. 9 is a diagram showing a read state of waveform data.

FIG. 10 is a diagram showing the contents of a frequency number accumulated value FA.

11 is a circuit diagram of a waveform data decompression interpolation circuit 50. FIG.

FIG. 12 is a diagram showing the correspondence between sample values for half a wavelength of waveform data and readout timings.

FIG. 13 is a diagram showing sample values and interpolation values of waveform data.

FIG. 14 is a diagram showing the contents of waveform data RD.

FIG. 15 is a diagram showing expanded contents of difference data RD0 to RD5 of waveform data.

FIG. 16 is a diagram showing the content of conversion from differential mantissa data RD to converted differential mantissa data RG.

FIG. 17 is a diagram showing the relationship among the upper bits FA9 to FA11 of the decimal part of the frequency number accumulated value, the multiplication data IM0 to IM2 of the difference data, and the interpolation contents of the sample values of the waveform data.

FIG. 18 is a circuit diagram of the envelope generator 60.

FIG. 19 shows an envelope speed data decompression circuit 600.
FIG.

FIG. 20 is a circuit diagram of a shift coefficient control circuit 610.

FIG. 21 is a circuit diagram of a phase control circuit 630.

FIG. 22 is a circuit diagram of a thin-out circuit 620.

FIG. 23: Expanded envelope speed data ESE
It is a figure which shows the content of.

FIG. 24 shows an envelope accumulated value EA during an attack.
FIG. 7 is a diagram showing a relationship between envelope power data EA12 to 15 and expanded envelope speed data ESE (SS).

FIG. 25 is a diagram showing the contents of an envelope accumulated value EA.

FIG. 26 is a diagram showing an envelope waveform according to an envelope accumulated value EA.

FIG. 27 is a diagram showing an envelope phase.

FIG. 28 shows a phase value PH stored in a latch group 652.
FIG.

FIG. 29 is a diagram illustrating conversion contents of a phase value in a phase control circuit 630.

FIG. 30 is a time chart of each part of the thin-out circuit 620.

FIG. 31 is a diagram showing a conventional envelope accumulation timing.

FIG. 32 is a diagram illustrating the accumulation timing of the envelope accumulated value EA due to thin out (thinning out of the latches into the latch group 650).

33 is a circuit diagram of the multiplication circuit 70. FIG.

34 is a circuit diagram of the shift circuit 80. FIG.

FIG. 35 is a diagram showing correction contents of an envelope waveform by a shift circuit 80;

FIG. 36 is a circuit diagram of a sequence accumulation circuit 90.

FIG. 37 is a time chart of each part of the sequence accumulation circuit 90.

[Explanation of symbols]

20 ROM, 30 key assigner circuit, 31 ROM
Address control circuit, 32 ... assignment memory circuit, 4
0: frequency number accumulator, 50: waveform data decompression interpolation circuit, 60: envelope generator, 70: multiplication circuit, 80
... Shift circuit, 90 ... Sequence accumulation circuit, 300 ... CPU,
320: assignment memory, 600: envelope speed data decompression circuit, 610: shift coefficient control circuit,
620: Thin out circuit, 630: Phase control circuit.

Claims (3)

(57) [Claims] An M bit- length waveform data at one point of a waveform is the same as an N bit at one point of a waveform.
Waveform storage means for storing waveform data having a bit length (M <N) , wherein a storage capacity of one address of the waveform storage means is stored.
The quantity is L bits long (M <L), and the L bit length
The entire M-bit waveform data is stored in the storage location.
And the remaining video data of the stored M-bit-length waveform data.
Stores the entire waveform data at another point
Is, the N bits or the waveform data is the M-bit long
A discriminating storage unit for storing discriminating information for discriminating whether the length is long , a unit for selecting any of the stored waveform data, a unit for reading the discriminating information relating to the selected waveform data, Means for determining the output discrimination information; means for reading the selected waveform data; and, according to the determination result, the read waveform data is the M-bit length (M <N) waveform data. if any, move the data length to the data length of the waveform data of the N-bit length of the waveform data of the M-bit long, another of the remaining bits
Data and the M-bit long wave at the point
Shape data or the above N-bit waveform data
Means for outputting at a timing corresponding to these points . 2. The M bitLongWaveform data and N bitsLong
These waveform data correspond to the differences in timbre.
Data is stored in the waveform storage means, and N bitsLong
(10 bitsLong) Is 6 bitsLongDifference data
Data with the dataLong(8 bitsLong) Wave
Shape data is the data of two sample points.
The distinction information is part of the tone data,
Is initially stored in the shape storage means, and
It is stored for each channel in the signature memory,
M bits aboveLongWaveform data and the above N bitsLongWaveform
The selection of one of the data depends on the tone selection.
The waveform data is read at the speed corresponding to the specified pitch.
The discrimination information is further stored in the waveform data decompression interpolation means.
Is sent as switching control information to the selection switching means of
 This selection switching means is an M bitLong(8 bitsLong)
Waveform data and N bitsLong(10 bitsLong) Waveform data
And M bitsLong(8 bitsLong)of
Waveform data is shifted to the higher order and N bitsLong(10 vi
ToLong) Or M bitsLong(8 vi
ToLong) Is M bitsLongAnd N bitsLongWith
Bit of differenceLong(2 bitsLong) Data is added,
The M bit of two sample points stored together
GLong(8 bitsLong) Waveform data
May be read out at each sample timing.
2. The musical sound waveform generator according to claim 1, wherein: 3. An M-bit- length waveform data at one point of the waveform as well as N at one point of the waveform.
Waveform storage means for storing waveform data having a bit length (M <N) , wherein a storage capacity of one address of the waveform storage means is stored.
The quantity is L bits long (M <L), and the L bit length
The entire M-bit waveform data is stored in the storage location.
And the remaining video data of the stored M-bit-length waveform data.
Stores the entire waveform data at another point
Is, the N bits or the waveform data is the M-bit long
There in a distinguished storage means for storing a distinguishing identification information whether the length, for these waveform storage means and the distinction memory means, a step of selecting one of the stored waveform data are the selected Reading the discrimination information according to the read waveform data, determining the read discrimination information, reading the selected waveform data, and reading the selected waveform data according to the determination result. and if waveform data is waveform data of the M bit length (M <N), Align the data length of the waveform data of the N-bit length data length of the waveform data of the M-bit long, the remaining bits in length of
Waveform data at another point and the M-bit length
Waveform data or the above N-bit-length waveform data
A step of outputting at a timing corresponding to each point .