JPH02203394A - Musical sound frequency modulating device for electronic musical instrument - Google Patents

Abstract

PURPOSE:To realize various modulation contents unitedly with a small amount of modulation data by varying the reading speed of waveform data according to modulation information read out of a modulation information storage means stored with plural pieces of modulation information. CONSTITUTION:The pieces of modulation information for varying the reading speed of musical sound waveform data on a musical sound waveform, etc., or basic waveform data on the basic waveform of a sine wave, etc., like real- time sine composition, an FM sound source, and a PD sound source. Then the reading speed of musical sound waveform data is varied according to the modulation information. Consequently, the pieces of modulation information corresponding to variation in timbre, tone length, etc., and variation in one musical sound effect can be stored by one modulating device and the best modulation contents for various musical sound states are easily realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial NII Field] The present invention relates to a musical tone frequency modulation device for an electronic musical instrument that performs frequency modulation by changing the data read speed when reading musical waveform data or basic waveform data.

SUMMARY OF THE INVENTION] The present invention changes the reading speed of musical waveform data based on a plurality of modulation information that changes the reading speed of musical waveform data or basic waveform data, thereby providing a' This is achieved by unifying the modulation contents using a small amount of modulation data.

[Prior Art] Conventionally, there have been various methods to obtain various musical effects by modulating the musical tone frequency, and representative ones include glide effect to growl effect, voltament effect, vibrato effect, tremolo effect, vent effect, etc. .

These are distinguished by the content of frequency modulation.

Among these, the vibrato effect is a musical effect that periodically changes the musical tone frequency, but in electronic musical instruments, this effect is applied to the reading address of the musical sound waveform at a constant level of about ±25 cents, and from 6 to 8H2. This was achieved by adding a constant cycle sine wave or triangular wave bias address. In this case, a special circuit or program is provided to add a bias address dedicated to this vibrato effect.

Also, among these vibrato effects, there is a delay vibrato effect in which the vibrato is delayed for a long time from the key-on timing, but this delay time is usually always constant regardless of the pitch or timbre.

Furthermore, the glide effect, which is often used in electronic organs, is a musical effect that changes the musical tone kite wave number so that it moves from a semitone below the key pressed note to the key pressed note. This was achieved by adding a semitone bias address to the tone waveform readout address when pressed, and gradually reducing the semitone bias address when the glide switch was released. In this case, a special circuit or program is also provided to add a bias address dedicated to this glide effect.

In addition, there are synthesizers such as "benders" that modulate the musical frequency by an amount corresponding to the amount of volume displacement by moving the volume, but this synthesizer detects the amount of volume displacement and This is achieved by adding a bias address corresponding to the tone waveform to the readout address of the tone waveform. This vendor also had a special @rosu program for vendors.

[Problems to be Solved by the Invention] As described above, conventional frequency modulation devices have separate circuits and programs dedicated to vibrato effects, glide effects, and vendors, and it is difficult to achieve many of these effects. To achieve this, a large number of circuits and programs were required.

In addition, in conventional products like this, the contents of each effect are almost fixed, except for the vibrato speed and depth of the vibrato effect, and it is not possible to change the modulation contents. For example, it was not possible to freely change the delay time of a delay vibrato effect or the duration of a glide effect. Furthermore, whether the content of each of these effects is uniformly the same regardless of tone, pitch, length, etc.
Or, it was a method of selecting from several types, and it was not possible to have a value suitable for each individual musical tone.

The present invention has been made to solve the above-mentioned problems, and it is possible to vary the modulation content quite widely and freely, and also to change the modulation content depending on the timbre, tone length, etc. Moreover, it is an object of the present invention to provide a musical tone frequency modulation device for an electronic musical instrument that can realize all kinds of musical effects by frequency modulation with one modulation device and easily obtain the optimum modulation content for each musical tone.

[Means for Solving the Problems] In order to achieve the above object, the present invention uses music waveform data that stores the music waveform itself, or basic sine waves such as real-time signature synthesis, FM sound source, PD sound source, etc. A plurality of pieces of modulation information for changing the readout speed of basic waveform data in which waveforms are stored are stored in advance, and the readout speed of musical waveform data is changed based on this modulation information.

[Effect 1] With the above configuration, one modulation device can store multiple pieces of modulation information corresponding to changes in timbre, tone length, etc., or changes in one musical effect, making it ideal for a wide variety of musical tones. Modulation contents can be easily realized.

Embodiment] Hereinafter, an embodiment embodying the present invention will be described in detail with reference to the drawings.

Overall Circuit> FIG. 2 shows an overall circuit diagram of the present invention, in which each key of the keyboard 1 and each switch of the tone switch 2 is scanned by a key assigner circuit 30, and the pitch is set according to the operated key. A musical tone having a tone corresponding to the operated tone color switch is assigned to an empty channel of a 16-channel musical tone generation system. This channel assignment content is stored in the assignment memory circuit 32. Further, the key depression pressure of each key on the keyboard 1 is detected by a pressure sensor 3 provided on each key,
The A-D converter 4 converts the data into digital touch data To indicating the key press pressure, and sends it to the CPU 300, which will be described later.

The ROM 20 contains a processing program for generating musical tone signals, tone data regarding waveforms and envelopes,
The waveform data RD itself etc. are stored, and the read address is controlled by the ROM address control circuit 31.
Reading of the processing program or tone data and reading of the waveform data RD are switched. The processing program read from the ROM 20 is executed by the key assigner circuit 30.
The data is sent to the CPU 300, which will be described later, and various processes are executed, and the tone data regarding the waveform and envelope read from the same ROM 20 is written to the area corresponding to the empty channel of the assignment memory circuit 32.
Furthermore, the same (waveform data R read from ROM20)
D itself is sent to the waveform data expansion interpolation circuit 50. In the assignment memory circuit 32, frequency number and speed data FS corresponding to the operation keys of the keyboard 1 are also written in areas corresponding to empty channels.

This frequency number speed data FS is a frequency number accumulation! The i40 accumulates j times for each channel, and R
The waveform data RD is given as read address data to the ROM 20 via the OM address control circuit 31, and is read out at a speed according to the frequency number speed data FS, that is, at a speed according to the pitch, and the waveform data expansion interpolation circuit 5
It is input to 0. The waveform data RD to be read is from the ROM
A large number of bank data are stored in the assignment memory circuit 32, and selection thereof is performed by bank data read out from the assignment memory circuit 32. In the waveform data expansion interpolation circuit 50,
The differential data read out from the ROM 20 in a compressed state is expanded, and each waveform data RD
The interpolation points between the sample point points are also determined and sent to multiplication circuit R70. This interpolation is performed using a portion of the frequency number accumulation value FA from the frequency number accumulator 40.

Further, data related to the envelope from the assignment memory circuit 32 is sent to an envelope generator 60 to generate an envelope waveform, and sent to the multiplier circuit 70, where the expanded interpolated waveform data 1.
Each sample value of P and each sample value of the envelope waveform E
A is multiplied by D-A, data is shifted in a shift circuit 80, and accumulated for each series in a series accumulation circuit 90.
Sound is output from the sound system 110 via the converter 100.

The envelope generator 60 stores the current phase value P of the envelope waveform in the assignment memory circuit 32.
H is sent to cause the envelope data for the next new phase to be output. Further, an on event signal is sent from the envelope generator 60 to the frequency number accumulator 40 at the key-on timing, and the accumulation of frequency number speed data FS is started. Further, from the envelope generator 60, the waveform data expansion interpolation circuit 5
0 is sent the data length signal D816, and the waveform data RD
A selection is made whether to perform interpolation or not. The data length signal D816 indicates whether the waveform data RD consists of two 8-bit sample values or a 10-bit sample value and 6-bit difference data. When the difference data is read out, interpolation of the waveform data RD is performed.

The shift circuit 80 shifts down the multiplied musical tone data according to the magnitude of envelope power data EA12 to EA15, which are the upper bits of the envelope 1 accumulated value EA, and exports the falling edge at the time of decay and release. This is to give it natural characteristics and bring it closer to natural sounds.

Further, in the D-A converter 100, four musical tone generation systems are formed in a time-sharing manner, and in the series accumulation circuit 90, the series data GR from the assignment memory circuit 32 is
Depending on this, it is determined which generation system the musical tone data will be sent to. The series accumulation circuit 90 is supplied with a waveform return signal FDU from the frequency number accumulator 40, and this waveform return signal FDU is generated after the generation of the first half waveform of the waveform data is completed. When the half waveform is generated, it becomes high level, which causes the series accumulation circuit 9
When it is 0, it is a value obtained by inverting the musical tone data plus or minus. The series accumulation circuit 90 also includes a key assigner circuit 3.
0, a DA gate signal is applied, and musical tone data output control to the DA converter 100 is performed.

From the system clock generator 10 to each circuit 30 in FIG.
．． 40-50.60.90 has a period of 1:2:4:8
Various clock signals CK I CR2 in the ratio of...
CR3, CR2, etc., their frequency divisions, logical sums, logical products, etc. are given, and the timing control of each circuit is performed.

<ROM 20> Figure 5 shows the memory contents of the ROM 20.
M20 is divided into 16 bank areas from 0 to 15, and each bank area has an address from 0000H (H is a hexadecimal value) to FFFFHJ. , "0000H" to "0FF" of bank [0]
"FH" is the area used by the CPU RAM 301 for the CPU 300, the assignment memory 320, the modulation calculation RAM 331, etc.
is the area used by the MMU latch 310, which will be described later;
2000 HJ~rFFFF+" stores a processing program for generating musical tone signals. bank"
1'', ``0000H'' to r3FFFHJ store timbre coefficient data for 128 timbres for selecting and determining the contents of the waveform and envelope 1.

Bank “1” from “4000HJ onward” to bank “15”
'FFFFHJ is read out with one selected tone for each bank (A> (B) Two musical waveform data RD are stored at the same address. This musical waveform data RD is a sine wave, a triangular wave, , sawtooth wave, square wave,
In addition to noise waveforms etc. and waveforms that are synthesized from these, it may be multiple types of waveforms that synthesize each frequency component corresponding to a spectral group of multiple specific frequency bands corresponding to a specific formant, or a loop top, waveform, etc. The storage area for timbre data, which may be a PCM waveform using a loop end or the like, is located at a position offset from the storage area for the processing program by 5 minutes of MMU address data, which will be described later.

Figure 6 shows '0OOOHJ~'0F of bank "0".
It shows the detailed contents of the FFHJ area, '0OO
O+-z~'0FFF+-+4, '0000)(
4~'07FFHJ is the area used for CPU RAM 301, '0800H1~'08FFHJ is the area used for assignment memory 320, '0900HJ~'0
9FFHJ is the area used for modulation calculation RAM 331,'
0AOOHJ to '0EFFHJ are not used, '0FO
O)II~'0FFPH1 is an area used for an interface between each circuit. Of these, '0FOOHJ~'
0FOF+4 is an area used for interfaces such as an input buffer 307 and an output latch 306 in the keyboard 1, which will be described later.
0FIFHJ is also the input buffer 305 and output latch 304 in the tone switch 2, which will be described later.
This is the area used for interfaces such as rOF20H.
4~'0F2FHJ is MMU latch 31, which will also be described later.
This is the area used for 0, '0F30H4~' OF
3FHJ is also an area used for a timer 302, which will be described later, and rOF40+-+4 to rOFFH1 are not used.

FIG. 7 shows the contents of the above-mentioned timbre coefficient data.
One tone is composed of four pieces of data with key scaling of 0.1.2.3 and one modulation coefficient. Key scaling 0.1.2.3 divides the sound range of the keyboard 1 into four parts, and changes harmonic components and noise components depending on the range, and changes the envelope waveform to achieve a tone that corresponds to the keyboard scaling. In addition, even a single timbre is memorized in order to further refine the timbre content. The modulation coefficient is data for subtly changing the frequency of a musical tone while emitting one musical tone, thereby realizing a musical tone that is more natural.

Among these, each timbre coefficient data of waveforms 0 to 3 of key scaling 0 to 3 is for the musical waveform and that for the envelope.The timbre coefficient data for the musical waveform is bank data, key number bias data ( KEY No. bias), cent bias data (CENT bias), data length signal data D81
6. Series data OR, initial frequency number data,
Consisting of loop top data and loop end data, the tone number data for envelope 1 is (A>(B)) for each tone assigned to one channel.
Two envelopes are selected, and the two envelope data (A) and (B) are divided into four phases, for example, attack, decay, sustain, and release, PH01P.
The envelope data exists for HI, PH82, and PH3, and the envelope level data E
L, envelope adjustment signal data ECU, thin-out data TH, and envelope speed data ES.Tone color coefficient data regarding modulation coefficients are modulation speed data MSPD, modulation depth data MDEP, phase speed data PSPD, and interpolation selection signal data. IN
P, return signal data RBT, start trigger selection signal data TRG, and initial phase angle data (initial MSACC).

The bank data is for selecting and specifying one of the 15 types of musical waveform data RD, and two waveforms (A), CB) are selected for each tone assigned to one channel.

The key number bias data is bias data that is added to or subtracted from the specified pitch of the keyboard 1 in order to realize the pitch specified by the keyboard 1 with respect to the standard foot range (pitch) of the timbre coefficient data. When the timbre coefficient data is based on 4 feet and the musical waveform data RD is based on 8 feet, if the key number bias data is set to r12 (OOOILOOB (B is a symbol indicating that it is a binary number)), it will increase by 1 octave. The foot range of musical sound waveform data RD can be made to match the foot range of timbre coefficient data, and when the timbre coefficient data is based on 16 feet, the key number bias data can be set to By moving down the octave, the foot range of the tone waveform data RD can be matched with the foot range of the timbre coefficient data. This value of "12" corresponds to the number of pitches for one octave, and if the foot range difference is one octave or less, the key number bias data will also be "121 or less."

If the foot range difference is less than an integer value equivalent to one pitch difference, cent bias data indicates the decimal value less than this integer value, and 100 cents is divided into 64 equal parts by 6 bits of data. The values of these key number bias data and cent bias data are determined using the same standards as the key number data and cent data shown in Fig. 14, which will be described later. Ru.

The data length signal D816 is the waveform data R as described above.
This indicates whether D is composed of two 8-bit sample values or a 10-bit sample value and 6-bit difference data.As mentioned above, the series data GR0 and GR1 also represent the musical tone after the above multiplication. This indicates which of the four tone generation systems the data ST is assigned to.

As shown in FIG. 11, the initial frequency number data indicates the frequency number accumulated value at the start point when reading out the waveform data RD by sequentially accumulating the frequency number speed data FS, and the loop end data is: The frequency number cumulative value FA is indicated at the point where the accumulation of frequency number speed data FS is turned around from the addition direction to the subtraction direction, and the loop top data is the point at which the accumulation direction of the frequency number speed data FS is turned around from the subtraction direction to the addition direction. By loop-changing the frequency number accumulation value FA between the loop top and the loop end as shown in Fig. 11, the waveform data for half a waveform can be converted into a continuous waveform. It can be read out in the current state.

Note that the waveform return signal FDU in FIG. 11 is the most significant cut data of the frequency number cumulative value FA, and after the generation of the first half of one wavelength of the waveform data is completed, the generation of the second half of the waveform data is completed. The frequency number cumulative value FA is set to high level when the signal FDtJ is
Addition/subtraction calculation switching and glass-minus switching of the sample value (amplitude value) of the waveform data (musical tone data) are performed.

Envelope bell data EL in envelope 1 data
indicates the envelope cumulative value at the final point of each phase PHO~3 of the envelope waveform's acknowledge, decay sustain, and release, and the envelope addition/subtraction signal data EDU is obtained by adding the envelope cumulative value EA of each phase PHO~3. This indicates whether to increase or subtract. Further, the envelope speed data ES of the envelope data is data indicating the acceleration/deceleration of the envelope cumulative value EA of each phase PHO to 3, and the larger this value is, the larger the slope of the envelope waveform is. Envelope speed data ES and envelope bell data EL
is determined according to the key press speed of the keys on the keyboard 1 or the key touch data corresponding to the key press pressure.

The thin-out data TH in the envelope is data indicating the thinning rate of the latch for introducing the envelope cumulative value X1iffE A into the cumulative system of the envelope cumulative value EA of each phase PHO~3, The intake latch is performed once every repeated time slot for all channels.When this data is "11", there is no thinning, when it is "10", it is taken once every four times, and when it is "011", it is taken 16 times. When it is "00", it is taken in once every 64 times.Oll
indicates the low state, h, i g h state of the binary logic level. This thinning out (intake latch thinning) allows the envelope speed to be changed to 1x, 4x, 16x, and 64x even with the same envelope speed data. This thin-out data TH may also be changed according to the key press speed of the keys on the keyboard 1 or the key touch data corresponding to the key press pressure.

The modulation speed data MSPD of the modulation coefficient data is the first
As shown in Figure A (1), the data corresponds to the period of frequency modulation, and the modulation depth data MDEP is as shown in Figure 1A (
As shown in 1), there is data corresponding to the amplitude of frequency modulation, and phase speed data is data that determines the phase time of each of the four phases O to 3 of frequency modulation for one musical tone. As shown in Figure (2), the larger the value, the shorter the phase time. The interpolation selection signal data INP interpolates the modulation contents between one phase of frequency modulation and the next phase so that the frequency modulation changes continuously between each phase ('
IJ)-L (thus "0"), and Figure 1A (1) shows the state in which interpolation is being performed.
As the modulation waveform shown by the solid line in Figure 1A (1) approaches the next phase, it gradually changes to the modulation waveform shown by the broken line.If this interpolation is not performed, the modulation waveform For example, this is the case between phase (0), phase (1), and phase (2) in FIG. 1A (1).

The return signal data RET is! After kP and Phase 3, select whether to return to the beginning of Phase 2 and repeat Phase (2) and Phase (3) (“1”) or continue Phase 3 (ro, +). This is what we do. FIG. 1A (3) shows a state in which the return to phase (2) is repeated.

The start trigger selection signal data TRG selects a trigger signal to start frequency modulation, and this trigger signal includes a key-on event signal ON EVNT and a key-on summing signal ON S as shown in FIG.
There is UMM. Start trigger selection signal data TRG
The key-on event signal is selected with =O, and even when there are many keys that are operated simultaneously, frequency modulation starts at the on timing of each key, and the key-on summing signal is selected with start trigger selection signal data TRG = 1. is,
If all keys are being pressed, frequency modulation will not start even if another key is turned on.

The initial phase angle data (initial MSACC) is
As shown in Fig. 13, the phase angle of the modulation waveform at the start of frequency modulation is shown.
90 degrees, phase angle ±1 at 10 0000 0000s1
80 degrees, phase angle -9 at '11 0000 0000BJ
It becomes 0 degrees. Of course, it is possible to take an intermediate value between these values.

In this way, the ROM 20 stores a processing program for generating and emitting musical tones and musical tone data representing the content of musical tones, so only one memory is required to store the program and data, and the circuit The configuration can be simplified.

key assigner circuit 1i1830> FIG. 3 shows the key assigner circuit 30.
300 is a device that can operate only when the applied master clock signal φ (CK2) is at a high level, and the ROM2
0 data bus line and address bus line, when master clock signal CK2 is at high level "1", C
Data regarding the PU 300 flows, and when the low level is "0", data unrelated to the CPU 300 flows.

<ROM address control circuit 31) Address data CAO-15 for accessing the ROM 20 and various memories from this CPU 300 is 16-bit data, but the lower 11 bits excluding the least significant bit CA
L to 11 are provided to the selector 313. Also, the top 4
The 4-bit data "00001" is added to the upper part of bits CAL2-15, and the bits are sent to the ROM2 via the selector 313 as 19-bit address data together with the lower 11 bits CAL-11 through the B input of the selector 312.
0, and the processing program is mainly read. Furthermore, when the CPU 300 reads out tone data or other data other than the processing program, the CPU 300 outputs 8-bit MMU address data through the data bus line, which is then passed through the MMU latch 310 and the selector 312 to the lower 11 Bit C
It is added to AL~11 and sent to the ROM via the selector 313.
given to 20.

The first example shows the switching state of this address data.
6, although the address data of the ROM 20 is 19 bits, the address data of the CPU 300 is 16 bits, so adding roooooj or adding MM
U address data is added.

In this way, add the MMU address or "0000"
By adding , program reading and tone data reading can be easily switched, and the entire area of ROM 20 can be read even with a smaller number of bits than the read address data of CPU 300 or the read address data of ROM 20.

Therefore, bank "0" of ROM20 is set to M
You can access it directly without using MU U7CH 310,
Processing programs dedicated to the CPU 300 and the like are stored. Further, the CPU 300 may, for example,
To access address 3524HJ, MMU latch 3
If "13H" is set to 10 and '1524HJ is set as the address data of the CPU 300, the composite address data becomes '13524HJ' and the bank "1" is set to '13H'.
'3524HJ address will be accessed.

In this case, CPU300 address data '1524H'
The most significant 4 bits of “IHL” are canceled by the selector 312.

The upper 4-bit data CAl2-15 mentioned above are also given to the comparator 311, and the 4-bit f(x) data is also given to this comparator 311, and when the two data do not match, the upper 4-bit data is "0000". 4-bit address data CAl2-15 is selected. Further, when both data match, a match signal is given from the comparator 311 to the selector 312, and the MMU latch 310
is selected. Therefore, when the upper 4 bits of address data CAl2-15 do not match the f(x) data, the processing program etc. of the CPU 300 is read out, and when they do match, the timbre data etc. are read out. This f(X) data may be selected and set by the CPU 300, or may be a pre-fixed value.If this f(x) is fixed to "IH", the r
loo.

When the area for the MMU latch 310 of 'H'~'IFFFH4 is accessed and f(x) is fixed to '0 day',
RAM20 bank “01”0000HJ~’QFF
F+" area will be accessed.

The selector 313 is also given bank data read out by the CPU 300 from an assignment memory 320 (described later) and frequency number accumulation @FA12 to FA26 from the frequency number accumulator 40, and stored in the ROM 20 via the selector 313. The waveform data RD of the corresponding bank is read out. Data selection switching in the selector 313 is performed by the clock signal CK2 from the system clock generator 10, and as shown in the lower part of FIG.
The reading with the sample value of D is switched. Among these, at the timing of reading the processing program, the reading of the processing program and the reading of the timbre data are switched based on the f (x) data. Then, these readout processes are repeated for 16 channels.

Among the data read from the ROM 20, the waveform data RD is sent as is to the waveform data expansion interpolation circuit 50,
The processing program and tone color data are divided into two pieces of 8 bit data and sent to the CPU 300 via the selector 314 or to the assignment memory 320 via the gate buffer 323. Data selection switching in the selector 314 is performed based on the least significant bit CAO of the address data CA from the CPU 300.

This allows the ROM to follow the processing speed of the CPU 300.
Data is taken in from CPU 3.
The number of bits of data read from the ROM 20 is larger than the number of bits of the data bus line 00 (although data processing can be performed smoothly).

(Modulation calculation circuit 33) In the modulation calculation circuit 33, the modulation coefficient data in the timbre coefficient data corresponding to the specified timbre of the timbre switch 2 is -CP.
The modulation coefficient data, key data, and tablet data in the modulation calculation RAM 331 are first written into the modulation calculation RAM 331 by the U 300 , and then the modulation coefficient data, key data, and tablet data in the modulation calculation RAM 331 are read out in a time-division manner for each series by the CPU 300 .
After the modulation calculation is performed, the result is written into the modulation calculation RAM 331 again as modulation data, which will be described below. The modulation calculation data MDATA, which is the final result of this modulation data, is subjected to the calculation processing of modulation addition shown in FIG.
0 and frequency modulation is performed independently for each sequence. This "modulation calculation circuit 33" is a "modulation calculation processor", and if it is provided, modulation calculation can be performed at high speed, but even if it is not provided, this processing can be performed by a program in the CPU 300. This modulation calculation circuit 33
includes a modulation calculation RAM 33L and FIGS.
A circuit group and the like for performing modulation calculations as shown in FIG. 1 are provided.

FIG. 8 shows the modulation calculation RAM 331, and this RA
M331 has three series 0 out of the four series 0 to 3 mentioned above.
.about.2, a modulation coefficient, key data, tablet data, and modulation data are stored. The modulation coefficients correspond to the four phases (0) to 4 of the modulation waveform shown in Figure 1A (1) and (2).
(3) For each, modulation depth data MDEP, modulation speed data MSPD, phase speed data PSP
D, interpolation selection signal data INP, return signal data R
These data, which are composed of ET, start trigger selection signal data TRG, and initial phase angle data (initial MSACC), have already been described in the explanation of the timbre coefficient data of the RAM 20.

Key data and doublet data are key-on summing signal ON SUMM and key-on event signal ON
It consists of EVNT and tone number. The key-on summing signal ON SUMM and the key-on event signal ON EVNT are as already described in the explanation of the timbre coefficient data of the RAM 20, and are the signals shown in FIG.

The timbre number is data representing the timbre corresponding to the switch operated by the above-mentioned timbre switch 2.

Modulation data is phase speed accumulation data PSACC
It consists of 2 modulation speed accumulation data MSACC and 1 modulation calculation data MDATA. As shown in FIG. 1 (2), the phase speed cumulative data PSACC is cumulative data of the phase speed data PSPD, and indicates the elapsed time of each phase of modulation. The modulation speed accumulation data MSACC, as shown on the left in FIG. 1 (1), is the accumulation data of the modulation speed data MSPD, and indicates a passing point in one cycle of the modulation waveform. The modulation calculation data MDATA is data indicating the magnitude of the modulation degree at each time, and is the modulation waveform data MWAV described later.
This value is obtained by multiplying E by modulation depth data MDEP indicating the depth of modulation.

Of the above-mentioned series O to 2, series O is assigned to the upper keyboard of the keyboard, series 1 is assigned to the lower keyboard, and series 2 is assigned to the foot keyboard, and different tones and different modulation contents can be set for each keyboard. be. Of course, it may be possible to set different tones and different modulation contents for each channel.

In this way, a wide variety of modulation contents can be set using one modulation calculation circuit 33.

<CPU RAM 301> FIG. 9 shows part of the contents of the CPU RAM 301, including key-on signal KEYON, -N-number data KEY NO, cent data CENT, and series for musical tones assigned to each of the 16 channels. Data GR, aftertouch data, and initial touch data are stored for each channel as described above. Among these, channels CHO to 7 are assigned to series O, channels CH8 to CH14 are assigned to series 1, and channel CH15 is assigned to series 2.

The key-on signal KEY ON is signal data indicating that a key on the keyboard 1 is being pressed, and the key number data K is "1" when the key is on and "0" when the key is off.
EY No is data indicating a key number corresponding to the specified pitch of keyboard 1, and cent data is data indicating a fine pitch difference below the key number, and the frequency values corresponding to each data are shown in Figure 14. It is shown. As described above, the series data GR indicates which of the four musical tone generation systems the musical tone data ST after multiplication is to be assigned to. The aftertouch data is data indicating the key pressing pressure on the keyboard 1, and the initial touch data is data indicating the key pressing speed on the keyboard 1.

(Assignment Memory Circuit 32) FIG. 10 shows the stored contents of the assignment memory 320 of the assignment memory circuit 32. The assignment memory 320 has a memory area for tone data for 16 channels. , RO in each channel area
Tone data from M20 is set. In this case, the envelope data of the tone data to be set is EG.
The data is set in each envelope 1 group area of 0 to 15, and the other data is divided and set to each channel area of CHO and 15. The data set in CHO to 15 are bank data (A), CB), envelope group data (A), (B), and modulation key number data (
M KEY NO), modulated cent data (MC
ENT), key-on signal data, data length signal data D
816, sequence data GR, initial frequency number data, loop top data, and loop end data, among which variable p-t-number data (M KE
Y NO), modulated cent data (MCENT),
The data other than the envelope group data (A>(B)) is as described in the description of the storage contents of the ROM 20.

The modulation key number data and modulation cent data are the 15th
As shown in the figure, the above-mentioned key number data KEY N
o and cent data CENT are added and corrected by the above key number bias data and cent bias data according to the specified tone, and modulation data MDATA for realizing frequency modulation, which will be described later. The corresponding data is used as the cumulative step value of the read address data of the waveform data RD. This process is performed by the CPU 300, and for series 0 of channels O to 7, the modulation data of series 0 is used in the modulation calculation RAM 331, for series 1 of channels 8 to 14, the modulation data of series 1 is used, and for channel 15, the modulation data of series 1 is used. In series 2, the modulation data of series 2 is also used. Envelope group data (A> (B) is data indicating the address of envelope group area EGO~15 where envelope data corresponding to the tone of the channel area is stored, and the tone assigned to one channel is divided into two Since it consists of musical tones, (A>
CB). Correspondingly, since there are two waveform data RD, bank data (A>
(B) There will be two. The envelope data set in EGO~15 is also stored in the ROM20 mentioned above.
This is as explained in the explanation of the memory contents.

The above modulation key number data and modulation cent data are (
A) (B) Shared for two tones, keyboard 1
Two musical tones (A) and (B) are synthesized and output in response to one operation key.

These two musical tones (A) and (B) have different bank data or envelope group data, so they have different tones, and the envelope control is also performed separately.

The data read from the assignment memory 320 is sent to the frequency number accumulator 40, envelope 1 generator 60, etc. via the AMC assignment memory bus, or provided to the CPU 300 via the gate buffer 322. Additionally, 4-bit envelope group data (
Regarding A) and (B), the phase data PA from the envelope 1 generator 60 is added to the lower 2 bits through the latch 324, and "1" is added to the higher 1 bit, resulting in a total of 7 bits.
bit, and is given again to the assignment memory 320 via the selector 321, and the envelope level data EL, thin-out data TH,
Envelope speed data ES and the like are read out and sent to the envelope generator 60. Via this selector 321, read address data, which is a set of clock signals CK from the system clock generator 10, is also given to the assignment memory 320, as well as access address data from the CPU 300.

The reset circuit 303 resets the CPU 300 and the output latch 304 when the power is turned on.

Output latch 304.306 has tone switch 2
, the sampling address of the keyboard 1 is temporarily set, and the sampling results are input to the input buffers 305 and 307. Above output latch 3
Of the sampled data of 04, only 1 bit is the above D-
It is used as a gate signal for the A converter 100.

Modulation calculation circuit 33> Fig. 17 (1) and Fig. 18 (1) show the modulation calculation circuit 3
Figure 17 (1) shows the circuit part that calculates the phase speed accumulated data PSACC, and Figure 18 (
1) is a circuit portion that calculates modulation calculation data MDATA.

First, in FIG. 17 (1), the modulation calculation RAM 331
Each phase (
The phase speed data PSPD of 0) to (3) is the data PSP of the phase currently being executed by the selector 331.
D is selected, the adder 332 adds it to the phase speed accumulated data PSACC up to that point, and the OR gate group 3
39, and is outputted as phase speed accumulation data PSACC via an AND gate group 336.

FIG. 17 (2) shows the phase speed data PSPD and the phase speed accumulated data PSACC, where the 13-bit phase speed data PSPD is
4. The following accumulated phase speed accumulated data PSAC
C, and this phase speed accumulated data PSACC
As shown in Figure 1A (3), the most significant bit PAL becomes intermediary data indicating that repeated modulation of phases (2) to (3) is in progress, and the next two most significant bits are PA13.14 is the phase data that indicates the phase at that time, and "00" indicates the phase (0>,
“01” means phase (1), “10” means phase (2)
, 'ill becomes phase (3), and the next 4 and PA9 to PA12 are weighting data (Rate) when moving the phase.

In FIG. 17(1), the phase data PAL3.14 of the phase speed accumulated data PSACC is applied to the selector 331, and the phase speed data PSPD of the phase currently being executed is selected. When the carrier signal Cout is output from the adder 332, when the return signal data RET=rO,
From the OR gate group 339 via the AND gate 338,
11...1" is phase speed cumulative data PSAC
C and this state is maintained, as shown in Figure 17 (
As shown in (1) of 3), the final point of the final phase (3) is reached, and the modulation state at this point is maintained. Further, when the return signal data RET=rlJ, the upper side PA14 of the phase data is always set to "1" via the AND gate 340 and the OR gate, and as shown in FIG.
), as shown in (2), Phase '10 (2) J
rll(3)" is repeatedly selected. At this time, the phase speed accumulated data PSACC is obtained through the OR gate.
The most significant bit of the returning data PAL also becomes "1".

Key-on summing signal ON as explained in Fig. 12 above
Either SUMM or key-on event signal ON EVNT is selected by the start trigger selection signal TRG.
After selection by the selector 333, it is inverted by the inverter 334 and the AND gate group 336 is closed, thereby changing the phase speed accumulated data PSACC to "00...
・Set to the initial state of 0. This inverter 334
The inverted signal from is used as an initial signal CLK, which will be described later.

In FIG. 18 (1), from the modulation calculation RAM 331, C
The modulation speed data MSPD of each phase read by the PU 300 is such that the selector 351 selects the modulation speed data MSPD of the phase currently being executed, and the selector 350 selects the modulation speed data MSPD of the phase scheduled to be executed next. The modulation speed data MSPD of the phase currently being executed is sent to the multiplier 35.
The modulation speed data MSPD of the phase to be executed next is multiplied by the weighting data R by a multiplier 353 and is provided to the adder 356. Both data are added. By this addition in the adder 356, interpolation processing is performed between the modulation speed data MSPD of the phase currently being executed and the modulation speed data MSPD of the phase scheduled to be executed next.

The interpolated modulation speed data MSPD from the adder 356 is added to the modulation speed accumulation data MSACC up to that point in the adder 362, and is output via the selector 363 as the modulation speed accumulation data MSACC. The relationship between the modulation speed accumulated data MSACC and the modulation speed data MSPD is as shown in FIG. 18(2). The selector 363 selects initial phase angle data (initial M
SACC). The modulation speed accumulation data MSACC is given to the modulation waveform creation circuit 364, and each step data MWAVE of the modulation waveform data as shown in FIGS. 365.

Further, modulation depth data M D of each phase is read out by the CPU 300 from the modulation calculation RAM 331.
The modulation depth data MDEP of the phase currently being executed is selected by the selector 358, and the modulation depth data MDEP of the phase scheduled to be executed next is selected by the selector 357, and EP is the modulation depth data of the phase currently being executed. MDEP is multiplied by complement weighting data (1-R) in a multiplier 360 and given to an adder 361, and the modulation depth data MDEP of the phase scheduled to be executed next is
The weighting data R is multiplied by the multiplier 35 and the adder 3
61, and both data are added. This adder 3
By the addition in step 61, interpolation processing is performed between the modulation depth data MDEP of the phase currently being executed and the modulation depth data MDEP of the phase scheduled to be executed next.

Interpolated modulation depth data M from this adder 361
DEP is the multiplier 365 described above, and the modulated waveform data MW
AVB is multiplied by the modulated waveform data MWAVE having an amplitude corresponding to the magnitude of the modulated depth data MDEP,
Depending on the sign bit data of the most significant bit of the modulated waveform data MWAVE, the two's complement circuit 366 converts the modulated waveform data MWAVE as is or converts it into two's complement data to obtain the modulated calculation data MDA.
Output as TA.

The phase data PA13.14 of the phase speed cumulative data PSACC is the next phase creation circuit 3.
At 52, based on the return signal data PNXT,
Next phase data PNXT indicating the phase scheduled to be executed is created and given to the selector 350.357, and phase data PAL3.14 indicating the phase currently being executed is directly passed to the selector 351.35.
given to 8.

Further, the weighting data PA9 to PA12 of the phase speed accumulation data PSACC are generated by the multiplication coefficient control circuit 355 based on the interpolation selection signal data INP described in 1, and complement weighting data C1 indicating the weighting of the phase currently being executed.
-R) and weighting data R indicating the weighting of the phase to be executed next are created, and complement weighting data (1
-R) is applied to the multiplier 354.360, and the weighting data R is applied to the multiplier 353.359.

Modulation waveform creation circuit 364> (A) to (I) in FIGS. 19A and 19B show specific circuits of the modulation waveform creation circuit 364.
Each modulation waveform creation circuit 364 (B), (C), and (D) creates modulation waveform data MWAVE as shown in (a>(b), (c), and (d), respectively).

(A) Variable plate waveform creation time F! @364 first uses the “2” complement circuit 371 to output the modulation speed accumulated data MSACC.
The 2nd bit of the upper 2 bits changes the lower 8 bits to “2”.
'' into a complement value, and further converts the most significant bit and the lower 9 bits into a 2's complement value in a 2's complement circuit 372. Triangular waveform modulation waveform data MWAVE is obtained.

The modulation waveform creation circuit 364 in (B) is a modulation ROM 373.
Modulated waveform data MWAVE of various waveforms as shown in FIG. 19A (b) are stored in advance, and this is read out using modulation speed cumulative data MSACC as read address data.

(The modulation waveform creation circuit 364 of C1
(L) Modulation ROM 374.375.37 that stores modulation waveform data MWAVE with different waveforms for each of (2) and (3).
6.377 and these modulation ROM374.375
．． For 376.377, modulation speed accumulated data MS
ACC is given as read address data, and phase data PA of phase speed accumulated data PSACC is given.
Each bit of a 4-bit select signal obtained by decoding 13.14 by a decoder 378 is applied to each modulation ROM 374, 375, 376, and 377 as a chip enable signal CE. This allows, for example, the 19th
As shown in Figure A (c), different modulation waveforms can be obtained for each phase (0) to (3).

The modulation waveform creation circuit 364 (D) is the same as the modulation waveform creation circuit 364 (C1) that performs interpolation between each phase of the modulation waveform.

That is, modulation ROM374.375.376.377
is the same as that in (C), and each modulation ROM 374 to
Each modulated waveform data MWAVE read from the modulation speed accumulation data MSACC from the selector 377 is set as the modulated waveform data MWAVE of the next scheduled phase by the next phase data PNXT.
is selected, and the selector 380 selects the modulated waveform data MWAVE of the phase currently being executed based on the phase data PA13.14.

Among these, the modulation waveform data M of the phase scheduled to be executed next
WAVE is multiplied by the weighting data R in the multiplier 381 and given to the adder 383, and is also modulated waveform data M W A V E of the phase currently being executed.
is the complement typed data (1-R
) is multiplied and given to the adder 383, and both data are added. As a result, as shown in FIG. 19 (d3), interpolation is performed between the modulation waveform of the phase currently being executed and the modulation waveform of the phase scheduled to be executed next.

Note that the two's complement circuits 371, 372, and 366 can be composed of an exclusive OR gate group and an adder.

FIG. 20 (1) shows a specific circuit of the next phase creation circuit 352 in FIG. 18 (1) above, in which the phase data PA of the phase speed accumulated data
The lower data PA13 of 13.14 is input to the AfllT position (0) of the selector 391 via the Nant gate NAI, and is input to the A (Pl upper position (1)) of the selector 391 via the OR gate OR1. The data PA14 is inverted by the inverter INI and passed through the Nant gate NAI to the selector 391 A (II!I lower (
0), and is also input to the A(P!I upper part (1)) of the selector 391 via OR1.

As a result, the phase data PAL3.14 plus 1 is input to AflD of the selector 391, and when the phase data PA13.14 is "11", [111 is input as is, and as shown in FIG. ), when the phase of the modulated waveform reaches the final phase rlL(3>'', the next phase is also set to rll(3)'', as shown on the right side of FIG. 1(2),
Only the final phase is executed repeatedly.

This is the case where the return signal data RET=rO, the output of the NAND game) NA2 is always "11", and the A side of the selector 391 is always selected, but when the return signal data RET=r I J, Only when phase data PA13.14 is "11", selector 391
B-side rlo(2)' is selected. As a result, the second
As shown in (2) in Figure 1 (2), when the modulation phase reaches the final phase rll (3) 1, the next phase is set to "10 (2)" and as shown in Figure 1 (3). Then, phases (2) and (3) are repeatedly executed.

FIG. 21 shows a specific circuit of the multiplication coefficient control cycle 1% 356, in which the weighting data PA9-12 of the phase speed accumulation data PSACC are controlled by the AND gates AN2-
Through AN5, 'Oj is added to the 1st place and output as the weighted data R, and in addition, it is inverted by inverters fN2 to INS through AND gates AN2 to AN5, and '0' is added to the north position. + with adder 392
1 and the complement of r2j, which is output as the complement typed data (1-R3).

Example of Frequency Modulation> Figures 1B (A), (B), (C), and (D) show examples of frequency modulation, and examples of setting values for each data to realize this modulation waveform are shown below.

(A) Trumpet type modulation phase (0) Initial phase angle data: 0 Modulation speed data MSPD: Large value modulation depth data MDBP: Large value interpolation selection signal data INP
:0 Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Interpolation selection signal data INP: 0 Phase (2) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Sleeve selection signal data INP: 1 Phase (3) Modulation speed data MSPD: Medium value Modulation depth data MDEP: Medium value return signal data RBT
:0 Interpolation is not performed in phase (0)<1), but interpolation is performed in phase (2) and changes gradually.

(B) Auto vent type modulation phase (0) Initial phase angle data 300H (-90 degrees) Modulation speed data MSPD: 0 Modulation depth data MDEP: Medium value interpolation selection signal data INP: 1 Phase (1) Modulation Speed data MSPD: 0 Modulation depth data MDEP: 0 Interpolation selection signal data INP: 0 Phase (2) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Interpolation selection signal data INP: 1 Phase (3) Modulation speed data MSPD: Medium value modulation depth data MDEP: Medium value return signal data RET
:0 It is possible to start producing musical tones with frequency modulation applied at the start of phase (0).

(C) Glide type modulation Phase (0) Initial phase angle data.

300) 4 (-90 degrees) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Interpolation selection signal data INP: 1 Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: Medium value interpolation selection Signal data INP: 1 Phase (2), Phase (3) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Interpolation selection signal data INP: 1 Return signal data RET: 0 Phase (01 to Phase (1) ), the modulation speed accumulated data MSACC remains unchanged at the initial phase angle data r300+-z, and the modulation depth data MD
Since only EP increases, the modulation level gradually increases slowly.

(D> String modulation phase (0) Initial phase angle data 20 Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Interpolation selection signal data INP: 0 Phase (1) Modulation speed data MSPD; Q Modulation depth data MDEP :0 Interpolation selection signal data INP :1 Phase (2) Modulation speed data MSPD : Slightly small value Modulation depth data MDEP : Slightly large value Interpolation selection signal data INP : L Phase (3) Modulation speed data MSPD: Slightly large value Modulation depth Data MDEP: Slightly small value Interpolation selection signal Data INP: 1 Return signal data RET: 1 As a result, it is possible to obtain a complex modulation waveform in which the amplitude changes with the modulation speed and becomes larger or smaller.

Note that the size of the phase speed data PSPD is inversely proportional to the length of each phase illustrated in FIGS.

In this way, it is possible to sequentially vary the frequency of one musical tone in a wide variety of ways based on modulation coefficients that differ for each phase.

Frequency number accumulator 40> FIG. 4 shows the frequency number accumulator 40, in which the modulation key number data and modulation cent data from the assignment memory circuit 32 are sent via a latch 404 to the frequency number accumulator 40. Modulation key number data M KEY is given to ROM419 as read address data.
Frequency number speed data FS indicating a frequency value corresponding to No. and modulation cent data M CENT is read out. This frequency number speed data FS is sent to an adder 407 via an exclusive OR gate group 405.
It is accumulated in the frequency number cumulative value FA up to that point, and the top 8
Bits FA19 to FA26 are passed through the selector 413 to the lower 1
9-bit FA O~18 is passed through exclusive OR gate group 414,
Via the latch t\415 and the selector 416, it is again given to the adder 407 as the frequency number accumulated value FA. As a result, the frequency number accumulated value FA is accumulated at a speed corresponding to the size of the frequency number speed data FS. The waveform data RD is sent to the ROM address control circuit 31 and read out. Also, the upper 3 bits of the decimal part FA9-11
The waveform folding signal FDU of the most significant bit is sent to the waveform data expansion and interpolation circuit 50 and used for expansion and interpolation of the sample value of the waveform data RD.

Figure 22 shows the contents of such frequency number cumulative value FA, and the frequency number cumulative value FA is 28 in total.
The most significant bit is the waveform return signal FDU, and the next 8 bits FA19 to FA26 are comparator bits, which are used to compare whether or not the loop end and loop top, which will be described later, have been reached. 7-bit FA
12 to 18 are integer parts, the last 12 and FAO to 11
is the decimal part. Such frequency number speed data FS is for 16 channels from CHO to 15,
The frequency number accumulator 40 accumulates the frequency numbers, and the frequency number accumulation @FA of each channel is stored in the latch group 415. This latch group 415 consists of 16 latches, and the latches in which frequency number and speed data are accumulated are switched at the timing of the clock signal CK3, and reading from the latches is performed at the timing during one cycle of the tarlock signal CK3. Writing to the latch is performed at the last timing in the second half of the clock signal CK3. The same readout address (the same frequency number cumulative value FA12 to FA26) is set in each latch of this latch group 415 for the two musical tone components (A) and (B). The difference in tone color is based on the difference in bank data (A) and (B).

Furthermore, the 8-bit initial frequency number from the assignment memory circuit 32 is transferred to the selector 4 via a latch 406.
At step 16, 1 bit "0" is added to the upper part, 19 bits "00...0" are added to the lower part, and the data is selected as 28 bit data, which is the same as the frequency number cumulative value FA. The select signal in the selector 416 is an on-event signal output from the envelope 1 generator 60 at the key-on timing, and as shown in FIG. Speed data FS is accumulated.

Further, the loop end data and loop top data from the assignment memory circuit 32 are passed through a latch 402 and a selector 403 selects either the loop end or the loop top, and is applied to a comparator 409 and also to a selector 413. . Comparator 40
9, the frequency number cumulative value FA is compared with the upper 8 bits PA49 to PA26, and when the frequency number cumulative value FA exceeds the range between the loop end and the loop top, the selector 410 An overrun signal FCP is output and given to the exclusive OR gate group 414 and selector 413 via the OR gate 411, and the loop end data or loop top data is the upper comparator bit P of the frequency number cumulative value FA.
It is taken in as new data instead of A19 to A26.

At this time, in the exclusive OR gate group 414, the values of the integer part and the decimal part of the frequency number accumulated value FA up to that point are inverted plus or minus, but this means that the reading direction of the waveform data RD is set to the loop end or the loop top. When inverting with
This is to use the fraction of A as it is in a plus/minus inverted state to provide consistency in the inverted readout of the waveform data RD.

1. The overrun signal FCP is also given to the exclusive OR gate 412 to invert the waveform return signal PDtJ, which is the most significant bit of the frequency number cumulative value FA,
As a result, the value of the frequency number speed data FS in the exclusive OR gate group 405 is inverted plus or minus, and the frequency number accumulated value F in the adder 407 is inverted.
The direction of accumulation of A is switched to increase or decrease. FIG. 11 shows the state of loop reproduction for each half waveform by switching the frequency number speed data FS.

The above waveform return signal FDU is transmitted to selectors 403 and 410.
When frequency number speed data FS is added, the loop end data and the A<B detection signal are selected, and when subtracted, the loop top data and the A>8 detection signal are selected. The waveform return signal FDU is also input to the Cin terminal of the adder 407,
When frequency number speed data FS is subtracted, frequency number cumulative value FA is incremented by 1, and is also given to exclusive OR gate 408 . This exclusive OR gate 408 is also given an output signal from the Cout terminal of the adder 407, and it is detected that the frequency number cumulative value FA has overflowed or underflowed. is output as

Further, the bank data (A> (B) from the assignment memory circuit 32 is passed through the latch 400, and the selector 401 selects either (Al, (B)), and the bank data (A> (B) is sent via the latch 417. , together with the integer part of the frequency number cumulative value FA mentioned above, are sent to the ROM address control circuit 31, where the waveform data RD is read out.

As a result, although the two musical tone components (A>(B)) assigned to one channel have different bank data, a common cumulative frequency number value FA is used, and the timing of musical tone generation processing is synchronized. .

The clock signal CK3 from the system clock generator 10 is used as the select signal of the selector 401,
The musical tone generation process for (A) is performed in the first half of this clock signal CK3, and the musical tone generation process for (B) is performed in the second half. System clock generator 10
The clock signal group CK from the latch 400.40
2.404.406.415.417.418 is also given as a latch signal to synchronize the channel period and timing.

The present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the present invention.9 For example, in addition to setting modulation information with the tone switch 2, the modulation information can be set using the numeric keys and the numeric display section. Speed data PSPD, modulation speed data MSPD.

Modulation depth data MDEP, modulation waveform data MWAVE
, interpolation selection signal data INP, return signal data RE
T, etc. may be set individually, and the shape of the modulation waveform may be not only the above-mentioned periodic waveform or linear waveform, but also a random shape using a random number generator, and the modulation information may be an envelope level or time. It may be changed based on changing data, or may be changed based on aftertouch data, initial touch data, selected rhythm, set tempo, or set volume. In this case, each value is sequentially modulated by RA.
It is sufficient to perform addition, subtraction, multiplication, and division on each data in M331.

[Effects of the Invention] As detailed above, according to the present invention, a plurality of pieces of modulation information for changing the reading speed of musical waveform data or basic waveform data are stored in advance, and the musical waveform data is adjusted based on this modulation information. By changing the readout speed, etc., one modulation device can store multiple pieces of modulation information corresponding to changes in timbre, tone length, etc., or changes in one musical effect, and can produce a wide variety of different musical tones. It is possible to easily realize modulation contents that are 'Ik-a' in the state.

[Brief explanation of the drawing]

1A and 1B are diagrams showing the contents and specific examples of modulation waveforms, FIG. 2 is an overall circuit diagram of the electronic musical instrument, and FIG.
4 is a circuit diagram of the key assigner circuit 30, FIG. 4 is a circuit diagram of the frequency number accumulator 40, and FIG. 5 is a circuit diagram of the ROM
FIG. 6 is a diagram showing the memory contents of the RAM 20, and FIG. 6 is address mapping regarding the CPU 300 other than the RAM 20,
FIG. 7 is a diagram showing the contents of timbre coefficient data, and FIGS. 8, 9, and 10 are diagrams showing the modulation calculation RAM 331, CPt
11 is a diagram showing the contents of the JRAM 301 and the assignment memory 320, FIG. 11 is a diagram showing the read state of waveform data RD, and FIG. 12 is a diagram showing the state of reading the waveform data RD.
EVENT and key-on summing signal ON SU
FIG. 13 is a time chart diagram showing the relationship between MM and the start of modulation control, and FIG.
FIG. 14 is a diagram showing a specific example of key number data and cent data, and FIG. 15 is a diagram showing the relationship between key number data KEY No. and cent data. Data CENT, modulation calculation data MDATA, key number bias data (KEY No bias), cent bias data (CENT bias), modulation key number data M
KEY No. and Modulated Cent Data M CENT
FIG. 16 is a diagram showing the correspondence between address data of the CPU 300 and address data of the ROM 20, and FIGS. 17 and 18 are diagrams showing the relationship between the address data of the CPU 300 and the address data of the ROM 20.
! FIG. 19A and FIG. 19B are circuit diagrams of the modulation waveform generation circuit 364 and diagrams showing examples of modulation waveforms, and FIG. 20 is the circuit diagram of the next phase generation circuit 352.
FIG. 21 is a circuit diagram of the multiplication coefficient control circuit 356, and FIG. 22 is a diagram showing the contents of the frequency number cumulative value FA. 33... Modulation calculation circuit, 331... Modulation calculation RAM
, 352...Next phase creation circuit, 355...
・Multiplication coefficient control circuit, 364...modulation waveform creation circuit,
366.371.372..."2" complement circuit, 37
3.374.375.376.377...Modulation R0M
.

Claims (1)

[Claims] 1. Waveform storage means for storing the level of each step of musical waveform data or basic waveform data; waveform reading means for sequentially reading each step level of the waveform data from the waveform storage means; readout speed setting means for setting a readout speed of waveform data of the waveform reading means; a modulation information storage means for storing a plurality of pieces of modulation information for changing the readout speed of waveform data of the waveform reading means; Modulation information reading means for reading modulation information from the storage means, and readout speed control means for changing the readout speed of the waveform data set by the readout speed setting means based on the modulation information read by the modulation information readout means. A musical tone frequency modulation device for an electronic musical instrument, characterized by comprising: 2. The modulation information reading means is means for reading out a plurality of pieces of modulation information, and the readout speed control means reads the waveform data set by the readout speed setting means based on the readout plurality of modulation information. 1. A musical tone frequency modulation device for an electronic musical instrument, characterized in that the device is a means for sequentially changing the readout speed of a musical tone. 3. A waveform storage means for storing the level of each step of musical waveform data; a waveform reading means for sequentially reading each step level of the waveform data from the waveform storage means; and setting a reading speed of the waveform data of the waveform reading means. a readout speed setting means; a modulation information storage means for storing a plurality of pieces of modulation information for changing the readout speed of waveform data of the waveform readout means; and a modulation information readout for reading modulation information from the modulation information storage means. a weighting means for weighting arbitrary two pieces of modulation information of the plurality of modulation information read out by the musical tone information reading means; weighting shifting means for shifting the weighting to the other side; and readout control means for sequentially changing the reading speed of the waveform data set by the reading speed setting means based on the modulation information whose weighting is shifted by the weighting shifting means. A musical tone frequency modulation device for an electronic musical instrument, characterized by comprising: 4. Waveform storage means for storing the level of each step of musical waveform data or basic waveform data; waveform reading means for sequentially reading each step level of the waveform data from the waveform storage means; and reading of the waveform data of the waveform reading means. A readout speed setting means for setting a speed; and a modulation information storage means for storing a plurality of pieces of modulation information for changing the readout speed of waveform data of the waveform readout means; A modulation information reading means for reading; a change time storage means for storing a change time at which the change information is executed for each of the plurality of change information read out in the change information reading; and a change time is read from the change time storage means. A change time readout means: Based on the plurality of modulation information read by the modulation information readout means, the readout speed of the waveform data set by the readout speed setting means is sequentially changed, and the change time readout means 1. A musical tone frequency modulation device for an electronic musical instrument, comprising readout speed control means for switching changes in the readout speed of each waveform data at a time corresponding to a readout change time. 5. Waveform storage means for storing the level of each step of musical waveform data or basic waveform data; waveform reading means for sequentially reading each step level of the waveform data from the waveform storage means; and reading of the waveform data of the waveform reading means. A readout speed setting means for setting a speed; and a modulation information storage means for storing a plurality of pieces of modulation information for changing the readout speed of waveform data of the waveform readout means; a modulation information reading means for reading; a repetition output means for repeatedly outputting only specific modulation information among the plurality of modulation information read by the modulation information reading means; and a plurality of modulation information read by the modulation information reading means. readout speed control means for sequentially or repeatedly changing the readout speed of the waveform data set by the readout speed setting means based on modulation information and specific modulation information repeatedly output from the repeating output means; Characteristic musical tone frequency modulation device for electronic musical instruments. 6. Claim 1, wherein the modulation information stored in the modulation information storage means is information indicating a modulation speed.
, 2, 3, 4 or 5, the musical tone frequency modulation device for an electronic musical instrument. 7. Claim 1, wherein the modulation information stored in the modulation information storage means is information indicating the depth of modulation.
, 2, 3, 4 or 5, the musical tone frequency modulation device for an electronic musical instrument. 8. The musical tone frequency modulation device for an electronic musical instrument according to claim 6 or 7, wherein the modulation speed or the modulation depth changes periodically. 9. The musical tone frequency modulation device for an electronic musical instrument according to claim 6 or 7, wherein the modulation speed and the modulation depth are periodically changed in synchronization with each other. 10. Phase information storage means for storing phase information at the start of a periodic change in the modulation speed and modulation depth; a phase information reading means for reading phase information from the phase information storage means; Claim 8 or 9 further comprising modulation starting means for starting periodic changes in modulation speed and modulation depth at a phase corresponding to the phase information read out by the information reading means. A musical tone frequency modulation device for an electronic musical instrument as described in . 11. The musical tone frequency of an electronic musical instrument according to claim 6 or 7, wherein the modulation information storage means stores information representing a temporal change in modulation depth at a large number of step levels. Modulator.