JP3062569B2 - Electronic musical instrument frequency modulation device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical tone frequency modulation device for an electronic musical instrument that performs frequency modulation by changing the generation speed of waveform data, and particularly relates to a tone pitch or a sound emitting operation state. The present invention relates to an improvement in changing a state of frequency modulation.

[Summary of the Invention] The present invention provides a musical tone frequency modulation device that changes a generation speed of waveform data based on a plurality of pieces of modulation information, by changing a frequency modulation state according to a pitch or a sound emitting operation state. Modulation contents optimal for each performance state are realized in a wide variety of ways with a small amount of modulation data.

[Prior Art] Conventionally, as such a musical tone frequency modulation device for an electronic musical instrument, the present applicant has filed an application for performing frequency modulation by changing the generation speed of waveform data (Japanese Patent Application No. 1-22883).
(JP-A-2-203394). This is because a plurality of pieces of modulation information for changing the reading speed of the waveform data are stored in advance,
The reading speed of the musical tone waveform data is changed based on the modulation information. According to this, it is possible to store a plurality of pieces of modulation information according to a change in tone color, tone length, and the like, or a change in one musical effect, with one modulation device, and it is possible to freely change the modulation content quite widely. The modulation content can be changed according to the timbre, the tone length, etc. In addition, all musical effects by frequency modulation can be realized with one modulation device, and the optimum modulation content for each musical tone can be easily obtained. Obtainable.

[Problems to be Solved by the Invention] According to the present invention, the tone frequency modulation apparatus can change the frequency modulation state according to the pitch or the sound emitting operation state, thereby changing the modulation content considerably widely. It is another object of the present invention to provide a musical tone frequency modulation device for an electronic musical instrument that can realize all musical effects by frequency modulation with one modulation device and can easily obtain optimum modulation content for each performance.

[Means for Solving the Problems] In order to achieve the above object, according to the present invention, a plurality of pieces of modulation information for changing the generation speed of waveform data are stored in advance, and the pitch or emission of the plurality of pieces of modulation information is stored. A sound operation state, for example, a key depression state is output, and the generation speed of waveform data is changed based on the output modulation information.

Here, the waveform data is used for musical sound data such as musical instruments such as pianos, violins, and drums, and for human voices, which are waveform data of sounds in the natural world, or used for real-time sine synthesis, FM sound sources, PD sound sources, and the like. , Sine waves, triangular waves, rectangular waves, sawtooth waves, and other basic waveform data, and all other waveform data that are elements of musical sounds. The pitch is a broad concept including a range indicating a plurality of pitch groups.

[Operation] With the above configuration, a single modulation device can output a plurality of pieces of modulation information according to a pitch or a sound emitting operation state, and can easily and optimally perform various kinds of modulation contents according to various performance states. Can be realized.

Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings.

1. Overall Circuit FIG. 2 shows an overall circuit diagram of the present invention. Each key of the keyboard 1 and each switch of the tone switch 2 are scanned by a key assigner circuit 30 and have a pitch corresponding to an operation key. A tone of a tone corresponding to the operation tone switch is assigned to an empty channel of the 16 tone generation system.
This channel assignment content is stored in the assignment memory circuit 32. The keyboard 1 instructs the emission of musical tones, and may be replaced with a stringed instrument, a wind instrument, a percussion instrument, an organ-type instrument, or the like.

The key press pressure of each key of the keyboard 1 is detected by a pressure sensor provided for each key, and is converted into digital after-touch data indicating the key press pressure by an AD converter, which will be described later. Sent to CPU 300. Further, the key pressing speed of each key of the keyboard 1 is detected by a detection circuit as selection initial touch data indicating a shift time of the on-timing of a plurality of step switches provided for each key, and is sent to a CPU 300 described later.

The ROM 20 stores a processing program for generating a tone signal, timbre data relating to waveforms and envelopes, the waveform data RD itself, and the like.A read address is controlled by a ROM address control circuit 31, and the processing program or timbre is stored. Switching between data reading and waveform data RD reading is switched. The processing program read from the ROM 20 is stored in a CPU 300 (described later) of the key assigner circuit 30.
Are sent to the ROM 20, and the timbre data relating to the waveform and the envelope read out from the ROM 20 are written in the area corresponding to the empty channel of the assignment memory circuit 32, and further read out from the ROM 20. The waveform data RD itself is the waveform data expansion interpolation circuit 50
Sent to. The assignment memory circuit 32 stores frequency number speed data corresponding to operation keys of the keyboard 1.
FS is also written in the area corresponding to the empty channel.

The frequency number speed data FS is sequentially accumulated for each channel by the frequency number accumulator 40, is given to the ROM 20 via the ROM address control circuit 31 as read address data, and the waveform data RD is the frequency number speed data FS. , Ie, at a speed corresponding to the pitch, and is input to the waveform data decompression interpolation circuit 50. A large number of waveform data RD to be read are stored in the ROM 20, and these selections are made by bank data read from the assignment memory circuit 32. In the waveform data decompression interpolation circuit 50, the ROM 20
The difference data thus read out is expanded, and an interpolation point between sample point points of each waveform data RD is also obtained and sent to the multiplication circuit 70. This interpolation is performed using a part of the frequency number accumulated value FA from the frequency number accumulator 40.

The data on the envelope from the assignment memory circuit 32 is sent to the envelope generator 60 to generate an envelope waveform, which is sent to the multiplication circuit 70. The multiplication circuit 70 multiplies each sample value of the above-described expanded interpolation waveform data IP by each sample value EA of the envelope waveform, performs data shift in the shift circuit 80, and accumulates each sequence in the sequence accumulation circuit 90. The sound is output from the sound system 110 via the DA converter 100.

The current phase value PH of the envelope waveform is sent from the envelope generator 60 to the assignment memory circuit 32, and acts to output envelope data for the next new phase. Further, the ON signal is delayed from the envelope generator 60 to the frequency number accumulator 40 at the key-on timing, and accumulation of the frequency number speed data FS is started. Further, a data length signal D816 is sent from the envelope generator 60 to the waveform data decompression interpolation circuit 50, and selection is made whether interpolation of the waveform data RD is performed or not. The data length signal D816 indicates whether the waveform data RD is made up of two 8-bit sample values or a 10-bit sample value and 6-bit difference data. Is read out, interpolation of the waveform data RD is performed.

The shift circuit 80 shifts down the multiplied musical tone data in accordance with the magnitude of the envelope power data EA12 to 15, which are the upper bits of the envelope accumulated value EA, and exposes the fall when the decay and release decay. The purpose is to make the sound characteristics similar to natural sounds.

In the DA converter 100, four tone generation systems are formed in a time-division manner. In the sequence accumulation circuit 90, any of the generation systems is set in accordance with the sequence data GR from the assignment memory circuit 32. It is determined whether or not the musical sound data is to be sent. The sequence accumulator circuit 90 includes a frequency number accumulator.
From 40, a waveform return signal FDU is also given, and this waveform return signal FDU goes to a high level when the generation of the first half of one waveform of the waveform data is completed, and the generation of the second half of the waveform is started, Thereby, in the sequence accumulation circuit 90,
This is a value obtained by inverting the musical tone data by plus or minus. In addition, the key is assigned to the series accumulation circuit 90 by the key assigner circuit 30.
A -A gate signal is also supplied, and the output of musical sound data to the DA converter 100 is controlled.

From the system clock generator 10, each circuit 30 in FIG.
40, 50, 60, and 90 include various clock signals CK1, CK2, CK3, CK4, etc. having a cycle of 1: 2: 4: 8, and the like, and their divided, logical sum, and logical product. , And the timing of each circuit is controlled.

2.ROM20 Fig. 5 shows the storage contents of ROM20.
Is divided into 16 bank areas "0" to "15",
Each bank area has an address of “0000 _H ( _H is a symbol indicating a hexadecimal value)” to “FFFF _H ”, and “0000 _H ” to “0FFF _H ” of the bank “0” are the CPU 300 CPU RAM30 for
1, the assignment memory 320, a use area, such as a modulation operation RAM 331, "1000 _H" - "1FFF _H" is the use area of the MMU latch 310 to be described later, to "2000 _H" ~ "FFFF _H" musical tone A processing program for generating a signal is stored. Bank "1", the "0000 _H" - "3FFF _H" is timbre coefficient data for selecting and determining the content of the waveform and envelope are 128 tone content storage.

From "4000 _H " of bank "1" and after "F" of bank "15"
Up to FFF _H, (A) and (B) two pieces of tone waveform data RD read out with one selected tone color for each bank are stored at the same address. The musical sound waveform data RD is used for musical sound such as musical instrument sounds such as piano, violin, and drum, and the sound of human voices, and is used for real-time sine synthesis, FM sound source, PD sound source, and the like. Sine wave,
In addition to basic waveform data representing basic waveforms such as triangular waves, rectangular waves, and sawtooth waves, noise sound waveforms, etc., as well as waveforms that combine these, each frequency component corresponding to a spectrum group of multiple specific frequency bands corresponding to specific formants A plurality of types of synthesized waveforms or the like may be used, a PCM waveform using a loop top, a loop end, or the like may be used, and any waveform data serving as a tone element may be used.
The storage area of the timbre data is located at a position shifted from the storage area of the processing program by the MMU address data described later.

FIG. 6 is, the bank of "0" and "0000 _H" - "0FFF _H"
Shows the detailed contents of the area, "0000 _H" - "0FF
Of F _H "," 0000 _H "~" 07FF _H "is the area used for CPU RAM 301," 0800 _H "~" 08FF _H "is the area used for the assignment memory 320," 0900 _H "~" 09FF _H "the area used for modulation operations RAM 331," 0A00 _H "-" 0EFF _H "is not used," 0F00 _H "-" 0FFF _H "is the area used for the interface between the circuits. Of these, "0F00 _H " to "0
F0F _H "is the input buffer 307 in the keyboard 1 to be described later, is the use area of the interface, such as output latch 306," 0F10 _H "-" 0F1F _H "is the input buffer 30 in the tone color switch 2 again later
5, a used area of the interface, such as output latch 304, "0F20 _H" - "0F2F _H" is also later
Is the use area for the MMU latch 310, "0F30 _H" - "0F3
“F _H ” is also a use area for a timer 302 described later, and “0F40 _H ” to “0FFF _H ” are not used.

FIGS. 7A (1) and 7B (1) show the contents of the above-mentioned timbre coefficient data. One timbre has four data of key scaling 0, 1, 2, 3 and one modulation. Consists of coefficients and Key scaling 0, 1, 2,
Numeral 3 divides the keyboard 1 into four ranges, and realizes a tone corresponding to keyboard scaling such as changing harmonic components or noise components or changing an envelope waveform according to this range, so that even one tone can be further finely divided. It is stored to change the tone content. The modulation coefficient is 1
This data is for subtly changing the tone frequency during the emission of one tone to realize a tone that is more natural.

The timbre coefficient data of the waveforms 0 to 3 of the key scaling 0 to 3 include those for the tone waveform and those for the envelope. The timbre coefficient data for the tone waveform includes bank data and key number bias data. (KEY NO bias), cent bias data (C
ENT bias), data length signal data D816, sequence data GR, initial frequency number data, loop top data, and loop end data. With regard to the tone color coefficient data for the envelope, two envelopes (A) and (B) are selected for one tone color assigned to one channel. The (A) and (B) two envelope data respectively include, for example, four phases PH0, PH1, PH2, and P of attack, decay, sustain, and release.
Each exists for H3. The envelope data for each phase further includes envelope level data EL,
Envelope adjustment signal data EDU, thin out data T
H, consisting of envelope speed data ES. The timbre coefficient data for the modulation coefficient includes modulation speed data MSPD, modulation depth data MDEP, phase speed data PSPD, key scale selection signal data KS, key touch selection signal data KT, initial after selection signal data I /
A, return signal data RET, start trigger selection signal data TRG, initial phase angle data (initial MSACC)
Is made up of

The bank data is used to select and designate one of the 15 types of tone waveform data RD, and two waveforms (A) and (B) are selected for one tone assigned to one channel.

The key number bias data is bias data that is added to or subtracted from the pitch specified by the keyboard 1 in order to achieve the pitch specified by the keyboard 1 with respect to the reference foot range (pitch) of the tone color coefficient data. For example, if the timbre coefficient data is based on 4 feet and the tone waveform data RD is based on 8 feet, if the key number bias data is "12 (0001100 _B ( _B is a symbol indicating a binary number))", By increasing the octave by one octave, the foot range of the musical tone waveform data RD can be matched with the foot range of the timbre coefficient data. Also, the timbre coefficient data
When the reference is 16 feet, the key number bias data is set to “−12 (1110100 _B )” and the octave is lowered by one octave so that the foot range of the musical tone waveform data RD matches the foot range of the timbre coefficient data. This value of "12" corresponds to the pitch number of one octave, and if the foot range difference is one octave or less, the key number bias data is also "12" or less.

If the foot range difference is equal to or less than the integer value of one pitch difference, the fractional value smaller than the integer value is the cent bias data, where 100 cents are 64 bits of 6-bit data. It can now be shifted by 100/64 ≒ 1.56 cents. The values of these key number bias data and cent bias data are determined on the same basis as the key number data and cent data of FIG.

The data length signal D816 indicates whether the waveform data RD is composed of two 8-bit sample values or a 10-bit sample value and 6-bit difference data, as described above. As described above, 1 also indicates to which of the four tone generation systems the tone data ST after the multiplication is assigned.

The initial frequency number data, as shown in FIG. 11, indicates the frequency number accumulated value at the start at the time of sequentially accumulating the frequency number speed data FS and reading out the waveform data RD, and the loop end data is: Indicates the frequency number accumulated value FA at the point where the accumulation of the frequency number speed data FS is turned from the addition direction to the subtraction direction, and the loop top data is the point where the accumulation direction of the frequency number speed data FS is turned from the subtraction direction to the addition direction. In FIG. 11, the frequency number accumulated value FA is loop-changed between the loop top and the loop end as shown in FIG. It can be read in the state.

Note that the waveform folded signal FDU in FIG. 11 is the most significant bit data of the frequency number accumulated value FA, and the generation of the first half wavelength of one wavelength of the waveform data is completed. When the signal FDU is at the high level, the switching of the addition / subtraction operation of the frequency number accumulated value FA and the plus / minus switching of the sample value (amplitude value) of the waveform data (tone data) are performed based on the signal FDU.

Envelope level data in envelope data
EL indicates the accumulated value of the envelope at the final point of each of the phases PHO to 3 of the ACK, DECAY, SUSTAIN, and RELEASE of the envelope waveform. It indicates whether to perform the subtraction or the subtraction. The envelope speed data ES of the envelope data is the accumulated value EA of the envelope of each phase PHO-3.
The data indicates the acceleration / deceleration of the envelope waveform. The larger the value, the larger the slope of the envelope waveform. The envelope speed data ES and the envelope level data EL are determined according to the key pressing speed of a key of the keyboard 1 or key touch data corresponding to the key pressing pressure.

The thin-out data TH in the envelope is data indicating the thinning rate of the latch that takes in the accumulated value EA of the envelope accumulated value EA into the accumulation system of the accumulated value EA of the envelope of each phase PHO to 3, and the original envelope accumulated value. The latching of the EA is performed once in the time slot for all the channels that is repeatedly performed. When this data is "11", there is no thinning out.
In the case of "1", take in once in 16 times, in the case of "00", take out one in 64
Take in the times. 0, 1 is the low state of the binary logic level, hig
This shows the h state. By this thin-out (taking-in latch thinning), the envelope speed can be changed to 1, 4, 16, or 64 times with the same envelope speed data. This thin-out data TH may also be changed in accordance with the key pressing speed of the key of the keyboard 1 or the key touch data corresponding to the key pressing pressure.

The modulation speed data MSPD of the modulation coefficient data is data corresponding to the frequency modulation period as shown in FIG. 1A (1), and the modulation depth data MDEP is the frequency as shown in FIG. 1A (1). There is data corresponding to the amplitude of the modulation, and the phase speed data PSPD is data for determining the respective phase times of the four phases 0 to 3 of the frequency modulation for one tone, as shown in FIG. 1A (2). In addition, the larger the value, the shorter the phase time.

The key scale selection signal data KS is used to select whether the frequency modulation content is changed (“1”) or not (“0”) according to the key scale content. Accordingly, the modulation speed data MSPD, the modulation depth data MDPE, and the phase speed data PSPD of the frequency modulation can be changed.

The key touch selection signal data KT is used to select whether to change the frequency modulation content (“1”) or not (“0”) in accordance with the key touch content. Modulation speed data MS of frequency modulation according to initial touch) and strength (after touch)
PD, modulation depth data MDPE, phase speed data PS
PD can be changed.

The initial after-selection signal data I / A uses the initial touch data (key pressing speed) IKT as the key touch data KTD or the after touch data (key pressing) when the frequency modulation content is changed according to the key touch content. Pressure) to select whether to use AKT. As a result, the phases 0, 1, and 2 shown in FIG. 1A and FIG.
Of the two or three, the first phase may use the initial touch data IKT, and the later phase may use the after touch data AKT.

After the final phase 3 ends, the return signal data RET returns to the beginning of the phase 2 and repeats the phases (2) and (3) (“1”) or continues the phase 3 (“1”). 0 "). FIG. 1A (3) shows a state in which the return up to the phase (2) is repeatedly performed.

The start trigger selection signal data TRG selects a trigger signal for starting frequency modulation, and includes a key-on event signal as shown in FIG.
There are ON EVNT and a key-on summing signal ON SUMM.
When the start trigger selection signal data TRG = 0, the key-on event signal is selected, and even when there are many simultaneously operated keys, frequency modulation starts at the on-timing of each key. Also, the start trigger selection signal data TRG = 1
When the key-on summing signal is selected and there is a key that is already being pressed, the frequency modulation is not started even if another key is turned on again.

Initial phase angle data (initial MSACC) is the first
As shown in Fig. 3, the phase angle of the modulation waveform at the start of frequency modulation is indicated by "00 0000 0000 _B " and the phase angle is ± 0.
Degrees, "01 0000 0000 _B ", phase angle + 90 degrees, "10 0000
0000 _B "results in a phase angle of ± 180 degrees, and" 11 0000 0000 _B "results in a phase angle of -90 degrees. Of course, it is also possible to take an intermediate value between these values.

As described above, since the ROM 20 stores the processing program for generating and emitting a musical tone and the musical tone data representing the content of the musical tone, only one memory for storing the program and the data is required, and the circuit The configuration can be simplified.

Memory contents of "74 _H" address - "7F _H" address is different exits Figure 7A (1) and Figure 7B (1). This is the 7A
The figure shows the key scale data KSD
FIG. 7B shows an example in which the content of frequency modulation is modified based on the key table and key touch data KTD.
This is because an example is shown in which the content of frequency modulation is corrected based on the key scale data KSD and the key touch data KTD based on data read from the S) (ROM) 231 and the touch table (KT) (ROM) 235.

Such arithmetic processing or reading from the tables 231 and 235 is performed by directly converting the key scale data KSD and the key touch data KTD into the modulation speed data MSPD, the modulation depth data MDEP and the phase speed data PSPD.
This is for realizing a musical tone closer to a natural sound when multiplying by. Of course, the key scale data KSD and the key touch data KTD may be directly multiplied as they are.

Figure 7A (1) of the aforementioned "74 _H" address - "7F _H" slope data SLOPE stored at the address, the bias data BIA
S is coefficient data of the above-described arithmetic processing. Such coefficient data is modulated speed data MSP for each of key scale data KSD and key touch data KTD.
D, Modulation depth data MDEP and phase speed data P
It is stored for each SPD. The coefficient data has different values for different timbres, but may be the same. The most significant bit of the slope data SLOPE indicates plus or minus of the data. The expression of this arithmetic processing is that the key scale data KSD is f (S), and the key touch data KTD is j
Assuming that (T), g (S) = SLOPE (KS) × f (S) + BIAS (KS) k (T) = SLOPE (KT) × j (T) + BIAS (KT)

FIG. 7A (2) shows these equations in a graph. The modulation speed data MSPD increases as the input key scale data f (S) and the input key touch data j (T) increase, but the modulation depth data MDEP and the phase speed data PSPD decrease conversely. In addition, by this arithmetic processing, the width of the possible values of the output key scale data g (S) and the output key touch data k (T) after the conversion is:
It becomes narrower than the range of possible values of the input keysur data f (S) and the input key touch data j (T).

These arithmetic expressions are the same for the key scale data KSD and the key touch data KTD for the modulation speed data MSPD, the modulation depth data MDEP, and the phase speed data PSPD, but may be different. Also, the arithmetic expressions may not be temporary functions but may be more complicated expressions, and all the arithmetic expressions may be the same or may be different expressions.

FIG. 7B (1) of the aforementioned "74 _H" address - "7F _H" table number stored in the address data TBL NO. Indicates the number of the table in the reading of the tables 231 and 235 described above. As shown in FIG. 7B (2), the tables 231 and 235 are composed of 64 table groups, and these table groups correspond to each of the above-mentioned 64 tones, and the table number data TBL NO. Specifies this.
Of course, these tables may be common to each tone.

The modulation speed data MSPD increases as the input key scale data f (S) and the input key touch data j (T) increase, but the modulation depth data MDEP and the phase speed data PSPD decrease conversely. These tables
231 and 235 are the same for the key scale data KSD and the key touch data KTD for the modulation speed data MSPD, the modulation depth data MDEP and the phase speed data PSPD, respectively, but may be different. The data contents of the tables 231 and 235 are not limited to those shown in FIG. 7B (2), and the data contents of each table may be the same.

3. Correction Circuit 200a (200b, 200c) FIGS. 7A (3) and 7B (3) show a correction circuit 200a for correcting the content of frequency modulation based on the key scale data KSD and key touch data KT described above. (200b, 200c)
It is shown.

The correction circuits 200a, 200b, and 200c are incorporated in three places in the modulation operation circuit 33 that performs the modulation operation shown in FIGS. And the modulation speed data MSP
D, Modulation depth data MDEP, Phase speed data PSP
D is corrected according to the key scale data and the key touch data.

In FIG. 7A (3), the modulation speed data MSPD is
The multiplier 210 multiplies the converted key scale data g (S), and performs correction according to the key scale data KSD. Next, the conversion key touch data k
(T) is multiplied, corrected according to the key touch data KT, and output.

In FIG. 7A (3), the input key scale data KSD and key touch data KTD are selected key scale data SKS, selected initial touch data SIKT, and selected after touch data SAKT.
Words have been added. This indicates that one value is selected from the key scale data KSD and the key touch data KTD of a plurality of keys that are simultaneously pressed. Specifically, select key scale data
The SKS is an average of the lowest key number and the highest key number among the pitches (key numbers) of currently assigned musical tones. Also, select key touch data
SKT is the maximum value of the music currently being played. Of course, other values such as bass priority, treble priority, back-push priority, and first-push priority may be used. These selection processes are executed by the CPU 300. Note that the content of the frequency modulation may be corrected for each of the musical sounds being played, based on the key scale data KSD and the key touch data KTD, by time division processing.

The selected key scale data SKS is input to the function generator 211 via the selector 212. The function generator 211 is also provided with the above-described slope data SLOPE (KS) and the bias data BIAS (KS), and obtains the above-mentioned g (S) = SL
The arithmetic processing of OP (KS) × f (S) + BIAS (KS) is executed, and the converted key scale data g (S) is calculated by the multiplier 210.
Is input to The function generator 211 can be configured by a multiplier, an adder, and a selector used when overflow or underflow occurs, but can also be configured by a microcomputer that performs arithmetic processing based on a program.

Further, the fixed data FIX is also supplied to the function generator 211 via the selector 212, and the fixed data FIX is
When selected at 212, the content of the frequency modulation is not modified according to the key scale data. The select signal of the selector 212 is the key scale selection signal data KS described above.

Either the selected initial touch data SIKT or the selected after touch data SAKT is selected by the selector 216, and is input to the function generator 214 via the selector 215. The function generator 214 is also provided with the above-described slope data SLOPE (KT) and bias data BIAS (KT), and the above-described k (T) = SLOPE (KT) × j (T) + BIA
The arithmetic processing of S (KT) is executed, and the converted key touch data k (T) is input to the multiplier 213. Like the function generator 211, the function generator 214 can be composed of a multiplier, an adder, and a selector used when an overflow or an underflow occurs, but performs arithmetic processing based on a program. It can also be constituted by a microcomputer.

The fixed data FIX is also supplied to the function generator 214 via the selector 215, and the fixed data FIX is
When selected at 214, the contents of the frequency modulation are not modified according to the key touch data. This selector
The select signal 215 is the key touch selection signal data KT described above. Further, the select signal of the selector 238 is the above-mentioned initial after-selection signal I / A.

The calculation contents of the function generators 211 and 214 are the same as those of the above-described 7A
This is shown in FIG.

These selection key data SKS, selection initial touch data SIKT, selection aftertouch data SAKT, slope data SLOPE (KS), SLOPE (KT), bias data
The BIAS (KS), BIAS (KT), fixed data FIX, and selection signal data KS, KT, and I / A are corrected by the CPU 300 by the correction circuit 200a (2
00b, 200c).

In this case, the correction circuit 200a uses the modulation speed data MSPD
To make corrections to the slope data SLOPE (K
S), SLOPE (KT) and bias data BIAS (KS), BIAS
(KT) is SLOP of modulation speed data for MSPD
E (MSPD), BIAS (MSPD), and the correction circuit 200b corrects the modulated depth data MDEP, so that the slope data SLOPE (KS), SLOPE (KT), and the bias data BI
AS (KS) and BIAS (KT) become the SLOPE (MDEP) and BIAS (MDEP) of the modulation depth data MDEP, and the correction circuit 200c corrects the phase speed data PSPD, so that the slope data SLOPE ( KS), SLOPE
(KT) and bias data BIAS (KS), BIAS (KT) are the SLOPE (PSP) of the phase speed data PSPD.
D), BIAS (PSPD).

FIG. 7B (3) shows another embodiment of the correction circuit 200a (200b, 200c). As shown in FIG. 7B (2), the frequency modulation is performed by reading from the tables 231 and 235. Is to correct the content of

The correction circuit 200a (200b, 200c) in FIG.
Function generator 21 of correction circuit 200a (200b, 200c) in FIG.
1 and 214 are replaced with a scale table (KS) 231, a touch table (KT) 235, a limiter 232, and a limiter 236.

The selected key scale data SKS or fixed data FIX from the selector 212 is converted from 7-bit data to 4
The data is compressed into bit data, and the above-mentioned 6-bit table number data TBL NO. (KS) is added to the higher order, and input to the scale table 231 as address data. The conversion key scale data is input from the scale data 231 to the multiplier 210, and is multiplied by the modulation speed data MSPD, the modulation depth data MDEP, or the phase data PSPD.

In addition, the selection initial data SIKT from the selector 215
Alternatively, the selected after touch data SAKT or fixed data FIX is compressed from 7-bit data to 4-bit data by the limiter 236, and the above-mentioned 6-bit table number data is compressed.
TBL NO. (KT) is added at the top, and the touch table 235
Is input as address data. The conversion key touch data is input from the touch table 235 to the multiplier 213, and is multiplied by the modulation speed data MSPD, the modulation depth data MDEP, or the phase data PSPD.

The data storage contents of the scale table 231 and the touch table 235 are as shown in the above-described 7B (2).

The limiter 232 of the 7-bit selection key scale data SKS to be entered, all the treble C ₂ following are the treble C _2, as all the treble C ₇ or more of treble C _7,
Those of treble C ₂ -C _7, together every four "0000
(0), "0001 (1)" ... "1111 (15)". Specifically, subtracting the key number data treble C ₂ from the selected key scale data SKS inputted, and outputs the 4-bit data obtained by removing the most significant bit and the lower 2 bits. In this case, the most significant bit is “1”
Are all “1111 (15)”.

Therefore, the limiter 232 is realized by a logic circuit that performs such a conversion process. Of course, it can also be realized by a microcomputer that performs arithmetic processing based on a program. This is the same for the limiter 236 described below. Key scale data of treble C ₂ or less and treble C ₇ or more
I ignore KS because this range is not used much. Of course, the output may be performed in a form other than the 4-bit data, or the limiter 232 may be omitted and the selected key scale data SKS may be directly input to the scale table 231.

The limiter 236 performs the same conversion as 232,
Among the input 7-bit selection key touch data SKT, those having a small value and those having a large value are ignored and output in the form of 4-bit data. For example, of the key touch data KT, “16” or less and “112” or more are ignored, and the data of “16” to “112” are grouped together by six to “0”.
000 (0), “0001 (1)”... “1111 (15)”. Needless to say, the same conversion as the limiter 232 may be performed, or the limiter 236 may be omitted and the selection key touch data SKT may be directly input to the touch table 235.

The other contents are the same as the correction circuit 200a (20) shown in FIG.
0b, 200c). In addition, table number data
TBL NO. (KS) and TBL NO. (KT) are also the correction circuits 200a and 20
Different values are taken for each of 0b and 200c.

4. Key Assigner Circuit 30 FIG. 3 shows the key assigner circuit 30 and the CPU 300
Is operable only when the applied master clock signal φ (CK2) is at a high level. When the master clock signal CK2 is at a high level “1”, the CPU 300 When the low level is “0”, data irrelevant to the CPU 300 flows.

4-1.ROM address control circuit 31 The address data CA0 to 15 for accessing the ROM 20 and various memories from the CPU 300 are 16-bit data, but the lower 11 bits CA1 to 11 excluding the least significant bit are given to the selector 313. Can be The upper 4 bits CA12 to 15 are set to "00"
00 ”is added, and the B
Through the input, as the 19-bit address data together with the lower 11 bits CA1 to CA11, the ROM 20
The processing program is mainly read. When the CPU 300 reads out tone data and other data other than the processing program, the CPU 300 sends an 8-bit MM data.
The U address data is output through the data bus line. The U address data is added to the lower 11 bits CA1 to CA11 through the selector 312 through the MMU latch 310 and is supplied to the ROM 20 through the selector 313.

The switching state of the address data is shown in FIG.
FIG. 16 shows that although the address data of the ROM 20 is 19 bits, the address data of the CPU 300 is 16 bits, so that “0000” and MMU address data are added.

In this way, the read of the program and the read of the timbre data can be easily switched by adding the MMU address or “0000”. Even if the read address data of the CPU 300 is smaller than the read address data of the ROM 20, Can be read from all regions.

Accordingly, the bank “0” of the ROM 20 has the MMU latch 31
Since it is possible to directly access without using 0, a processing program dedicated to the CPU 300 is stored. Also, CPU300
But, for example, to access the "3524 _H" address of the bank "1" is set to "13 _H" to the MMU latch 310, when set to "1524 _H" as CPU300 address data, the synthetic address data, become a "13524 _H", the bank "1"
"3524 _H" address is to be access. In this case, the most significant 4 bits “1 _H ” of the address data “1524 _H ” of the CPU 300 are canceled by the selector 312.

The upper 4-bit data CA12 to CA15 are supplied to the comparator 311.
This comparator 311 is also supplied with 4-bit f (x) data. When the two data do not match, "0000" and the upper 4-bit address data CA12
~ 15 is selected. When the two data match, a match signal is provided from the comparator 311 to the selector 312, and the MMU latch 310 is selected. Therefore, when the upper 4-bit address data CA12 to CA15 do not match the f (x) data, the processing program of the CPU 300 is read, and when they match, the tone color data and the like are read.
The f (x) data may be selected and set by the CPU 300 or may be a fixed value. When you fix the f (x) to "1 _H", "1000 _H" of the bank of RAM20 "0"
When the area for the MMU latch 310 of “1FFF _H ” is accessed and f (x) is fixed at “0 _H ”, the area of “0000 _H ” to “0FFF _H ” of the bank “0” of the RAM 20 is accessed. The Rukoto.

The selector 313 includes an assignment memory 3 described later.
The bank data read by the CPU 300 from 20 and the frequency number accumulated value FA12 to 26 from the frequency number accumulator 40
Is given to the ROM 20 via the selector 313, and the waveform data RD of the corresponding bank is read. Data selector switching in the selector 313 is performed by a clock signal CK2 from the system clock generator 10, and switching between reading of a processing program and reading of a sample value of waveform data RD is performed as shown in the lower part of FIG. . Of these, at the timing of reading the processing program, based on the above f (x) data,
The reading of the processing program and the reading of the timbre data are switched. Then, these reading processes are repeatedly performed for 16 channels.

Of the data read from ROM 20, waveform data RD
Is sent to the waveform data decompression interpolation circuit 50 as it is, and the processing program and timbre data are divided into two pieces of 8-bit data and sent to the CPU 300 via the selector 314 or to the assignment memory 320 via the gate buffer 323. Or sent. The data select switching in the selector 314 is performed by the least significant bit of the address data CA from the CPU 300.
Performed based on CA0.

Thus, data is taken in from the ROM 20 following the processing speed of the CPU 300. Further, even if the number of bits of data read from the ROM 20 is larger than the number of bits of the data bus line of the CPU 300, data processing can be performed smoothly.

4-2. Modulation Calculation Circuit 33 In the modulation calculation circuit 33, the modulation coefficient data in the timbre coefficient data corresponding to the timbre designated by the
00 is first written to the modulation operation RAM 331, and then
The modulation coefficient data, key data, and tablet data in the modulation operation RAM 331 are read out by the CPU 300 in a time-division manner for each system, and the modulation operation is performed by the modulation operation circuit 33. As the modulation operation RAM3 again
It is written in 31. Using the modulation operation data MDATA which is the final result in the modulation data, the operation of addition of modulation shown in FIG. 15 is performed for each channel of each stream, and the result is temporarily stored in the assignment memory 320. It is written in the area of modulation key number data (M KEY NO) and the area of modulation cent data (M CENT). These values in the assignment memory 320 are sent to the frequency number accumulator 40, and frequency modulation is performed independently for each sequence. The "modulation operation circuit 33" is a "modulation operation processor", and if it is provided, the modulation operation can be performed at high speed. However, the CPU 300 can perform this processing by a program without it. The modulation operation circuit 33 includes a modulation operation RAM 331 and a circuit group for performing a modulation operation as shown in FIGS. 17 to 21 described later.

FIGS. 8A and 8B show a modulation calculation RAM 331. The RAM 331 stores modulation coefficients, key data and tablet data, and modulation data for three sequences 0 to 2 among the four sequences 0 to 3 described above. Data, key scale coefficient data, and key touch coefficient data are stored. The modulation coefficients are represented by four phases (0) to 4 of the modulation waveform shown in FIGS. 1A and 1B.
(3) Modulation depth data MDEP, modulation speed data MSPD, phase speed data PSPD, key scale selection signal data KS, key touch selection signal data KT,
It consists of initial after selection signal data I / A, return signal data RET, start trigger selection signal data TRG, and initial phase angle data (initial MSACC). These data have already been described in the description of the timbre coefficient data in the RAM 20.

Key data and doublet data are selected key scale data SKS, selected initial touch data SIKT,
It consists of selected after touch data SAKT, a key-on summing signal ON SUMM, a key-on event signal ON EVNT, and a timbre number. Selection key scale data SKS
, Selected initial touch data SIKT, selected after touch data SAKT, and key-on summing signal ON SUMM
And the key-on event signal ON EVNT are already in RAM20
This is the signal as shown in the description of the timbre coefficient data of FIG. The timbre number is data representing a timbre corresponding to the switch operated by the timbre switch 2 described above.

Modulation data is phase speed accumulated data PSACC,
It consists of modulation speed accumulation data MSACC and modulation operation data MDATA. Phase speed accumulated data PSACC
Is accumulated data of the phase speed data PSPD, as shown in FIG. 1 (2), and indicates the elapsed time of each phase of the modulation. Modulation speed accumulation data MSACC
Is the modulation speed data as shown on the left of FIG.
This is accumulated data of the MSPD, and indicates an elapsed point in one cycle of the modulation waveform. The modulation operation data MDATA is data indicating the magnitude of the modulation degree at each time, and is obtained by multiplying modulation waveform data MWAVE described later by modulation depth data MDEP indicating the modulation depth.

The key scale coefficient data and the key touch coefficient data are also as described in the description of the tone color coefficient data in the RAM 20. The slope data SLOPE and the bias data BIAS of the key scale coefficient data and the key touch coefficient data in FIG. 8A are coefficient data of the arithmetic expression in FIG. 7A (2),
The table number data TBL NO. Of the key scale coefficient data and the key touch coefficient data in FIG. 8B is shown in FIG. 7B (2).
Is the data indicating the number of each table.

Of the above-described series 0 to 2, the system 0 is assigned to the upper keyboard of the keyboard 1, the system 1 is assigned to the lower keyboard, and the system 2 is assigned to the foot keyboard. Different tone colors and different modulation contents can be set for each keyboard. is there. Of course, different timbres and different modulation contents may be set for each channel.

As described above, one modulation operation circuit 33 can set various kinds of modulation contents.

4-3. CPU RAM301 Fig. 9 shows a part of the contents of CPU RAM301.
Key on signal KEY ON, key number data KEY NO,
Cent data CENT, series data GR, after touch data, and initial touch data are stored for each channel as described above. Of these, series 0
Channels CH0 to CH7 are assigned, channel 1 is assigned channels CH8 to 14, and channel 2 is assigned channel CH15.

The key-on signal KEY ON is signal data indicating that a key of the keyboard 1 is being pressed, and is "1" when the key is on and "0" when the key is off. Key number data KE
Y NO is data indicating a key number corresponding to the designated pitch of the keyboard 1, and cent data is data indicating a fine pitch difference equal to or less than the key number, and the frequency value corresponding to each data is shown in FIG. It is shown. Series data
GR indicates, as described above, to which of the four tone generation systems the tone data ST after the multiplication is assigned. The after touch data is data indicating a key pressing pressure of the keyboard 1, and the initial touch data is data indicating a key pressing speed of the keyboard 1.

4-4. Assignment Memory Circuit 32 FIG. 10 shows the storage contents of the assignment memory 320 of the assignment memory circuit 32. The assignment memory 320 has a memory area for timbre data for 16 channels. The tone color data from the ROM 20 is set in each channel area. In this case, among the tone data to be set, the envelope data is set in each of the envelope group areas EG0 to EG15, and the other data is set separately in the respective channel areas of CH0 to CH15. Data set in CH0 to CH15 are bank data (A) and (B), envelope group data (A)
(B), consisting of modulation key number data (M KEY NO), modulation cent data (M CENT), key-on signal data, data length signal data D816, sequence data GR, initial frequency number data, loop top data, and loop end data The modulation key number data (M
The data other than the KEY NO), the modulated cent data (M CENT), and the envelope group data (A) and (B) are as described in the storage contents of the ROM 20.

Modulation key number data and modulation cent data
As shown, the key number data KEY NO and the cent data CENT are added with the key number bias data and the cent bias data corresponding to the designated tone color, and the modulation data MDATA for implementing frequency modulation described later. The data corresponding to the correction data is used as an accumulation step value of the read address data of the waveform data RD. This processing is performed by the CPU 300. In the series 0 of the channels 0 to 7, the modulation arithmetic RAM 3
Channels 8 to 14 are used by using the modulation data of series 0 in 31.
In series 1, the modulation data of series 1 is used, and in series 2 of channel 15, the modulation data of series 2 is used. The envelope group data (A) and (B) are data indicating the addresses of the envelope group areas EG0 to EG15 in which the envelope data corresponding to the tone color of the channel area is stored. Two tone colors are assigned to one channel. Because it is composed of musical sounds,
(A) and (B) exist. Accordingly, since there are two waveform data RDs, there are two bank data (A) and (B). The envelope data set in EG0 to EG15 is also described in ROM20 above.
As described above.

The modulation key number data and modulation cent data are
(A) and (B) are shared for two musical tones, and two musical tones (A) and (B) are synthesized and output according to one operation key of the keyboard 1. These two tones (A) and (B) have different tone colors because the bank data or the envelope group data are different, and the envelope control is also performed separately.

The data read from the assignment memory 320 is sent to the frequency number accumulator 40, the envelope generator 60, and the like via an AM (assignment memory) bus, or is supplied to the CPU 300 via the gate buffer 322. Also 4
With respect to the bit envelope group data (A) and (B), the 2-bit phase data PA from the envelope generator 60 is added to the lower part via the latch 324, and the 1-bit "1" is added to the upper part. 7 bits in total,
The signal is again supplied to the assignment memory 320 via the selector 321, and the envelope level data EL, thin-out data TH, envelope speed data ES, etc. of the corresponding envelope are read out and sent to the envelope generator 60. The system clock generator 1 is connected via the selector 321.
Read address data, which is a set of clock signals CK from 0, is also given to the assignment memory 320, and the CPU 300
Is also given.

The reset circuit 303 resets the CPU 300 and the output latch 304 when the power is turned on. The sampling addresses of the tone switch 2 and the keyboard 1 are temporarily set in the output latches 304 and 306, and the sampling results are input to the input buffers 305 and 307. Only one bit of the sampling data of the output latch 304 is used as a gate signal of the DA converter 100.

5. Modulation Operation Circuit 33 FIGS. 17 (1) and 18 (1) show the modulation operation circuit 33, and FIG. 17 (1) is a circuit portion for calculating the phase speed accumulated data PSACC. FIG. 18A shows a circuit part for calculating the modulation data MDATA.

First, in FIG. 17 (1), the CP
Each phase (0) to (3) read by U300
As for the phase speed data PSPD of the phase, the data PSPD of the currently executing phase is selected by the selector 331, and the adder 33 is selected.
In 2, the data is added to the previous phase speed accumulated data PSACC, and through the OR gate group 339 and the AND gate group 336,
Output as phase speed accumulated data PSACC.

FIG. 17 (2) shows the phase speed data PSPD and the phase speed accumulation data PSACC. The 13-bit phase speed data PSPD is sequentially accumulated to become the phase speed accumulation data PSACC. The most significant bit PAL of the phase speed accumulated data PSACC is a return data indicating that the repetitive modulation of the phases (2) to (3) is being performed as shown in FIG. 1A (3). Becomes The next upper 2 bits are PA13 and 14, which are phase data indicating the phase at that time. "00" is phase (0), "01" is phase (1), "10" is phase (2), "11". Is the phase (3). Next 4
Bits PA9 to PA12 are weighting data (Rate) for moving the phase.

In FIG. 17 (1), the phase data PA13, PA14 of the phase speed accumulated data PSACC are stored in the selector 3
31, the phase speed data PSPD of the currently executing phase is selected. The selected phase speed data PSPD is input to the correction circuit 200c,
Correction is performed according to the values of the key scale data KS and the key touch data KT.

When the carry-out signal Cout is output from the adder 332, when the return signal data RET = "0", "11 ... 1" is output as phase speed accumulated data PSACC from the OR gate group 339 via the AND gate 338. Being
This state is maintained, and as shown in (1) of FIG. 17 (3), the end point of the final phase (3) is reached, and the modulation state at this point is maintained. Also, return signal data
When RET = "1", the upper PA14 of the phase data is always set to "1" via the OR gate via the AND gate 340, and as shown in FIG. 17 (3) (B), the phase "10" Only (2) and “11 (3)” are repeatedly selected. At this time, solve the OR gate to calculate the phase speed accumulated data
The data PAL during return of the most significant bit of PSACC also becomes “1”.

The key-on summing signal ON SUM described in FIG.
Either M or the key-on event signal ON EVNT is inverted by the inverter 334 after being selected by the selector 333 by the start trigger selection signal TRG. AND gate group 3 above
By closing 36, the phase speed accumulated data PSACC is set to the initial state of "00 ... 0". The inverted signal from the inverter 334 is used as an initial signal CLK described later.

In FIG. 18 (1), the modulation speed data MS of each phase read by the CPU 300 from the modulation operation RAM 331.
The PD selects the modulation speed data MSPD of the phase currently being executed by the selector 351 and the selector 350.
Then, the modulation speed data MSPD of the phase to be executed next is selected. The modulation speed data MSPD of the currently executing phase is supplied to the multiplier 354 as complement weight data (1-R).
Is multiplied to the adder 356, and the modulation speed data MSPD of the phase to be executed next is multiplied by the weighting data R by the multiplier 353, and the multiplied data is supplied to the adder 356, and both data are added. By the addition in the adder 356, an interpolation process is performed between the modulation speed data MSPD of the phase currently being executed and the modulation speed data MSPD of the phase to be executed next.

Interpolated modulation speed data M from this adder 356
The SPD is input to the correction circuit 200a, and correction is performed according to the values of the key scale data KS and the key touch data KT. And this modified modulation speed data MSPD
Is the adder 362 and the modulation speed accumulated data M
It is added to SACC and output as modulation speed accumulated data MSACC via selector 363. The relationship between the modulation speed accumulated data MSACC and the modulation speed data MSPD is as shown in FIG. 18 (2). The selector 363 selects initial phase angle data (initial MSACC) based on the initial signal CLR. The modulation speed accumulation data MSACC is supplied to a modulation waveform creation circuit 364, and step data MWAVE of each of the modulation waveform data is created as shown in FIGS. Given to the vessel 365.

The modulation depth data MDEP of each phase, which is read by the CPU 300 from the modulation operation RAM 331, is supplied to the selector 35.
At 8, the modulation depth data MDEP of the currently executing phase is selected, and the selector 357 selects the modulation depth data MDEP of the phase to be executed next. The modulation depth data MDEP of the currently executing phase is multiplied by the complement weighting data (1-R) in the multiplier 360 and given to the adder 361, and the modulation depth data MD of the phase to be executed next is given.
The MDEP is multiplied by the weighting data R in the multiplier 359 and provided to the adder 361, where both data are added. By the addition in the adder 361, interpolation processing is performed between the modulation depth data MDEP of the phase currently being executed and the modulation depth data MDEP of the phase to be executed next.

Interpolated modulated depth data MDE from this adder 361
P is input to the correction circuit 200b, and the key scale data K
Correction is made according to the values of S and the key touch data KT.
Then, the modified modulation depth data MDEP is multiplied by the modulation waveform data MWAVE in the multiplier 365 to form modulation waveform data MWAVE having an amplitude corresponding to the magnitude of the modulation depth data MDEP. In accordance with the sign bit data of the most significant bit of the modulated waveform data MWAVE, the complement circuit 366 converts the data as it is or converts it into 2's complement data, and outputs it as modulation operation data MDATA.

The phase data PA13 and phase data PAACC of the phase speed accumulated data PSACC are generated by a next phase generation circuit 352, on the basis of the return signal data PNXT, next phase data PNXT indicating a phase to be executed next is generated. Given to 350, 357. The phase data PA13 and PA14 indicating the currently executing phase are directly supplied to the selectors 351 and 358.

The weighting data PA9 to PA12 of the phase speed accumulation data PSACC are supplied to the multiplication coefficient control circuit 355 by complement weighting data (1) indicating the weight of the phase currently being executed.
-R) and weighting data R indicating the weight of the phase to be executed next are created. The complement weight data (1-R) is provided to the multipliers 354 and 360, and the weight data R is provided to the multipliers 353 and 359.

6. Modulation Waveform Creation Circuit 364 FIGS. 19A and 19B show specific circuits of the modulation waveform creation circuit 364. FIGS.
Each of the modulation waveform creation circuits 364 of (C) and (D) respectively (a)
(B) Modulated waveform data MWAVE as shown in (c) and (d)
Create

The modulation waveform creation circuit 364 of FIG. 7A first converts the lower 8 bits of the upper 2 bits of the modulation speed accumulated data MSACC into the 2's complement value by the "2" complement circuit 371. Further, the 2's complement circuit 372 converts the most significant bit and the lower 9 bits into a 2's complement value, thereby forming a triangular waveform as shown in FIG. 19A (a). Data MWAVE is obtained.

The modulation waveform creation circuit 364 of FIG.
Modulated waveform data MWAVE of various waveforms as shown in FIG.
And accumulate the modulation speed accumulation data MSACC
Is read as read address data.

The modulation waveform creation circuit 364 of FIG.
(1) The modulation ROMs 374, 375, 376, and 377 storing modulation waveform data MWAVE of different waveforms are prepared for each of (3), (3), and the modulation speed accumulation is performed on these modulation ROMs 374, 375, 376, and 377. Calculation data MSACC is given as read address data. Furthermore, phase speed accumulated data PS
Each bit of the 4-bit select signal obtained by decoding the phase data PA13 and PA14 of the ACC by the decoder 378 is supplied to each of the modulation ROMs 374, 375, 376 and 377 as a chip enable signal CE. Thereby, for example, the nineteenth
A different modulation waveform can be obtained for each of the phases (0) to (3) as shown in FIG.

The modulation waveform creation circuit 364 of (D) performs interpolation between the phases of the modulation waveform with respect to the modulation waveform creation circuit 364 of (C). That is, the modulation ROM 37
4, 375, 376, and 377 are the same as those in (C). Each of the modulation waveform data MWAVE read from each of the modulation ROMs 374 to 377 by the modulation speed accumulated data MSACC is supplied to a selector 379.
Then, the modulation waveform data MWAVE of the phase to be executed next is selected by the next face data PNXT, and the phase data PA13, PA13 is selected by the selector 380.
The modulation waveform data MWAVE of the currently executing phase
Is selected. Among them, the modulation waveform data MWAVE of the phase to be executed next is multiplied by the weighting data R in the multiplier 381 and given to the adder 383.
The modulation waveform data MWAVE of the phase currently being executed is multiplied by the complement weight data (1-R) in the multiplier 382, and is given to the adder 383, where both data are added.
As a result, as shown in FIG. 19 (d), interpolation is performed between the modulation waveform of the phase currently being executed and the modulation waveform of the phase to be executed next.

The above-mentioned "2"'s complement circuits 371, 372, and 366 can be constituted by an exclusive OR gate group and an adder.

FIG. 20 (1) shows a specific circuit of the next phase creation circuit 352 of FIG. 18 (1). Among the phase data PA13 and PA14 of the phase speed accumulation data PSACC, the lower data PA13 is a NAND gate. The data is input to the lower A side (0) of the selector 391 via NA1, and is input to the upper A side (1) of the selector 391 via the OR gate OR1. The upper data PA14 is inverted by the inverter IN1, and the NAND gate NA1 is output. Is input to the lower side (0) of the selector 391 via the OR gate OR1, and the selector 3 is output via the OR gate OR1.
It is input to the upper side (1) of 91 on the A side. Thus, the data obtained by adding +1 to the phase data PA13, 14 is input to the A side of the selector 391, and the phase data PA13,
Is “11”, “11” is input as it is, and as shown in (1) of FIG. 20 (2), when the phase of the modulation waveform reaches the final phase “11 (3)”, the next phase Is also set to "11 (3)", and only the final phase is repeatedly executed as shown on the right of FIG. 1 (2).

This is the case where the return signal data RET = "0", the output of the NAND gate NA2 is always "1", and the A side of the selector 391 is always selected.
When RET = “1”, the phase data PA13 and PA14 are “1”.
Only in the case of “1”, “10 (2)” on the B side of the selector 391 is selected. As a result, as shown in (2) of FIG. 20 (2), when the modulation phase reaches the final phase “11 (3)”, the next phase is set to “10 (2)”, and FIG. As shown in 3), phases (2) and (3) are repeatedly executed.

FIG. 21 shows a specific circuit of the multiplication coefficient control circuit 356. In the weighting data PA9 to PA12 of the phase speed accumulated data PSACC, “0” is added as a higher order as it is via AND gates AN2 to AN5. The weighted data R
Is output as Further, the data is inverted by the inverters IN2 to IN5 via the AND gates AN2 to AN5, added with “0” at the upper position, and incremented by +1 in the adder 392, thereby obtaining the complement of “2”. (1-
R).

7. Example of Frequency Modulation FIGS. 1B, 1A, 1B, 1C, and 1D show examples of frequency modulation, and examples of set values of respective data for realizing this modulation waveform are shown below.

(A) Trumpet sound type modulation phase (0) Initial phase angle data: 0 Modulation speed data MSPD: Large value Modulation depth data MDEP: Large value Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 phase (2 Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Phase (3) Modulation speed data MSPD: Medium value Modulation depth data MDEP: Medium value Return signal data RET: 0 (B) Auto vent type modulation phase ( 0) Initial phase angle data: 300 _H (-90 degrees) Modulation speed data MSPD: 0 Modulation depth data MDEP: Medium value Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 phase (2) Modulation Speed data MSPD: 0 Modulation depth data MDEP: 0 phase (3) Modulation speed data MSPD: Medium value Modulation depth data MDEP: Medium value Turn signal data RET: 0 at the start point of the phase (0), in a state in which frequency modulation is applied, it is possible to go to start sound of the musical tone.

(C) Glide type modulation phase (0) Initial phase angle data: 300 _H (-90 degrees) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: Medium Phase value (2), phase (3) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Return signal data RET: 0 From phase (0) to phase (1), the modulation speed accumulation data MSACC is initialized Phase angle data `` 3
Since the modulation depth data MDEP only increases without changing “00 _H ”, the modulation level gradually increases gradually.

(D) Strings type modulation phase (0) Initial phase angle data: 0 Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 phase (2) Modulation speed Data MSPD: Somewhat small value Modulated depth data MDEP: Somewhat large value Phase (3) Modulation speed data MSPD: Somewhat large value Modulated depth data MDEP: Somewhat small value Return signal data RET: 1 As a result, the modulation speed and amplitude are It is possible to obtain a complicated modulation waveform that becomes larger or smaller instead.

The size of the phase speed data PSPD is the first
The size is inversely proportional to the length of each phase shown in FIGS. (A), (B), (C), and (D).

In this manner, the frequency of one musical tone can be sequentially and variously changed based on the modulation coefficient that differs for each phase.

8. Frequency Number Accumulator 40 FIG. 4 shows the frequency number accumulator 40. The modulation key number data and the modulation cent data from the assignment memory circuit 32 are transmitted via the latch 404 to the frequency number accumulator 40. The ROM 419 is given as read address data, and frequency frequency speed data FS indicating a frequency value corresponding to the modulation key number data M KEY NO and the modulation cent data M CENT is read. The frequency number speed data FS is accumulated by the adder 407 through the exclusive OR gate group 405 to the accumulated frequency number FA up to that time, and the upper 8 bits FA 19 to 26 are transmitted via the selector 413 to the lower 19 bits. The bits FA0 to FA18 are supplied to the adder 407 again as the above-mentioned frequency number accumulated value FA via the exclusive OR gate group 414, the latch group 415 and the selector 416. As a result, the frequency number accumulated value FA is accumulated at a speed corresponding to the size of the frequency number speed data FS,
The accumulated value FA is sent to the ROM address control circuit 31 via the latch 418 through the 15-bit FAs 12 to 26 corresponding to the upper integer part, and the waveform data RD is read. The waveform return signal FDU of the upper three bits FA9 to 11 and the most significant bit of the decimal part is sent to the waveform data decompression interpolation circuit 50, and is used for decompression and interpolation of the sample value of the waveform data RD.

FIG. 22 shows the contents of such a frequency number accumulated value FA. The frequency number accumulated value FA is 28-bit data in total, and the most significant bit is the waveform folding signal FDU.
The next 8 bits FA19 to 26 are comparator bits, which are used for comparing a loop end described later or whether or not the loop top has been reached. Further, the next 7 bits FA12 to 18 are an integer part, and the last 12 bits FA0 ~ 11 is the decimal part.
Such frequency number speed data FS is CH0 to CH15.
The 16 channels are accumulated by the frequency number accumulator 40,
The accumulated frequency number FA of each channel is calculated by the latch group 41
5 is stored in the memory. The latch group 415 includes 16 latches. The latch for accumulating the frequency number speed data is switched at the timing of the clock signal CK3, and the reading from the latch is performed during the timing of one cycle of the clock signal CK3. The writing to the latch is performed at the last timing of the latter half of the clock signal CK3. In each of the latches of the latch group 415, the same read address (the same frequency number accumulated value FA12 to FA26) is set for the two tone components (A) and (B). The difference in timbre is based on the difference in the bank data (A) and (B).

The 8-bit initial frequency number from the assignment memory circuit 32 is supplied to the selector 416 via the latch 406.
, The upper 1-bit “0” and the lower 19-bit “00”
.. 0 "are added, and selected as the same 28-bit data as the frequency number accumulated value FA. As the select signal in the selector 416, an on-event signal output at the key-on timing from the envelope generator 60 is used, and as shown in FIG.
The frequency number speed data FS is sequentially accumulated with respect to the initial frequency number.

Further, the loop end data and the loop top data from the assignment memory circuit 32 are transmitted via the latch 402,
Either the loop end or the loop top is selected by the selector 403 and is supplied to the comparator 409 and also to the selector 413. In the comparator 409, the upper 8 bits of the frequency number accumulated value FA
When the comparison with 19 to 26 is performed and the frequency number accumulated value FA exceeds the range between the loop end and the loop top, the selector 410 outputs the overrun signal FCP, and
Via 411, the above-mentioned exclusive OR gate group 414 and the selector 413 are provided, and the loop end data or the loop top data is taken in as new data instead of the higher-order comparator bits FA19 to 26 of the frequency number accumulated value FA. It is. At this time, the exclusive OR gate group 41
In FIG. 4, the values of the integer part and the decimal part of the frequency number accumulated value FA up to that point are inverted plus or minus. This is because when the reading direction of the waveform data RD is inverted at the loop end or the loop top, This is for using the frequency number accumulative value FA in a state where the fraction is inverted in the plus and minus directions as it is and to provide consistency in inversion reading of the waveform data RD.

The overrun signal FCP is also given to the exclusive OR gate 412, and inverts the waveform folding signal FDU, which is the most significant bit of the frequency number accumulated value FA. The value of FS is inverted plus or minus, and the direction of accumulation of the frequency number accumulated value FA in the adder 407 is switched between increasing and decreasing. FIG. 11 shows a state of loop reproduction for each half-waveform by the switching of the frequency number speed data FS.

The waveform folding signal FDU is given as a select signal to the selectors 403 and 410, and the frequency number speed data
When FS is added, the loop end date and A <B detection signal are selected, and when subtracted, the loop top data and A> B
The detection signal is selected. In addition, the waveform folding signal FDU
Is also input to the Cin terminal of the adder 407, and when the frequency number speed data FS is subtracted, the frequency number accumulated value FA is incremented by +1.
In addition to performing the processing, it is also provided to an exclusive OR gate 408. An output signal from the Cout terminal of the adder 407 is also given to the exclusive OR gate 408, and it is detected that the frequency number accumulated value FA has overflowed or underflowed, and this is also output as the overrun signal FCP. You.

Further, the bank data (A) and (B) from the assignment memory circuit 32 are sent through the latch 400, one of the bank data (A) and (B) is selected by the selector 401, and is sent through the latch 417. Is transmitted to the ROM address control circuit 31 together with the integer part of the above-described frequency number accumulated value FA, and the waveform data RD is read.

As a result, although the two tone components (A) and (B) assigned to one channel have different bank data, a common frequency number accumulated value FA is used, and the timing of the tone generation process is synchronized. .

The clock signal CK3 from the system clock generator 10 is used as the select signal of the selector 401. The tone generation processing for (A) is performed in the first half of the clock signal CK3, and the tone generation processing for (B) is performed in the second half. Generation processing will be performed. The clock signal group CK from the system clock generator 10 corresponds to the latches 400, 402, 404, 406, 41
5, 417, and 418 are also provided as latch signals, and channel synchronization and timing synchronization are achieved.

The present invention is not limited to the above embodiment, and can be variously modified without departing from the spirit of the present invention. For example, instead of multiplying the modulation speed data MSPD, the modulation depth data MDEP and the phase speed data PSPD by the multipliers 210 and 213 in changing the frequency modulation content by the key scale data KSD and the key touch data KTD, Operation processing such as addition and subtraction and division may be performed, or operation may be performed based on an arithmetic expression. In addition to the modulation information set by the tone switch 2, the numerical keys and the numerical display unit are used to control the phase speed data PSPD, the modulation speed data MSPD, the modulation depth data MDEP, and the modulation waveform data MWAV.
E, key scale selection signal data KS, key touch selection signal data KT, initial after selection signal data I / A,
The return signal data RET etc. may be set individually, and the shape of the modulation waveform may be a periodic shape or linear shape as described above, a random shape by a random number generator, or the modulation information may be an envelope. It can change based on level and time-varying data, select rhythm, set tempo,
It may be changed based on the setting volume, and in this case, each selection or setting data value may be sequentially subjected to an operation such as addition, subtraction, multiplication, division, or the like to each data in the modulation operation RAM 331, or each selection or setting data value may be changed. What is necessary is just to input to the correction circuit 200a (200b, 200c).

 Embodiments of the present invention are as follows.

(1) In an electronic musical instrument provided with a waveform generating means for generating waveform data, and a generating speed setting means for setting a generating speed of the waveform data of the waveform generating means, a pitch specifying means for specifying a pitch of a musical tone; Modulation information storage means for storing a plurality of pieces of modulation information for changing the generation speed of the waveform data of the waveform generation means; and modulation information for outputting, from the modulation information storage means, modulation information corresponding to the contents specified by the pitch specification means. An electronic device comprising: an output unit; and a generation speed control unit that changes a generation speed of the waveform data set by the generation speed setting unit based on the modulation information output by the modulation information output unit. Musical instrument frequency modulation device for musical instruments.

(2) In an electronic musical instrument including a waveform generating means for generating waveform data, and a generating speed setting means for setting a generating speed of the waveform data of the waveform generating means, a sound emitting operation means for performing a sound emitting operation of a musical sound; A sound emitting operation state detecting means for detecting a sound emitting operation state of the sound emitting operation means; a modulation information storage means for storing a plurality of modulation information for changing a generation speed of waveform data of the waveform generating means; A modulation information output means for outputting modulation information corresponding to the detection content of the sound emitting operation state detection means from the storage means; and a generation speed setting means based on the modulation information output by the modulation information output means. And a generation speed control means for changing a generation speed of the generated waveform data.

(3) The tone frequency modulating device for an electronic musical instrument according to claim 1 or 2, wherein the waveform generating means is means for generating musical tone waveform data.

(4) The modulation information output means is means for outputting a plurality of pieces of modulation information, and the generation speed control means is configured to output the waveform set by the generation speed setting means based on the plurality of output modulation information. 3. A tone frequency modulating device for an electronic musical instrument according to claim 1, wherein said tone frequency modulating device is means for sequentially changing a data generation speed.

(5) The tone frequency modulating device for an electronic musical instrument according to claim 2, wherein the sound emitting operation state detecting means is a speed of a sound emitting operation of a musical sound.

(6) The tone frequency modulating device for an electronic musical instrument according to claim 2, wherein the sound emitting operation state detecting means is a sound emitting operation intensity of a musical sound.

(7) The modulation information output means performs an arithmetic processing according to the contents specified by the pitch specifying means or an arithmetic processing according to the contents detected by the sound emitting operation state detecting means. Item 3. The tone frequency modulation device for an electronic musical instrument according to Item 1 or 2.

(8) The modulation information output means converts and outputs a value corresponding to the contents specified by the pitch specifying means or converts and outputs a value corresponding to the contents detected by the sound emitting operation state detecting means. The tone frequency modulating device for an electronic musical instrument according to claim 1 or 2, wherein

(9) The modulation information output means outputs a plurality of pieces of modulation information, weights any two of the pieces of modulation information, and shifts the weighting from one to the other as time passes. 3. The tone frequency modulating device for an electronic musical instrument according to claim 1, wherein

(10) The modulation information output means sequentially outputs a plurality of pieces of modulation information, and outputs each piece of modulation information as time passes.
3. A tone frequency modulating device for an electronic musical instrument according to claim 1, wherein said tone frequency modulating device is a means for sequentially switching.

(11) The tone frequency modulating device for an electronic musical instrument according to claim 1 or 2, wherein the modulation information output means is means for repeatedly outputting one piece of modulation information.

(12) The tone frequency modulation device for an electronic musical instrument according to claim 1 or 2, wherein the modulation information stored in the modulation information storage means is information indicating a modulation speed.

(13) The tone frequency modulation device for an electronic musical instrument according to claim 1 or 2, wherein the modulation information stored in the modulation information storage means is information indicating a modulation depth.

(14) phase information storage means for storing phase information at the start of a change in the periodic change between the modulation speed and modulation depth, phase information output means for outputting phase information from the phase information storage means, 3. The method according to claim 1, further comprising a modulation start unit configured to start a periodic change between a modulation speed and a modulation depth at a phase corresponding to the phase information output by the phase information output unit. A tone frequency modulating device for an electronic musical instrument according to the above.

[Effects of the Invention] As described in detail above, according to the present invention, a plurality of pieces of modulation information for changing the generation speed of waveform data are stored in advance,
Since a plurality of pieces of modulation information corresponding to a pitch or a sound emitting operation state are output, and the generation speed of waveform data is changed based on the output modulation information, a single modulation device may be used. It is possible to output a plurality of pieces of modulation information according to a high or sound emitting operation state, and it is possible to easily and variously realize optimum modulation contents according to various performance states.

[Brief description of the drawings]

1A and 1B are diagrams showing the contents and specific examples of the modulation waveform, FIG. 2 is an overall circuit diagram of the electronic musical instrument, FIG. 3 is a circuit diagram of a key assigner circuit 30, and FIG. FIG. 5 is a circuit diagram of the frequency number accumulator 40, FIG. 5 is a diagram showing storage contents of the ROM 20, FIG. 6 is an address mapping relating to the CPU 300 other than the RAM 20, and FIGS. 7A and 7B are timbres. FIG. 8A and FIG. 8B, FIG. 9 and FIG. 10 are diagrams showing the contents of the coefficient calculation RAM 331, the CPU RAM 301, and the assignment memory 320. FIG. 8 shows the contents of the coefficient data and the correction circuit 200a (200b, 200c). FIG. 11 is a diagram showing a read state of the waveform data RD, and FIG. 12 is a diagram showing a key-on event signal ON EVEN.
FIG. 13 is a time chart showing the relationship between T and a key-on summing signal ON SUMM and the start of modulation control, and FIG. 13 is a diagram showing the relationship between initial phase angle data INITIAL MSACC and the phase angle at the start of modulation control. FIG. 14 shows a specific example of key number data and cent data. FIG. 15 shows key number data KEY NO and cent data CENT, modulation operation data MDATA, and key number bias data (KEY NO
Bias), cent bias data (CENT bias), modulation key number data M KEY NO, and modulation cent data M CENT.
FIG. 17 and FIG. 18 are diagrams showing the correspondence between the address data of FIG.
19A and 19B are a circuit diagram of a modulation waveform creation circuit 364 and a diagram showing an example of a modulation waveform, FIG. 20 is a circuit diagram of a next phase creation circuit 352, and FIG.
FIG. 22 is a circuit diagram of the multiplication coefficient control circuit 356, and FIG. 22 is a diagram showing the contents of the frequency number accumulated value FA. 200a, 200b, 200c …… Correction circuit, 210, 213 …… Multiplier,
211, 214 …… Function generator, 232, 236 …… Limiter, 33…
… Modulation calculation circuit, 331… Modulation calculation RAM, 352… Next phase creation circuit, 355… Multiplication coefficient control circuit, 364…
… Modulation waveform creation circuit, 366, 371, 372... “2” complement circuit, 373, 374, 375, 376, 377.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seijiro Imamura 200 Terashimacho, Hamamatsu-shi, Shizuoka Prefecture Kawai Musical Instruments Co., Ltd. (56) References JP-A-60-60693 (JP, A) 246096 (JP, A) JP-A-1-293395 (JP, A) JP-A-1-55992 (JP, U) JP-A-60-112295 (JP, U)

Claims (6)

(57) [Claims] 1. Means for generating waveform data, means for setting the generation speed of the waveform data, means for specifying the pitch of a musical tone, and modulation information for changing the generation speed of the waveform data, Means for storing a plurality of pieces of modulation information comprising at least a modulation speed and a modulation depth; means for outputting first modulation information from the stored plurality of pieces of modulation information in accordance with the designated pitch; Means for changing a generation speed of the set waveform data based on the first modulation information, and means for detecting a length of a phase in which the first modulation information is executed, wherein the phase is Indicates the length of the first modulation information executed in one musical tone. The first modulation information is obtained from the stored plurality of modulation information according to the detection result of the phase length. Different from Means for outputting the next second modulation information in accordance with the designated pitch; and changing the generation speed of the set waveform data based on the output second modulation information. A tone frequency modulating device comprising: means for changing the frequency modulation of one tone; and means for switching the length of the phase independently of the modulation speed of each piece of modulation information. 2. Modulation information stored for generating waveform data, setting a generation speed of the waveform data, detecting a pitch of a designated musical tone, and changing a generation speed of the waveform data. A first modulation information is output according to the detected pitch from at least a plurality of pieces of modulation information including a modulation speed and a modulation depth, and the set waveform is based on the output first modulation information. Changing the generation rate of the data to detect the length of the phase in which the first modulation information is executed, in which the first modulation information in one tone is executed. In accordance with the detection result of the length of this phase, the next second modulation information different from the first modulation information from the stored plurality of pieces of modulation information is represented by the designated pitch. Output according to Based on the output second modulation information, the generation speed of the set waveform data is changed, thereby changing the frequency modulation within one musical tone. A tone frequency modulation method, wherein the length of the phase is switched independently. Means for generating waveform data; means for setting the generation speed of the waveform data; means for performing a sound emitting operation; and means for detecting the speed or strength of the sound emitting operation. Means for storing a plurality of pieces of modulation information for changing the generation speed of the waveform data, the plurality of pieces of modulation information comprising at least a modulation speed and a modulation depth; Means for outputting in accordance with the detected speed or intensity of the sound emitting operation; means for changing the generation speed of the set waveform data based on the output first modulation information; Means for detecting a length of a phase in which one piece of modulation information is executed, wherein the phase indicates a length in which one piece of the first modulation information is executed in one musical tone; Response to the Means for outputting, from the stored plurality of pieces of modulation information, the next second modulation information different from the first modulation information in accordance with the detected speed or strength of the sound emitting operation; Means for changing the generation speed of the set waveform data based on the outputted second modulation information, thereby changing the frequency modulation within one musical tone; Means for independently switching the length of the phase. 4. A method of generating waveform data, setting a generation speed of the waveform data, detecting a speed or intensity of a sound emitting operation of a musical tone, and storing modulation information for changing a generation speed of the waveform data. And outputting, from at least a plurality of pieces of modulation information including a modulation speed and a modulation depth, first modulation information in accordance with the detected speed or intensity of the sound emitting operation. Changing the generation speed of the set waveform data on the basis of the modulation information, and detecting the length of the phase in which the first modulation information is executed. This phase is included in one musical tone. Indicates the length of time during which the first modulation information is executed, and according to the detection result of the length of this phase, from the stored plurality of pieces of modulation information, the next second modulation information different from the first modulation information Up modulation information of 2 The output is performed in accordance with the detected speed or intensity of the sound emitting operation, and based on the output second modulation information, the generation speed of the set waveform data is changed. In particular, a tone frequency modulation method characterized by changing frequency modulation and switching the length of the phase independently of the modulation speed of each piece of modulation information. 5. A means for generating waveform data, means for setting a generation speed of the waveform data, and modulation information for changing the generation speed of the waveform data, the modulation information comprising at least a modulation speed and a modulation depth. Means for generating a plurality of different types of sound, means for dividing one musical tone into a plurality of phases, and generating information for designating combinations of all the modulation information to be executed for each phase, and designating the generated combinations. Based on the information, the plurality of types of modulation information is switched in each phase,
Based on the switched modulation information, the generation speed of the set waveform data is changed, thereby changing the frequency modulation in one musical tone, and specifying information of a combination over all phases of the modulation information. A tone frequency modulating device comprising: means for switching. 6. A method for generating waveform data, setting a generation speed of the waveform data, and generating a plurality of types of modulation information for changing the generation speed of the waveform data, the modulation information comprising at least a modulation speed and a modulation depth. Dividing one musical tone into a plurality of phases, generating combination designation information for all phases of the modulation information executed for each phase, and generating the plurality of types based on the designation information of the generated combination. Is switched in each phase, and based on the switched modulation information, the generation speed of the set waveform data is changed.
A tone frequency modulating method characterized by changing frequency modulation among two tones and switching designation information of a combination over all phases of the modulation information.