JP2997470B2 - Music information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical sound information processing apparatus that processes information for generating musical sounds.

[Prior Art] Conventionally, data representing a musical tone and a processing program for generating or controlling the musical tone are stored in separate storage devices, and the musical tone data and the processing program are read by separate reading devices. Was. In this case, the read address data of each read device is controlled completely independently.

[Problems to be Solved by the Invention] However, providing a storage device for musical sound data and a storage device for a processing program separately complicates the circuit configuration and causes an increase in cost. Also, providing such separate storage devices is
The read address data must be controlled completely independently, which complicates information processing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a tone information processing apparatus having a simple circuit configuration and a simple information reading process.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a data storage means for storing musical sound data relating to musical sounds, and a program storing means for storing a processing program for generating or controlling the musical sounds. Are provided integrally with each other, and switching means for switching reading between both storage means is provided.

[Operation] Thereby, the musical tone data and the processing program can be stored in one storage means, and the read address data is switched only by the difference between the address of the area where the musical tone data and the processing program are stored. The program reading can be switched. This example is based on the MMU latch 310, the selector 312, and the ROM 20 shown in FIG. 4. The CPU addresses CA1 to CA15 are selected at the time of reading a program, and the CPU addresses CA12 to 1 are read at the time of reading timbre data.
Only 5 is changed to the MMU address, and all are switched to the frequency numper accumulated value when reading the waveform data.

Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings.

<Overall Circuit> FIG. 1 shows an overall circuit diagram of the present invention. Each key of a keyboard 1 and each switch of a tone switch 2 are scanned by a key assigner circuit 30 and have a pitch corresponding to an operation key. A tone of a tone corresponding to the operation tone switch is assigned to an empty channel of the 16 tone generation system.
This channel assignment content is stored in the assignment memory circuit 32.

The ROM 20 stores a processing program for generating a tone signal, timbre data relating to a waveform and an envelope, and the waveform data RD itself, and a read address is controlled by a ROM address control circuit 31. And reading of the waveform data RD is switched. The processing program read from the ROM 20 is sent to a CPU 300, which will be described later, of the key assigner circuit 30 to execute various types of processing.In addition, the tone data relating to the waveform and envelope read from the ROM 20 is
The waveform data RD itself written in the area corresponding to the empty channel of the assignment memory circuit 32 and read from the ROM 20 is sent to the waveform data decompression interpolation circuit 50. In the assignment memory circuit 32, the frequency number speed data FS corresponding to the operation key of the keyboard 1 is also written in the area corresponding to the empty channel.

The frequency number speed data FS is sequentially accumulated for each channel by the frequency number accumulator 40, is given to the ROM 20 via the ROM address control circuit 31 as read address data, and the waveform data RD is the frequency number speed data FS. , Ie, at a speed corresponding to the pitch, and is input to the waveform data decompression interpolation circuit 50. A large number of the read waveform data RD are stored in the ROM 20, and the selection is made by the bank data read from the assignment memory circuit 32. In the waveform data decompression interpolation circuit 50, the ROM 20
The difference data thus read out is expanded, and an interpolation point between sample point points of each waveform data RD is also obtained and sent to the multiplication circuit 70. This interpolation is performed using a part of the frequency number accumulated value FA from the frequency number accumulator 40.

The data on the envelope from the assignment memory circuit 32 is sent to the envelope generator 60 to generate an envelope waveform, which is sent to the multiplication circuit 70. The multiplication circuit 70 multiplies each sample value of the above-described expanded interpolation waveform data IP by each sample value EA of the envelope waveform, performs data shift in the shift circuit 80, and accumulates each sequence in the sequence accumulation circuit 90. The sound is output from the sound system 110 via the DA converter 100.

The current phase value PH of the envelope waveform is sent from the envelope generator 60 to the assignment memory circuit 32, and acts to output envelope data for the next new phase. Further, an ON event signal is sent from the envelope generator 60 to the frequency number accumulator 40 at the key-on timing, and accumulation of the frequency number speed data FS is started. Further, a data length signal D816 is sent from the envelope generator 60 to the waveform data decompression interpolation circuit 50, and selection is made whether interpolation of the waveform data RD is performed or not. The data length signal D816 indicates whether the waveform data RD is made up of two 8-bit sample values or a 10-bit sample value and 6-bit difference data. Is read out, interpolation of the waveform data RD is performed.

The shift circuit 80 shifts down the multiplied musical tone data in accordance with the magnitude of the envelope power data EA12 to 15, which are the upper bits of the envelope accumulated value EA, and exposes the fall when the decay and release decay. The purpose is to make the sound characteristics similar to natural sounds.

In the DA converter 100, four tone generation systems are formed in a time-division manner. In the sequence accumulation circuit 90, any of the generation systems is set in accordance with the sequence data GR from the assignment memory circuit 32. Is determined. The sequence accumulator circuit 90 includes a frequency number accumulator.
From 40, a waveform return signal FDU is given, and this waveform return signal FDU becomes high level when generation of the first half of the first half of one waveform of the waveform data is completed and when the second half of the waveform is generated, Thereby, in the sequence accumulation circuit 90,
This is a value obtained by inverting the musical tone data by plus or minus. In addition, the key is assigned to the series accumulation circuit 90 by the key assigner circuit 30.
A -A gate signal is also supplied, and the output of musical sound data to the DA converter 100 is controlled.

From the system clock generator 10, each circuit 30 in FIG.
Clock signals and the like as shown in FIG. 2 are given to 40, 50, 60, and 90, and the timing of each circuit is controlled.

<ROM 20> FIG. 3 shows the stored contents of the ROM 20. The ROM 20 has a processing program for generating a tone signal, tone color data for selectively determining the contents of the waveform and the envelope, and each sample value of the waveform. And stored waveform data RD. The storage area of the timbre data is located at a position shifted from the storage area of the processing program by the MMU address data described later. The timbre data consists of bank data, data length signal data D816, sequence data GR, initial frequency number data, rape top data, loop end data, and envelope data, and the envelope data further includes phase level data PL and envelope adjusted signal data EDU. , Thin-out data TH, and envelope speed data ES.

The bank data is used to select and designate one of a plurality of waveform data RD. For one tone color assigned to one channel, two waveforms (A) and (B) are selected, and a data length signal is selected. D816 indicates whether the waveform data RD is composed of two 8-bit sample values or a 10-bit sample value and 6-bit difference data, as described above. As you did,
This shows to which of the four tone generation systems the tone data ST after the multiplication is assigned.

As shown in FIG. 8, the initial frequency number data indicates the frequency number accumulated value at the start at the time of sequentially accumulating the frequency number speed data FS and reading out the waveform data RD, and the loop end data indicates Indicates the frequency number accumulated value FA at the point where the accumulation of the frequency number speed data FS is turned from the addition direction to the subtraction direction, and the loop top data wraps the accumulation direction of the frequency number speed data FS from the subtraction direction to the addition direction. The frequency number accumulated value FA at the point is shown. As shown in FIG. 8, the frequency number accumulated value FA is loop-changed between the loop top and the loop end, so that the waveform data for a half waveform is continuously outputted. Reading can be performed in a waveform state.

The waveform folded signal FDU in FIG. 8 is the most significant bit data of the frequency number accumulated value FA, and the generation of the first half of the wavelength of the waveform data is completed. When the signal FDU is at the high level, the switching of the addition / subtraction operation of the frequency number accumulated value FA and the plus / minus switching of the sample value (amplitude value) of the waveform data (tone data) are performed based on the signal FDU.

Envelope level data in envelope data
EL is an envelope waveform ack, as shown in Fig. 24.
Indicates the accumulated value of the envelope at the end point of the decay, sustain, and release, and the envelope addition / subtraction signal data
EDU indicates whether to add or subtract the envelope accumulated value EA. The envelope speed data ES of the envelope data is data indicating the acceleration / deceleration of the accumulated value EA of the envelope. The larger the value, the larger the slope of the envelope waveform. Envelope speed data ES and envelope level data EL
It is determined according to the key pressing speed of the key of the keyboard 1 or the key touch data corresponding to the key pressing pressure.

The thin-out data TH in the envelope is the envelope accumulated value EA to the accumulation system of the envelope accumulated value EA.
And the data indicating the thinning rate of the latch, and the latch of the original envelope accumulated value EA is performed once in the time slot for all the channels that is repeatedly performed. When this data is "11", there is no thinning, "10"
In the case of, take in once in four times, in the case of "01", take in once in 16 times, and in the case of "00", take in once in 64 times. 0 and 1 indicate a low state and a high state of the binary logic level. By this thin out (take-in latch thinning),
Even with the same envelope speed data, the envelope speed can be changed to 1, 4, 16, or 64 times. The shift-out data TH may also be changed according to the key pressing speed of the key of the keyboard 1 or the key touch data corresponding to the key pressing pressure.

As described above, since the ROM 20 stores the processing program for generating and emitting a musical tone and the musical tone data representing the content of the musical tone, only one memory for storing the program and the data is required, and the circuit The configuration can be simplified.

<Key Assigner Circuit 30> FIG. 4 shows the key assigner circuit 30, in which the CPU 300
Is operable only when the applied master clock signal φ (CK2) is at a high level. As shown in the lower part of FIG. 2, the master clock signal CK2 is high on the data bus line and the address bus line of the CPU 300. When the level is “1”, data relating to the CPU 300 flows, and the low level is “0”.
In this case, data unrelated to the CPU 300 flows.

<< ROM Address Control Circuit 31 >> Although the address data CA0 to CA15 for accessing the ROM 20 and various memories from the CPU 300 are 16-bit data, the lower 11 bits CA1 to 11 excluding the least significant bit are given to the selector 313. The upper 4 bits CA12 to 15 are set to "00"
00 ”is added, and the B
Through the input, it is supplied to the ROM 20 via the selector 313 as 19-bit address data together with the lower 11 bits CA1 to CA11, and the processing program is mainly read.
When the CPU 300 reads tone data and other data other than the processing program, 8-bit MMU address data is output from the CPU 300 through the data bus line, and this is output through the selector 312 through the MMU latch 310 and the lower 11 bits CA1 described above. 11 are provided to the ROM 20 via the selector 313.

FIG. 5 shows the switching state of the address data. Although the address data of the ROM 20 is 19 bits, the address data of the CPU 300 is 16 bits. MMU address data is added.

In this way, the reading of the program and the reading of the timbre data can be easily switched by adding the MMU address or adding “0000”. Further, even when the read address data of the CPU 300 is smaller in the number of bits than the read address data of the ROM 20, the entire area of the ROM 20 can be read.

The upper 4-bit data CA12 to CA15 are supplied to the comparator 311.
This comparator 311 is also supplied with 4-bit f (x) data. When the two data do not match, "0000" and the upper 4-bit address data CA12
~ 15 is selected. When the two data match, a match signal is provided from the comparator 311 to the selector 312, and the MMU latch 310 is selected. Therefore, when the upper 4-bit address data CA12 to CA15 do not match the f (x) data, the processing program of the CPU 300 is read, and when they match, the tone color data and the like are read.
The f (x) data may be selected and set by the CPU 300 or may be a fixed value.

The selector 313 includes an assignment memory 3 described later.
2, the bank data read by the CPU 300 and the frequency number accumulated values FA12 to 26 from the frequency number accumulator 40 are also given, and given to the ROM 20 via the selector 313.
The waveform data RD of the corresponding bank is read. Data selector switching in the selector 313 is performed by a clock signal CK2 from the system clock generator 10, and switching between reading of a processing program and reading of a sample value of waveform data RD is performed as shown in the lower part of FIG. . Among these, at the timing of reading the processing program, the reading of the processing program and the reading of the timbre data are switched based on the f (x) data. Then, these reading processes are repeatedly performed for 16 channels.

Of the data read from ROM 20, waveform data RD
Is sent to the waveform data decompression interpolation circuit 50 as it is, and the processing program and timbre data are divided into two by 8 bit data and sent to the CPU 300 via the selector 314 or to the assignment memory 320 via the gate buffer 323. And others. The data selector switching in the selector 314 is performed by switching the least significant bit of the address data CA from the CPU 300.
Performed based on CA0.

Thus, data is taken in from the ROM 20 following the processing speed of the CPU 300. Further, even if the number of bits of data read from the ROM 20 is larger than the number of bits of the data bus line of the CPU 300, data processing can be performed smoothly.

<< Assignment Memory Circuit 32 >> FIG. 6 shows the storage contents of the assignment memory 320 of the assignment memory circuit 32. The assignment memory 320 has a memory area of 16 channels of timbre data. The timbre data from the ROM 20 is set in each channel area. In this case, among the tone data to be set, the envelope data is set in each of the envelope group areas EG0 to EG15, and the other data is set separately in the respective channel areas of CH0 to CH15. Data set in CH0 to CH15 are bank data (A) and (B), envelope group data (A)
(B), frequency number speed data FS, key-on signal data, data length signal data D816, sequence data GR, initial frequency number data, loop top data, loop end data, of which frequency number speed data FS, key-on For data other than signal data and envelope group data (A) and (B),
This is as described for the storage contents of the ROM 20.

The frequency number speed data FS is data corresponding to the pitch of the operation key of the keyboard 1 and is used as an accumulation step value of the read address data of the waveform data RD. The key-on signal data is data indicating that the key is currently on, and is "1" for key-on and "0" for key-off.
The envelope group data (A) and (B) are data indicating the addresses of the envelope group areas EG0 to EG15 in which the envelope data corresponding to the tone color of the channel area is stored. Two tone colors are assigned to one channel. Because it is composed of musical sounds,
(A) and (B) exist. Accordingly, since there are two waveform data RDs, there are two bank data (A) and (B). The envelope data set in EG0 to EG15 is also as described in the description of the storage contents of the ROM 20 described above.

The data read from the assignment memory 320 is sent to the frequency number accumulator 40, the envelope generator 60, and the like via an AM (assignment memory) bus, or is supplied to the CPU 300 via the gate buffer 322. Also 4
As for the bit envelope group data (A) and (B), the phase data PA from the envelope generator 60 is added to the lower two bits via the latch 324, and is set to "1".
Is added to the upper bit by one bit to make a total of 7 bits, and is again provided to the assignment memory 320 via the selector 321.
Envelope level data EL of the corresponding envelope,
The thin-out data TH, the envelope speed data ES and the like are sent to the read envelope generator 60. Read address data, which is a set of clock signals CK from the system clock generator 10, is also supplied to the assignment memory 320 via the selector 321, and also access address data from the CPU 300 is supplied.

The switching state of these address data is shown in the second section.
It is a time chart at the bottom of the figure. After reading out bank data (A) and (B) and envelope group data (A) and (B) based on a clock signal group CK, and subsequently reading out frequency number speed data FS, The envelope speed data (A) ES and the envelope level data (A) EL based on the envelope group data (A) and the phase data PA are read, and thereafter, the CPU 300 accesses. Similarly, the initial frequency number, key-on, data length signal data D816, and sequence data GR based on the clock signal group CK are read, followed by the loop top data and the loop end data. (B) and envelope speed data based on phase data PA (B)
The ES and the envelope level data (B) EL are read, and thereafter the CPU 300 accesses. These access processes are repeated for 16 channels.

In this case, as the clock signal group CK used as read address data, CK1 to CK in FIG. 2 are used. The selection of each address data in the selector 321 is performed based on the clock signals CK1 and CK2 from the system clock generator 10, and the clock signal group CK is selected at timings of “00” and “01”, and is selected at “10”. The envelope group data and the phase data PA from the latch 324 are selected, and the address data from the CPU 300 is selected at "11".

The RAM 301 stores various types of intermediate processing data, and the timer 302 outputs an interrupt signal at a cycle set by the CPU 300.
The reset circuit 303 resets the CPU 300 and the output latch 304 when the power is turned on. The output latches 304 and 306 have a tone switch 2,
The sampling address of the keyboard 1 is temporarily set, and the sampling results are input to the input buffers 305 and 307. Only one bit of the sampling data of the output latch 304 is the DA converter.
Used as 100 gate signals.

<Frequency Number Accumulator 40> FIG. 7 shows the frequency number accumulator 40. The frequency number speed data FS from the assignment memory circuit 32 is transmitted via a latch 404 to an exclusive OR gate group 405. Via the adder 407, is accumulated to the frequency number accumulated value FA so far, the upper 8 bits FA19 to 28 are through the selector 413, the lower 19 bits FA0 to 18 are through the exclusive OR gate group 414, Via the latch group 415 and the selector 416, the adder 40 is again used as the frequency number accumulated value FA.
Given to 7. As a result, the frequency number accumulated value FA is accumulated at a speed corresponding to the size of the frequency number speed data FS, and the accumulated value FA is transferred via the latch 418 to the 15-bit FA12 to 26 corresponding to the upper integer part. The reading of the waveform data RD sent to the ROM address control circuit 31 is performed. The waveform return signal FDU of the upper three bits FA9 to 11 and the most significant bit of the decimal part is sent to the waveform data decompression interpolation circuit 50, and is used for decompression and interpolation of the sample value of the waveform data RD.

FIG. 9 shows the contents of the frequency number accumulated value FA. The frequency number accumulated value FA is 28-bit data in total, and the most significant bit is the waveform folding signal FDU.
Then, the next 8 bits FA19 to 26 are comparison bits, which are used for comparing a loop end described later or whether or not the loop top has been reached. Further, the next 7 bits FA12 to 18 are an integer part, and the last 12 bits. FA0 to 11 are decimal parts.
Such frequency number speed data FS is CH0 to CH15.
The 16 channels are accumulated by the frequency number accumulator 40,
The accumulated frequency number FA of each channel is calculated by the latch group 41
5 is stored in the memory. This latch group 415 is composed of 16 latches, and has the same read address (the same frequency number accumulated value FA12 to FA26) for two tone components (A) and (B).
Is used. The difference of tone is the above bank data (A)
(B).

Also, the 8-bit initial frequency number from the assignment memory circuit 32 is supplied to the selector 416 via the latch 406, where the upper 1 bit is “0” and the lower 19 bits are “00.
"0" is added and the selector is selected as 28-bit data which is the same as the frequency number accumulated value FA. As the selector signal in the selector 416, an on-event signal output at the key-on timing from the envelope generator 60 is used, and as shown in FIG. Data FS is accumulated.

Further, the loop end data and the loop top data from the assignment memory circuit 32 are transmitted via the latch 402,
Either the loop end or the loop top is selected by the selector 403 and is supplied to the comparator 409 and also to the selector 413. In the comparator 409, the upper 8 bits of the frequency number accumulated value FA
When the comparison with 19 to 26 is performed and the frequency number accumulated value FA exceeds the range between the loop end of the loop end, the selector 410 outputs the overrun signal FCP, and the OR gate
Via 411, the exclusive OR gate group 414 and the selector 413 are supplied to the above-mentioned exclusive OR gate group 414, and the loop end data or the loop top data is taken in as new data instead of the upper comparator bits FA19 to 26 of the frequency number accumulated value FA. . At this time, the exclusive OR gate group 41
In FIG. 4, the values of the integer part and the decimal part of the frequency number accumulated value FA up to that point are inverted plus or minus. This is because when the reading direction of the waveform data RD is inverted at the loop end or the loop top, The frequency number accumulative value FA is used as it is in a state where the fraction of the accumulated value FA is plus / minus inverted to provide consistency in inversion reading of the waveform data RD.

The overrun signal FCP is also given to the exclusive OR gate 412, and inverts the waveform folding signal FDU, which is the most significant bit of the frequency number accumulated value FA. The value of FS is inverted plus or minus, and the direction of accumulation of the frequency number accumulated value FA in the adder 407 is switched between increasing and decreasing. FIG. 8 shows a state of loop reproduction for each half-waveform due to the switching of the frequency number speed data FS.

The waveform folding signal FDU is supplied to the selectors 403 and 410 as a selector signal, and the frequency number speed data
When FS is added, the loop end data and A <B detection signal are selected, and when subtracted, the loop top data and A> B
The detection signal is selected. In addition, the waveform folding signal FDU
Is also input to the Cin terminal of the adder 407, and the frequency number accumulated value FA at the time of subtraction of the frequency number speed data FS is +1.
In addition to performing the processing, it is also provided to an exclusive OR gate 408. An output signal from the Cout terminal of the adder 407 is also given to the exclusive OR gate 408, and it is detected that the frequency number accumulated value FA has overflowed or underflowed, and this is also output as the overrun signal FCP. You.

Further, the bank data (A) and (B) from the assignment memory circuit 32 are sent through the latch 400, one of the bank data (A) and (B) is selected by the selector 401, and is sent through the latch 417. Is transmitted to the ROM address control circuit 31 together with the integer part of the above-described accumulated frequency number FA and the comparison bit, and the waveform data RD is read.

As a result, although the two tone components (A) and (B) assigned to one channel have different bank data, a common frequency number accumulated value FA is used, and the timing of the tone generation process is synchronized. .

The clock signal CK3 from the system clock generator 10 is used as the selector signal of the selector 401. The tone generation processing is performed for (A) in the first half of the clock signal CK3, and the tone generation processing for (B) is performed in the second half. Processing will be performed. The clock signal group CK from the system clock generator 10 corresponds to the latches 400, 402, 404, 406, 41
5, 417 and 418 are also provided as latch signals to synchronize the channel cycle and timing.

<Waveform Data Expansion Interpolation Circuit 50> FIG. 10 shows the waveform data expansion interpolation circuit 50.
The difference data in the waveform data RD as shown in FIG. 14 is expanded by the gates 500 to 510 and the selectors 511 to 513, and the gates 514 to 517, the gate groups 518, 519, the adder 520, and the selector 5 are expanded.
Each sample value of waveform data RD as shown in Fig. 12 at 21
Interpolation of R ₀ , R ₁ , R ₂ , R ₃ … is performed, and the gate group 524, 522, the gate 526, the selector 525, and the adder 527 generate 10 waveform data RD.
Interpolation is performed for a bit sample value and 6-bit difference data (D816 = 0), and no interpolation is performed for two 8-bit sample values (D816 = 1).

<< Outline of Data Processing of Waveform Data Decompression Interpolator 50 >> FIG. 13 shows the data structure of waveform data RD read from the ROM 20. The data length signal D816 is a low-level 10-bit sample value and 6 bits. When the data consists of bits and differential data, the upper 10 bits RD6 to 15 are sample values, RD5 is differential code data, RD2 to 4 are differential power data, RD0, 1
Is difference Mantissa data. Difference data RD
0 to 4 are stored in a compressed state, and when expanded, become 10-bit expanded difference data IE0 to IE8 and IES as shown in FIG. In other words, the difference power data RD2 to RD4 are data indicating the first bit of the difference value where "1" is present, and the difference mantisser data RD0 and RD1 are two bits of data following the "1". It shows itself. Thus, the data in the upper part of FIG. 14 is for adding the decompression difference data, while the data in the lower part is for subtraction. In this case, the difference power data RD2 to RD4
Is the data indicating how many bits of the difference value “1” continues, and the exchanged difference mantisser data RD0
.About.2 are obtained by converting the differential mantisser data RD0, RD1 by the logical expression shown in the lower part of FIG. 14, and the contents of the conversion are as shown in FIG.

Such expanded difference data IE0 to IE8 and IES are の of the difference between the sample values of the waveform data RD indicated by the large circles in FIG.
And indicates the difference between each sample value and the virtual value indicated by the mark x. The virtual values in FIG. 12 overlap with the interpolation values and are in a state in which the crosses are superimposed on the crosses.

Since the sample values R ₀ , R ₁ , R _2, ... Of the waveform data RD are obtained when the decimal number of the frequency number accumulated value FA is 1/2, X in FIG. 11 (2) and FIG. In order to execute the waveform connected by the mark, it is only necessary to store the sample value of the intermediate point between each of the sample values G ₀ , G ₁ , G ₂ ,. The sample value of this intermediate point is R ₀ = (G ₀ + G ₁ ) / 2, R ₁
= (G ₁ + G ₂ ) / 2, R ₂ = (G ₂ + G ₃ ) / 2.

In this way, by storing the sample value of the midpoint of the cross instead of the sample value of the cross, the frequency number accumulated value FA becomes "00" as shown in FIGS. 12 and 11 (2). …
The waveform data level is exactly "0" at the starting point of "0"
Can be That is, the waveform data RD of the ROM 20
In the first address of the memory area, waveform data RD which is not the “0” level in the first step is normally stored. When the frequency number accumulated value FA is “00... 0”, this first step is performed. Even if a process for preventing reading is not performed, the phase can be automatically adjusted by storing the sample value of the intermediate point, and a phase shift as shown in FIG. 11 (1) may occur. Disappears.

Further, the difference data between the midpoint of the mark x and the interpolation points before and after the midpoint is the same before and after, and as a result, the difference data to be stored is only 1/2 of the original difference data.
Therefore, when the sample value of the normal waveform data RD is 10 bits, the difference data is 10 bits. Even if the above-described compression method is used, the number of bits of the difference power data is 4 bits. Although the data is compressed to only 7 bits, the difference data can be reduced to half as described above, so that the difference data can be reduced to 6 bits, so that a total of 16 bits can be accessed once in normal data access.

Therefore, the waveform data RD and the program (or timbre data) are alternately read from one ROM 20, so that even if the chance of reading the waveform data RD per unit time is reduced by half, it is possible to cope with the situation.

Note that the stored waveform data RD may be a waveform in which the X points are connected in a polygonal line.

If 1/4, 2/4, 3/4, and 4/4 of the above-described decompression difference data are added to or subtracted from the sample values as shown in FIG. 16, an interpolation value is obtained. In this case, each sample value in Fig. 12
For R ₀ , R ₁ , R ₂ , R ₃ …, E ₀ , D ₁ , D ₂ , D ₃ …
When the interpolated value is larger, the decompressed difference data becomes an added value as shown in the upper part of FIG. 14, and when the interpolated value is smaller, such as D ₀ , E ₁ , E ₂ , E ₃ . The difference data is a subtraction value as shown in the lower part of FIG.

There are two types of data format of the waveform data RD: 10-bit data format and 8-bit data format. The noisy quantization noise does not cause much problem even if the number of quantization bits is reduced. The sound that is noticeable is properly used as 10 bits, and uses less memory.

<< Circuit Configuration of Waveform Data Decompression Interpolation Circuit 50 >> In FIG.
The difference Mantissa data RD0 is directly input to the terminal “1”. The A side “1” terminal and the B side “2” terminal of the selector 511 have the most significant bit IE of the decompression difference data.
When S is “0”, the differential mantissa data RD1 is input as it is, and when the most significant bit IES is “1”, the AND gate 502 is opened.
Exclusive OR data RG1 of D0 and RD1 is input. Further, when the most significant bit IES is "0", the output of the NAND gate 505 becomes "1" and the exclusive OR gate 506 outputs the NOR gate to the "2" terminal on the A side and the "3" terminal on the B side of the selector 511. Since the output of 509 is inverted, the logical sum of the difference power data RD2 to RD4 is input and the most significant bit I
When ES is “1”, exclusive OR data RG2 of the inverted data of the OR of the difference mantisser data RD0 and 1 by the OR gate 504 and the inverted data of the OR of the difference power data RD2 to RD4 is input. . The most significant bit IES is input to the “3” terminal on the A side of the selector 511,
“0” data is input to the side “0” terminal.

As a result, as shown in FIG. 14, data of the differential mantissa data RD0, RD0, 1 and the upper bits, or data of the converted differential mantissa data RD0, RD1, 1, 2 are created. The specific contents of the exchange difference mantisser data RG0 to RG2 are as shown in FIG.

The 4-bit data of the selector 511 is
At 513, it is selected whether the uppermost bit IES is added by 2 bits or 4 bits or the lower "0" data is added by 2 bits or 4 bits, and is output as 10-bit data. . By appropriately selecting the select state of each of the selectors 511, 512, 513, the difference mantisser data RD0,
1 can shift RG0 to RG2 as shown in FIG. 14, and the selection of this selection state is based on the difference power data.
This is performed based on RD2-4.

In this way, the expanded differential data can be expanded to 10 bits, even though the differential compressed data is 6 bits, and the memory usage can be reduced.

The most significant bit IES of the expanded differential data is the difference code data RD5 of the input of the exclusive OR gate 500, the most significant bit FA11 of the decimal part of the frequency number accumulated value FA of the input of the NOR gate 501, and the most significant bit FA11 of the NOR gate 508. It is determined by the inverted data of the logical sum of the bits RD0 to RD4 of the difference data. That is, as shown in FIG. 12, FA11 of D ₀
Is “0” and the difference code RD5 is “0” (addition direction), and when FA11 of E ₁ , E ₂ ... Is “1” and RD5 is “1” (subtraction direction), The most significant bit IES becomes “1”, indicating that the difference data must be subtracted from the sample value. The NOR gate 501 receives the inverted data of the logical sum of the bits RD0, 1, 2, 3, 4, and 5 of the difference data, and outputs the difference data of "0000".
At the time of “0”, the output of the NOR gate 501 is set to “0”, and control is performed so that the most significant bit IES of the decompression difference data does not become “1”.

The decompression difference data IE is shifted down by one bit and
The value of 4 is input to one terminal of the adder 520 via the AND gate group 519, and is also shifted down by 2 bits to a 1/4 value to be added to the adder 520 via the AND gate group 518.
The output of the adder 520 is supplied to the A side of the selector 521. On the B side of the selector 521, the decompressed difference data IE is not shifted but is given at the same magnification. Therefore, the AND gate group 518, 519
As shown in FIG. 16, the expansion difference data IE is 1/4 times, 2 times, as shown in FIG. 16, by appropriately selecting the rate data IM including the opening signals IM0 and IM1 and the selection signal IM2 of the selector 521.
/ 4 times, 3/4 times, 4/4 times, 0 times.

The extended difference data IE having such a multiplication factor is given to the adder 527 via the AND gate group 522, and is added to or subtracted from the sample values RD6 to RD15 of the waveform data RD described later. Interpolation will be performed.

Thus, one sample value RD6 to RD15 and the difference data RD0
5, the waveform data RD can be created at eight points, smooth waveform characteristics can be obtained, and the memory capacity can be reduced. Waveform data RD that can determine eight points with one such data
Can be read in one read, and the waveform data RD
A sufficient smooth waveform can be realized even if there is little opportunity to read the waveform data.As a result, even if the waveform data RD and other programs are read alternately from the ROM 20, the waveform generation processing will not be disturbed, and Even if the program and the waveform data RD are stored together, it is not necessary to increase the reading speed of each information.

The above-mentioned multiplication data IM0 to 2 are determined by the upper 3 bits FA9 to 11 of the decimal part of the frequency number accumulated value FA.
Created by 14-517. By the gate groups 514 and 517, data conversion as shown in FIG. 16 is performed, and an interpolation value of the waveform data RD is obtained. in this case,,
When only the most significant bit FA11 of the decimal part of the frequency number accumulated value FA is “1”, that is, when the frequency number accumulated value FA is 1 /
In the case of 2, no interpolation is performed on the sample value, and the interpolation value becomes a subtraction value of 1/4, 2/4, 3/4, 4/4 of the difference data at the timing before this centered at this point. , At later timing, the interpolation value is 1/4, 2/4, 3/4
Is the added value of

When the waveform data RD0 to RD15 consist of a 10-bit sample value and 6-bit difference data, the sample value RD6
.About.15 are input from the A side of the selector 525, and are given to the adder 527 as they are, and the interpolation value is adjusted. At this time, since the data length signal D816 becomes "0", the AND gate groups 524 and 522 are opened, the AND gate 526 is closed, and the selector 525 selects the A side. When the waveform data RD0 to RD15 consist of two 8-bit sample values, the waveform data RD0 to RD7 are input from the B side of the selector 525 and are given to the adder 527. And is given to the adder 527. At this time, each data RD0-7, 2
Bit “00” is added to form 10-bit data. At this time, since the data length signal D816 is "1",
The AND gates 524 and 522 are closed and no interpolation is performed. Further, at this time, since the AND gate 526 is opened, the most significant bit of the decimal part of the frequency number accumulated value FA is obtained.
Depending on the value of FA11 (1, 0), the sample value (2n = RD0-
7, 2n + 1 = RD8-15).

The present invention is not limited to the above embodiment, and can be variously modified without departing from the spirit of the present invention. For example, the program read by one reading may be an 8-bit program, and the means for storing data and the program may be an integrated ROM and RAM, a magnetic memory, an optical memory, or the like. The reading means of CPU3
00, a device other than the frequency number accumulator 60 may be used, and switching between data and program reading may be performed by a device other than the MMU address data and the clock signals CK1 to CK7.

[Effects of the Invention] As described in detail above, according to the present invention, the present invention stores data and programs for musical sounds in an integrated storage means, thereby making the storage device compact and simplifying the circuit configuration. In addition, by simply switching the read address data by the difference between the address of the data and the address of the area where the program is stored, the switching between the data and the program can be performed, and the process of reading the information can be simplified. It has effects such as becoming.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of the present invention, FIG. 2 is a time chart of each part in FIGS. 1 and 4, and FIG.
FIG. 4 is a diagram showing the contents stored in the ROM 20, FIG. 4 is a circuit diagram of the key assigner circuit 30, FIG. 5 is a diagram showing the correspondence between the address data of the CPU 300 and the address data of the ROM 20, and FIG. FIG. 7 is a diagram showing the storage contents of the assignment memory 320, FIG. 7 is a circuit diagram of the frequency number accumulator 40, FIG. 8 is a diagram showing a state of reading waveform data, and FIG. FIG. 10 is a circuit diagram of a waveform data decompression interpolating circuit 50, showing the correspondence between sample values for half a wavelength of waveform data and readout timing in FIG. 11. FIG. 12 is a diagram showing sample values and interpolation values of waveform data, and FIG.
FIG. 14 is a diagram showing the contents of the waveform data RD, FIG. 14 is a diagram showing the expanded contents of the difference data RD0 to RD5 of the waveform data, and FIG. FIG. 9 is a diagram showing the contents of conversion to
Figure 16 shows the high-order bit FA9 of the decimal part of the accumulated frequency number.
FIG. 11 is a diagram showing a relationship between the interpolation data IM0 to 2 of difference data and the interpolation contents of sample values of waveform data. 20 ROM: 30 Key assigner circuit 31 ROM address control circuit 32 Assignment memory circuit 40 Frequency number accumulator 50 Waveform data decompression interpolator 60
... Envelope generator, 70 Multiplying circuit, 80 Shift circuit, 90 Sequence accumulating circuit, 300 CPU, 320 Assignment memory.

Continuation of the front page (72) Inventor Yoichi Nagashima 200 Terashimacho, Hamamatsu-shi, Shizuoka Prefecture Kawai Musical Instruments Manufacturing Co., Ltd. (56) References JP-A-51-60515 (JP, A) JP-A-60-149092 (JP, A) JP-A-63-143594 (JP, A)

Claims (7)

(57) [Claims] 1. A data storage section provided in a storage means for storing musical tone waveform data relating to a musical tone, and a program storage section also provided in the storage means for storing a processing program for generating or controlling a musical tone. First read address data generating means for generating read address data for periodically reading the tone waveform data from the storage means for each of a plurality of channels; and reading by the first read address data generating means. Processing means for processing the generated musical tone waveform data, and means separate from the first read address data generating means for sequentially reading out the processing program of the central processing unit from the storage means as the processing proceeds. Second read address data generating means for generating read address data; A central processing unit for performing processing based on the processing program read by the generating means; and a read address data from the first read address data generating means and a read address data from the second read address data generating means. A tone information processing apparatus comprising: an address switching unit that alternately switches at predetermined intervals and supplies only one of the read address data to the storage unit. 2. A data storage section provided in the storage means for storing musical sound data relating to musical sounds, and a program provided in the storage means and different from the program for processing the musical sound data. A program storage unit for storing a processing program for generating or controlling; a first read address data generating unit for generating read address data for reading musical tone data from the storage unit; First processing means for processing the musical tone data read by the means, and means separate from the first read address data generating means, wherein read address data for reading a processing program from the storage means are read out. The second read address data generating means generated, and the second read address data generating means Means for performing processing based on the read processing program, the second processing means being different from the first processing means, and read address data from the first read address data generating means. Address switching means for alternately switching the read address data from the second read address data generating means at predetermined intervals and supplying only one of the read address data to the storage means. Music information processing device. 3. The second read address data generating means and the second processing means or the central processing unit reads a processing program from the program storage unit and performs control for allocating the musical tone to a channel. 3. The musical tone information processing apparatus according to claim 1, wherein 4. The musical tone information according to claim 2, wherein said first read address data generating means and said first processing means read musical tone waveform data from said data storage unit and generate musical tone. Processing equipment. 5. The address switching means for switching between the read address data from the first read address data generating means and the read address data from the second read address data generating means in a time sharing manner. The musical sound information processing apparatus according to claim 1, 2, 3, or 4, wherein: 6. A processing program in said program storage section is read out by a central processing unit, and said tone data in said data storage section is for each tone channel formed by time-division processing for processing tone data. 3. The musical tone information processing apparatus according to claim 2, wherein the musical tone information is sequentially read out for each of the channels. 7. The method according to claim 1, wherein the data is read out once from the data storage unit.
4. The method according to claim 1, wherein a plurality of steps of tone data or tone waveform data are read, and a plurality of steps of a processing program are read from the program storage unit by one reading. A musical tone information processing apparatus according to 4, 5, or 6.