JP3176901B2 - Music sound information processing apparatus and music sound information processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical sound information processing apparatus for processing information for generating musical sounds.

[0002]

2. Description of the Related Art Conventionally, data representing a musical tone and a processing program for generating or controlling the musical tone are stored in separate storage devices, and the musical tone data and the processing program are read by separate reading devices. Was. In this case, the read address data of each read device is controlled completely independently.

[0003]

However, separately providing a storage device for musical sound data and a storage device for a processing program complicates the circuit configuration and causes an increase in cost. In addition, providing such separate storage devices requires that the read address data be controlled completely independently, complicating information processing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a tone information processing apparatus having a simple circuit configuration and a simple information reading process.

[0005]

In order to achieve the above object, the present invention provides a data storage means for storing musical sound data relating to musical sounds, and a program storing means for storing a processing program for generating or controlling the musical sounds. Are provided integrally with each other, and switching means for switching reading between both storage means is provided. As a result, the tone data and the processing program can be stored in one storage means, and the read address data is switched only by the difference between the address of the area where the tone data and the processing program are stored. Can be switched.

One example of this is the MMU latch 310 of FIG.
The selector 312 and the ROM 20 select the CPU addresses CA1 to CA15 when the program is read, and the CPU addresses CA12 to CA15 when the timbre data is read.
Only the MMU address is changed to the MMU address, and all are switched to the frequency number accumulated value when reading the waveform data.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS << Overall Circuit >> FIGS. 1 and 2 show an overall circuit diagram of the present invention. Each key of a keyboard 1 and each switch of a tone switch 2 are scanned by a key assigner circuit 30, and FIG. A musical tone having a tone corresponding to the operation key and a tone corresponding to the operation tone switch is assigned to an empty channel of the 16-channel tone generation system. This channel assignment content is stored in the assignment memory circuit 32.

The ROM 20 stores a processing program for generating a tone signal, tone color data relating to a waveform and an envelope, and the waveform data RD itself. A read address is controlled by a ROM address control circuit 31, and the processing program is executed. Alternatively, reading of the tone color data and reading of the waveform data RD are switched.

The processing program read from the ROM 20 is sent to a CPU 300 (to be described later) of the key assigner circuit 30 to execute various processing, and tone data relating to waveforms and envelopes read from the ROM 20 is also stored in an assignment memory circuit. The waveform data RD itself written in the area corresponding to the 32 empty channels and further read out from the ROM 20 is sent to the waveform data decompression interpolation circuit 50. In the assignment memory circuit 32, the frequency number speed data FS corresponding to the operation key of the keyboard 1 is also written in the area corresponding to the empty channel.

The frequency number speed data FS is
The frequency number accumulator 40 sequentially accumulates the data for each channel, and stores the data in the ROM 20 through the ROM address control circuit 31.
Is provided as read address data, and waveform data RD
Is read out at a speed corresponding to the frequency number speed data FS, that is, at a speed corresponding to the pitch, and is input to the waveform data expansion interpolation circuit 50. Read waveform data RD
Are stored in the ROM 20, and these selections are made by bank data read from the assignment memory circuit 32.

The waveform data decompression interpolation circuit 50 decompresses the differential data read from the ROM 20 in a data-compressed state, and also obtains an interpolation point between sample points of each waveform data RD. The signal is sent to the multiplication circuit 70. This interpolation is performed by the frequency number accumulator 4
This is performed using a part of the frequency number accumulated value FA starting from 0.

The data on the envelope from the assignment memory circuit 32 is sent to an envelope generator 60 to generate an envelope waveform, which is sent to the multiplication circuit 70. The multiplication circuit 70 multiplies each sample value of the expanded interpolation waveform data IP by each sample value EA of the envelope waveform, shifts the data by the shift circuit 80, and accumulates the data for each sequence by the sequence accumulation circuit 90. And the sound system 1 via the DA converter 100.
The sound is output from 10.

From the envelope generator 60, the current phase value PH of the envelope waveform is sent to the assignment memory circuit 32, and acts to output envelope data for the next new phase. In addition, the envelope generator 60 outputs the frequency number accumulator 4
At 0, an on-event signal is sent at key-on timing, and accumulation of the frequency number speed data FS is started. Further, a data length signal D816 is sent from the envelope generator 60 to the waveform data decompression interpolation circuit 50,
A selection is made whether interpolation of the waveform data RD is performed or not.

The data length signal D816 is the waveform data RD
Indicates whether the data consists of two 8-bit sample values or 10-bit sample values and 6-bit differential data. When a 10-bit sample value and 6-bit differential data are read out, , The interpolation of the waveform data RD is performed.

The shift circuit 80 shifts down the multiplied musical tone data in accordance with the magnitude of the envelope power data EA12 to 15 which are the upper bits of the envelope accumulated value EA, and falls when the decay and release are attenuated. This is to make the sound more exponential and closer to natural sound.

In the DA converter 100, four tone generation systems are formed by time division. In the sequence accumulating circuit 90, any one of the tone accumulating circuits 90 is provided in accordance with the sequence data GR from the assignment memory circuit 32. Is determined whether or not the musical sound data is to be sent to the generation system. The sequence accumulating circuit 90 receives the waveform folded signal FD from the frequency number accumulator 40.
U is also given, and this waveform folded signal FDU has generated the first half of one waveform of the waveform data.
When the second half waveform is generated, the level becomes a high level, so that the sequence accumulation circuit 90 has a value obtained by inverting the tone data by plus or minus. The sequence accumulation circuit 90 is also supplied with a DA gate signal from the key assigner circuit 30, and controls output of musical sound data to the DA converter 100.

A clock signal or the like as shown in FIG. 3 is provided from the system clock generator 10 to each of the circuits 30, 40, 50, 60, and 90 in FIG. 1, and the timing of each circuit is controlled. .

<< ROM 20 >> FIG. 4 shows the contents stored in the ROM 20. The ROM 20 has a processing program for generating a tone signal, tone color data for selectively determining the contents of the waveform and the envelope, and each of the waveforms. Waveform data RD composed of sample values are stored. The storage area of the timbre data is
It is at a position shifted by MMU address data described later. The timbre data includes bank data, data length signal data D816, sequence data GR, initial frequency number data, loop top data, loop end data, and envelope data. The envelope data further includes phase level data PL and envelope adjusted signal data EDU. , Thin-out data TH, and envelope speed data ES.

The bank data is used to select and designate one of a plurality of waveform data RD. (A) and (B) correspond to one tone assigned to one channel.
Two waveforms are selected, and the data length signal D816 indicates whether the waveform data RD consists of two 8-bit sample values or a 10-bit sample value and 6-bit difference data, as described above. And the series data GR
As described above, the musical tone data ST after the multiplication is also 0 and 1 as described above.
Is assigned to any of the four tone generation systems.

The initial frequency number data, as shown in FIG. 9, indicates the frequency number accumulated value at the start at the time of sequentially accumulating the frequency number speed data FS and reading out the waveform data RD. Indicates the frequency number accumulated value FA at the point where the accumulation of the frequency number speed data FS is turned from the addition direction to the subtraction direction. The loop top data indicates that the accumulation direction of the frequency number speed data FS is changed from the subtraction direction to the addition direction. A frequency number accumulated value FA at a turning point is shown. As shown in FIG. 9, the frequency number accumulated value FA is loop-changed between a loop top and a loop end, so that waveform data for a half waveform is continuous. Can be read in the state of.

The waveform return signal FDU in FIG. 9 is the most significant bit data of the frequency number accumulated value FA, and the generation of the first half of one wavelength of the waveform data is completed.
The signal is at a high level when the second half wavelength is generated. Based on the signal FDU, the frequency number accumulation value FA is switched between addition and subtraction, and the waveform data (musical sound data) sample value (amplitude value) is switched. Is switched between plus and minus.

The envelope level data EL in the envelope data indicates the accumulated value of the envelope at the last point of the ack, decay, sustain, and release of the envelope waveform, and the envelope added / subtracted signal data EDU.
Indicates whether the envelope accumulated value EA is to be added or subtracted. The envelope speed data ES of the envelope data is data indicating the acceleration / deceleration of the envelope accumulated value EA. The larger the value, the larger the slope of the envelope waveform. Envelope speed data ES and envelope level data EL
Is determined according to the key pressing speed of the key of the keyboard 1 or the key touch data corresponding to the key pressing pressure.

Thin out data TH in the envelope
Is the data indicating the thinning rate of the latch for taking in the envelope accumulated value EA into the accumulation system of the envelope accumulated value EA. Once in a slot. When this data is "11", there is no thinning out, and when it is "10", it is taken once every four times,
When it is "01", it is taken once every 16 times, and when it is "00", it is taken once every 64 times. 0 and 1 are binary logic level l
It indicates an ow state and a high state.

This thin out (take-in latch thinning)
Thus, even with the same envelope speed data, the envelope speed can be changed to 1, 4, 16, or 64 times. This thin-out data TH may also be changed in accordance with the key pressing speed of a key of the keyboard 1 or key touch data corresponding to the key pressing pressure.

As described above, since the ROM 20 stores the processing program for generating and emitting a musical tone and the musical tone data representing the content of the musical tone, only one memory for storing the program and the data is required. The circuit configuration can be simplified accordingly.

<< Key Assigner Circuit 30 >> FIG. 5 shows the key assigner circuit 30, in which the CPU 300 can operate only when the applied master clock signal φ (CK2) is at a high level, as shown in the lower part of FIG. And CP
When the master clock signal CK2 is at the high level “1”, data relating to the CPU 300 flows through the data bus line and the address bus line of the U300, and when the master clock signal CK2 is at the low level “0”, data unrelated to the CPU 300 flows.

<< ROM address control circuit 31 >> This CP
The address data CA0 to CA15 for accessing the ROM 20 and various memories from the U300 are 16-bit data, but the lower 11 bits CA1 to 11 excluding the least significant bit are given to the selector 313. Also, the upper 4 bits CA
12 to 15 have 4-bit data of “0000” added to the upper bits, and the lower 1 bits are input through the B input of the selector 312.
The data is supplied to the ROM 20 via the selector 313 as 19-bit address data together with the 1-bit CA1 to CA11, and the processing program is mainly read.

When the CPU 300 reads out tone color data and other data other than the processing program, the CPU 3
00, 8-bit MMU address data is output through the data bus line, and this is added to the lower 11 bits CA1 to CA11 through the MMU latch 310 through the selector 312.
OM20.

FIG. 6 shows the switching state of the address data.
Although the address data is 9 bits, the address data of the CPU 300 is 16 bits, so that "0000" and MMU address data are added.

Thus, the MMU address is added or
By adding “0000”, it is possible to easily switch between reading the program and reading the timbre data. Also C
Even when the read address data of the PU 300 is smaller in bit number than the read address data of the ROM 20, the entire area of the ROM 20 can be read.

The upper 4-bit data CA12 to CA15 are also supplied to a comparator 311. The comparator 311 is also supplied with 4-bit f (x) data. When the two data do not match, "0000" is output. And the top four
Bit address data CA12 to CA15 are selected. When both data match, a match signal is supplied from the comparator 311 to the selector 312, and the MMU
Latch 310 is selected. Therefore, when the upper four bits of the address data CA12 to CA15 do not match the f (x) data, the processing program of the CPU 300 is read, and when they match, the tone color data and the like are read. The f (x) data may be selected and set by the CPU 300 or may be a fixed value in advance.

The selector 313 is also supplied with bank data read by the CPU 300 from an assignment memory 320 to be described later and frequency number accumulated values FA12 to FA26 from the frequency number accumulator 40. The waveform data RD of the corresponding bank is read out. Selector 313
Is switched by the clock signal CK2 from the system clock generator 10, and as shown in the lower part of FIG. 3, the reading of the processing program and the reading of the sample value of the waveform data RD are switched. At this time, at the timing of reading the processing program, the reading of the processing program and the reading of the tone color data are switched based on the f (x) data. These reading processes are repeatedly performed for 16 channels.

Of the data read from the ROM 20, the waveform data RD is sent to the waveform data decompression interpolation circuit 50 as it is, and the processing program and timbre data are divided into two pieces of 8-bit data each.
It is sent to the PU 300 or sent to the assignment memory 320 via the gate buffer 323. The data selection switching in the selector 314 is performed by the CP
Least significant bit CA of address data CA from U300
This is performed based on 0.

Thus, data is taken in from the ROM 20 following the processing speed of the CPU 300. Further, even if the number of bits of data read from the ROM 20 is larger than the number of bits of the data bus line of the CPU 300, data processing can be performed smoothly.

<< Assignment memory circuit 32 >> FIG.
Indicates the storage contents of the assignment memory 320 of the assignment memory circuit 32. The assignment memory 320 has a memory area of 16 channels of timbre data, and a ROM area is provided in each channel area.
20 is set. In this case, among the tone data to be set, the envelope data is EG0.
~ 15 are set in each envelope group area,
Other data is set separately for each channel area of CH0 to CH15.

Data set in CH0 to CH15 include bank data (A) and (B), envelope group data (A) and (B), frequency number speed data FS, key-on signal data, data length signal data D816, and sequence data. GR, initial frequency number data, loop top data, and loop end data. Of these, data other than the frequency number speed data FS, key-on signal data, and envelope group data (A) and (B) are stored in the ROM 20. As described above.

The frequency number speed data FS is data corresponding to the pitch of the operation key of the keyboard 1 and is used as an accumulation step value of the read address data of the waveform data RD. The key-on signal data is data indicating that the key is currently on, and is "1" for key-on and "0" for key-off. Envelope group data (A)
(B) is data indicating the addresses of the envelope group areas EG0 to EG15 in which the envelope data corresponding to the tone of the channel area is stored. The tone assigned to one channel is composed of two tones. Therefore, there are two (A) and (B). Accordingly, since there are two waveform data RDs, there are two bank data (A) and (B). The envelope data set in EG0 to EG15 is also as described in the description of the storage contents of the ROM 20 described above.

The data read from the assignment memory 320 is transferred to a frequency number accumulator 40 and an envelope generator 6 via an AM (assignment memory) bus.
0 or the like, or C
It is provided to the PU 300. For the 4-bit envelope group data (A) and (B), the latch 324 is used.
, The phase data PA from the envelope generator 60 is added to the lower two bits and “1” is added to the upper one bit to make a total of 7 bits, which are again provided to the assignment memory 320 via the selector 321. Envelope level data EL, thin out data TH, and envelope speed data ES of the corresponding envelope
Are read out and sent to the envelope generator 60.
Through this selector 321, the system clock generator 1
Read address data, which is a set of clock signals CK from 0, is also provided to the assignment memory 320.
Access address data from CPU 300 is also provided.

FIG. 3 is a time chart showing the switching state of these address data. The bank data (A) and (B) and the envelope group data (A) and (B) based on the clock signal group CK are shown. After that, after reading the frequency number speed data FS, reading of the envelope speed data (A) ES and the envelope level data (A) EL based on the envelope group data (A) and the phase data PA is performed.
Thereafter, access of the CPU 300 is performed.

Similarly, the initial frequency number, key-on, data length signal data D816, and sequence data GR based on the clock signal group CK are read, followed by the loop top data and the loop end data. Reading of the envelope speed data (B) ES and the envelope level data (B) EL based on the envelope group data (B) and the phase data PA is performed, and thereafter the CPU 300 accesses. These access processes are repeated for 16 channels.

In this case, as the clock signal group CK used as the read address data, CK1 to CK in FIG. 3 are used. The selection of each address data in the selector 321 is performed based on the clock signals CK1 and CK2 from the system clock generator 10, and "00""0"
1 ”, the clock signal group CK is selected,
“10” selects the envelope group data and phase data PA from the latch 324, and “11” selects CP.
The address data from U300 is selected.

A RAM 301 stores various intermediate processing data, a timer 302 gives an interrupt signal to the CPU 300 at a cycle set by the CPU 300, and a reset circuit 303 resets the CPU 300 and the output latch 304 when the power is turned on. It is. The sampling addresses of the timbre switch 2 and the keyboard 1 are temporarily set in the output latches 304 and 306, and the sampling results are input to the input buffers 305 and 307. Only one bit of the sampling data of the output latch 304 is used as a gate signal of the DA converter 100.

<< Frequency Number Accumulator 40 >> FIG. 8 shows the frequency number accumulator 40. The frequency number speed data FS from the assignment memory circuit 32 is shown.
Is accumulated by the adder 407 through the exclusive OR gate group 405 via the latch 404 and the accumulated frequency number FA up to that time, and the upper 8 bits FA19 to FA2 are output.
6 is the lower 19 bits FA0 through FA1 through the selector 413.
8 is again supplied to the adder 407 as the above-mentioned frequency number accumulated value FA via the exclusive OR gate group 414, the latch group 415 and the selector 416.

As a result, the frequency number accumulated value FA is accumulated at a speed corresponding to the magnitude of the frequency number speed data FS, and the accumulated value FA is transmitted via the latch 418 to the 15-bit FA12- 26 is R
The data is sent to the OM address control circuit 31, and the waveform data RD is read. Upper 3 bits FA of decimal part
The waveform folded signal FDU of 9 to 11 and the most significant bit is sent to the waveform data decompression interpolation circuit 50 and used for decompression and interpolation of the sample value of the waveform data RD.

FIG. 10 shows the contents of such a frequency number accumulated value FA. The frequency number accumulated value FA is data of 28 bits in total, and the most significant bit is a waveform return signal FDU. The next 8-bit FAs 19 to 26 are compare bits, which are used for comparing whether or not a loop end and a loop top described later have been reached.
Bits FA12-18 are integer part, last 12 bits F
A0 to 11 are decimal parts.

Such frequency number speed data F
S is accumulated by the frequency number accumulator 40 for 16 channels of CH0 to CH15, and the accumulated frequency number FA of each channel is stored in the latch group 415. This latch group 415 is composed of 32 latches.
(B) The same read address (the same frequency number accumulated value FA12 to FA26) is used for two tone components. The difference in timbre is based on the difference in the bank data (A) and (B).

The 8-bit initial frequency number from the assignment memory circuit 32 is added with 1-bit “0” and 19-bit “00... 0” at the lower order by the selector 416 via the latch 406. , Is selected as the same 28-bit data as the frequency number accumulated value FA. As the select signal in the selector 416, an on-event signal output at the key-on timing from the envelope generator 60 is used. As shown in FIG. 9, from the key-on timing, the initial frequency number is sequentially changed to the frequency number speed data. FS is accumulated.

Further, the loop end data and the loop top data from the assignment memory circuit 32 are selected via the latch 402 by the selector 403, either of the loop end data or the loop top data, supplied to the comparator 409 and supplied to the selector 413. Is also given. The comparator 409 compares the frequency number accumulated value FA with the upper 8 bits of the comparison bits FA19 to 26, and when the frequency number accumulated value FA exceeds the range between the loop end and the loop top, the selector 410 The overrun signal FCP is output to the exclusive OR gate group 414 and the selector 413 via the OR gate 411, and the loop end data or the loop top data is compared with the upper compare bits FA19 to 26 of the frequency number accumulated value FA. Instead, it is imported as new data.

At this time, the exclusive OR gate group 4
At 14, the values of the integer part and the decimal part of the frequency number accumulated value FA up to that point are inverted plus or minus. This is because the reading direction of the waveform data RD is inverted at the loop end or loop top. This is to use the frequency number accumulated value FA as it is in a state where the fraction of the accumulated value FA is plus / minus inverted and to provide consistency in inversion reading of the waveform data RD.

The overrun signal FCP is also applied to an exclusive OR gate 412, which inverts the waveform folding signal FDU which is the most significant bit of the frequency number accumulated value FA.
The value of the frequency number speed data FS at 5 is inverted plus or minus, and the direction of accumulation of the frequency number accumulated value FA at the adder 407 is switched. FIG. 9 shows a state of loop reproduction for each half waveform by the switching of the frequency number speed data FS.

The waveform folded signal FDU is supplied to the selector 4
03 and 410 are provided as select signals. When frequency number speed data FS is added, loop end data and A <B detection signal are selected, and when subtraction, loop top data and A> B detection signal are selected. . The waveform folding signal FDU is also input to the Cin terminal of the adder 407, and when the frequency number speed data FS is subtracted, +1 processing of the frequency number accumulated value FA is performed.
Also provided to the exclusive OR gate 408. An output signal from the Cout terminal of the adder 407 is also given to the exclusive OR gate 408, and it is detected that the frequency number accumulated value FA has overflowed or underflowed.
Is output as

Further, with respect to the bank data (A) and (B) from the assignment memory circuit 32, one of the bank data (A) and (B) is selected by the selector 401 via the latch 400, and the latch 417 is selected. Is sent to the ROM address control circuit 31 together with the integer part of the frequency number accumulated value FA and the comparator bit, and the waveform data RD is read.

As a result, although the two tone components (A) and (B) assigned to one channel have different bank data, the common frequency number accumulated value FA is used, and the timing synchronization of the tone generation process is performed. Is taken.

The select signal of the selector 401 includes
Clock signal CK3 from system clock generator 10
Is used, the tone generation process for (A) is performed in the first half of the clock signal CK3, and the tone generation process for (B) is performed in the second half. The clock signal group CK from the system clock generator 10 corresponds to the latches 400, 402, 404, 406, 415, 417, 4
18 is also provided as a latch signal to synchronize the channel cycle and timing.

<< Waveform Data Expansion Interpolation Circuit 50 >> FIG.
Indicates a waveform data decompression interpolation circuit 50, in which gates 500 to 510 and selectors 511 to 513 decompress differential data in the waveform data RD as shown in FIG. 518, 519,
With the adder 520 and the selector 521, each sample value R0, R1, R2, R3... Of the waveform data RD as shown in FIG.
Are interpolated, and the gate groups 524 and 522 and the gate 52
6, the selector 525 and the adder 527 perform interpolation when the waveform data RD is a 10-bit sample value and 6-bit difference data (D816 = 0), and do not interpolate when two 8-bit sample values are used (D816 = 1). Done.

<< Overview of Data Processing of Waveform Data Decompression Interpolation Circuit 50 >> FIG. 14 shows the data structure of waveform data RD read from ROM 20.
When 816 is a low level and includes a 10-bit sample value and 6-bit differential data, the upper 10 bits RD6
15 is a sample value, RD5 is difference code data, RD
2 to 4 are differential power data, and RD0 and 1 are differential mantissa data. The difference data RD0 to RD4 are stored in a compressed state, and when expanded, become 10-bit expanded difference data IE0 to IE8 and IES as shown in FIG.

That is, the difference power data RD2 to RD4 are
The difference mantissa data RD0, RD1 is data indicating the first bit of the difference value that has "1", and the two bits following the "1" are data themselves. As described above, the data in the upper part of FIG. 15 is for adding the decompression difference data, while the data in the lower part is for subtraction. In this case, the difference power data RD2 to RD4 are data indicating how many bits of the difference value are followed by “1”, and the subsequent conversion difference mantisser data RG0 to RG2 are difference mantisser data. Data RD0,
1 is converted by the logical expression shown in the lower part of FIG. 15, and the content of the conversion is as shown in FIG.

The decompression difference data IE0 to IE8, I
ES is の of the difference between each sample value of the waveform data RD indicated by a large circle in FIG. 13, and indicates the difference between each sample value and a virtual value indicated by a cross. The virtual value in FIG. 13 overlaps with the interpolation value and is in a state where the mark “x” overlaps the mark “x”.

Each sample value R0, R1 of the waveform data RD
, R2... Are obtained by dividing the frequency number accumulated value FA by half.
12 (2) and FIG.
In order to realize a waveform connected by the mark x, the sample value at the intermediate point between the sample points G0, G1, G2,. The sample values at the intermediate point are R0 = (G0 + G1) / 2 and R1 = (G1 + G2).
) / 2, R2 = (G2 + G3) / 2.

As described above, instead of the sample values indicated by the crosses,
By storing the sample values at the midpoints of the crosses, FIG.
3 and FIG. 12 (2), the frequency number accumulated value F
The waveform data level can be accurately set to "0" at the start point where A is "00 ... 0". That is, ROM2
In the first address of the memory area of the waveform data RD of 0, the waveform data RD which is not the "0" level in the first step is normally stored.
Is stored, but the frequency number accumulated value FA is “0”.
In the case of "0 ... 0", the phase can be automatically adjusted by storing the sample value of the above-mentioned intermediate point even if a process for preventing the reading of the first step is not performed.
The phase shift as shown in FIG. 12 (1) does not occur.

Further, the difference data between the midpoint of the mark x and the interpolation points before and after this midpoint are the same before and after, and as a result, the difference data to be stored is only half of the original difference data. . Therefore, when the sample value of the normal waveform data RD is 10 bits, the difference data is 10 bits. Even if the above-mentioned compression method is used, the number of bits of the difference power data is required to be 4 bits. 7
The difference data can be reduced to half as described above, but the difference data can be reduced to 6 bits, and can be accessed once in normal data access as a total of 16 bits.

Therefore, the waveform data RD and the program (or timbre data) are alternately read from one ROM 20, and the readout of the waveform data RD per unit time can be reduced to half. Note that the stored waveform data RD may be a waveform in which the x points are connected in a polygonal line shape.

[0063] 1/4, 2/4,
If 3/4 and 4/4 are added or subtracted from the sample values as shown in FIG. 17, an interpolated value will be obtained. In this case, when the interpolated values are larger than the sample values R0, R1, R2, R3,... In E0, D1, D2, D3,. When the interpolation value is smaller, such as D0, E1, E2, E3,..., The decompression difference data is a subtraction value as shown in the lower part of FIG.

There are two types of data format of the waveform data RD, that is, 10-bit data format and 8-bit data format. A lively sound is 8-bit data in which quantization noise does not cause much problem even if the number of quantization bits is reduced. Sounds in which quantization noise is noticeable are selectively used as 10 bits, and the amount of memory used is reduced.

<< Circuit Configuration of Waveform Data Decompression Interpolation Circuit 50 >> In FIG. 11, the difference Mantissa data RD0 is supplied to the A-side “0” terminal and the B-side “1” terminal of the selector 511.
Is input as it is. When the most significant bit IES of the decompressed difference data is “0”, the difference mantisser data RD1 is directly input to the A-side “1” terminal and the B-side “2” terminal of the selector 511. Is "1", the AND gate 502 is opened.
Exclusive OR data RG1 of the difference mantisser data RD0 and RD1 is input.

Further, the A side “2” terminal and the B side “3” terminal of the selector 511 have the most significant bit IES set to “0”.
At this time, the output of the NAND gate 505 becomes "1" and the output of the NOR gate 509 is inverted by the exclusive OR gate 506, so that the logical sum of the difference power data RD2 to RD4 is input and the most significant bit IES is "1". "When,
Difference Mantissa data RD by OR gate 504
Inversion data of OR of 0 and 1 and difference power data RD2
Exclusive OR data RG with inverted data of OR of .about.4
2 is input. Then, the A side “3” of the selector 511
The terminal is supplied with the most significant bit IES, and the B-side “0” terminal is supplied with “0” data.

As a result, as shown in FIG. 15, data of the differential mantissa data RD0, RD0, 1 and the upper one bit data, or data of the converted differential mantissa data RG0, RG1, 2, RG2 are created. . The specific contents of the conversion difference mantisser data RG0 to RG2 are as shown in FIG.

The 4-bit data of the selector 511 is
The selectors 512 and 513 select whether the most significant bit IES is added by 2 bits or 4 bits at the high order, or whether the “0” data is added by 2 bits or 4 bits at the low order. Is output. Each selector 5
11, 512, 513 by appropriately selecting the select state, the difference mantissa data RD0, 1 or RG0
2 can be shifted as shown in FIG. 15, and the selection of the selection state is performed by the difference power data RD2 to RD4.
It is performed based on.

In this manner, the expanded differential data can be expanded to 10 bits, even though the differential compressed data is 6 bits, and the amount of memory used can be reduced.

The most significant bit IES of the decompressed difference data
Are the difference code data RD5 input to the exclusive OR gate 500, the most significant bit FA11 of the decimal part of the frequency number accumulated value FA input to the NOR gate 501, and each bit RD0 to RD4 of the difference data from the NOR gate 508.
And the inverted data of the logical sum of That is, as shown in FIG. 13, when the FA11 of D0 is "0" and the difference code RD5 is "0" (in the addition direction), E1 and E1
2 ... FA11 is "1" and RD5 is "1" (subtraction direction)
In this case, the most significant bit IES of the decompressed difference data becomes “1”, indicating that the difference data must be subtracted from the sample value.

The NOR gate 501 receives the inverted data of the logical sum of the bits RD0, 1, 2, 3, 4, and 5 of the difference data, and when the difference data is "00000",
The output of the NOR gate 501 is set to “0”, and control is performed so that the most significant bit IES of the decompressed difference data does not become “1”.

The decompressed difference data IE is shifted down by one bit to a value of ４ and input to one terminal of an adder 520 via an AND gate group 519.
The value is shifted to the lower side by 2 bits to become a value of 1/4, and is input to the other terminal of the adder 520 via the AND gate group 518. On the B side of the selector 521, the decompressed difference data IE is not shifted but is given at the same magnification. Accordingly, by appropriately selecting the ratio data IM including the opening signals IM0 and IM1 of the AND gate groups 518 and 519 and the selecting signal IM2 of the selector 521, the expansion difference data IE as shown in FIG.
Can be reduced to 1/4, 2/4, 3/4, 4/4 and 0 times.

The decompression difference data I having such a multiplication factor
E is given to the adder 527 via the AND gate group 522, and the sample values RD6 to RD6 of the waveform data RD to be described later.
15 is added and subtracted, and interpolation of each sample value of the waveform data RD is performed.

Thus, one sample value RD6 to RD15
And the difference data RD0 to RD5, the waveform data R at eight points
D can be created, smooth waveform characteristics can be obtained, and the memory capacity can be reduced. In addition, such waveform data RD that can determine eight points by one data can be read out by one reading, and a sufficiently smooth waveform can be realized even if the reading time of the waveform data RD is small.
Even if the waveform data RD and other programs are read alternately, the waveform generation processing is not hindered. Even if the program and the waveform data RD are stored together in the ROM 20, the reading speed of each information is reduced. There is no need to increase

The multiplying factor data IM0 to IM2 are created by the logic gates 514 to 517 by the upper three bits FA9 to FA11 of the decimal part of the frequency number accumulated value FA. By the gate groups 514 and 517, data conversion as shown in FIG. 17 is performed, and an interpolation value of the waveform data RD is obtained. In this case, when only the most significant bit FA11 of the decimal part of the frequency number accumulated value FA is “1”, that is, when the frequency number accumulated value FA is １ ／, no interpolation is performed on the sample value. As a center, at an earlier timing, the interpolated value is a subtraction value of 1/4, 2/4, 3/4, 4/4 of the difference data,
At a later timing, the interpolated value is 1/4, 2
/ 4, 3/4.

When the waveform data RD0 to RD15 are composed of a 10-bit sample value and 6-bit difference data, the sample values RD6 to RD15 are input from the A side of the selector 525 and are supplied to the adder 527 as they are. Then, the interpolation value is adjusted. At this time, the data length signal D8
16 becomes “0”, so that the AND gate groups 524, 5
22 is opened, the AND gate 526 is closed, and the selector 525 selects the A side. Also, the waveform data RD0
When ~ 15 consists of two 8-bit sample values,
The waveform data RD0 to RD7 are input from the B side of the selector 525, and are provided to the adder 527.
To 15 are input from the A side of the selector 525 and supplied to the adder 527.

At this time, two bits "00" are added to the lower part of each data RD0 to RD7 and RD8 to RD15 to form 10-bit data. At this time, since the data length signal D816 becomes "1", the AND gate groups 524 and 522 are closed and no interpolation is performed. Further, at this time, since the AND gate 526 is opened, the frequency number accumulated value F
In accordance with the value (1, 0) of the most significant bit FA11 of the decimal part of A, the sample value (2n = RD0 to 7, 2n + 1 = R
D8 to D15) are switched.

The present invention is not limited to the above embodiment, but can be variously modified without departing from the spirit of the present invention. For example, the program read by one reading may be an 8-bit program, and the means for storing the data and the program may be an integrated ROM and RAM, a magnetic memory, an optical memory, or the like. Are read out by the CPU 300 and the frequency number accumulator 60.
Other than the above, the read / write switching between data and program is performed by MMU address data and clock signal CK.
Other than 1 to 7 may be used.

A summary of the embodiments described herein is as follows. [A] a data storage unit provided in the storage means for storing musical sound waveform data relating to musical sounds, a program storage unit also provided in the storage means for storing a processing program for generating or controlling musical sounds, First read address data generating means for generating read address data for periodically reading the musical tone waveform data from the storage means for each of a plurality of channels; and read data read by the first read address data generating means. A processing means for processing musical tone waveform data, and a read address for reading the processing program of the central processing unit from the storage means in order as the processing progresses, which is different from the first read address data generating means. Second read address data generating means for generating data, and second read address data generating means Accordingly, a central processing unit for performing processing based on the read processing program, and the read address data from the first read address data generating means and the read address data from the second read address data generating means are transmitted at a predetermined cycle. A tone information processing apparatus comprising: an address switching means for alternately switching the data every (fixed period) and supplying only one of the read address data to the storage means.

[B] A data storage unit provided in the storage means for storing musical sound data relating to musical sounds, and a program different from the program provided in the storage means for processing the musical sound data. A program storage unit for storing a processing program for generating or controlling the first read address data; a first read address data generating unit for generating read address data for reading musical tone data from the storage unit; First processing means for processing the tone data read by the generating means, and read address data for reading a processing program from the storage means, which is different from the first read address data generating means. And a second read address data generating means for generating Means for performing processing based on the processing program read and read, the second processing means being different from the first processing means, and read address data from these first read address data generating means. Address switching means for alternately switching the read address data from the second read address data generating means and the read address data from the second read address data generating means at a predetermined cycle (constant cycle), and supplying only one of the read address data to the storage means. A music information processing apparatus characterized by the following.

[C] The second read address data generating means and the second processing means or the central processing unit read out a processing program from the program storage unit and perform control for allocating the musical tone to a channel. The musical tone information processing apparatus according to claim A or B. [D] The musical tone information processing apparatus according to claim B, wherein the first read address data generating means and the first processing means read musical tone waveform data from the data storage unit and generate musical tone. .

[E] The address switching means is means for switching the read address data from the first read address data generating means and the read address data from the second read address data generating means in a time-division manner. The musical tone information processing apparatus according to claim A, B, C or D. [F] The reading of the processing program from the program storage unit is performed by the central processing unit, and the reading of the musical sound data from the data storage unit is performed by processing each of the musical sound data formed by the time division processing. The method according to claim B, wherein the data is sequentially read out for each channel.
The musical tone information processing apparatus described in the above.

[G] A plurality of steps of tone data or tone waveform data are read from the data storage unit by one reading, and a plurality of steps are read from the program storage unit by one reading. A, B, C, D, E or F, wherein the processing program is read out.
The musical tone information processing apparatus described in the above. [H] The musical sound information processing apparatus includes divided output means for dividing and switching and outputting the musical sound data or musical sound waveform data or the processing program read out by one reading, and the divided musical sound data or musical sound waveform data or the processing program. Switching control means for performing a switching output of the two read address data generation means based on a value of a specific bit of one of the address data generated by the two read address data generation means. , E, F or G.

[I] Data storage means for storing data representing the contents of musical sounds, program storage means provided integrally with the data storage means and storing a processing program for generating and emitting musical sounds, Musical tone information comprising: data reading means for reading data from a storage means; program reading means for reading a program from the program storage means; and switching means for switching between reading between the data reading means and the program reading means. Storage device. [J] The musical tone information processing apparatus according to claim I, wherein said data reading means is means for reading out waveform data for a plurality of steps in one reading.

[K] The musical tone information processing apparatus according to claim I, wherein said program reading means is means for reading a processing program for a plurality of steps in one reading. [L] In claim I, J or K, the divided output means for dividing and switching and outputting the data or the program read in one reading, and the switching output of the divided data or program, the two reading means And a switching control means for performing the switching by using the value of the least significant bit of any of the address data.

[M] A data storage section provided in the storage means for storing musical tone waveform data relating to musical tones and interpolation data relating to interpolation of each musical tone waveform data, and also provided in this storage means, for storing the musical tone data. A program storage unit for storing a processing program for generating or controlling a musical tone, and a second program for generating read address data for reading musical tone waveform data and interpolation data from the storage means. One read address data generating means and each tone waveform data read out by the first read address data generating means are used to generate a tone waveform data based on the interpolation data read out by the first read address data generating means. Interpolation means for performing the interpolation of the sound waveform data interpolated by the interpolation means A tone generating means for generating a tone based on each tone waveform data read by the first read address data generating means, and means different from the first read address data generating means; Second read address data generating means for generating read address data for reading a processing program from the storage means, and means for performing processing based on the processing program read by the second read address data generating means. The second processing means independent of the first processing means, and the read address data from the first read address data generating means and the read address data from the second read address data generating means. Address switching for alternately switching at predetermined intervals to supply only one of the read address data to the storage means Tone information processing apparatus characterized by comprising a stage.

[N] The read address data generated by the first read address data generating means starts from the head address of the musical tone waveform data stored in the data storage unit and repeats a predetermined section after the head address. The musical tone information processing apparatus according to claim M, wherein: [O] The read address data generated by the first read address data generating means reads a plurality of tone waveform data in parallel for one tone generation instruction. Musical sound information processing device.

[P] Tone generating means capable of simultaneously producing a plurality of musical tones simultaneously by time-division processing, control for assigning channels to the tones to be produced, and timing of producing the tones produced for the tones producing means A central processing means for controlling the central processing means; a storage means comprising one storage element for storing together the program read by the central processing means and the musical tone data read by the musical tone generating means;
Clock signal generating means for supplying clock signals synchronized with each other to the central processing means and the musical sound generating means; and a musical signal generated by the musical sound generating means based on a clock signal supplied from the clock signal generating means. And an address switching means for switching the read address data of the tone data and the read address data of the program generated by the central processing means and supplying the read address data to the storage means. .

[Q] The musical tone according to claim P, wherein the musical tone data stored in the storage means is musical tone waveform sample data, and the musical tone waveform sample data is read out by the musical tone generating means. Information processing device.

[0090]

As described above in detail, according to the present invention, the present invention stores data and programs for musical sounds in an integrated storage means, thereby making the storage device compact and simplifying the circuit configuration. In addition, the read address data can be switched only by the difference between the data and the address of the area where the program is stored.
Data and program reading can be switched.
This has the effect of simplifying the information reading process.

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of an electronic musical instrument.

FIG. 2 is a circuit diagram of an input unit of the electronic musical instrument.

FIG. 3 is a time chart of each part in FIGS. 1 and 5;

FIG. 4 is a diagram showing stored contents of a ROM 20.

FIG. 5 is a circuit diagram of the key assigner circuit 30.

FIG. 6 is a diagram showing a correspondence relationship between address data of a CPU 300 and address data of a ROM 20.

FIG. 7 is a diagram showing the contents stored in an assignment memory 320.

8 is a circuit diagram of a frequency number accumulator 40. FIG.

FIG. 9 is a diagram showing a read state of waveform data.

FIG. 10 is a diagram showing the contents of a frequency number accumulated value FA.

11 is a circuit diagram of a waveform data decompression interpolation circuit 50. FIG.

FIG. 12 is a diagram showing the correspondence between sample values for half a wavelength of waveform data and readout timings.

FIG. 13 is a diagram showing sample values and interpolation values of waveform data.

FIG. 14 is a diagram showing the contents of waveform data RD.

FIG. 15 is a diagram showing expanded contents of difference data RD0 to RD5 of waveform data.

FIG. 16 is a diagram showing the contents of conversion from difference mantissa data RD to converted difference mantissa data RG.

FIG. 17 is a diagram showing the relationship among the upper bits FA9 to FA11 of the decimal part of the frequency number accumulated value, the multiplication data IM0 to IM2 of the difference data, and the interpolation contents of the sample values of the waveform data.

[Explanation of symbols]

20 ROM, 30 key assigner circuit, 31 ROM
Address control circuit, 32 ... assignment memory circuit,
40: frequency number accumulator, 50: waveform data decompression interpolation circuit, 60: envelope generator, 70: multiplication circuit, 8
0: shift circuit, 90: series accumulation circuit, 300: CP
U, 320: Assignment memory.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoichi Nagashima 200 Terashimacho, Hamamatsu-shi, Shizuoka Prefecture Kawai Musical Instruments Manufacturing Co., Ltd. (56) References JP-A-60-149092 (JP, A) (JP, A) JP-B-60-44679 (JP, B2)

Claims (2)

(57) [Claims] 1. A program for detecting an instruction of a pitch and a timbre of a musical tone to be generated and controlling sound generation and musical tone waveform data for generating the musical tone.
A storage means comprising two storage elements; and a means for supplying read address data of a program to the storage means, reading the program, and determining a pitch and tone of a musical tone to be generated based on the read program. And generating read address data corresponding to each tone and each tone of the plurality of musical tones whose pitch and tone have been determined, supplying each of the generated read address data to the storage means, Means for sequentially reading out the tone waveform data and generating a plurality of tone based on the read tone waveform data; switching between a plurality of read address data of the tone waveform data and read address data of the program; The plurality of read address data of the musical tone waveform data are also switched, and And means for supplying to the means, on the basis of the storage means, the musical tone by the program
Both determination of pitch and timbre, and generation of the plurality of musical tones
Tone information processing apparatus, characterized in that it comprises a means to perform. 2. A program for detecting tone pitch and tone color of a musical tone to be generated and performing tone generation control and musical tone waveform data for generating the musical tone.
The storage means including the two storage elements is supplied with the read address data of the program, and the program is read out. Based on the read out program, the pitch and timbre of the musical tone to be generated are determined. And generating read address data corresponding to each tone and each pitch of the plurality of musical tones whose pitch and tone have been determined, and supplying the generated read address data to the storage means. Read out the musical tone waveform data sequentially, generate a plurality of musical tones based on the read musical tone waveform data, and switch between a plurality of read address data of the musical tone waveform data and a read address data of the program. At the same time, multiple read address data of the musical tone waveform data are also switched. By, is fed to the storage means, based on the storage means, the musical tone by the program
Both determination of pitch and timbre, and generation of the plurality of musical tones
Musical information processing method characterized by causing the.