JPH079582B2 - Electronic musical instrument - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an electronic musical instrument, and more particularly to an electronic musical instrument that generates a noise signal.

(Prior Art) In recent years, electronic musical instruments have become capable of producing sophisticated tones by the introduction of digital signal processing, but it is necessary to reproduce noise components in air lead musical instruments such as flutes. As an electronic musical instrument that reproduces this noise component,
There is a number 59-75294. A block diagram is shown in FIG. 14, and its operation will be described below.

Information about the musical sound to be output, which is instructed by the input unit 1, is sent to the control unit 2. The control unit 2 reads information for synthesizing musical tone waveforms from the table memory 3 based on the information given from the input unit 1, and based on this, reads waveform data from the phoneme unit memory 4 to synthesize musical tone waveforms. At the same time, the noise data is read from the noise memory, added to the tone waveform, and output from the DA converter 5. In this way, a musical tone signal containing a noise component is obtained.

(Problems to be Solved by the Invention) However, the above-mentioned configuration has a problem that an adder for adding noise data and a musical tone waveform is required and the circuit scale increases.

In view of the above points of the present invention, it is an object of the present invention to provide an electronic musical instrument that generates a musical tone signal containing a noise component without significantly increasing the circuit scale.

(Means for Solving Problems) In order to solve the above problems, the electronic musical instrument of the present invention generates predetermined waveform data and a predetermined envelope based on the performance information sent from the performance operation section. A musical tone generating section that generates predetermined musical tone data by multiplying the waveform data and the envelope, a noise generating section that generates a noise signal, and a predetermined bit of the waveform data by the instruction of the performance information. Or the output of the waveform data and the noise signal is replaced with any one of the outputs of the logical sum, the logical product, and the exclusive logical sum.

(Operation) According to the present invention, by the above configuration, the bit operation of the predetermined bit of the waveform data is performed by the noise signal. Therefore, a tone signal containing a noise signal is generated without using an adder.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram when the information processing apparatus according to the present invention is used in an electronic musical instrument. To explain FIG. 1, 1-
1 is a keyboard. Reference numeral 1-2 is a tablet, which is an operation unit for instructing selection of a tone color of a musical sound output from the electronic musical instrument.
1-3 are effect switches for controlling various effects on musical sounds, for example, turning on effects such as vibrato and tremolo.
This is a switch for instructing to turn off. 1-4 are microcomputers (microcomputers), which correspond to, for example, the Intel microcomputer 8049. Reference numeral 1-5 is a tone generation unit, which performs waveform calculation and frequency calculation based on the control signal given from the microcomputer 1-4. Reference numeral 1-6 is a data bank, which is a ROM (read-only memory) in which waveform data and envelope data used in the musical tone generator 1-5 are stored. Reference numeral 1-7 is a filter that removes aliasing noise of the tone signal output from the tone generator 1-5. 1-8 are speakers.

Next, the operation of the electronic musical instrument shown in FIG. 1 (a) will be described. The microcomputer 1-4 sequentially searches the states of the keyboard 1-1, the tablet 1-2, and the effect switch 1-3 according to a command written in advance. Also, the microcomputer 1-4 turns on / off the key on the keyboard 1-1.
The code of the key being pressed based on the state of FF is sent to the multiple channels of the musical tone generating section 1-5, and an assignment signal is sent out, while the tablet 1-2 and the effect switch 1-3 are sent.
Control data is sent according to the state of. Music tone generator 1-5
In the above, the assignment signal and other control signals sent from the microcomputer 1-4 are fetched into the internal register, and the necessary waveform data and envelope data are read from the data bank 1-6 based on these signals while Perform synthesis. The musical tone signal synthesized by the musical tone generating section 1-5 is sent to the speaker 1-8 through the filter 1-7 to generate a musical tone.

FIG. 1 (B) shows a timing chart when data is transferred from the microcomputer 1-4 to the musical tone generating section 1-5. Table 1 shows the contents of the data sent from the microcomputer 1-4 to the musical tone generator 1-5. In Table 1, NOD is note octave data, which consists of note data ND, octave data OCT, and key-on data Kon. Table 2 shows the bit structure of NOD, Table 3 shows the correspondence between note data ND and note names, and Table 4 shows the correspondence between octave data OCT and range. There is. That is, if it is desired to output the sound of the sixth octave of the note G # (hereinafter abbreviated as G # 6) from the channel 1 to the tone generator 1-5, the address 0000 in FIG.
0001, 10011110 as data will be transmitted from the microcomputer 1-4. Next, PDD is pitch detune data, which is 8-bit data for shifting the tuning. PDD is expressed in 2's complement notation, and the variable range is from -128 to +126.
There are 256 ways. RLD is release data, which is 4-bit data that controls the attenuation characteristics after key-off. VOL is a volume flag, and when this bit is set to "1", the output level of the tone signal from the tone generating unit 1-5 can be controlled according to the volume data VLD described later. DMP is a damper flag, which is a flag that causes the attenuation after key-off in the case of a piano type envelope to be rapidly attenuated, and functions when DMP = 1. SOL is a solo flag,
It is a flag to select whether to match the phase characteristics of the tone generated by that channel with the tone that is about to be generated when a tone with the same note name as another channel is signed. To cancel. TAB is tablet data, and the data specified by tablet 1-2 in FIG. PE is a pitch extend flag. Pitch extend is applied to the channel for which this bit is set to "1". VLD is volume data, and controls the level of the musical sound output from the channel with the fineness of 8 bits together with the volume flag VOL described above. Note that this series of data can be set independently for each channel.

Next, the calculation sequence in the musical sound generating section 1-5 will be described.

Tables 5 and 6 show the operation sequences of the musical tone generator 1-5. In the musical tone generating section 1-5, the operation sequence has two modes of initial mode and normal mode in order to perform more data processing in a short operation cycle. Further, both modes are long sequence and short mode, respectively. Divided into sequences. Also, the initial mode short sequence and the normal mode long sequence have two states of EVEN and ODD, respectively.

In the initial mode, when the microcomputer 1-4 commands the musical tone generator 1-5 to generate a new musical tone, the initial stage of various registers etc. for the channel specified by the microcomputer 1-4 in the musical tone generator 1-5. It is a mode for setting and starts from the long sequence, and after performing the short sequence twice, enters the normal mode. Regarding the two short scenes in this initial mode, the first is ODD, 2
This is the EVEN short sequence. After the end of the initial mode, the mode shifts to the normal mode, but the short sequence is repeated 6 times and the long sequence is repeated once.

In this embodiment, for each channel, two independent waveforms are multiplied by two independent envelopes, and a fine pitch adjustment function is also provided. A large number of calculation steps are required to perform the processing for eight channels in a time division manner. Therefore, short sequences are used for operations that need to be performed in short cycles, and long sequences are used for operations that are infrequently operated, that is, operations that can be performed in long cycles. The long sequence is inserted between the short sequences to improve the efficiency of calculation.

FIG. 1C shows a timing diagram of the short sequence and the long sequence. As shown in FIG. 1C, the short sequence consists of 11 time slots (0) to (10), and the long sequence consists of 9 time slots (11) to (19). Each time slot is 250 ns, and is divided into four, and the whole system operates with a non-overlapping two-phase clock of ψ1, ψ3. Regarding the relationship between the short sequence and the long sequence, every time the short sequence is repeated eight times from channel 0 to channel 7, a long sequence for one channel is inserted. Thus, for example, a short sequence on channel 3 will occur once every 11 × 8 + 9 97 time slots and a long sequence will occur once every 97 × 8 776 time slots. Furthermore, since the normal mode long sequence has two states, EVEN and ODD, the system is operating with 776 × 2 1552 time slots as a cycle.

Next, each operation sequence will be described based on Tables 5 and 6. As described above, the musical tone generating unit 1-5 starts from the initial mode long sequence by a new key depression, so the explanation will be given for each time slot from the initial mode long sequence.

Adder (13) PDD + PED → PDR (15) 0 → TR1 (16) 0 → TR2 (17) 0 → ZR1 (18) 0 → ZR2 The meaning of the time slot (13) is the contents of the PDD register. Add the contents of the PED register to P
This means storing in a register called DR. Time slots (15) to (18) mean that 0 is written in registers TR1, TR2, ZR1, and ZR2.

Data bank reading section (12) WTD → HAD → HAD (14) HAD → CONT → CONT, DIF1 (16) ~ (17) HAD → STE → EAR1 These meanings mean the data at the left end (for example, time slot ( 14) Then, the data called HAD) is used as an address to read the data CONT described in the center from the data bank 1-6 and store it in the registers CONT and DIF1 with the names at the right end.

Initial mode sequence Adder (1) PDR + JD LB; 0 → ER2 / 1 (3) ORG + OCT + 1 → WE2 → ΔWAR (4) DB + EAR1 → EAR2 (6) 0 → WR1 (8) 0 → ER1 (9) 0 → WE2 (10 ) 0 → WE1, WR2 0 → ER2 / 1 in time slot (1) is ER2 during the first short sequence, that is, ODD, and during the second short sequence, that is, EVEN.
This means writing 0 to the register ER1. Further, LB means that the operation result of PDR + JD is sent to the operation unit (described later) via the L bus (described later) without being stored in the register. In the time slot (3), it means that the calculation result is once stored in the register WE2, then decoded and stored in ΔWAR. DB in the time slot (4) means that the value obtained by the data bank reading unit described later is sent to the adder via the D bus (described later) without passing through a register or the like.

Multiplying unit (4) to (6) CB × CN1 → FR The above CB means that the result obtained by the adding unit is directly input to the multiplying unit without passing through the register, and in this case, the time slot ( It means the calculation result of PDR + JD obtained in 1).

Data bank reading section (1) HAD → ΔSTE → AB (3) to (4) EAR1 / 2 → E1 / 2 → ΔT1 / 2, ΔE1 / 2, ΔZ1 / 2 (6) to (7) HAD → STW / ΔSTW → STW / WAR Here, AB in time slot (1) means that the value obtained by reading the data bank is directly input to the A input of the adder without passing through a register or the like. In addition, STW / ΔSTW → STW / WAR of time slots (6) to (7) reads the data STW in the first short sequence, that is, at the time of ODD, and stores it in the register STW, and the second time, that is E
In VEN, it means reading the data ΔSTW and storing it in the register WAR.

Next, the normal mode will be described.

Normal mode short sequence In Table 6, the part marked with * indicates that the calculation is performed only in the first short sequence after the note clock is generated, and the flag that controls this operation is the calculation request flag CLRQ. I will call it.

Adder (1) WE2 + WE1 → LB (2) STW + WAR → DB, BB (3) ZR1 + ΔZ1 → ZR1 (4) DIF1 + C.B. → DB (5) ER1 + ΔE1 + Ci → ER1 (6) ZR2 + ΔZ2 + ZR2 (7) WAR + ΔWAR → WAR * (8) ) ER2 + ΔE2 + Ci → ER2 (9) FR + CDR → CDR * Here, LB of the time slot (1) means that the operation result is directly input to the multiplication unit without passing through the register.
Similarly, DB and BB of the time slot (2) mean that the calculation result is directly input to the B input of the data bank reading unit and the addition unit. C. in timeslot (4)
B. means to directly input the operation result of the adder without passing through the register, and in this case, the operation result of STW + WAR in the time slot (2) is input. The DB means that the calculation result is directly input to the data bank reading unit. Ci in time slots (5) and (8)
Means adding carry (carry) of the calculation in the time slots (3) and (6), respectively.

Multiplier (1) to (3) WR2 + ER2 → WE2 * (4) to (6) CB × CN → (DAC) (7) to (9) WR1 × ER1 → WE1 * where time slots (4) to (6) CB in 6) means that the output of the addition unit is directly input to the multiplication unit without passing through a register or the like. In this case, WE for time slot (1)
Equivalent to the calculation result of 2 + WE1. Further, (DAC) means that the result of this operation is input to a DAC (DA converter; described later).

Data bank reading section (4) to (5) CB → W1 → WR1 * (7) to (8) CB → W1 → WR2 * where CB of time slots (4) to (5) is the calculation result of the addition section Is directly input to the data bank reading unit and used as the address of the data tanks 1-6. In this case, this corresponds to the operation result of STW + WAR of the time slot (2) in the adding unit. C. of time slots (7) to (8)
Similarly for B., time slot (4) DIF1 + (STW + WAR)
Corresponds to the calculation result of.

Long sequence adder (13) ΔT1 / 2 + TR1 / 2 → TR1 / 2 (14) PDR + JD → LB (15) ΔEAR1 / 2 + EAR1 / 2 + Ci → EAR1 / 2 (16) PDD + PED → PDR where LB of time slot (14) Means that the calculation result of the adder, that is, the value of PDR + JD is directly input to the multiplier without passing through the register. Ci of the time slot (15) means a carry (carry) resulting from the calculation of the time slot (13).

Multiplier (16) to (18) CN + C.B. → FR Here, CB means that the operation result of the adder is directly input to the calculator without passing through the register. In this case, the adder time slot (14 The calculation result of PDR + JD in () is input.

Data bank readout section (14) to (15) EAR2 / 1 → E2 / 1 → ΔT2 / 1, ΔE2 / 1, ΔZ2 / 1 where 2/1 is the odd number, that is, 2 when ODD.
(E2 for E2 / 1, for example), 1 for the even number of times, ie EVEN
(Same E1) means that another data is read by EVEN and ODD and stored in another register.

FIG. 2 is a detailed diagram of the musical tone generating section 1-5 in FIG. First, the outline of the function of each block will be explained using this figure. 2-1 is the master clock.
I am using 8.00096MHz. 2-2 is a sequencer (hereinafter referred to as SEQ), which divides the clock signal by the master clock 2-1 to generate sequence signals (hereinafter referred to as SQ signals) and various control signals in the entire musical tone generation section 1-5. To do. 2-3 is a microcomputer interface unit (hereinafter referred to as UCIF), and various data shown in Table 1 is stored in the microcomputer.
1-4 is a circuit which sends out asynchronously with the tone generating section 1-5, but is a circuit which takes in this data and synchronizes with the SQ signal generated by SEQ. Further, the flag Kon generates a flag INI for instructing switching between the initial mode and the normal mode. 2-4 is a comparison register block (hereinafter CDR
Register) shown in the operation sequence above.
CDR 8 channels and master clock divided by 1
The 10-bit frequency-divided signal is compared to generate a note clock for eight channels and a calculation request flag CLRQ. A random access memory unit (hereinafter referred to as a memory) 2-5 stores various calculation results performed in the musical tone generating unit 1-5. 2-6
Is a full adder unit (hereinafter referred to as FA), which has a built-in 16-bit full adder that adds various data. 2-7
Is a multiplication unit (hereinafter referred to as MPLY), and has a multiplier that performs a calculation of (2's complement 12 bits) × (absolute value 10 bits). Reference numeral 2-8 is a digital-analog converter (hereinafter referred to as DAC), which converts the digital musical tone data output from the MPLY2-7 into analog musical tone data. 2-9 is the analog buffer memory part (hereinafter A
In BM), the tone data generated by the machine cycle period from DAC2-8 is converted into pitch synchronization by the note clock generated by CDR2-4. The ABM2-9 has the same function and configuration as the analog buffer memory disclosed in Japanese Patent Laid-Open No. 59-214091. Reference numeral 2-10 is an input / output circuit section (hereinafter referred to as I / O), which sends an address signal to the data bank 1-6, reads out waveform data and envelope data corresponding to the address signal, and if necessary, The data read out is converted. 2-11 is a matrix switch section (hereinafter referred to as MSW), which is UCIF2-3,
Horizontal bus line (H) connected to CDR2-4 and memory 2-5
A, HB, HC, HD, HE, HL buses) and FA2-6, MPLY2-7, I / O 2-
It is a circuit that connects the vertical bus lines (A, B, C, D, and L buses) connected to 10 in accordance with the SQ signal. These circuits execute the operation sequences shown in Tables 5 and 6.

Next, individual blocks will be described.

FIG. 4 is a detailed view of SEQ2-2 in FIG. 4-1 is a counter, which divides the master clock to generate various timing signals shown in FIG. TS is a signal representing the time slot in FIG.
CHC is a channel code, which is a signal representing the channel number in FIG. EV is a signal that represents ODD and EVEN in the calculation sequence, and EV = 0 means OD.
D and EV = 1 means EVEN. 4-2 is SQROM (sequence R
OM). A signal TS indicating a time slot and a flag INI are input to the address input of the SQROM4-2, and various control commands in each time slot are generated based on these inputs. 4-3 is a logic gate, SQROM
The output by 4-2 is further controlled by various flags and calculation request flag CLRQ, etc., and SQ signal (calculation information, effect switch 1-3
, Etc., a signal for instructing how each functional block should operate for each time slot is generated (abbreviated as SQ in the figure).

Figure 5 is a detailed diagram of UCIF2-3. In Fig. 5, 5-1
Is a latch which latches A / D 0 to 7 given by the microcomputer 1-4 in FIG. 1 by ALE. A / D 0-7 and A
Since the relation of LE is as shown in FIG. 1 (b), the dress shown in Table 1 is latched in the latch 5-1. 5-2 is a latch, which is an A / that is given by the microcomputer 1-4.
Latch D 0 to 7 with ▲ ▼. A / D 0-7 and ▲
Since the relationship of ▼ is as shown in FIG. 1B, the data shown in Table 1 is latched in the latch 5-2. 5-3 is a latch, which is controlled by ▲ ▼ and latches the output of the latch 5-1. 2 addresses like this
Latching in stages is because ALE is periodically set to "1" regardless of ▲ ▼, and by latching addresses in two stages in this way, latching until new data is written by ▲ ▼. Addresses and data are stored in 5-3 and latch 5-2, respectively. 5-4 is a 1-word 8-bit RAM, A is an address input, OE is an output control terminal, and a data terminal D is connected to the HE bus. Here, the data of the address given by the A input with OE = 1 is output from the D terminal. WE is a write control terminal, and when WE = 1, the data given to the D terminal is written to the address given by the A input. OE, WE is SQ
It is controlled by a signal. RAM5-4 has various data (NOD, PDD, RLD, VOL, DMP, SOL, TAB, PE, V) shown in Table 1.
LD) and control data CONT (written from the data bank, details will be described later), data in the pitch data register
Each PDR stores 8 channels. 5-5 is a selector, which is the address specified by the microcomputer 1-4 and SQ
The address designated by the signal is selectively output by using another SQ signal and is given to the A input of the RAM 5-4. A signal processor 5-6 is connected to the HE bus and takes in data on the bus to generate various flag signals. In addition, the microcomputer 1-4
16 types of release envelope data corresponding to 4 bits of the release data RLD sent from the generator are generated and sent to the HE bus. Reference numeral 5-7 is a gate, which outputs the output of the latch 5-2, that is, the data from the microcomputer 1-4 to the HE bus in response to the SQ signal.

Next, the operation of UCIF2-3 will be described.

Assuming that the data shown in Table 1 is given from the microcomputer 1-4 at the timing shown in FIG. 1 (b), it is assumed that the address is 05 ₁₆ and the data is 89 _{16 that} is, the channel 5 is pressed with F # 1. If an instruction is given, the address is first latched in the latch 5-1 by the ALE signal, and then by the ▲ ▼ signal.
At the same time as the data is latched in 5-2, the address is latched in the latch 5-3. Next, at a predetermined timing, the selector 5-5 selects the output of the latch 5-3 and, at the same time, the gate 5-
7 is opened and a write signal is given to WE of RAM5-4. By this write signal, the data latched in the latch 5-2, that is, the data that the microcomputer 1-4 tries to write, that is, 89 ₁₆ is given to the HE bus, and the A input of the RAM 5-4 is the output of the latch 5-3. 05 ₁₆ is given, so address 05 of RAM5-4
Data that 89 ₁₆ is written at address _16. In this way, the various data shown in Table 1 are written in the RAM 5-4. As shown in Table 1, RAM5-4 is written with flags such as VOL flag and PE flag. These flags are sent to the signal processor 5-6 via HE bus. It is used after being latched once.

FIG. 6 is a detailed diagram of CDR2-4. 6-1 is a 10-bit frequency divider with a master clock as input. 6-2 is R with comparator
AM (hereinafter referred to as CDRAM), which has 8 words with 13 bits per word. A comparator is provided in the upper 10 bits of each word, and the frequency divider 6-1 is input from the terminal T.
Is compared with the frequency-divided data, and if all 10 bits match, a matching pulse is output from the terminal C. OE, WE,
The functions of A and D are the same as those of RAM5-4 described above. Reference numeral 6-3 is a decoder, and the relationship between A input, EN input and D output is as shown in Table 8. Reference numerals 6-4 to 6-11 are RS latches. When a positive pulse is applied to the S input, the Q output becomes "1", and when a positive pulse is applied to the R input, the Q output becomes "0". The coincidence pulse of RS latch 6-4 is applied to channel 0, RS latch 6-5 is applied to channel 1, ... 6-12 is a selector, A
One signal is selected from 8 signals given to the input by the channel code CHC3 bit and is output from D.
6-13 is a latch that latches the output of the selector 6-12 according to the SQ signal. 6-14 are AND gates.

Next, the operation of CDR2-4 shown in FIG. 6 will be described. The frequency divider 6-1 divides the master clock and gives a 10-bit frequency division output to the T input of the CDRAM 6-2. Each word of the CDRAM6-2 contains an arbitrary value, and a matching pulse is output from the C terminal each time the upper 10 bits of these values match the output value of the frequency divider 6-1. Since a signal representing CHC, that is, a channel is input to the A input of the CDRAM 6-2, since each word corresponds to each channel, a coincidence pulse is generated for each channel. Since the coincidence pulses are input to the R latches 6-4 to 6-11, the Q output of the RS latch corresponding to the channel in which the coincidence pulse is generated is set to "1". One of the Q outputs of the RS latches 6-4 to 6-11 is selected by the selector 6-12 according to the channel code CHC.
Are sequentially selected by and are latched by the latch 6-13. latch
Since the output of 6-13 is given to the AND gate 6-14, the Q output of the RS latch currently selected by the selector 6-12 is “1”.
Then, the corresponding channel of the D output of the decoder 6-3 becomes "1" by the SQ signal applied to the AND gate 6-14, and the Q output of the RS latch is reset to "0".

The seventh is a detailed view of the memory 2-5. In Figure 7, 7-1
~ 7-4 is a RAM, each function of OE, WE, A, D is RAM5-4
Is the same as. Here, RAM7-1 has WAR, EAR1, ΔZ1, ΔE
1, WE1, EAR2, ΔZ2, ΔE2 registers, RAM7-2 WR2,
WR1, ∆T1, FR, ∆WAR, ZR2, ∆T2 registers, RAM7-3 ER1, TR1, DIF1, DW1, ER2, TR2, STW, TAB ', HAD registers, RAM7-4 NOD Each of the registers ', WE2, and VLD' stores eight channels. Note that NOD ′, TA
B ', VLD' are the data of NOD, HAB, VLD in the RAM 5-4 described above. Reference numeral 7-5 is a ROM of 1 word 10 bits and 13 words, and stores the note coefficient CN in the operation sequence shown in Tables 5 and 6. Where Q
Is an output, A is an address input, OE is an output control terminal,
ROM content is output to Q when OE = 1, and when OE = 0, Q =
It has high impedance. The value of note coefficient CN is 7th
As shown in the table. The 10-bit output of ROM7-5 is connected to the lower 10 bits of the HD bus. Reference numeral 7-6 is a signal processor which reads ND (note data) and OCT (octave data) from NOD 'stored in RAM 7-4 and generates pitch detune data PED based on these data and PE flag. , And a decoding circuit for reading and decoding the data in the register WE2.

FIG. 8 is a detailed view of FA2-6. In FIG. 8, 8-1 to
Reference numeral 8-8 is a latch, which operates with the signals of ψ1 and ψ3 generated by SEQ2-2. An adder 8-9 adds the value given to the A input, the value given to the B input (both 16 bits) and the value given to the carry input Ci, and outputs from C and Co. Co is the carry output resulting from the operation.
8-10 and 8-11 are bit processing circuits, and include latch 8-1 and latch 8
It is a circuit that performs bit operation of output by -2. Reference numeral 8-12 is a logic gate which forcibly sets the output of the latch 8-6 to "1" or "0" according to the SQ signal. Alternatively, the output is performed as it is. 8-13 is a RAM, and its size is 9 bits per word and 12 words. A, D, WE, OE
Each function of is the same as RAM5-4 described above. The 9 bits of D output are connected to the lower 9 bits of the C bus. The RAM 8-13 is a phase register for phase matching (described later) and manages the phase of the read address (WAR) for individual waveform data of 12-note notes.

FIG. 9 (a) is a detailed view of MPLY2-7. In FIG. 9, 9-1 to 9-9 are latches. Bits 0 to 9 of the L bus are connected to the latch 9-3, and bits 9 to 12 of the L bus are connected to the latch 9-5. 9-10 is an encoder. The input / output relationship is shown in Table 9. 9-
A shifter 11 shifts the 16-bit signal input from I according to the control signal input to C, and outputs it from O. The details of the shift are shown in Table 10. Reference numeral 9-12 is a bit processing circuit, which performs bit processing of the signal output from the latch 9-3 according to the SQ signal. Reference numeral 9-13 designates a decoder, which has an input A and an output D and has a relation as shown in Table 11. 9-
Reference numeral 14 is a selector, which is input to A when C = 1 and to N when C = 0 according to the SQ signal input to C 16
A book signal is selected and output from Y. The lower 11 bits of the A input are connected to GND (ground potential) (that is, "0" is given). Numeral 9-15 is a shifter which shifts a 14-bit signal input from I in accordance with a control signal input to C and outputs it from O. The details of the shift are shown in Table 12. Reference numeral 9-16 is a multiplier / multiplier, the A input of which is 12 bits in the complement notation, the B input of which is 10 bits in absolute value, and the output of which is 14 bits in the 2's complement notation. Normally, a 12-bit × 10-bit operation produces a 22-bit result, but of course, the 14-bit output of the multiplier 9-16 is the upper 14 bits of the 22 bits. Therefore, the input / output relationship in the multiplier 9-16 is as follows.

The multiplier 9-16 in MPLY2-7 uses the following method in order to further simplify the circuit.

When constructing a normal multiplier, a multiplier of 2's complement value of 12 bits × absolute value of 10 bits can obtain an accurate calculation result of 22 bits by 116 adder cells. However, in this system, only the upper 14 bits of the 22 bits originally obtained are used. That is, since the output of the lower 8 bits is not used, the arithmetic error due to the omission of the adder cell is higher in the present embodiment.
All the adder cells for the lower 7 bits which do not affect the LSB of the bits are omitted. So, in this multiplier 9-16,
The adder cell 28 for lower bit operation is omitted and the configuration is as shown in FIG. In FIG. 9B, similar cells are abbreviated in the broken line. Further, each block is a full adder, the inputs are A, B, Ci (carry input), and the outputs are sum S and carry Co.

Figure 10 is a detailed view of I / O 2/10. 10-1 in FIG.
~ 10-8 are latches. Here, the latch 10-3 is a latch with a set, and the input of the latch is bit 7 to bit 9 of the D bus.
It is connected to the. Numeral 10-9 is a shifter selector, which switches between A input and B input by C input and shifts A bit by 1 bit. A bit processing circuit 10-10 is a circuit for forcibly setting the lower 3 bits to “1” or “0” according to the SQ signal. Reference numeral 10-11 is a decoder, and the relationship between the input I and the output D is as shown in Table 13. Bits 12 to 15 of the output of the latch 10-7 are applied to the A input of the decoder 10-11. Reference numeral 10-12 is a selector which selects either the signal given to the A peak or the signal given to the B according to the C input and outputs it from Y. Reference numeral 10-13 is a shifter, which shifts the input from I according to the input of the control terminal C and outputs it from O. Ten
-14 is a noise circuit, which mixes noise with the input data according to the noise flag NA.

FIG. 11 (a) is a detailed diagram of MSW2-11. The part surrounded by a circle is a switch, and specifically it is composed of Nch MOSFET as shown in Fig. 11 (b). When the SQ signal becomes "1", the MOSFET turns on and the vertical line Then, the horizontal line becomes conductive and data is transferred. In this MSW2-11, for speeding up, immediately before data transfer, all bus lines are precharged by the ψ1 signal for each time slot and then data is transferred. This is to prevent the "1" level of the transferred data from dropping by the threshold voltage of the MOSFET because the switch is composed of Nch MOSFETs. Figures 11 (c) to 11 (re)
This is an example of the switch pattern used in MSW2-11, where the points of intersection surrounded by circles are connected via switches. In this example, each bus will be described as having 8 bits for convenience. In Fig. 11 (c), bn and
and an (n = 0 to 7) are connected. FIG. 11 (d) shows that four values b0 to b3 and "0" are written in the vertical bus by a switch. In Fig. 11 (e), b0 to b3 are written to a0 to a3, and c4 to c7 are written to a4 to a7. This makes it possible to mix the data that appear separately on two sets of buses. It is designed so that it can be transferred to another bus. Figure 11 (f) shows the bit positions converted and transferred from bus to bus. By arranging the switches in this way, the positions of the upper and lower 4 bits of the horizontal bus data can be changed. Transfer to the vertical bus. 11 (g) to 11 (d) are circuit examples for setting constants in the bus, and FIG. 11 (g) is a circuit for setting all "0" s in the bus. ) Is on the bus
This is a circuit for setting 10101010, that is, AA ₁₆ . This is because a7, a5, a3, a1 which is a part without a switch holds the one to which "1" is written by precharge immediately before the switch is opened. Figure 11 (li) shows the flag
The value of the constant is changed by TO, TO = 0
If so, 00 ₁₆ is written to the bus, and if TO = 1, EB ₁₆ is written to the bus. Data transfer from any bus to any other bus can be performed by arranging the switches shown in FIGS. 11 (c) to 11 (i) according to the way and selectively opening / closing the switches. It is possible including necessary bit processing. For example, if you want to transfer data from HA bus to A bus, HB bus to B bus, and C bus to HC bus at the same time, SW1, SW7,
SW13 should be turned on at the same time. Further, when it is desired to transfer the data of the C bus to the L bus and the D bus, if SW28, SW29 and W30 are turned on, the data is transferred through the paths of C bus → HL bus → L bus and D bus.

In MSW2-11, data transfer is shown in Fig. 11 (nu).
It is performed at the timing shown in. That is, the vertical and horizontal bus lines are precharged in the section where ψ1 = 1, data is transferred in the section from the falling edge of ψ1 to the falling edge of ψ3, and latched at the falling edge of ψ3. Here, the section from the falling edge of ψ3 to the rising edge of ψ1 is a margin for stably performing the latch operation.

Next, the data banks 1-6 will be described. Data bank 1
-6 stores four types of data. that is,
(1) Header address data, (2) Header data,
(3) Waveform data and (4) Envelope data.
Here, the header address data is 8-bit data indicating at which address the header data is stored, and the header data is 8 bytes indicating the address where the waveform data and the envelope data are stored and their attributes. Data. Next, the four types of data will be described in more detail.

(1) Header Address Data (HAD) This data is data indicating the address of the header data with the note data assigned to each tablet, each octave, and each three keys as an address. The storage location of the header address data is as shown in Table 14, bit 9 to bit 5 is tablet data TAB, bit 4 to bit 2 is octave data OCT, bit 1 to bit 0 is the upper 2 bits of note data ND, All the remaining bits contain "1". Here 10 consisting of TAB, OCT, ND
It goes without saying that the bits are called WTD, and each of them is as shown in Table 1. The address of the header data according to the header address data is shown in Table 15, the header address data is contained in bits 10 to 3, and the upper bits are all "1". Also, 00 for the lower 3 bits
Enter the data of 0 to 111.

(2) Header data (HD) The header data is data of 8 words with 1 word 8 bits stored in the address shown in Table 15, and the contents of 8 words are as shown in Table 16. In Table 16, CONT is control data and represents the attributes of the waveform data and envelope data indicated by this header data. E1 'is one of the two types of envelope data. The start address of the other envelope data E2 'is given by STE + ΔSTE. W1 and W2 are two types of waveform data, and the start address of W1 is STW +
Given by ΔSTW.

The CONT has the structure shown in Table 17, and its meaning is as follows.

P / O: A flag indicating whether the musical sound according to this header data has a piano type envelope or an organ type envelope, and if P / O = 1, it means that it is a piano type.

ORG: 3-bit information indicating which musical range the relevant musical tone data originally belonged to, and correspondence between CRG and musical range is as shown in Table 18. Therefore, it is also information indicating how many samples the waveform data actually have for one cycle.

W8: Indicates whether the waveform data has 12-bit precision or 8-bit precision. If W8 = 1, 8-bit precision is obtained. W8 ＝
When it is 1, 4-bit "0" is added to the lower part of the waveform data, and the amplitude level of the waveform is maintained.

PCM: Indicates that PCM = 1 and the rising edge of the waveform data W1 is PCM.

NA: Used when superimposing a noise signal on a tone signal 2
It is a bit signal.

(3) Waveform data (W1, W2) As described above, the musical tone generator 1-5 uses two types of waveform data, 12-bit data and 8-bit data. Most of the commercially available ROMs have a word of 8 bits or less, and a word of 12 bits is rare. Therefore, in the present invention, the waveform is stored in the ROM as follows.
That is: In the case of 8 bits, one word is sequentially stored from the address determined by STW and ΔSTW.
In the case of bit waveform data, as shown in Fig. 12, the upper 8 bits are stored sequentially from the address indicated by STW + ΔSTW, but the lower 4 bits shift the value of STW + ΔSTW by 1 bit to the right and set MSB to 1. 4 lower than the entered address
Two words are sequentially stored in the upper 4 bits of the bit. For example, if the lower 4 bits of the upper 8 bits of the waveform data at the address 0444 ₁₆ are the upper 4 bits of the address 1222 ₁₆ , the address 0445 ₁₆ is the lower 4 bits of the address 1222 _16. .

(4) Envelope data (E1 ', E2') The envelope data is 16 bits and forms one word, and its data format is as shown in Table 19. Δ
T is data that determines the update interval of the envelope address. S is a flag indicating the inclination (increase or decrease) of the envelope. Z is a flag indicating the magnitude of the inclination of the envelope, and DATA is the magnitude thereof. The data shown in Table 19 is stored in the data bank according to the addresses defined by STE and ΔSTE shown in Table 16.

Since the data bank is configured as described above, it is possible to change the timbre of three adjacent keys, while conversely, if the same octave has the same header address data, waveform data can be obtained. , Tones of the same tone color can be obtained without increasing the envelope data and the header data. Further, since arbitrary waveform data and envelope data can be designated in the header data, it is possible to generate various musical tones even with a small amount of waveform data and envelope data, depending on how they are combined.

Next, the initial processing at the time of key depression in the tone generator 1-5,
This section describes the note clock generation method, envelope generation method, and waveform generation method.

(1) Initial processing In the initial processing, various registers are initialized when a tone is generated by pressing a key. Since the operation sequence is started from the long sequence in the initial mode by pressing the key, the PDR is initialized in the time slot 13 in the adding section. This operation will be described in more detail. The PDD is read from RAM5-4 in FIG. 5 and data is loaded on the HE bus. At the same time, PED is given to the HD bus from the signal processor 7-6 in FIG. 7, and SW21 in FIG.
And SW17 turns on and PDD gets on A bus and PED gets on B bus. This data is added by FA2-6 shown in FIG. 8 and the calculation result is put on the C bus. This calculation result is sent via SW23
Take the HE bus and store it in the register PDR in RAM5-4. In this calculation, the PDD and PED are transferred to FA2-6 one time slot before the time when the PDD + PED calculation is actually performed, and the calculation result is stored in the PDR.
It is performed one time slot after the DD + PED operation is performed. The same applies to the following addition operations. Then TR1, TR2, ZR1, ZR in time slots (15) to (18)
“0” is written to 2. This operation will be described by writing "0" to TR1. In time slot (15), SW33 and S-13 are turned on in MSW2-11 of FIG. 11 (a). SW33 has the structure shown in Fig. 11 (g), and C
"0" is given to the bus. At the same time, SW13 is on, so the data on the C bus is given to the HC bus, as shown in Fig. 7.
"0" is written to register TR1 in RAM7-3.

On the other hand, the data tank reading section operates as follows. The description will be centered on FIG. 10 below. Header address data HAD is read by WRD composed of TAB, ND, and OCT. In the initial mode for performing this initial processing, the latch 10-3 is set to 111 by the SQ signal. This data is for I / O 2-10 shifter 10
Data is converted into the format shown in Table 15 by -13, and register H of RAM7-3 via D bus SW15, HC bus
Stored in AD. At the same time as this operation, the header address data HAD read from the data bank is latched by the latch 10-
8 、 Latch 10-6 latched one after another, shifter selector 10-
At 9, the data is converted into the format shown in Table 15 and latched in the latch 10-4. For the output of the latch 10-4, first, 000 is given to the lower 3 bits by the bit processing circuit 10-10, the control data CONT is read from the data bank 1-6, and the latch 10-8 is supplied via the latch 10-8. -
Latched in the upper 8 bits of 7. Control data C
ONT is selector 10-12, shifter 10-13, noise circuit 10-14,
It is stored in the register CONT of the RAM 5-4 from the D bus via the latch 10-2. On the other hand, since the upper 4 bits of the latch 10-7 are connected to the decoder 10-11, 16-bit data can be obtained according to the truth table shown in Table 14. However, at this time, the C input of the decoder 10-11 is "1". Selector 10-
12 selects this decoder output, shifter 10-13 6
Bit-shift right and output. Where this shifter 10-1
Considering the output of 3, the decoder 10-
The data input to 11 are P / O and ORRG 3 bits. Since the C input of the decoder 10-11 is "1", the output of the decoder 10-11 is determined only by the ORG3 bit. Therefore, the value obtained by right-shifting the output of the decoder 10-11 by 6 bits by the shifter 10-13 is the value shown in Table 18. This value is given to D bus via noise circuit 10-14 and latch 10-2, and MSW2-
In 11, it is stored in the register DIF1 of the RAM7-3 via SW15.

Next, the bit processing circuit 10-10 gives 001 and then 010 to the lower 3 bits to the output of the latch 10-4, and reads the upper 8 bits and lower 8 bits of the STE of the header data. The value of this STE is selector 10-12, shifter 10-13, noise circuit 1
0-14, given to D bus via latch 10-2, MSW2-11
Is stored in the register EAR1 of RAM7-1 via SW5.

Then enter the short sequence. The short sequence is executed twice. PDR and JD are added in time slot (1), where JD is a constant and SW3 in MSW2-11
Obtained by turning on 2. SW32 is shown in Fig. 11 (H).
The structure is as shown in, and JD = 45B ₁₆ . Multiply this addition result by the note coefficient CN
Get FR. To elaborate on this series of yen calculations, PDR + JD
Is calculated in the time slot (1), and the result is given to the C bus in the time slot (2) as described above.
Here, in MSW2-11, SW28 and SW29 turn on, C bus → H
Data is transferred in the order of L bus → L bus, as shown in FIG.
It is latched in the latch 9-1 of MPLY2-7 in. In the next time slot (3), the value of CN corresponding to the note data ND is read from the ROM 7-5 in FIG. 7 and given to the HD bus. This value is given to the L bus via SW19 in MSW2-11 and latched in the latch 9-3 of MPLY2-. Latch 9
The output of -1 goes to the latch 9-2 via the shifter 9-11, and the latch 9-3.
Is output to the latch 9-4 via the bit processing circuit and is latched. Therefore, the value of PDR + JD is latched in the latch 9-2.
The value of CN is latched in 9-4. Then multiplier 9-1
6 calculates the product of (PDR + JD) and CN and is sent to the latch 9-8 via the shifter 9-15 and latched. In this series of operations, the shifter 9-11, the bit processing circuit 9-12, and the shifter 9-15 operate so as to pass data. That is, "1" is given to the C input of the encoder 9-10. The value of latch 9-8 is RAM7-2 from L bus via SW9 of MSW2-11
It is stored in the register FR. Therefore, in time slot (2), ORG + OCT + 1 is calculated. In this operation, the +1 operation is performed by the logic gate 8-12 in FA2-6 in FIG. That is, if the logic gate 8-12 forcibly outputs "1" in the corresponding time slot, the latch 8-
5 latches "1" and gives "1" to the Ci input of the adder. The meaning of this operation is as follows. That is: ORG is the octave data OCT which is a value (probably N) indicating which range the waveform data originally belongs to.
The reverse logic of is shown. Tables 18 and 22 show the relationship between OCT and ORG and the number of waveform samples. Therefore ORG
+1 will represent -N. In other words, ORG + OCT + 1 = OCT-N, which is the difference between the tone range of the tone signal that is currently being generated and the original tone range of the waveform data that is actually being used, that is, the value indicating the amount of octave shift. is there. That is, it indicates how many octaves higher the range of the original waveform is read. This value is temporarily stored in the register WE2 of the RAM 7-4, then decoded by the signal processor 7-6 and stored in the register ΔWAR of the RAM 7-2. ORG + OCT
The value of ΔWAR for +1 value is shown in Table 20.

Hereafter, in time slot (4), EAR2, same (6),
Initialization of each register of WR1, ER1, WE2, WE1 and WR2 is performed in (8), (9) and (10).

On the other hand, in the data bank reading section, the header address data HA stored in the RAM7-3 in the long sequence described above is used.
Read D, D bus → latch 10-1 → shifter selector 10-
Latch to latch 10-4 via 9, bit processing circuit 10-10
Input 001 to the lower 3 bits and read out ΔSTE of the header data from the data bank. This value is latch 10-7 → selector 10-12 → shifter 10-13 → noise circuit 10-14 → latch 1
It is given to D bus through 0-2, and SW26, S in MSW2-11
It is input to the A bus via W30 and added to EAR1 at FA2-6. Next, the STE stored in register EAR1 of RAM7-1
(Start address of envelope data E1 ') is read out and latched in latch 10-4 via D bus-> latch 10-1-> shifter selector 10-9. The bit processing circuit 10-10 inputs "0" and then "1" to the LSB of the output of the latch 10-4 to read 2-byte envelope data as shown in Table 19. This value 16 bits is latch 10
Latched to -7. According to the output of the latch 10-7, the values of ΔT1, ΔE1, ΔZ1 are generated in the first short sequence, and the values of ΔT2, ΔE2, ΔZ2 are generated in the second short sequence. First, the upper 4 bits of the latch 10-7 are input to the decoder 10-11, and the upper 4 bits of the latch 10-7 contain the value of ΔT shown in Table 19. Therefore the decoder 10
-11 decodes ΔT according to Table 13 and selects
Output to. In the selector 10-12, C = 1 at this time
And outputs the B input to the selection shifter 10-13. The output of this selector 10-12 is the latch 10-2 without any bit operation being performed in the shifter 10-13 and the noise circuit 10-14.
Is supplied to the D bus via MSW2-11 and stored in the register ΔT1 of RAM7-2 via the SW10 and HB buses in MSW2-11. ΔE1,
ΔZ1, ΔE2, ΔZ2 are Z, S, DATA as shown in Table 19.
The bit operation is performed by the shifter 10-13 in accordance with the above and stored in each register. What kind of bit operation is performed is as shown in FIG. It is shown that the data format differs depending on the value of Z in Table 19.

Next, the same as when reading ΔSTE from data bank 1-6
The value of the register HAD is read from RAM7-3 and latched in the latch 10-4, and the bit processing circuit 10-10 sets the lower 3 bits of the header address data HAD to 100 in the initial mode first, then 101, 2 times. 11 in initial mode
ST from databank 1-6 by giving 0 and then 111
W, ΔSTW is read and STW is stored in RAM7-3 register STW, ΔSTM
Is stored in the register WAR of RAM7-1.

By the above, the initial setting of all the registers is completed.

(2) Note Clock Generating Method First, the principle of the note clock generating method used in the musical tone generating section 1-5 will be described with reference to FIG. In FIG. 3, 3-1 is a frequency divider, which divides the master clock input to the terminal CK and outputs a 10-bit frequency division output from Q. 3-2 is a comparator, which compares A input and B input,
When A = B, "1" is output from Q. Reference numeral 3-3 is a flip-flop which takes in the signal given to the D input at the rising edge of the CK input and outputs it from the Q. Reference numeral 3-4 is an adder, which outputs the sum of A input and B input from C. 3-5 is a constant circuit for inputting a constant M to the B input of the adder 3-4. Reference numeral 3-6 is an RS latch, which becomes Q = 1 when a positive pulse is input to the S input, and Q = 0 when a positive pulse is input to the R input. A delay circuit 3-7 delays an input signal and outputs it. 3-8 are AND gates.

Next, the operation of FIG. 3 will be described. First, the Q of RS latch 3-6
If the output is "0", the output of the AND gate 3-8 is always "0", so the Q output of the flip-flop 3-3 is constant. On the other hand, the frequency divider divides the master clock by 000 ₁₆
To 3FF ₁₆ and output 10-bit Q. If the output of the flip-flop 3-3 is N, naturally 0
Since 00 ₁₆ ≤ N ≤ 3FF ₁₆ , there is always a moment when the Q output of the frequency divider 3-1 becomes N, and at this time, a coincidence pulse is output from the Q output of the comparator 3-2. Then, since the coincidence pulse is input to the RS latch 3-6, the Q output of the RS latch 3-6 becomes "1", and the write pulse is output from the AND gate 3-8. Adder 3 is added to D input of flip-flop 3-3
Since the C output of -4 is given, the value of N + M is written. At the same time, the write pulse is delayed by the delay circuit 3-7 and then the Q output of the RS latch 3-6 is set to "0". Therefore, the Q output of the flip-flop 3-3 becomes constant again, but the value changes from N to N + M. So next is the divider
A coincidence pulse will be generated when the Q output of 3-1 becomes N + M. By repeating this, the comparator 3-2
Generates a pulse when the output value of frequency divider 3-1 becomes N, N + M, N + 2M .... That is, every time the frequency divider 3-1 counts the master clock M times, a coincidence pulse is generated. Further, when N + nM> 3FF ₁₆ , the output of the adder 3-4 becomes N + nM-3FF ₁₆ after the overflow, so that it goes without saying that a coincidence pulse is generated when the master clock is counted M times. . That is, if the coincidence pulse of the comparator 3-2 is used as the note clock and the constant M is changed, note clocks of various cycles can be obtained, and the frequency thereof is (frequency of the master clock) ÷ M. The Q output of the SR latch 3-6 corresponds to the calculation request flag CLRQ.

The above is the principle of the note clock generation method in the present invention.

Next, the details of the operation sequence of note clock generation in the musical tone generating section 1-5 shown in FIG. 1 will be described.

A key is pressed on the keyboard 1-1, and the microcomputer 1-4 causes the musical tone generator 1-
When the generation of a musical tone is instructed to 5, the operation sequence starts from the initial mode long sequence as described above. First, in the time slot (13), PDD + PED → PDR ...... (2-1) Then, in the short sequence, in time slot (1) ... (6) PDR + JD → LB ...... (2-2) CB × CN → FR ... … The operation of (2-3) is performed. Then, the normal mode is entered, and FR + CDR → FR …… (2-4) in the short sequence time slot (9) and PDR + JD → LB …… (2-5) CB in the long sequence time slot (14) to (18). CN → FR …… (2-6) PDD ＋ PED → PDR …… (2-7) is calculated. Here, PDD is the PDD shown in Table 1, that is, pitch detune data, and PED is the above-mentioned pitch extended data. JD is a constant and is 11 15 ₁₀ (16
A value of 45B in decimal is set. Note coefficient C
N is a value determined by the assigned note name, and the note name and C
The relationship of N is shown in Table 7. As described in the explanation of Tables 5 and 6, the operations (2-2), (2-3) and the operations (2-
5) and (2-6) can be expressed as the following equation.

(PDR + JD) × CN → FR …… (2-8) Since PDR is PDD + PED, the calculation (2-8) is (PDD + PED + JD) × CN → FR …… (2-9). The value of this FR is accumulated in CDR as shown in the operation (2-4). As described above, this accumulation is performed once every time the note clock is generated. Therefore, assuming that the initial value of CDR is N, the value of CDR changes to N, N + FR, N + 2 × FR, .... The upper 10-bit value of this CDR is compared with the 10-bit divided signal obtained by sequentially dividing the master clock, and a match pulse is generated, so in practice, And the upper 10 bits of CDR are the 3rd
Corresponds to flip-flop 3-3 in the figure, Corresponds to the value M of the constant circuit 3-5 in FIG. Therefore, the above (2
-1) to (2-7) can be performed to obtain a note clock with a constant period, and its frequency is Becomes

(3) Waveform generation method The waveform generation method shown in Fig. 1 musical tone generator 1-5 is roughly divided into the following five steps. That is: Address generation Generates an address when waveform data is read from the data bank 1-6.

Waveform reading Waveform data specified by the above address is stored in the data bank 1-6
Read out and perform bit processing according to the control data CONT.

 Envelope multiplication Two-wave mixing CN multiplication Each step is described in detail below.

Address generation STW of header data (W
2 start address), ΔSTW (number of W1 words), DIF1
(The number of samples included in one waveform) is the register STW, WAR, DI
It is stored in F1 and the register ΔWAR is determined by arithmetic operation. Addresses are generated in normal mode based on these data. In the following processing, the waveform data has a PCM part (PCM = 1) and no waveform data (PCM).
= 0), the address generation is different, so if there is a PCM part and P
I will explain separately if there is no CM.

When there is no PCM part, STW is used in time slot (2) as shown in Table 6.
And WAR are obtained, waveform 1 is read from data bank 1-6 with this sum, and DIF1 is added to the above sum in time slot (4), that is, STW + WAR + DIF1 data bank 1- Waveform 2 is being read from 6. Here, STW is the start address of waveform 2, and register WAR contains ΔSTW as an initial value, that is, a negative number of words included in waveform 1, and ΔWAR is accumulated in time slot (7). . Therefore, the value of STW + WAR is a value that sequentially increases from the start address of waveform 1 for each value of ΔWAR. Further, the value of ST + WAR + DIF1 is the value obtained by adding DIF1 to this value, and therefore the value increases every ΔWAR from the start address of the waveform 2. Here, .DELTA.WAR is a value that represents the skip of reading the waveform, so that the addresses for waveform 1 and waveform 2 can be generated as described above.

Further, in the present sound generation unit 1-5, phase matching is performed when there is no PCM unit, the solo flag SOL = 0, and octave shift is not performed. In the phase matching method, 9-bit data having the same-sound name in the RAM 8-13 as an address is stored in the register WAR as a calculation result in the first time slot (7) when the calculation sequence is switched from the initial mode to the normal mode. The output of RAM8-13 is 9 bits, but since the C bus is precharged, all 16
“1” is entered in the upper 7 bits of the above 9 bits. The calculation results of the second and subsequent time slots (7) are
As shown in Table 6, R is stored in register WAR
It is updated to the register (phase register) whose address is the same name in AM8-13. By doing this,
Even if a tone with the same name has already been generated on another channel, the value of register WAR for that channel is given to register WAR of the channel that is about to generate a tone via RAM8-13. It is possible to match the phase between these two channels.

Here, the calculation WAR + ΔWAR of the time slot (7) will be described.

When WAR + ΔWAR ≧ 0, −512 ₁₀ (FF00 ₁₆ ) is given to the C bus as the calculation result regardless of the range. When there is no octave shift, ΔWAR = 1, so the value of the register WAR is repeated with 512 as the cycle.

As described above, since the registers WAR of the plurality of channels that generate the same note are always the same, the phases of the waveforms of the same note that the different channels generate are completely the same, and the phase matching is realized.

Next, the calculation STW + WAR in the time slot (2) will be described in more detail.

Data is read from the register STW of RAM7-3, and MSW2-11
Clock ψ via HC bus, SW11 and A bus as shown in
It is latched by the latch 8-1 of FA2-6 by 3. RAM7 at the same time
The value of the register WAR of -1 is latched in the latch 8-2 of FA2-6 by the clock ψ3 via the HA bus, SW2 and B bus. The output of the latch 8-1 is latched in the latch 8-3 by the clock ψ1 without undergoing any bit processing in the bit processing circuit 8-10. On the other hand, the output of the latch 8-2 is the bit processing circuit 8
At -11, ORG is input and bit processing as shown in Table 21 is performed and then latched by the latch 8-4 at the clock ψ1. An adder 8-9 adds the outputs of the latch 8-3 and the latch 8-4, and the result is given to the C bus via the latch 8-7 and the latch 8-8. By performing the bit processing as described above in the bit processing circuit 8-11, even though the register WAR changes in 512 cycles, it changes in cycles corresponding to each octave. For example, when ORG = 5 and OCT = 2, there is no octave shift and ΔWAR = 1 as described in the section of initial processing. Also, from Table 21, bits 7 and 8 of register WAR are always 1, so the calculation result of time slot (2) is -10, -9, ... -1, -128,-if STW '= 0. It becomes 127,… −1, −128… and repeats in 128 cycles. Also, ORG =
When 4 and OCT = 5, it becomes 2 octave shift and ΔWAR =
It becomes 4. In addition, according to Table 21, bits 6, 7, 8 of register WAR
Is always 1, so that -40, ...- 8, -4, -64, -60, -56 ...- 4, -64, ... are repeated in 16 cycles.

The repetition period of 128 when OCT = 2 and the repetition period of 16 when OCT = 5 indicate that the desired waveform points are obtained from Table 22.

When ORG = 4 and OCT = 5, the register WAR is incrementing by 4 means that the number of waveform samples is 64 as shown in Table 18.
It is shown that the octave of the original waveform data can be increased by 2 octaves by obtaining the data of 1 point for every 4 samples.

When there is a PCM part The address generation when there is a PCM part is the same as in the case where there is no PCM part, except for the calculation in time slot (2).

In time slot (2), STR + WAR calculation is performed. That is: Data is read from the register STW of the RAM 7-3 and latched in the latch 8-1 of the FA 2-6 by the clock ψ3 via the HC bus, SW11 and A bus. At the same time, register W of RAM7-1
The value of AR is the HA bus, SW2, and FA2-6 latches via the bus 8-2
Latched on. Here, the output of the latch 8-1 is input to the bit processing circuit 8-10, and the output of the latch 8-2 is input to the bit processing circuit 8-11, but both outputs are latched without bit processing. , Is sent to the latch 8-4 and added by the adder 8-9.

Here, considering the value of the register WAR, if there is no PCM part, the negative value of the number of samples included in one cycle of the waveform is written to the register WAR as an initial value. As the initial value of, a negative number of all the sample numbers of the waveform used as the PCM part is written. Therefore, the calculation result of the time slot (2) is sequentially Δ from the PCM head address of the waveform 1 in the data bank 1-6.
The value increases by WAR. The end of the PCM part is detected by detecting that WAR + ΔWAR ≧ 0 in the calculation in the time slot (7), and the address generation after the end of the PCM part is P
The bit processing circuit 8-11 is exactly the same as when there is no CM section.
Bit processing is performed.

Note that the address calculation in the musical tone generating section 1-5 is 16 bits, but it is naturally conceivable that a 16-bit address signal is not sufficient. Therefore, in the musical tone generating section 1-5, the address space can be expanded by using the upper 3 bits of the tablet data TAB. Latch 10-3 in I / O 2-10 is a latch for address space expansion,
The upper 3 bits of the tablet data TAB are latched by the latch 10-3. That is: When the key is pressed to enter the initial mode, the tablet data stored in the RAM 5-4 is stored in the register TAB 'of the RAM 7-3 via the MSW 2-11. Next, when the normal mode is entered, the value of register TAB ′ in RAM7-3 is read and MSW2-11
Latch 10-3 in I / O 2-10 via.
In this way, although the internal operation is 16 bits, it is possible to access the 19-bit address space.

Waveform reading Waveform reading is performed based on the addresses performed in the time slots (2) and (4). The calculation result by time slot (2) is C bus, SW28, HL bus, SW30,
It is latched by the latch 10-1 of the I / O 2-10 via the D bus.
First, the output of the latch 10-1 is the shifter selector 10-9, the latch
10-4, data bank with data latched by latch 10-3, which is latched by latch 10-5 via bit processing circuit 10-10
Reads 1-6 and the outputs of data bank 1-6 are latched in latch 10-8. Next, the output of the latch 10-1 is right-shifted by 1 bit by the shifter selector 10-9, "1" is added to MSB, and the result is latched by the latch 10-4. The output of the latch 10-4 is latched in the latch 10-5 through the bit processing circuit 10-10, and the data in the data bank 1-6 along with the data by the latch 10-3
Is read, and the outputs of the data banks 1-6 are latched in the latch 10-7. At this time, since the output of the latch 10-8 is given to the upper 8 bits of the latch 10-7, it is latched together with the previous value of the data bank 1-6. Where the latch 10-7
The data latched in the lower 8 bits of 2 corresponds to 2 words of the lower 4 bits of the 12-bit waveform as described in the section of the data bank. The output of the latch 10-7 is given to the shifter 10-13 via the selector 10-12, the upper 8 bits are shifted to the right by 4 bits, and if the LSB of the output of the latch 10-1 is 0, the lower 8 bits are also 4 bits. Bits are shifted right, and if LSB = 1, the lower 4 bits are not shifted and are output from the shifter 10-13. Here, when W8 = 1 is specified in the control data CONT, that is, when an 8-bit waveform is designated, the shifter 10-13 sets the lower 4 bits to “0” and outputs. The output of the shifter 10-13 is given to the D bus via the noise circuit 10-14 and the latch 10-2, and is stored in the register WR1 of the RAM 7-3 via the MSW2-11. This value is the waveform data of waveform 1.

Similar processing is performed on the address obtained by the time slot (4). However, if NA = 00 in control data CONT, noise circuit 10-14
At, the noise signal is added. Bit 9 is replaced with a noise signal when AN = 01, bit 10 is replaced with NA = 10, and bits 9 and 10 are replaced with NA = 1. In this way, the noise signal is superimposed without using the adder.
This is the waveform data of waveform 2 and register WR2 of RAM7-2
Stored in.

In the present embodiment, the ninth bit and the tenth bit of 12-bit waveform data
An example in which bits and NA signals are selectively replaced with noise signals has been shown, but which bits are replaced with noise signals is completely free, and the volume of noise can be suppressed by changing the bit position.

Specific circuit examples of the noise circuit 10-14 in FIG. 10 (a) are shown in FIG. 10 (b) to FIG. 10 (e).

A is an input signal of a bit to which noise is added, C is an output signal of a bit to which noise is added, B is a noise signal to be added, NA is a signal to instruct addition of noise, and SQ is a timing to add noise. Is a sequence signal representing.
That is, a bit operation is performed on a predetermined bit signal (A) of data by a noise signal (B) at a predetermined timing according to the instruction of NA. The reason why the SQ signal is necessary is that various data other than the data to be added with noise passes through the data line of this predetermined bit, so it is necessary to indicate the timing of the data to be added with noise by the SQ signal. Because there is.

FIG. 10B shows an example in which bit A of the waveform data is replaced with a noise signal.

FIG. 10C is an example in which the bit A of the waveform data and the noise signal are ORed and replaced with the bit A.

FIG. 10D is an example in which the logical product of bit A of the waveform data and the noise signal is calculated and replaced with bit A.

FIG. 10 (e) is an example in which the bit A of the waveform data and the noise signal are exclusive-ORed and replaced with the bit A.

The purpose of adding noise is to add freshness to the sound of a musical instrument, and is essential as a breathing sound, especially for flutes.

In the example of FIG. 10B, noise is added irrespective of the waveform, that is, the tone color, because specific bits of the waveform data are simply replaced with noise. On the other hand, Fig. 10 (c) ~
In the example of FIG. 10 (e), there is some relationship between the timbre and the noise. These can be selected according to the characteristics of the adaptive musical instrument.

The example in which the noise signal is added to the predetermined bit of the waveform data has been described above, but the noise addition is not limited to this.

Similarly, the present invention includes adding a noise signal to a predetermined bit of the envelope E1 or E2. In this case, the noise circuit shown in FIGS. 10 (b) to 10 (e) is provided after the adder 8-9 in FIG.

Similarly, the present invention also includes applying a noise signal to a predetermined bit of the tone signal, WE1 or WE2 or (WE1 + WE2) × VLD. In this case, the noise circuit is provided after the multiplier 9-16 in FIG.

Envelope multiplication Two types of waveform data of waveform 1 and waveform 2 are obtained as described above, and envelope multiplication is performed on this waveform data. The envelope for waveform 1 is in register ER1 of RAM7-3 and the envelope for waveform 2 is in register ER2 of RAM7-3. Here, the envelope is described as a 13-bit floating point display with an exponent part 4 bits and a mantissa part 9 bits. The envelope multiplication is performed twice for each channel, but the operation of each is the same, so time slots (7) to (9)
The calculation of WR1 × ER1 will be described.

The data of register ER1 of RAM7-3 is sent to MPLY2- via MSW2-11.
7 is latched by the latch 9-3 and the latch 9-5. here,
The lower 10 bits of register ER1 are stored in latch 9-3 as latch 9-
Bits 9-12 of register ER1 are latched into 5. Then
The data of register WR1 of RAM7-3 is sent to MPLY2- via MSW2-11.
Latched to 7 latch 9-1. The output of the latch 9-3 has its MSB set to "1" in the bit processing circuit 9-12, and the latch 9-3
-4 is latched. That is, the latch 9-4 latches the hypothetical part of the envelope. Latch 9-1 output is shifter 9-1
Latched via 1 to latch 9-2. At this time the encoder
1 is given to the C input of 9-10 by the SQ signal,
00001 is given to the C input of the shifter 9-11. Therefore, the shifter 9-11 is the lower 12 bits of the latch 9-1, that is, the data bank 1-6.
12-bit waveform data of waveform 1 read out is latched 9-
Send to 2. The multiplier 9-16 multiplies the data in the latches 9-2 and 9-4, and the product 14 bits are latched in the latch 9-7 and sent to the shifter 9-15.

On the other hand, the exponent part of the envelope is latched in the latch 9-5, decoded by the degoder 9-13 via the latch 9-6, and given as a control signal to the shifter 9-15 via the selector 9-14. To be Therefore, the output of the latch 9-7 is shifted by the exponent part of the envelope and latched by the latch 9-8. In this way, the fixed-point waveform data and the floating-point envelope are multiplied. Latch 9-8
Output from the L bus via MSW2-11 to register W of RAM7-1
Stored in E1. The multiplication of the waveform data of the waveform 2 and the envelope is performed in the same manner and stored in the register WE2 of the RAM 7-4.

Two-wave mixing Waveforms are stored in the registers WE1 and WE2 as described above. In this step, the sum of WE1 and WE2 is calculated. The calculation in the time slot (1) corresponds to this.

Two-wave mixing is performed in the CN multiplication time slot (1), but in this musical tone generator 1-5, the sound pressure level generated according to the note name depending on the sex of the ABM 2-9 and filter 1-7. May be different. The correction for this is CN multiplication. Here, note coefficient CN is used as it is as a coefficient for correction. The calculation result of WE2 + WE1 in time slot (1) is MP from the C bus via SW28, HL bus, SW29, L bus.
Latched to the LY2-7 latch 9-1. On the other hand ROM of memory 2-5
The note coefficient CN is read from 7-5 according to the note data ND, and latched by MPLY2-7 via HD bus, SW24, and L bus 9
Latched to -3.

Here, WE1 + WE2 is 16-bit data, but the multiplier 9-
Since 16 A inputs are 12 bits, MPLY2-7 performs the following processing. That is, the upper 5 bits of the latch 9-1 are input to the encoder 9-10, and the encoder 9-10 outputs the data as shown in Table 9 from both terminals A and B. That is, the number of bits of the data in the latch 9-1 is obtained, and the shifter 9-11 latches the data in the latch 9-
Take out 12 bits from 1. For example, the value of latch 9-1 is 3A
In the case of 26 ₁₆ , since this data is substantially 15-bit data, the shifter 9-11 takes out 12 bits below bit 14 of the latch 9-1 and the output of the shifter 9-11 becomes 744 ₁₆ . In this way, the substantial part of WE2 + WE1 is multiplied by the note coefficient, the shifter 9-15 restores the original number of bits, and the latch 9-9 latches it.

As described above, data with a large number of bits is multiplied by using a multiplier with a small number of bits. The value thus obtained is output to the DAC 2-8, corrected in a predetermined cycle by the ABM 2-9, and output as a tone signal.

By the way, in the musical tone generating section 1-5, as described above, by the instruction of the microcomputer, the flag VOL in Table 1 causes the C
N multiplication can be switched to VLD multiplication. That is, in the long sequence, the register VLD8 bit of RAM5-6 is
It is sent to the register LVD ′ of RAM7-4 via MSW2-11. At the time of transmission, bit shifting is performed in MSW2-11, 8-bit data is left-shifted by 2 bits, "0" is added to the lower 2 bits, and converted to 10-bit data. This makes the number of VLD bits the same as the number of CN bits. W
Whether the value of E2 + WE1 is multiplied by the value of ROM7-5 or the value of register VLD 'is determined by the flag VOL in Table 1. If VOL = 0, ROM7-5 sends the data to the HD bus and V
If OL = 1, RAM7-4 sends data to HD bus.

With the above configuration, it becomes possible to change the level of the musical tone signal output from the musical tone generating section 1-5 by the microcomputer 1-4, and the amplitude modulation is performed by sequentially changing the value of VLD in Table 1. It becomes possible.

VL based on at least one of pressing speed and pressure
Creating D will realize the touch response function.

The touch response function is to change the volume, tone, etc. according to the speed and strength of keyboard operation. For example, when a piano key is strongly pressed, not only the volume is loud but also the tone color is gorgeous. When the key is weakly pressed, not only the volume is low but the tone color is also muffled. Although the volume and timbre change freely according to the strength of keystrokes, in the case of a piano, even if the strength with which the keyboard is pressed after keystrokes is changed, the sound quality that is decaying cannot be changed. In this way, the piano has a touch response function only with the strength of keystrokes, and such a function is particularly called initial touch control. Percussion instruments generally belong to this category.

On the other hand, since the trumpet can change the sound quality that is sustained depending on the strength of the breath, even when imitating this sound and playing with the keyboard of an electronic musical instrument, pressing the key while the trumpet sound is being generated It is necessary to change the volume and timbre by increasing or decreasing the strength of the key. Such a function is particularly called aftertouch control. Generally, string instruments and wind instruments belong to this category.

In the embodiment of the present invention, as described above, the volume can be controlled independently for each channel by performing VLD multiplication with the VOL flag.

As an application example, the strength of keystrokes is measured and VL is calculated according to the strength.
By creating the value of D and transferring it from the microcomputer, the volume of each sound changes according to the different VLD transferred for each keystroke.

When the microcomputer transfers VLD, if the tablet data is switched and transferred according to the value of VLD, the tone generation unit of the present embodiment can change the tone and the tone color according to the value of VLD. It is clear from the function description.

This tone color switching will be described using an example in which VLD is 8 bits.

Table 23 shows an example of the VLD value range and the corresponding strong and weak names and tablet names.

Each time VLD is reduced by 1 bit, the volume is reduced by 1/2 or 6 dB, which is assigned to each of the strong and weak names of musical terms. Also, since a strong tone is required for the strength, waveform data rich in harmonics is assigned to the tablet 0, and a tone tone with a volume lower than mp is required, so waveform data similar to a sine wave is assigned to the tablet 3. Prepare multiple types of waveform data in the data bank.

In this way, four tones can be switched within the VLD numerical range depending on the strength of keystrokes, and at the same time, 256 tones can be specified according to the 8-bit VLD.

The above is the initial touch control, but similarly, VLD that changes momentarily according to the magnitude of key pressing pressure after keystroke.
And the tablet data that changes momentarily according to the value of VLD is sent out by the microcomputer, the musical tone generation unit of this embodiment changes the tone color and the volume momentarily according to the change of the key pressing pressure after keystroke. be able to.

The above is the aftertouch control.

(4) Envelope generating method The envelope generating method in the musical tone generating section 1-5 is divided into the following three steps. That is, address generation, reading of envelope data, envelope calculation, and steps will be described in detail below.

Address generation STE of header data by initial setting by key depression
(Start address of envelope data E1 '), ΔST
Registers EAR1, EAR2, TR1, TR2, ΔT1, ΔT2 are initialized based on E (the number of words of envelope data E1 ′). An address calculation is performed based on these data. The calculation of the address is performed in the long sequence of the calculation sequence because the calculation frequency may be low. In addition, the envelope data can be
E1 ′ address calculation is performed evenly for envelope data
E2 'address calculation is performed.

In the odd-numbered long sequence, ΔT1 + TR1 → TR1 …… (4-1) is calculated in the time slot (13) and ΔEAR1 ＋ EAR1 ＋ Ci → EAR1 …… (4-2) is calculated in the time slot (15) and the value of EAR1 is used. Read data banks 1-6. Ci of the time slot (15) corresponds to the overflow caused by the accumulation of ΔT1 performed in the time slot (13). Here, the calculation (4-1) will be described in detail.

First, the value of the register ΔT1 of the RAM 7-2 is latched by the latch 8-1 of the FA 2-6 via the HB bus and MSW 2-11. At the same time, RAM7
-3 Register TR1 value is HC2, FA2-6 via MSW2-11
Latch 8-2. The bit processing circuit 8-10 forcibly sets the output of the latch 8-1 to "0" for the bit 3 (the reason for setting the bit 3 to "0" will be described later), and the latch
Latched at 8-3. The output of the latch 8-2 is a bit processing circuit
Latch 8-4 through 8-11. Here, the bit processing circuit 8-11 does not perform processing such as bit conversion. The outputs of the latch 8-3 and the latch 8-4 are added by the adder 8-9 and given to the C bus via the latch 8-7 and the latch 8-8,
Store the addition result in register TR1 of RAM7-3 via MSW2-11. If an overflow occurs in the addition result, "1" is output from Co of the adder 8-9. This output is latched by the latch 8-6 and used in the calculation of the time slot 15. However, this is for the case where the waveform data does not have a PCM part. When the waveform data has a PCM part (flag PCM = 1), the register TR1 is read until the PCM part is read.
However, "0" is forcibly input as the calculation result. Therefore, overflow due to accumulation of ΔT1 does not occur
The value of EAR1 is not updated until the PCM is read. ΔT1 is the value of D output when C = 0 in Table 13 as described in the section of initial processing, and register TR1 is 16
Since it is a bit register, for example, if ΔT1 = 4000 ₁₆ , the calculation (4-1) overflows the register TR1 when the operation (4-1) is performed four times, and Ci = 1 in the operation (4-2) is performed to update the address. . Here, the operations (4-1) and (4-2) are performed once every two times in the long sequence. As shown in FIG. 1 (c), the long sequence of the same channel appears in the period of 388 time slots, that is, in the period of 97 μs because one time slot is 250 ns. Therefore, calculation (4-1), (4
-2) is performed every 194 μs, and when ΔT1 = 4000 ₁₆ , the address is updated in 776 μs.

By the way, since the envelope data consists of 2 bytes, it must be updated by 2 when updating the address. In the time slot (15), the address is updated as follows.

First, ΔEAR1 is a value determined by ΔT1, and ΔT1 ≠ 00
When 08 ₁₆ , ΔEAR1 = 0000 ₁₆ , and when ΔT1 = 0008 ₁₆ , ΔEAR1 = FFEB ₁₆ = −21 ₁₀ . This operation is MSW2-1
It is performed by SW31 in 1. SW31 is as shown in Fig. 11 (i), and is a flag that indicates the value of bit 3 of ΔT1.
It is controlled by TO. If ΔT1 ≠ 0008 ₁₆ is assumed now, W31 will be 0000 _{16 on the} A bus and register EAR of RAM7-1.
From 1, the value of EAR1 is given to the B bus via the HA bus and SW2 of MSW2-11. These values are FA2-6 Latch 8-1, Latch 8
Latched to -2. The output of the latch 8-1 is the bit processing circuit 8
Sent to latch 8-3 via -10. Here, in the bit processing circuit 8-10, data conversion is not performed. At the same time, the output of the latch 8-2 is given to the bit processing circuit 8-11, the LSB of the data is forcibly set to "1", and the latch 8-2 is output.
-4 sent to. That is, 1 is added in advance in the bit processing circuit 8-11. Further, the overflow due to the operation (4-1) stored in the latch 8-6 described above is latched in the latch 8-5. Therefore, when the values of the latches 8-3, 8-4 and 8-5 are added, if the value of the latch 8-5 is "1", "2" is added to the value of EAR1. On the other hand, when the value of latch 8-5 is "0", the value of EAR1 remains incremented by 1. However, as described in the initial processing section, I / O 2-10 is forced to LSB. Since "0" and "1" are given, no inconvenience occurs.

By the way, when ΔT1 = 0008 ₁₆ , ΔEAR1 becomes FFEB ₁₆ (−
21 ₁₀ ). Therefore, 21 _{10 is} subtracted from the value of EAR1, and the envelope data 10 words before is read. As a result, the address of the envelope data is looped, and a repeating envelope like a mandolin can be generated. In operation (4-1), it was stated that bit 3 is set to “0” in bit processing circuit 8-10. The reason is that bit 3 is ΔEAR1-FFEB ₁₆ and this operation is 0008 ₁₆ to register TR1 when doing
This is to prevent adding.

ΔT2, TR2, ΔEAR2, in even number of long sequence
The calculation of EAR2 is performed in the same manner.

Since the calculations for EAR1 and EAR2 are performed completely independently, it is needless to say that completely different envelope signals can be generated for waveform 1 and waveform 2. Further, since it is easy to make the repetition cycle different for the repetition of EAR1 or EAR2, various effects can be obtained.

Reading Envelope Data Envelope data is read in a long sequence, and the envelope data of waveform 1 is
The envelope data of waveform 2 is read at an odd number of times.

The method of reading envelope data based on the values of registers EAR1 and EAR2 is exactly the same as that described in the section of initial processing, and I / O 2-10 uses data bank 1-
The data read from 6 is stored in registers ΔT1, ΔT2, ΔZ1, ΔZ2, ΔE1, ΔE2 while performing format conversion.

Envelope calculation By reading envelope data, ΔZ1, ΔZ2, ΔE
Data is stored in 1, ΔE2, and initial values are given to ER1, ER2, ZR1, and ZR2 by initial processing. The envelope is calculated according to these values.

The basis of envelope calculation is the time slots (3), (5), (6), and (8) of the adder. The envelope of the waveform 1 is calculated by the time slots (3) and (5), and the envelope of the waveform 2 is calculated by the time slots (6) and (8). Here, Ci of the time slots (5) and (8) is an overflow caused by the calculation by the time slots (3) and (6). Which overflow is caused by the time slots (3) and (6)? In this way, as to whether the time slots (5) and (8) are added, the time slot (13) for address generation,
The same as described in (15). The values of ER1 and ER2 thus obtained are the envelope data.

By the way, envelope calculation differs depending on various modes. The various modes are: 1) When the waveform has PCM and when it does not. (PCM =
1/0) 2) For piano type envelope and organ type envelope. (P / O = 1/0) 3) When the damper flag is turned on and when it is turned off.
(DMP = 1/0). The individual cases will be described below.

PCM = 0 and P / O = 0 The initial settings are "0" for both ER1, ER2, ZR1 and ZR2, and when the key is pressed, the envelope is calculated according to the values in registers ΔE1, ΔE2, ΔZ1 and ΔZ2. . When the key is released, ΔZ1 and ΔE of time slots (3), (5), (6) and (8)
As the values of 1, ΔZ2, ΔE2, release data is generated from the signal processor 5-6 of UCIF2-3, and registers ΔZ1, ΔE1, ΔZ2,
It is used instead of the value of ΔE2.

In this mode, the damper flag DMP has no influence on the operation.

PCM = 0 and P / O = 1 The initial setting is "0" for both ER1, ER2, ZR1 and ZR2, and when the key is pressed, the envelope is calculated according to the values in registers ΔE1, ΔE2, ΔZ1 and ΔZ2. . When the key is released, if the damper flag DMP = 1, the registers ΔE1, ΔE2,
The envelope calculation is performed according to the values of ΔZ1 and ΔZ2, and when the damper flag DMP0 is the same as when PCM = 0 and P / O = 0.

PCM = 1 and P / O = 0 The initial settings are EA1 = 1FFF ₁₆ , ER2 = 0, ZR1 = 0, ZR2 = 0. When the key is pressed and the waveform 1 is reading the PCM part, the initial value is held, and after reading the PCM part, the envelope is calculated according to the values of the registers ΔE1, ΔE2, ΔZ1, ΔZ2. When the key is released, the calculation is performed based on the release data by the signal processor 5-6 of the UCIF 2-3 regardless of whether the waveform 1 reads the PCM section. Ie PC
Reduce if M = 0 and P / O = 0.

In this mode, the damper flag DMP has no influence on the operation.

PCM = 1 and P / O = 1 The initial settings are ER1 = 1FFF ₁₆ , ER2 = 0, ZR1 = 0, ZR2-0. When the damper flag DMP = 0, when the key is pressed once, the calculation is performed regardless of the key release timing. That is, when waveform 1 is reading the PCM section, register ER
Initial values of 1, ER2, ZR1 and ZR2 are held, and when the reading of the PCM part is completed, calculation is started according to the values of the registers ΔE1, ΔE2, ΔZ1 and ΔZ2. When the damper flag DMP = 1, PCM = 1 and
This is exactly the same as when P / O = 0.

As described above, the envelope signal can be freely generated according to various modes. Also, ΔE1, ΔZ1
, And ΔE2, ΔZ2 can be set independently, and the data is updated at the time determined by ΔT1, ΔT2, as is clear in the section of address generation, so various musical tones can be produced in combination with the above-mentioned two types of waveform data. Can occur.

(Effects of the Invention) As described above, the present invention generates predetermined waveform data and a predetermined envelope based on the performance information sent from the performance operation unit, and multiplies the waveform data and the envelope to obtain predetermined musical tone data. By adding a tone generating section for generating a noise signal, a noise generating section for generating a noise signal, and a means for bit-manipulating a predetermined bit of the waveform data with the noise signal according to the instruction of the performance information. It is possible to generate a musical tone signal including a noise signal of various volume with a simple circuit configuration without being provided in the above.

[Brief description of drawings]

FIG. 1 (a) is a block diagram of an embodiment of an information processing apparatus according to the present invention, FIG. 1 (b) is a timing diagram of data transfer by a microcomputer, and FIG. 1 (c) is used in the present invention. FIG. 2 is a diagram showing a calculation time slot, FIG. 2 is a block diagram of the musical tone generator 1-5 in the present invention, FIG. 3 is a principle diagram of note clock generation in the musical tone generator 1-5, and FIG. 4 is a musical tone generator 1 -5 is a detailed view of SEQ2-2, FIG. 5 is a detailed view of UCIF2-3, FIG. 6 is a detailed view of CDR2-4, and FIG. 7 is a detailed view of memory 2-5, and FIG. Is also a detailed view of FA2-6, Fig. 9 (a) is a detailed view of MPLY2-7, and Fig. 9 (b) is a multiplier 9-1 used in MPLY2-7.
6 is a detailed diagram, and Fig. 10 (a) is the I / O in the tone generator 1-5
2-10 is a detailed view, FIGS. 10 (b) to 10 (e) are detailed views of the noise circuit 10-14, and FIG. 11 (a) is a detailed view of the MSW2-11, FIG. 11 (b). ) ~ Fig. 11 (i) is a pattern diagram of the switch used in MSW2-11, and Fig. 11 (nu) is MSW2-11.
12 is a timing chart of data transfer in FIG. 12, FIG. 12 is a diagram showing a data format in the data bank 1-6, FIG. 13 is a diagram showing a data format of envelope data in the data bank 1-6, and FIG. 14 is a conventional electronic musical instrument. It is a block diagram of. 1-1 …… Keyboard, 1-2 …… Tablet, 1-3 …… Effect switch, 1-4 …… Microcomputer, 1-5 …… Music tone generator, 1-6 …… Data bank, 1-7… ... filter, 2-1 ... master clock, 2-2 ... sequencer (SEQ), 2-3 ... microcomputer interface (UCIF), 2-4 ... comparison register (CD
R), 2-5 ... Memory, 2-6 ... Full adder (FA), 2-7
...... Multiplying unit (MPLY), 2-8 …… Digital-to-analog converter (DAC), 2-9 …… Analog buffer memory unit (AB
M), 2-10 …… I / O circuit section (I / O), 2-11 …… Matrix switch section (MSW).

Claims (1)

[Claims] 1. A musical tone generating section for generating predetermined waveform data and a predetermined envelope based on performance information sent from a performance operating section, and for multiplying the waveform data and the envelope to generate predetermined musical tone data. A noise generating unit that generates a noise signal and a predetermined bit of the waveform data is replaced with the noise signal according to the instruction of the performance information, or a logical sum, a logical product, or an exclusion of the waveform data and the noise signal An electronic musical instrument having means for performing one of the processes of replacing any one output of the logical OR.