JPS58174999A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument that generates musical tones based on digitally generated musical sound waveforms.

In the IMJ and tif music synthesizers, musical tones are generated by reading musical waveforms such as sine Yoshichi waves and sawtooth waves from a waveform memory. Also, one way to change the timbre of the generated musical sound is to add noise to the musical waveform from the waveform memory, but in this case, if the musical waveform and noise are input to an adder and simply added, Composite amplitude value f: The number of bits expressed may be larger than the number of bits expressing the maximum amplitude value of the musical sound waveform, and therefore exceed the capacity of the digital/analog conversion circuit connected to the output side of the musical tone generation circuit. There is a risk of inconveniences such as being lost.

On the other hand, in order to eliminate such drawbacks, it may be possible to keep the maximum amplitude value of the musical sound waveform small in advance.If this is done, the musical sound level when no noise is added will be reduced, and it may be possible to consider the sly ratio etc. There are drawbacks that are not a good idea when doing so.

This invention was made against the background of the above-mentioned circumstances, and its purpose is to change the timbre of a generated musical sound by adding another musical sound waveform to a predetermined musical sound waveform. To provide an electronic musical instrument that performs the addition by determining the polarity and switching addition or subtraction of another musical sound waveform to the predetermined musical sound waveform according to the polarity, thereby generating musical tones. be.

Various embodiments of the present invention will be described below with reference to the drawings. 1 to 7 show a first embodiment in which the present invention is applied to a music synthesizer. In Figure 1,
A keyboard 1 of a music synthesizer is provided with a plurality of keys arranged in musical scale order. The switch unit 2 also includes a switch for selecting each sound source waveform (fundamental wave (BASIOWi)) such as a rectangular wave, a PWM wave (asymmetric square wave), and a #Jg1111i wave. Various switches are provided, such as a switch that makes the amount of generation variable, and a switch that controls the digital filter 7, envelope generator 8, etc., respectively. The keyboard 1 and the switch unit 2 are periodically scanned by the opυ (central processing unit) 3, and the keyboard 1
Each key switch output and each switch output of the switch section 2 are supplied to 0PU3.

cpU3ti This is a device that controls all operations of this music synthesizer, and consists of a microprocessor, etc., but its details will be omitted.

ROM (Read Only Memory) This is a memory that stores the 4Fi scale frequency code β. Then, address data for reading the scale frequency code β corresponding to the pitch of the operation keys on the keyboard 1 is supplied from the 0PU3, and the previous layer frequency code β read as a result is supplied to the unive generator 5.

The Unibu generator 5 has the above-mentioned scale frequency code β,
This is a circuit that creates the above-mentioned sound source waveform (that is, musical sound waveform) by digital calculation based on their data α, γ, and K supplied from the CPU 3, and the created waveform data is sent to the noise control unit 6. The signal is supplied to the digital filter 7 through the filter. When changing the tone, the noise control unit 6 adds or subtracts noise to the waveform data while determining the polarity of the waveform data from the Unibu generator 5, that is, whether the amplitude value is positive or negative. As a result, a musical tone with a slightly different timbre is generated than the original musical tone.

The digital filter 7 removes predetermined overtone components from the waveform data via the noise control 116 based on the simple signals from the 0PU3, and supplies the output to the envelope generator 8. Empe o-7 Ciennere-18
Based on the *'J11'll signal, an envelope is applied to the output of the digital filter to obtain a musical tone signal, which is supplied to the digital/analog converter 9. As a result, a musical tone signal converted into an analog quantity is output from the digital/analog converter 9, and the musical tone is emitted via the amplifier 10 and the speaker 11. In addition, this digital filter 7 is equipped with Fi% Kujira Sho 5.
No. 5-53179 ``Digital Filter Device'', Envelope Generator 8Kti% Gusho No. 56-74244 1 Envelope Control Hook Method for Electronic Musical Instruments'' can be applied.

Next, the configuration of the Unibu generator 5 will be specifically explained with reference to FIG. Input end of full adder 151. ~
The 16-bit data output from the shift register 17 is circulated and applied to A0.

In addition, the B input terminals B1i to B0 of the full adder 15 are equipped with a CPU.
The 16-bit data data (α1. to α.) output by the circuit 3 is applied. Note that this data a is a constant value. Further, a high level signal "'H" is always applied to the carry input terminal C1n of the full adder 15. Therefore, the full adder 15 subtracts the input data α to the B input terminal from the input data to the B input terminal, and converts the resulting data to the 8 output terminal '1
The input terminal of the full adder 16 is outputted from 8 to S0 and connected to the output side of the full adder 15. ~mu. Apply to.

B input of this full adder 16! E, , ~B, contains the scale frequency code β output from the game circuit G1 (in the case of rectangular wave creation) or the data β±(β-K)γ output from the gate circuit G2 (in the case of PW A& creation). 181. Preset through ~18°. Note that the carry output output from the terminal Cout of the full adder 15 is applied to each control input terminal of the AND gates 1815 to 18° via the inverter 19.

The result data of the full adder 16 is sent to the S output terminal S1. ~S0 and applied to the shift register 17 connected to the output side of the full adder 16. If we assume that this music synthesizer is an 8-note polyphonic synthesizer, it has a shift register of 17 ti and a capacity of 1.
It consists of 8 stages of 6-bit shift registers connected in cascade. The circuit shown in FIG. 2 executes 8-channel time-division processing operations under the control of 0PU3.

Of the output data of the shift register 17, the data in the lower 9 pits is sent to the exclusive OR gate 20. ~200 and Inmu, 1!
It will be done. The 10 to 15 bits of the above output data are applied to the control input terminals of AND gates 22-1 to 22-6 via inverters 21-1 to 21-6, respectively.

Further, the most significant bit of the output data is applied to the other input terminal of the input I (another input terminal via the input terminal 21-7) 22-6. Ant games) 22-1 to 22-6 are connected in series as shown in the figure.
) 22-6 is applied to the other input terminal of the AND gate 22-L, and similarly, the AND gates 22-5 to 22-2
22-A to 22-
1 to each other input terminal. And anime game) 2
The output of 2-1 is an exclusive OR gate 20. ~20°.

Exclusive or gate 20. ~20° output qROM (read only memory) 23 input terminal M, ~M. Applied as hair address data. 10M231i Stores sine wave data of the waveform shown in FIG. This waveform data is used to interpolate points where the amplitude level of the rectangular wave etc. generated by the Unibu generator 5 suddenly changes. Value data haoage-)246~24
Enter o.

On the other hand, the output of #'i or ant game) 22-2 is applied to the OR gates 246 to 24o via the input I (-25).The output of the OR gates 24. to 24° is then supplied to the noise control section 6. Ru.

The subtraction circuit 41 receives the scale frequency code β and the data K (
constant values) are applied respectively. The result data β- output from the subtraction circuit 41 is applied to the multiplication circuit 42.

This multiplier circuit 42 also contains data γ (this data γ is data that determines the duty ratio of the generated waveform,
≦1) is applied, and the resulting data (takes a value of 1) is applied.
β-K)r is input to the addition/subtraction circuit 43. A scale same wave number code β is applied to the other end of the addition/subtraction circuit 43, and an output of a polarity inverting circuit 32, which will be described later, is applied to the control input terminals. Then, the result data β± of the addition/subtraction circuit 43
(β-K) γd is applied to the gate circuit G2. Note that the scale frequency code β is input to the gate circuit G1, and opening/closing is controlled by a control signal output from the OPU 3 in response to operation of a switch specifying rectangular wave generation. Further, opening and closing of the gate circuit G2ij is controlled by a control signal outputted from 0PU3 in response to operation of a switch specifying PVM wave generation.

Polarity reversal circuit 32F! It consists of a shift F register 48 and an exclusive OR gate 49 connected to the output side of this shift register 48. and exclusive or gate 49
A signal from the other end t/Cjd and the output terminal C' of the full adder 15 is inputted via the inverter 50. In addition, the output of the exclusive OR gate 49 is fed back to the input side of the shift register 48 as a polarity inversion signal.
is input to the addition/subtraction circuit 430 as an addition/subtraction command.
Applied to the control input terminal. In addition, the shift register 48
In the case of the 8-tone polyphonic synthesizer described above, eight stages of shift registers each having a capacity of 1 bit are connected in cascade. Further, the output terminal C' of the full adder 15 outputs a signal (carry) at the ``H'' level when the result data of the full adder 15 becomes ``U12''.

Next, the configuration of the noise control section 6 will be specifically explained with reference to FIG. The input terminals A6 to A0 of the lower 7 bits of the program input terminal of the full adder 6-1 are exclusive OR games) 662i to 6.
-2° outputs are applied. In addition, other input terminals B, %B, , except for the input terminal M 7 of the five input terminals of the full adder 6-1 and the input terminal B of the B input terminal,
The above polarity inversion signal is applied to B4 to B0 as well as the inverter 6-.
The voltage is applied via a triple inverter 6-4. Further, the output of the OR gate 6-5 is applied to the input terminal B of the sixth bit of the B input terminal. Also full adder 6-1
The above polarity inversion signal is directly applied to the carry input terminal 01nKIfi of . Therefore, the above exclusive OR gate 6-
At each end of 4-6-2 degrees, there is an or gate 24. ~2
Data 06 to Oo via 4o are input correspondingly, and polarity inversion signals are input to each other. Also, the polarity inversion signal is sent to the OR gate 6-5.
-4,) In addition to being input through the run filter 6--, a noise signal is input through the AND gate 6-7.

Thus, the transfer gate 6-6 performs gate control using a control signal outputted from the 0PU3 via the inverter 6-8 in response to the operation condition IIK of the noise switch on the switch section 2 that is operated when changing the tone. be done. In addition, the gates of the analog gates 6-7t'i are directly controlled by the control signals mentioned above. Further, the noise signal is a signal whose level changes randomly to "H" or "L" when the noise switch is turned on.The result data output from the S output terminal 87 of the full adder 6-1 is as follows. The signal is sent to the digital filter 7.

Next, the operation of the above embodiment will be explained with reference to FIGS. First, the operation when generating a rectangular wave will be explained with reference to the time chart of FIG. Now, it is assumed that noise is not added to change the timbre of the generated musical tone. In this case, first, the switch for specifying the rectangular wave on the switch unit 2 is turned on, the noise switch is turned off, and other necessary switches are operated. Therefore, by turning on the rectangular wave setting switch, the aptrBtj wake generator 56 gate circuits G1 and GjC receive a signal with a ``H'' (i.e., ``1'') level t and an H``L'' (i.e., ``o'') level signal. Output. Therefore, from now on, the gate circuit G is opened and the gate circuit G is closed. 0PU3 also outputs a control signal of "0 level" to the noise control unit 6, and therefore the AND gate 6-7 in FIG. 11”.

In the above situation, press a certain key on keyboard 1, for example 1.
The following will explain the case where the switch is turned on. In this case, when the above-mentioned one key is turned on, the 0PU3 outputs to the ROM4 predetermined address data for reading out the scale frequency code β corresponding to the operation key from the ROM4. As a result, R
The scale frequency code β is read out from the OM4 and supplied to the unive generator 5. This scale cycle number code β is applied to the AND gates 18□ to 180 via the gate (B) path G1 which is being opened. Therefore, the output of the output terminal 0out of the full adder 15 is Fi'"0',
Therefore, the output ""1' of the inverter 19 causes the AND gate 18. ~18°I/i is under development. Therefore, the above scale frequency code β is ten gate 18 to 1.
It is applied to the B input end of the full adder 16, ~B0, through 8o. - 10,000, at this time 8 output terminal 8□ of full adder 15
,~1 voice to the input terminal of the full adder 16. Yum. to 1
6-bit all "0" data is applied. Therefore, the result data of the full adder 16 at that time becomes data having the same value as the set scale frequency code β, and is inputted to the shift register 17 when outputted from the S output terminals S18 to S18B. After this data is shifted, it is output from the shift register 17 and the full adder 15 input terminal M1. ~Mu0 is input repeatedly and exclusive or game)
20r20° invar fi 21. ~21, input.

In the case of this embodiment, all values of the scale frequency code β of each scale are output as values larger than [102AJ. That is, any one of the upper 11 to 16 bits of the 16-bit data always contains the data l''. Therefore, when one key is turned on, the scale wave number code β is set, and then the shift register is set. 17 outputs data of the same value, the output of the AND gate 22-2 is always at the 102 level as shown in FIG. ) While the output of 22-2 is 0', Fig. 5(b
), it is 10 lebel. Furthermore, at this time, the direction of the inverter ~ is 1" as shown in Figure 5 (C).
The level, and hence the output (& polarity inversion signal) of the polarity inversion circuit 32, is @o level as shown in FIG. 5(d).

As a result, a signal of 0 level is supplied to the exclusive OR gates 20. to 20o, and the data of the lower 9 bits of the output of the shift register 17 is
It is applied to the input terminals A, ~M0 of 0M23.

In addition, a @1 level signal obtained by inverting the 0 level signal by the inverter 25 is applied to the OR gates 24. to 24o, and therefore the OR gate 24.
Output signals 0. to 0 of 1 level from 6 to 24o, respectively, and output exclusive or game signals in the noise control section 6) 6-2. to
6-2° is applied to each end.

Therefore, F is applied to each other end of the exclusive OR gate 6- to 6-2°.
A polarity inversion signal of i"o" level is applied. Therefore, the lower 7 bits of the A input terminals of the full adder 6-1 in the noise control #W66 are input terminals A, .

A 12-level signal is input to all of the input terminals 7 and 7. The output of the inverter 6-3 is also input to the input terminal 7 of the most significant bit.
" is input. On the other hand, full adder 6-10B input end B7
~BOK lfi, ``signal C1'' obtained by inverting the o2o2 level inverted signal by the inverter 6-4 is input.

That is, 'transfer gate 6-6 is being opened,
Also, since the output of AND gate 6-7 is 10'', B
A polarity inverted signal inverted by the inverter 6-4 is also applied to the input terminal B of the input terminal via a transfer gate 6-6 and an OR gate 6-5. Furthermore, full adder 6-
A polarity inversion signal of ``0'' level is also applied to the carry input terminal 01n of No. 1. As a result, the resultant data output from the output terminals S7 to So of the full adder 6-1O8 becomes rllllllllOJ and is sent to the digital filter 7. The waveform diagram in FIG. 5 (&) shows a rectangular wave sent to this digital filter 7. Therefore, in the digital filter 7, C! Under the control of the PU 3, the specified overtone component is removed, and an envelope generator 8/I'i envelope is applied to the output thereof, and generation and emission of musical tones of the scale of the operation keys is started.

When data with the same value as the set scale frequency code β is input in circulation to the full adder 15OA input terminals A6 to Ao,
The constant value data α output from FicpU3 is input as 16-bit data to the B input terminals "15 to 8. Also, since the carry input terminal 01n is always set to the "H# level," the full adder 15Fi at this time β-a
o Execute the first subtraction operation, output the resulting data from the S output terminal, and apply it to the ^ input terminal of the full adder 16.

In addition, "-α" in the above equation "β-α" becomes the "L" level of the output of the carry output terminal Cout of α in FIG. 2, so the output of the inverter 19 becomes 1"0" and the 〜〜18° is closed. For this reason, full adder
The input of the scale frequency code βO to the B input terminal of No. 16 is blocked. Therefore, the result data of the full adder 16 at this time is the same as the above-mentioned l-th Q-book data of the full adder 15, and is applied to the shift register 17. And this one
When the result data of the second time is output from the shift register 17, the I+I input is input to the A input terminal of the full adder 15.
Exclusive or gate 20. ~200, inverter 21~-
7 to 21-1. After this first operation, the state of data input to the A input terminal, B input terminal, and carry input terminal 01n of the full adder 6-1 is unchanged from the previous time, and therefore, the above data is input to the digital 7 IlTough. l"
lllll1110J is sent.

Full adder 15, Antogame) 18. ,~18o.

Thereafter, the full adder 16 and shift register 17 perform an accumulation subtraction operation that is exactly the same as the first subtraction operation described above. As a result, the data, that is, the output of the shift register 17 becomes "1o2
*J (see FIG. 5(f)) is repeated. During this time, the input terminal to the full adder 6-1, the input terminal B,
The data input state to the carry input terminal C1n is also unchanged, and therefore the digital filter 7 continues to operate during this period.
The data "1111111O" is sent to. Then, by the next subtraction operation, the shift register 17 (D output becomes "
1024'', the data in the upper 11th to 16th bits of the output of the shift register 17 are all ``0'', and therefore the output of the anime game) 22-2 is as shown in FIG. As shown in 1, it is inverted to the "1.N level. Therefore, from now on, the output -bi of the i/putter 25
It becomes the n on n level and is input to the OR gates 246 to 24o.

On the other hand, if the output of the shift register 17 is
During the cumulative subtraction operation from J to [5L2J, the 10th bit data of the output of the shift register 17 holds 11', and therefore, during this period, as shown in FIG. The output of 1 is "0#" and is supplied to the exclusive OR gate 2 to 20o. Therefore, between [1024J and The voltage continues to be applied until that time.
), the output of the polarity inversion circuit 32 continues to be 1.
0″ level.

Therefore, assuming that the output of the shift register 17 becomes ``1024'' or less, for example, 1-102JJ, the lower 9 bits of the output of the t5σ shift register 17 are all ``1'', and the ROM 23 is applied to the system input terminal. Therefore, the ROM 23 is addressed by this 9-bit all ``1'' address data, and 7-bit all ``1'' m data is successively outputted to the noise control section 6 as shown in FIG. On the other hand, in the noise control section 6, since the polarity inversion signal is still at the 10" level, all "L" data is input to the A input terminal of the full adder 6-1, and all "L" data is also input to the B input terminal. Furthermore, data “0′” is input to the carry input terminal C1n.
enters. Therefore, the resulting data is the same as last time.
11111110'' and is sent to the digital filter 7.

Next, when the output of the shift register 17 becomes a value α smaller than [1023J by the next cumulative subtraction operation, uoM23# is changed to address data α smaller than the above-mentioned 9-bit all 11″ data (i.e., [11J). Therefore, as can be seen from FIG. 4, data smaller by a predetermined value than the above-mentioned 7-bit all 71'' data, fil, and data of Takenobu, which is slightly smaller than the previous time, are successively output from the ROM 23, and the full adder 6-1 It is applied as is to the input terminal of the input terminal. Then, the S output terminal of the full adder 6-1 outputs result data that is 11'' smaller than the manual data input to the A input terminal, and is sent to the digital filter 7.

Thereafter, in the same way, the output of the shift register 17 decreases by α by each cumulative subtraction operation, and the value becomes "U1".
2'', the ROM 23 is sequentially addressed in the direction in which the address data becomes smaller by α, and correspondingly, each time, amplitude value data with a smaller value than the previous one is read out. And during this time, Full Adder 6-1
The input state It of data to the A input terminal, the B input terminal and the carry input terminal 01m is the same as described above, and accordingly, the digital filter 7 receives "1" from the above-mentioned sequentially decreasing amplitude value data. Only smaller data will be sent. And the output of shift register 17 is J512J
At this time, the ROM 23 is addressed by address data of 9 bits all @0''.

Next, the result data of the cumulative subtraction operation is sent to the full adder 15.
When the value changes from r512J to l'-51IJ or less, the @l'' signal is output from the output terminal 0' of the full adder 15, and in response, one signal is output from the inverter 50 as shown in Figure (c). As a result, as shown in FIG. 5(d), the output of the polarity inversion circuit 32, that is, the polarity inversion signal is inverted to the "1'" level, and the exclusive OR gate 6-26 ~6-2. Inverter 6-3.6
-4 and are applied to the carry input terminal C1n of the full adder 6-1, respectively.

Therefore, the data below J't1xJ is shown in Figure 5 (f
), when the shift register 17 outputs the data, the upper 10 to 16 bits of the output are all 02 data, so the output of the AND gate 22-1 is as shown in FIG.
As shown in b), it changes to the "'1" level and is applied to the exclusive OR gates 208-20°. On the other hand, exclusive or gate 20. ~20o other end again 9 bits all 6
1'' data is applied, and the output is inverted to 9 bits all 10'' and applied to the ROM 230A input terminal. Therefore, the result data of cumulative subtraction is ('511J~'
The RoM 23tj near address data is sequentially addressed from all ``0'' to all ``1'' while decreasing sequentially by α. Furthermore, as a result, the S width value data that is generated one after another becomes larger as shown in FIG. 4, but the amplitude value data is an exclusive or game) 6-2. ~6-2o, all bits are inverted and input to the A input terminals of the full adder 6-1, ~Mume, and the 5th input terminal M, the @O'' signal is input, and furthermore, the input terminal B
All 10" data is input to 7 to B0, and an 11" signal is input to the carry input terminal C1n, so the data output from the full adder 6-1 during this period is input to the ROM 23.
The polarity of the amplitude value data successively output from r
It becomes equal to the data obtained by adding lJ, and the data is sent to the digital filter 7.

As shown in FIG. 5(f)K, the output of the shift register 17 is 1.
Between 1024J and "0", the amplitude of the clam wave shown in FIG.

When the cumulative subtraction result becomes "0" or less as described above, the carry output terminal 0o of the full adder 15 is output during the next subtraction operation.
A 10'' signal is output from ut, and as a result, the AND gates 18. and 18 degrees are temporarily opened, and the scale frequency code β is applied to the B input terminals B4 to B of the full adder 16. Then, the data given to the input terminal V (of the full adder 16) and this scale frequency code β are added, and when the resulting data is output from the shift register 17, as described above, the above data, that is, the scale frequency code β is "
Since the value is larger than "024", for the reason mentioned above, from this point on, as shown in FIG. Each output of 22-4 is inverted to the 0'' level.

After the scale frequency code β is set again as described above, the cumulative subtraction operation by α is executed as described above, and the output of the shift register 17 decreases from β by α, and becomes “1024 ”. During this period, the input terminal of the full adder 6-1
Both A and B input terminals h~re are 8 bits all '''0'
"Data is input, and the carry input terminal 01n is "
Since 12 signals are input, data [ooooooooIJ is sent to the digital filter 7 during this period.

The cumulative subtraction result is “1oz4J or less,” and further “U12
'', first, the value decreases to ``1o'' as shown in Figure (f).
From the time when the voltage becomes smaller than z4J, that is, 1-1023J or less, the output of the anti-game 22-2 is inverted to the "1" level. Therefore, between "1023" and "U12", the output of the full adder 6-1 directs the ROM 23 from its forge address (9 bits all ``1'' data) to the minimum address (9 bits ``0'' data). It is equal to the data obtained by adding rlJ to the inverted polarity of the amplitude value data sequentially addressed and output.

Furthermore, when the cumulative subtraction result becomes 12J, the "1" signal is output from the output terminal 0' of the full adder 15 as described above, and in response, the polarity inversion circuit 32 is activated as shown in FIG. 5(d). The output is inverted to ``'0 level. Then, if the cumulative subtraction result is less than l-511J, then the anime game)2
The output of 2-1 is inverted to "L" level. As a result, as already mentioned, the above JiK calculation subtraction result is 7'-511
Between J and "0", the output of the full adder 6-1 is "0" from the amplitude value data read out by sequentially addressing the ROM 23 from the minimum address to the maximum address.
1'' is subtracted from the data, and the data is sent to the digital filter 7.

As shown in FIG. 5(f), the amplitude of the rectangular wave in FIG. . Then, when the cumulative subtraction result becomes "0" or less, the carry output terminal 0out of the full adder 15 is
0'' signal is output, the scale frequency code β is set based on the full adder 16, and the calculation process of the next cycle of rectangular waves is started.

With the above, the arithmetic processing operation for generating a rectangular wave for one cycle is completed. For example, the calculation period in which the output of the shift register 17 changes from "0" to rOJ shown in FIG. When the net period is Tm, the calculation period T' is expressed by the following equation (IJ).

T.=-r8. -7! −・・・・・・(])α Also, the frequency fotI of the rectangular wave generated as described above
′i When the sunfling frequency is fl, the following equation (2)
It is represented by

f·=7F Next, in the case of the above-mentioned rectangular wave generation, the operation when adding noise to change the timbre of the generated musical tone will be explained. For this purpose, in advance, the noise switch is turned on together with the switch for specifying the rectangular wave on the switch s2. Therefore, a control signal of "1" level is output from the CPU 3 to the noise control @6, and as a result, the AND gate 6-7 is opened, the transfer gate 6-6 is closed, and the full adder 6 is opened.
-1 (to the input end B of the DJ1 input port, a noise signal that randomly changes at a level of 1 level is applied.

First, as mentioned above, from the time when the scale frequency code β is set at the B input terminal of the full adder 16 until the data as a result of cumulative subtraction becomes l-1o2AJ, the noise signal is either at the "0" level or the "'1 level". The operation of the noise control unit 6 will be explained for each case. During this period, the A input of the full adder 6-1) JmKFi8 bits all l'
l z #Data is input and also carry input terminal 01
A "0' signal is input to m.The B input terminal of the nest is
When the noise signal is 0', the data is ``11011111''.
'' is input, and on the other hand, when the noise signal is 1'', 8 bits all''12 data is input. Therefore, the noise signal is supplied to the digital filter 7.
The result data from adder 6-i is (-11oxlxl
oJ, and the data applied to the input terminal is 0. From ~0° “ootoo.

01'' smaller data (amplitude value data) will be supplied. Further, the result data supplied to the Tokichi digital filter 7 with a noise signal of 11" is [IIIIIIIII
OJ, that is, the data applied to the input terminal 0. ~
The left half of the waveform in Figure 6, which is data (amplitude value data) smaller than O0 by rlJ, that is, the waveform with the positive polarity amplitude based on &width value data "10000000", is actually The waveform shown is a noise signal 'l''
, and the waveform indicated by the broken line is °゛0''.Therefore, the generated waveform shows that the noise signal is @0''.
or 1'', the width value data of the 12 buildings can be expressed by one of the 111 ilt and broken lines.

The result data of the above cumulative subtraction is from J102AJ (-5L
23, the amplitude value data read from the tiROM 23 at the input terminal of the full adder 6-1 changes to its tt data 0.23. Manually set it to ~0°,
In addition, Fi"l" (No. 1 is input to the input terminal ~, and the signal ""0101 is sent to the carry input terminal 01n. Then, B
When the noise signal is 101, the input terminal receives data [l
lol1111J is input, and on the other hand, the noise signal is "1'"
When , 8 bits all "1" data is input. Therefore, this period will be exactly the same as the previous period,
When the noise signal is 10", data smaller by "001OO001" than the data input to the table input terminal of the full adder 6-1 is sent to the digital filter 7, and when the noise signal is @1', data smaller by "1" is sent to the digital filter 7. is sent. That is, the waveform shown in FIG. 6 is obtained.

While the result data of the above cumulative subtraction changes from "5L2J" to "O", the input terminal A of the table input terminal of the full adder 6-1
, ~A0 contains amplitude value data 0.0 from ROM 2I. ~O
The inverted data of o is input, and I/i''' is input to the input terminal A.
O'' signal is input, and @ is input to the carry input terminal C1n.
z Ill signal is input. When the noise signal is "0", 8-bit all 10'' data is input to the B input terminal, and when the noise signal is I''', data [0O100OOOJ is input. Therefore, the data supplied to the digital filter 7 during this period is 11" larger than the data applied to the A input terminal when the noise signal is @O", and when the noise signal is 11" From the data applied to the end,
The data is larger by 0O100OOIJ. That is, the 6th rI! The right half of the waveform shown in J, that is, the waveform of the solid line (when the noise signal is @0'') or the waveform of the broken line (when the noise signal is 112) is the amplitude of the polarity of V inus.

Next, as shown in FIG. 1(f), the output of the shift register 17 is between rOJ and
The scale frequency code β is set again at the 60B input terminal, and then the data as a result of cumulative subtraction reaches [LO24J]. II'i 8-bit all 'm01 data is input to the table input terminal of the full adder 6-1. In addition, the @1' signal is input to the carry input terminal 01n, and when the noise signal is 02, 8-bit all "'O" data is input to the B input terminal, and on the other hand, when the noise signal is "P", the data is [o OI OOOOOJ is input. Therefore, the data supplied to the digital filter 7 during this period is the data "00" when the noise signal is 90#.
0oooool", that is, the data is "1" larger than the data applied to the A input terminal, and the noise signal is 1
1", the data "o OI O0001J", that is, the data applied to the table input terminal, "ooloooolJ
This is only large data. That is, the waveform shown in FIG. 6 is obtained.

The result data of the above cumulative subtraction is “1024J to [U12
During the change to J, the inverted data of data O6 to O0 from the kiROM 23 is manually input to the front input terminal of the full adder 6-1, and the Fi"o" signal is input to the input terminal A7. Furthermore, a 112 signal is input to the carry terminal C1m, and when the noise signal is "om", 8-bit all "0" data is input to the B input terminal, and on the other hand, when the noise signal is "l", data "o" is input. OI OOOOOJ input.

Therefore, during this period, the data supplied to the digital filter 7 will be rlJ larger than the data applied to the input terminal when the noise signal is 60#, and will be larger than the data applied to the input terminal by rlJ when the noise signal is 11''. Data “oolo.

The data is larger by 001.

Furthermore, the result data of the above cumulative subtraction is [512J to [O
While changing at Jt, data 0r-Oa from IfiROM23 is input to the input terminal of the full adder 6-1 OA input terminal.
lfi is input as is, the @1''' signal is input to the input terminal ~, and the carry input terminal 01nKi'i "0'
A signal is input. And there is a noise signal at the B input terminal.
When the signal is 0'', data [11011111J is input, and on the other hand, 8-bit all @ll'' data is input to the cell where the noise signal is @1'. Therefore, the data supplied to the digital filter 7 during this period is the data "
The data is smaller by 00100001, and when the noise signal is 11'', the data is smaller by 1 than the data applied to the table input terminal.

As explained above, when adding noise to change the timbre of a generated musical sound, when the polarity of the amplitude of the generated rectangular wave is on the positive side, the noise is added in the direction where the amplitude decreases, and if the polarity is When is on the negative side, noise is added in the direction where the amplitude increases. Therefore, the inconvenience that the amplitude of the generated musical tone exceeds the capability of the D/MU converter 9 does not occur.

Next, the operation in the case of generating PWM waves will be explained with reference to FIG. Note that it is assumed that no noise is added. In this case, the PWM wave designation switch on switch s2 is turned on, and the noise switch is turned off. As a result, gate circuit G1 is turned off and gate circuit G2 is turned on. In this state, when one key on the keyboard 1 is turned on, the calculation and generation process of the PWM wave is started.

Now, the shift register output shown in Figure 7(f) is "O".
The explanation will start from the timing ("0" at the left end of the figure). That is, at this point, the output (polarity inversion signal) of the polarity inversion circuit 32 is at the 1" level as shown in FIG. Exclusive Oagu within 6) 6-2
．． ~6-4, inverter 6-3.6-4, full adder 6
The @l'' signal is applied to each carry human power leaker 01n of -1.

On the other hand, the subtraction circuit 41 outputs the result data β- and gives it to the multiplication circuit 42, and the multiplication circuit 42 outputs the result data β-
K)r is outputted and given to the addition/subtraction circuit 43. The history addition/subtraction circuit 43 outputs result data β0(β−K)γ,
It is applied to the gate circuit G2. For example, the above data is l'-10241, and the data γ-branch that determines the duty ratio takes a value of 04y71.

Therefore, when the above-mentioned one key is turned on, the data .beta.+(.beta.-K).gamma. is set in the full adder 16 at the start of arithmetic processing in accordance with an operation similar to that described for the rectangular wave generation operation. Then, a cumulative subtraction operation is performed to subtract data α (a constant value) from this setting data β0(β−K)r. and the resulting data, i.e., shift register 17
Until the output of decreases by a to [1024J,
As shown in FIGS. 7(b), (c), (d), and (・), the outputs of the Antogame 122-1, the inverter 50, the polarity inverting circuit 32, and the Antogoo 22-2 are respectively '0 ”
12, II', and IO1''. Therefore, during this period, the read waveform from the ROM 23 is invalidated, and the data output from the full adder 6-1 and sent to the digital filter 7 is [00000001J]. becomes.

The cumulative subtraction result data νI, the shift register output is [
When it becomes smaller than 1 ozAJ, the output of the AND gate 22-2 is inverted to the "1" level. Therefore, while the above result data changes from 1024J to 512J, the ROM
23 is addressed sequentially from the maximum address to the minimum address direction, and the data obtained by inverting the polarity of the amplitude value data 06 to 0° and inverting the polarity by +1 is output from the full adder 6-1 and sent to the digital filter 7. .

When the result data becomes l'-512j, the polarity inversion circuit 3
The output of 2 is inverted to @o level as shown in FIG. The @0'' signal is applied to the carry input terminal 01m of the full adder 6-1. Also, when the above result data becomes "511" or less, as shown in FIG.
The appearance of the number is reversed to 61 lebel. Therefore, until the result data changes from r511J to "0", the output of the full adder 6-1 is the amplitude value data read out by addressing the ROM 23 from the small address to the maximum address. The data obtained by subtracting rlJ from is output and sent to the digital filter 7.

Then, as shown in FIG. 7(f), the result data is "0".
If the value is below, data β-(β-K)γ is set for the full adder 16 during the next subtraction operation. In addition, as shown in FIG. 7(b) and (,), the result data is rOJ
When the result is as follows, each output of the AND gates 22-1 and 22-2 is reversed to 10 levels. The above data β-(β-K
) When γ is set in the full adder 16, the subtraction operation for each value and α is started. And the resulting data is l-102
The output of the full adder 6-1 is held at the data "1111111o" until the number is reduced to 4J.

If the result data is less than 11oz4J, it will be a/toge.)
The output of 22-2 is inverted to the "'1" level as shown in FIG. 7(I). Therefore, the data since #a is “512J
While the output of Full Atta"-6-1 decreases to
23 from the maximum address to the minimum address and is read out by "1" from the amplitude value data 06 to Oo, and is sent to the digital filter 7.

Next, while the result data becomes smaller than ``-ra, 12J'' and decreases to rOJ, the outputs of the AND gate 22-1 and the polarity inversion circuit 32 are both inverted and held at the ``1'' level. Therefore, the output of the full adder 6-1 during this period is data obtained by adding "1" to the data obtained by inverting the polarity of the amplitude value data 0. to Oo, which are continuously output by addressing the ROM 23 from the minimum address to the maximum address. The signal is sent to the digital filter 7.

This completes the arithmetic processing operation for the 1M1 period of the PWM wave, and the following is a repetition of what has been described above. and its frequency fo
is the same as in the case of a rectangular wave, and is given by equation (2). In addition, the operation when adding noise to change the timbre of the generated musical sound is the same as in the case of the square wave described above.
The explanation of its operation will be omitted.

Next, the case of a sawtooth wave will be explained with reference to FIGS. 8 to 11. First, in FIG. 8, a part of the circuit is added to the circuit of the Unibu generator 5 shown in FIG.
This is a highly functional circuit. In the circuit of Figure 8, the second
Components that are the same as those in the circuit shown in the figure are given the same reference numerals and their explanations will be omitted, and the configuration of the circuit added to FIG. 8 will be explained first.

That is, in FIG. 8, OR gate 24. ~24°, the amplitude value data read from the ROM 23 is 0. In addition to ~Op, the output of an ant game) 22-2 is applied via an inverter 25 and a transfer gate 26. And orgate 24. The ~24° output is exclusive OR gate 27. ~27o. Exclusive or gate 27. ~27o at each other end, and goo) 22-1
The output of the inverter 28 and transfer gate 29
is applied via. And exclusive or gate 21~
The output of 270 is the full adder 3 that constitutes the polarity inversion circuit.
0 is applied to the input terminal Ar−. Also full adder 3
The output of the above-mentioned ANDGOO) 22-1 is applied to the input terminal A7 of 0 through the inverter 28, transfer gate 29, and inverter 31. Furthermore, the carry person terminal 0121 of Full Adder '30 is also connected to the anime game) 22-
The way 1 comes out is inverter 28, transfer gate 29
The voltage applied through the polarity inverting circuit 32, which will be described later, is applied through the transfer gate 33. and 8 output terminals 8 of the full adder 30. The data output from ~s0 is sent to the digital filter 7 via the transfer gates 347-340 and the noise control section 60.

In addition, when operating the switches for specifying the rectangular wave and PWM wave in the transfer gate 26II'i, 0PU
A control signal output from 3 is applied to the gate to control opening and closing. The transfer gates 29 and 35 receive control signals output from the 0PU3 when a switch for specifying a sawtooth wave is operated, respectively, and the transfer gate 33 receives the control signals via the inverter 36 to control opening and closing.

Further, the output of the transfer gate 34p34/j (the above-mentioned analog gate) 22-2 is applied to the gate via the inverter 25, transfer gate 35, and inverter 37, respectively, to control opening and closing.

Output data M and data K of the shift register 17 are input to the subtraction circuit 45 . The resulting data M- is applied to the input terminal M of the divider circuit 440. On the other hand, the input terminal B of the division circuit 44 receives the result data β of the subtraction circuit 41.
-K is applied. Then, the result data (M7K)/(β-X) of the division circuit 44 is sent to the transfer gate 4 through the digital filter 7 through the 46° noise control # section 60.
The data is sent out as sawtooth wave data. Further, the output of the AND gate 22-2 is applied to each of the transfer gates 467 to 46° through the inverter 25, the transfer gate 35, and the inverter 37.47, respectively, to control opening and closing. The opening and closing of the gate circuit G1 is controlled by a control signal output from OFυ3 when a switch for specifying a sawtooth wave is operated in addition to a switch for specifying a rectangular wave.

FIG. 9 does not show the specific configuration of the noise control section 60. Full adder 6O-1OA input terminals A7-A0 receive output data 87-Sp from full adder 30 or division circuit 44, transfer gates 347-34° or transfer gates 46. ˜46°. Further, the data 87 to the town hall signal S (sign bit data) are directly applied to each of the B input terminals except input terminal B. Further, the output of the 60-3 is applied to the input terminal B of the sixth bit of the B input terminal.

Further, the signal S7 is applied to the carry input terminal 01m via the inverter 60-2. Also, oagu)
60-5, the signal S7 is transferred to the transfer gate 60-5.
In addition to inputting the noise signal through the AND gate 60
Input via -5. 60
-4a, the control signal output from the 0PU3 is gate-controlled by the signal via the inverter 60-6 in accordance with the operation state of the noise switch on the switch unit 2 which is operated when changing the tone color. In addition, the gate is directly controlled by the control button of the 60-5Fi. And the result data from the full adder 60-1 is 0 output terminal C2 to C0
The signal is output from the digital filter 7 and sent to the digital filter 7.

Next, referring to Fig. 10, the saw when no noise is added -
The operation of wave generation will be explained. First, the switch on the switch section 2 is turned on. As a result, gate circuit G1 and transfer gate 29.35 are opened, and gate circuit G1 is opened.
2. Transfer Goo) 26.33 is closed. In this state, when one key on the key chain 1 is turned on, arithmetic processing for generating a sawtooth wave starts.

The explanation will now start from the timing when the shift register 17 output is "0"("0" at the left end of the figure) shown in FIG. 1O(d). At this point, the scale frequency code β is set in the full adder 16. Therefore, this scale frequency code β
When the next output from the shift register 17, the data is larger than the code β 11024 J, so the first
As shown in Figures 0 (b) and (Q) K, the outputs of the AND gates 22-1 and 22-2 are both inverted to ``0 level''.Then, the output of the AND gate 22-2 becomes ``o''. Therefore, the output of the inverter 37 is "o-inverter 47
The output of the transformer 7 becomes ``1'', and accordingly, the transformer 7 fugates 347 to 34 degrees are closed, and the transformer X7 arc) 46 (-46, 1>4) is opened. , and gate 18
, ~18δ company A multiplication subtraction operation for subtracting data α (constant value) from the above-mentioned scale frequency code β starts. Then, until the data as a result of the cumulative subtraction operation decreases to the value of 11024J, the output state of the above-mentioned ANDG) 22-2 does not change.
46. -46
．． and the noise control unit 60, respectively. Thus, the output data M-K of the subtraction circuit 45 is input to the input terminal ^ of the division circuit 44, and the output data M-K of the subtraction circuit 45 is input to the input terminal B of the subtraction circuit 41.
output data β-K are applied respectively. Therefore, the output data H' of the division circuit is expressed by the following equation (3).

H = β I × H song - (8) In the drum, M is the output of the shift register 17, K is a constant value, in this example [l O24J , H is the maximum width value, in this example ``2'54J. Therefore, equation (3) can be rewritten as the following equation (4).

-1024 H'=β-0゜24X254 ・・・・・・
(4) Therefore, the result data of the above cumulative subtraction is 11024J
Since the data M#i gradually becomes smaller until it becomes , the value of the data M#i according to the above equation (4) decreases accordingly. In this case, data 87 to 8o are S
bit all ``1'' data to data ``xoooooo''
While the noise is reduced to ooJ, the noise control section 60 sends data h to S to the A input terminal of the full adder 60-1.
o is input, and data “1111111” is input to the B input terminal.
1" is manually input, and furthermore, the carry input terminal 01n is set to "0'.
” signal is input. Therefore, during this time, the full adder 60
The data output from the -100 output terminal and supplied to the digital filter 7 is the data obtained by subtracting "1" from the data applied to the human input terminal of the full adder 60-1. The above data S7 to S〃data l'-1oo.

While decreasing from ooooJ to 8-bit all "Q" data, data SA to S0 are input to the full adder 6O-1CiJA input terminal, and 8-bit all 10" data is input to the B input terminal, and the carry input is also input. Terminal C
A ``1'' signal is input to 1n. Therefore, the data supplied to the digital filter 7 during this period is the data obtained by adding the data L:riJ applied to the A input terminal.

Next, when the output M1 of the shift register 17, that is, the cumulative reduction result data becomes 1024J, the full adder 60-1
Deke S7 to 5OFi group applied to And if the result data is [1024J or less, Antgame)2
The output of 2-2 is inverted to ``1 level. Therefore, the transfer gate 34 (-34 degrees) is opened, and the transfer gates 46, ~4~ are closed. During this period, the output of the AND gate 22-1 is held at 10 lB, so the output of the inverter 28 is exclusively output through the open transfer gate 29).27. -27° is applied to the carry input terminal 01n of the inverter 31 and full adder 30, respectively. That is, the result data is [1oz3J~1
12'', the ROM 23 is addressed from the highest address to the lowest address, and the data obtained by reversing the polarity of the amplitude value data 0r-Oo that is continuously output is data 8.
7 to S0 from the full adder 30 and applied to the A input terminal of the full adder 60-1 of the noise control section 60 via the transfer gates 34 to 3. During this time, the data 87 to S0 gradually increase from the 8-bit all 'O' data to the data [100OOOOJ. Meanwhile, during this time, the B input terminal of the full adder 60-1 has an 8
Bit all "02" data is applied, and a 1" signal is input to the carry input terminal 01n. Therefore, while the above result data changes from "1024" to "5 work 2", the data supplied to the digital filter 7 is "1" in the data S7-50 applied to the 5 input terminal of the full adder 60-1.
The data will be added.

When the above result data becomes smaller than [512J, the output of Antogame) 22-1 also decreases as shown in Fig. 10(b).
1" level. Therefore, after that "1" signal is applied to the exclusive OR gates 20.~20°, the ROM2
3 is addressed from the minimum address to the maximum address, while the output "0" of the inverter 28 is exclusive OR gate 276-27° Inverter 31, full adder 3
0 carry input terminal 01n, respectively. Therefore, between "U11" and I'OJO, data 87 to S0 varying from data "10000000" to all 8 bits "1" are applied to the program input terminal of the full adder 60-1, and data 87 to S0 varying from data "10000000" to all 8 bits "1" are applied to the input terminal B of the full adder 60-1. Data rllll111LIJ is applied, and a 10'' signal is also applied to the carry input terminal C1n. Therefore, during this period, the digital filter 7 is supplied with data obtained by subtracting "1" from the data applied to the human input terminal. Ru. Then, the scale frequency code β is set in the h full adder 16.

This concludes the explanation of one cycle of sawtooth wave generation when no noise is added. And its frequency f.

is expressed by the following equation (5).

fO=f--7 (6) Next, the operation in the case of sawtooth wave generation with added noise is described in the first example.
This will be explained with reference to 1-. In this case, the noise switch is turned on together with the switch for specifying the sawtooth wave on the switch unit 2. Therefore, noise -4 is closed, and a noise signal that irregularly changes between '0' and 1' is applied to the input terminal B of the full adder 60-1. Then, the scale frequency code β is set in the full adder 16, and the noise control unit 6
Data “1lO11111” is applied to the 00B input terminal (・, t); a “0” signal is applied to the input terminal C1n. Therefore, the data supplied to the digital filter 7 is input to the full adder 60-1. Data S7 to S applied to the input terminal.

The data is smaller by data "00100001". On the other hand, when the noise signal is "1", 8-bit all 111 data is applied to the B input terminal, and the #'i'"On signal is applied to the carry input terminal 01n, so that it is supplied to the digital filter 7. The data is "1" smaller than the data applied to the input terminal.

Next, the above data 87~So is the data “10000000
” to 8-bit all “0” data, when the noise signal is “O”, 8-bit all “0” data is input to the B input terminal of the full adder 60-1, and the carry input is IIi'' to terminal 01n
"1" signal is input. Therefore, data larger by the data 57-S series rlJ is sent to the digital filter 7. On the other hand, when the noise signal is @1'', B
Data "0O100OOOJ" is applied to the input terminal, and a "l" signal is input to the carry input terminal 01n.

Therefore, the above data s7 to s are sent to the digital filter 7.
Data obtained by adding data/'0O100OOIJ to 0 is supplied.

Next, the cumulative subtraction result data is [1024J to [512J
During this period, when the noise signal is o2, as mentioned above, the B input terminal of the full adder 60-1 has 8 bits all@
0” data is applied and F is applied to the carry input terminal 01n.
The i'''1'' signal is applied. Therefore, the data obtained by adding the above data s and -8jcl"l" is sent to the digital filter 7. On the other hand, when the noise signal is '1'', data l'''oo1ooooooJ is applied to the B input terminal, and #i'''12 is applied to the carry input terminal 01n.
Since the signal is applied, at this time the above data 87 to
Data larger than So by data l'-00100001J is sent to the digital filter.

Next, while the data as a result of cumulative subtraction decreases sequentially from [lzJ to country], when the noise signal is 0'', the data ``is sent to the B input terminal of the full adder 60-1 as described above.
11011111'' is applied, and the @O'' signal is applied to the carry input terminal 01m. Therefore, data smaller by the data roozooooozJ than the data J~S0 is supplied to the digital filter 7 at this time.

On the other hand, when the noise signal is "1", 8-bit all 11" data is applied to the B input terminal, and the F1"'O" signal is applied to the carry input terminal. Therefore, at this time, data smaller by 11'' than the data 87 to S0 is supplied to the digital filter 7.

In the waveform diagram of FIG. 11, data [1O00oooo
At an amplitude level greater than the reference level of J, that is, an amplitude level of the glass side polarity, the solid line indicates when the noise signal is 11'', and the broken line indicates when the noise signal is 1a1''. At an amplitude level smaller than the above reference level, that is, an amplitude level of negative polarity, the actual Il!
indicates when the noise signal is '02', and the broken line indicates when the noise signal is '1'. When adding noise to this sawtooth wave, do the same as when adding noise to the above-mentioned square waves and PWM waves.If the polarity of the generated sawtooth wave is on the glass side, noise is added in the direction where the amplitude becomes smaller. is added, and when the polarity is on the negative side, noise is added in the direction where the amplitude increases. Therefore, the inconvenience that the amplitude of the generated musical tone exceeds the capability of the D/A converter 9 does not occur.

In addition, each operation in the case of generating a rectangular wave and a PWM wave in the Uniibu generator 5 shown in FIG. 8 is almost the same as that in the Uniibu generator 5 shown in FIG. 2, and therefore the explanation of the operation will be omitted. .

Next, with reference to FIGS. 12 and 13, the structure of the noise control section in which the lid of the added noise control section can be changed will be described. FIG. 12 shows the noise control section 6 shown in FIG.
This is an example of the 0ga form. In addition, the same reference numerals are given to the same component parts as in the pattern 3 diagram, and the explanation thereof will be omitted. As is clear from the figure, in this case the noise signal consists of 8-bit data (N,
-8) are output. For this reason, in addition to the noise switch, the switch section 2 is provided with, for example, a slide switch that increases or decreases the noise cover. And noise (N number N, ~Nρ each bit data is the corresponding anime) 6
-7, ~6-7°, Oagoo) 6-5. ~6-51° is applied to the full adder 6-10B input end horse ~fuku. Therefore, the opening and closing of the angles 6-87 to 6-8 degrees (C) are controlled by corresponding bit data of the 8-bit control signal. Further, each bit data of the control signal is further applied to each of the corresponding transfer gates 6-6□ to 6-6° via the corresponding inverters 6-87 to 6-8o, and is applied to each of the transfer gates 6-6□ to 6-6°. Control opening and closing to -. Also transfer goo) 6-ro 7-
A polarity inversion signal is input to both 6-60 via the inverter 6-4, and each transfer signal 6-67~
The output of 6-6° is the corresponding OR gate 6-5. ~6-9 to the B input terminal Bw%.

Above e! When adding noise, the built-in noise control section 6 turns on the noise switch and sets the slide switch for increasing/decreasing the noise cover to a desired position.

Therefore, the AND gate specified by the slide switch among the AND gates 6-7□ to 6-7° is opened, and the valley output of the input gates 6-87 to 6-8° is opened. The inverter output corresponding to the Rinding gate becomes the ``02 level, and the corresponding transfer gates 6-6, ~6-6, and Z (closed).As a result, noise signals N7~N0 of the desired level are output. , B of full adder 6-1 through the AND gate and OR gate being opened.
It is applied to the input terminal 87NB0. Noise % facing above
N7~No(Z)i is set digitally from the minimum value of 8-bit all "O" data to the maximum value of 8-bit all"12, and is set to L at the setting position of the slide switch.
The data 0 . ~Oo will be added as a variable Iil' noise signal. Therefore, musical tones with different tones are generated at any time depending on the level of the noise signal.

On the other hand, if you do not want to add noise to the color, turn off the noise switch. As a result, a control signal for all bits "♂" is output, all of the gates (6-7, -6-7o) are closed, and all of the transfer gates (6-67 - 6-6o) are opened. ~N〆 is not applied to the full adder 6-10B input terminal, but instead a polarity inversion signal is applied, and the noise control section 6 in Fig. 3
Operations similar to those described above are performed.

FIG. 13 shows a modification of the noise control section 60 shown in FIG. Note that the same reference numerals are given to the same components as in FIG. 9, and the explanation thereof will be omitted. In this embodiment as well, the noise signal is output as 8-bit data (N, to No).

Therefore, in addition to the noise switch, a slide switch is also provided which allows the amount of noise to be adjusted. And the valley pit data to the noise signal N7~ is the corresponding AND gate 60-~60--OR gate 60-3 60-3
It is applied to the B input terminals of the full adder 60-1 through . Therefore, the above Ando Goo) 60-5° ~ 60-%
The opening and closing of each Id is controlled by corresponding bit data of an 8-bit control signal. Furthermore, each bit data of the above control signal is further set to the corresponding inver melodies 0-6□ to 60-6.
o via the corresponding transfer gate 60--60
−4° applied to each gate, each transfer goo)
60-4. ~60-4° opening/closing control. Also, transfer gate 60-4. A signal command is input to both transfer gates 60-4.about.60-4.degree. ~6
The tU force of O-4o is the corresponding OR gate 60-3. ~6
It is applied to the B input terminal through 0-3o.

When adding noise, the noise control unit 60 of Kaisei turns on the noise switch and sets the slide switch for varying the amount of noise to a desired position. Therefore, AND gate 60-5. -60-5°, the AND gate specified by the slide switch above is 1&
In I Kuichitaro 0-6. The input I (corresponding to the AND gate opened above) of the output of ~60-6°
- When the evening output reaches the 60'' level, the corresponding transfer gears (60-4. to 60-4° are both closed).

In addition, noise signals j7 to N0 of a magnitude corresponding to the general convergence of the slide switch are output, and are applied to the full adder 60-1 (DB input terminal "y-"o) through the AND gate and OR gate that are being opened. Therefore, full adder 6
A variable amount of noise signals N7 to No are added to the data S7 to St applied to the O-1OA input terminal.

On the other hand, when noise is not to be added, at least the noise switch is turned off. As a result, the 'AiIJ control signal of all bits "0" level becomes a black signal, ant game) 60-5□
~60-57ri both closed and transfer goo) 60-4. ~60-4. Both f and f are open-bottomed. This causes noise signal N7 to Ndri full adder 6O-10B
The signal S7 is not applied to the input end, but the signal S7 is applied instead, and the same operation as described for the noise control section 60 of FIG. 9 is performed.

In the above-described rectangular wave, PWM wave, and sawtooth wave generation operations, we have explained the case where only 11- keys on the 11-keyboard 1 are turned on, but in this example, the music synthesizer is used for 8-tone polyphonic. Even if up to 8 keys are turned on at the same time,
Each of the circuits in FIGS. 1 to 3, No. 81, #139, No. 121, and No. 13 has 8 channels of time/minute start 3!1! By operation, it is possible to simultaneously generate the above-mentioned fundamental waves that are applied to each key, and the details thereof will be explained below.

In addition, in each of the above-mentioned embodiments, when changing the timbre of a musical sound generated by a fundamental wave such as a square wave, noise is added as another musical sound waveform to the fundamental wave, but it is not limited to this noise. The Eiso waveform of the designated waveform may be added. Furthermore, although three types of fundamental waves are used, rectangular waves, PWM waves, and sawtooth waves, other types of fundamental waves such as triangular waves, slope waves, etc. may be used. Furthermore, in the above embodiment, after setting the initial value β to a full adder, the constant value a is cumulatively subtracted to obtain the fundamental wave.However, after setting the initial value β, the calculation process is performed to cumulatively add the constant value α. In that case, the second
The design of the circuits shown in FIG. 8 and FIG. 8 may be changed. Furthermore, this invention can be used not only for music synthesizers but also for other electronic musical instruments.

As explained above, when adding another musical sound waveform to a predetermined musical sound waveform to change the timbre of the generated musical sound, the present invention determines the polarity of the predetermined musical sound waveform and uses the predetermined musical sound waveform according to the polarity. Since an electronic musical instrument is provided in which the above-mentioned addition is performed by switching addition or subtraction of another musical sound waveform to the musical sound waveform, the amplitude level of the generated musical sound to which the other musical sound waveform has been added is changed by the digital/analog converter. It is possible to reliably prevent the occurrence of inconveniences that would exceed the capabilities of the musical tones, and to generate the desired musical tones.In addition, when no other musical sound waveform is added, that is, the timbre is not changed, the amplitude level of the generated musical tones is maximized. This has the advantage that the S/N ratio can be fully considered. Furthermore, since the amount of other musical sound waveforms to be added can be made variable, there is also the advantage that extremely effective timbre changes can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an embodiment in which the present invention is applied to a music synthesizer, FIG. 2 is a specific circuit diagram of the Unibu generator 5, FIG. 3 is a specific circuit diagram of the noise control s6, and FIG. A diagram of the waveforms stored in the ROM 23. Figure 5 is a time chart explaining the square wave generation operation. Figure 6 is a diagram showing the change in amplitude level when noise is added during square wave generation. Figure 7 is a diagram of the tfi PWM wave. A time chart explaining the generation operation, FIG. 8 is a specific circuit diagram of the Unibu generator 5 according to another embodiment, FIG. 9 is a specific circuit diagram of the noise control section 60 of another embodiment, and FIG. A time chart that explains the sawtooth wave generation operation! Figure 11 is a diagram showing the change in amplitude level when noise is added to the sawtooth wave. Figure 12 is a circuit configuration diagram showing a modification of the noise control section 6 shown in Figure 3. Figure 13 is a diagram showing a modification of the noise control unit 6 shown in Figure 3. 10 is a circuit configuration diagram showing a modification of the noise control section 60 shown in FIG. 9. FIG. 1...Keyboard, 2...Switch part, 3...CPU, 4...ROM, 5...
... Unibu generator, 6 ... Noise control section, 7 ... Digital filter, 8 ...
... Envelope generator, 9 ... Digital/analog converter, 10 ... Amplifier,
15.16.30... Full adder, 17...
...Shift register, 18□, ~18°...
And gate, 2~~20°, 27. ~27°...
・・Exclusive or gate, 21-7~21-1・・・・
・Inverter, 22-6 to 22-1...AND gate, 23...self...ROM. 24, ~24o...Or Gate, 26.29.
33.34~34o, 35.4~46°...
Transfer gate, 31...Inverter,
32...Polarity inversion circuit, 41.45...
・Subtraction circuit, 42...Multiplication circuit, 43...
... Addition/subtraction circuit, 44... Division circuit, G, %
G,...Gate circuit, 6-1.6o-1...
...Full adder. Patent applicant Casio Computer Co., Ltd. Figure 4 Figure 9 T a) 71L/if to γ't Figure 5

Claims (2)

[Claims] (1)! a tone waveform generating means for generating several kinds of tone waveforms; an addition/subtraction means for adding or subtracting a predetermined tone waveform among the tone waveforms generated by the tone waveform generating means and other tone waveforms; polarity discrimination means for discriminating the polarity of an amplitude value; and while the polarity discrimination means subtracts the other tone waveform from the predetermined tone waveform while the polarity discrimination means is discriminating positive polarity, the polarity discrimination means subtracts the other tone waveform from the predetermined tone waveform; control means for controlling the operation of the addition/subtraction means so as to add the predetermined musical sound waveform and the other musical sound waveform during the discrimination; and musical sound generation means for generating a musical sound based on the output of the addition/subtraction means. An electronic musical instrument characterized by (2) The electronic musical instrument according to claim 1, wherein the musical sound waveform generating means generates noise as a musical sound waveform corresponding to the predetermined musical sound waveform. 2. The electronic musical instrument according to claim 1, further comprising: (j) variable means for varying the amount of said other musical sound waveform supplied to said addition/subtraction means.