JPH0230035B2 - - Google Patents

Description

[Detailed description of the invention]

(Industrial application field) The present invention relates to electronic musical instruments, and particularly to reading waveform memories.
generate musical tones based on the contents of memory
related to things. (Conventional technology) In recent years, electronic musical instruments have introduced digital signal processing technology.
This allows for more advanced sound creation. especially the waveform
There are various ways to read memory and generate musical tones.
It is often used because it can freely generate waveforms of any shape.
ing. Tokkosho is an example of such an electronic musical instrument.
There is one shown in No. 58-42479. This servant
The next example will be explained using the block diagram in Figure 14.
Ru. Note data is transferred to F number memory 1 by pressing the key.
is given and the 10-bit F number is read out.
Ru. F number is accumulator according to machine cycle
It is accumulated by 2. Accumulator 2 has an 18-bit configuration.
The 18-bit accumulated result is sent to shifter 3.
It will be done. Shifter 3 receives 3-bit octave data.
The input signal is controlled by the decoder 4 which receives the input signal.
The accumulated results are calculated according to the output of the decoder 4, that is,
Shifted left according to octave data, top 11
Bits are output. wave by the output of shifter 3
Waveform data is read from the shape memory 5. Here, the lowest octave (0th octave) and
the musical note one octave above (first octave)
When considering the occurrence, first, the lowest octave range
shifter 3 shifts the output of accumulator 2.
Output as is. This shifter output allows the waveform to be
Read the waveform data from memory 5. Also, the range is
If it is one octave higher (first octave), the
Lid 3 shifts the output of accumulator 2 to the left by 1 bit.
The waveform data is stored in the waveform memory 5 using this shifter output.
Read the data. Shifts the output of accumulator 2 one bit to the left.
To ft means to double
Therefore, the readout period of waveform memory 5 is doubled.
This results in the output of a musical tone one octave higher.
Ru. In this way, you can prepare a waveform memory for each range.
It is possible to generate musical tones in all ranges without
It is possible. (Problem to be solved by the invention) However, with the configuration of the conventional example above, the
This is a problem when reading out one wave repeatedly.
However, for example, if you read out the PCM waveform,
It should be used when reading out several waves only once.
I can't. Also, I want to change the tone depending on the range.
For example, from the 0th octave to the 3rd octave
For each, separate waveform memories are read and the fourth waveform memory is read.
Above the octave, use the same tone as the third octave.
In this case, even if the waveform is periodic,
Even if the waveform has a short period, the lowest octave
The same amount of memory as the memory block (2048 words in this conventional example)
is not suitable as it requires more memory.
There is a problem. In view of the above problems, the present invention has been developed by repeatedly reading one wave.
Needless to say, it is necessary to read out the PCM waveform.
Even in cases where it is necessary to prepare data for each range
If you don't need it and want to change the waveform for each range
A power supply system that prevents memory redundancy from increasing even in
It provides child instruments. (Means for solving problems) In order to solve the above problems, the electronic music of the present invention
The device receives waveform data and a start point for the waveform data.
address, and the octave value to which the waveform data belongs.
and an address of the first data.
a data bank that stores the second data including the second data;
and; includes at least timbre selection data and pitch data.
Receives performance information from the above data bank and retrieves the corresponding sound from the data bank.
Part or all of the color selection data and the pitch data
Read the second data corresponding to the address
and means for acquiring said second data from said data bank.
Part or all of the applicable first address
means for reading data;
wave in the first data corresponding to the octave value
The value obtained by subtracting the octave value to which the shape data belongs is 2
means for creating a numerical value A as an exponent of;
Add the above value A to the start address in the data of
Use the added value as the address in the data bank above.
Equipped with a means to read out the corresponding waveform data from the
It is something that (effect) With the above-described configuration, the present invention enables
This is the start of the waveform data that should be read out.
Address and the range to which the waveform data belongs (octave)
terb value) and try to generate from this
The octave value of the range and the octave of the waveform data
The difference between the values is taken to obtain the numerical value A, which is a power of 2. then
Sequentially add the number A to the start address,
The waveform data is read even with this value. on shift
generated by changing the values that are added sequentially.
Since the range of sound produced is changed, it is similar to the PCM waveform.
Waveforms can be easily read out, and waveform data can be read out easily.
The octave value to which the data belongs and the attempt to occur from this value.
Take the difference between the octave values and calculate the value based on this.
Since A has been determined, the waveform of which range should be assigned to which sound.
There is no problem even if it occurs in the area. Furthermore, by pressing the key
Read the start address and based on this value
Since the waveform data is read out, the range
Even if you want to change the tone for each
I can handle it very well. (Example) An embodiment of the present invention will be explained below based on the drawings.
Ru. FIG. 1 shows an information processing device according to the present invention as an electronic musical instrument.
FIG. This first figure
To explain, 1-1 is a keyboard. 1-2 is a tab
of the musical tones output from this electronic musical instrument.
This is an operation section for instructing tone selection. 1-3 is effective
It is a switch that controls various effects on musical sounds.
For example, you can control effects such as vibrato and tremolo.
This is a switch that instructs to turn on and off. 1-4 is ma
It is an icon (microcomputer), for example
Equivalent to Intel's microcontroller 8049. 1-5
is a musical tone generating section, and is given by microcontroller 1-4.
Waveform calculation and frequency calculation are performed based on the control signal
conduct. 1-6 is a data bank, which is a musical tone generator.
Waveform data and envelope data used in 1-5
ROM (read-only memory) where the data is stored
It is. 1-7 is a filter, which is a musical tone generator 1
-5 to suppress the aliasing noise of the musical tone signal output from
Remove. 1-8 are speakers. Next, we will explain the operation of the electronic musical instrument shown in Figure 1A.
Ru. Microcontrollers 1-4 have instructions pre-written internally.
In accordance with the order, keyboard 1-1, tablet 1-2,
The status of the output switches 1-3 is sequentially searched. Also ma
Icon 1-4 is the ON/OFF key on keyboard 1-1.
The code of the key being pressed based on the OFF state
divided into multiple channels of musical tone generators 1-5.
At the same time, the tablet
depending on the status of switch 1-2 and effect switch 1-3.
Send control data. Musical tone generator 1-5 smell
In this case, the assignment signal sent from microcontroller 1-4 is
and other control signals to internal registers.
data bank 1- based on these signals.
6. Enter the necessary waveform data and envelope data.
Musical tone signals are synthesized while being read. this musical tone
The musical tone signal synthesized in the generating section 1-5 is
is sent to speakers 1-8 through routers 1-7.
Generates musical sounds. Figure 1 (b) shows the musical tone generator 1- from the microcomputer 1-4.
The timing diagram for transferring data to 5 is shown below.
vinegar. Also, Table 1 shows musical sounds generated from microcontrollers 1-4.
The contents of data sent to section 1-5 are shown. Table 1
In this case, NOD is a note octagon that indicates pitch data.
Turb data, note data ND and octa
Constructed from key-on data OCT and key-on data Kon.
It's on. Of course, octave data OCT is based on pitch data.
means the octave value to which the data belongs. The specifics
Table 2 shows the bit configuration of NOD.
Yes, Table 3 shows the correspondence between note data ND and note names.
is shown, and Table 4 shows the octave data OCT
The correspondence between the range and the range is shown. In other words, if a musical tone is generated
6th octare of note G# for parts 1-5
B sound (hereinafter abbreviated as G#6) from channel 1
When you want to output, use the address in Figure 1 B.
00000001 and 10011110 as data to microcontroller 1
-4 will be sent. Then the PDD
This is data that is used to shift the tuning.
It is 8bit data. PDD is displayed in two's complement notation.
The variable range is -128 to +127, 256 ways.
It is. RLD is release data, after key off
This is 4-bit data that controls the attenuation characteristics of .
VOL is the volume flag, and this bit
When set to “1”, it corresponds to the volume data VLD described later.
The output level of the musical tone signal from the musical tone generating section 1-5
This makes it possible to control the DMP is a damper
flag and for piano type envelopes
A flag that causes the decay after key-off to be rapid.
function, and functions when DMP=1. SOL is SO
This is a low flag and has the same note name as other channels.
occurs when the channel is assigned.
the current musical tone and the musical tone about to occur.
This flag is used to select whether or not to match the phase characteristics.
When SOL=1, phase matching is canceled.
do. TAB is tablet data, as shown in Figure 1.
The data specified by tablet 1-2 in
data is included in this 5 bit. PE is pitch extend
Channels that set this bit to “1” with flags
requires pitch extend. VLD is boli
Youum data, and the volume flag mentioned above.
The musical sound output from the channel along with the VOL
Control the level with 8bit precision. Furthermore, these
All series of data are set independently for each channel.
It can be determined. Next, the calculation sequence in the musical tone generator 1-5 is
Let me explain about this. Tables 5 and 6 show the calculation system of musical tone generator 1-5.
- indicates the sequence. In the main musical tone generating section 1-5
processes more data in shorter computational cycles
In order to perform the operation sequence is the initial mode,
It has two modes: normal mode, and the above
Both modes are long sequence and short, respectively.
Divided into sequences. Also, the initial
Doshoto sequence and normal moderon
There are two sequences, EVEN and ODD, respectively.
It has a state. In the initial mode, microcontrollers 1-4 generate musical sounds.
When commanding section 1-5 to generate a new musical tone
From the microcomputer 1-4 in the musical tone generator 1-5
Various registers etc. for the specified channel
This mode is used to perform initial settings and is a long sequence.
The shot sequence was started twice.
Then enter normal mode. This initial mode
Once for two shot sequences in
Shooting sequence where the first eye is ODD and the second time is EVEN.
It becomes After this initial mode ends, the normal
After 6 shoot sequences
There will be one long sequence. In this embodiment, two independent systems are provided for each channel.
Multiplies a standard waveform and two independent envelopes.
It has become possible to match it, and it has become even more precise.
It also has various adjustment functions, but these calculation processing
A large amount of performance is required to time-share eight channels.
Calculation steps are required. So in a short cycle
Short sequence of things that need to be calculated
and those with low calculation frequency, that is, long cycles.
A long sequence is one that can be operated on by
Ru. and long sea during shoot sequence
Improving the efficiency of calculations by inserting sequences
ing. Short sequence, long sequence in Figure 1
The timing diagram is shown below. As shown in Figure 1 C.
11 times of shot sequence (0) to (10)
The long sequence consists of (11) slots.
It consists of nine time slots (19).
Each time slot is 250ns, divided into four
Non-overlap two-phase crossover of φ1 and φ3
The whole system is working together with the system. Shyo
The relationship between short sequence and long sequence is
Yoto sequence changes from channel 0 to channel
Each time up to 7 is repeated 8 times, one channel's worth of
Contains a long sequence. Therefore, for example, Chiyanne
The shot sequence for Le 3 is 11 x 8 + 9, 97 ties.
Once per muslot, long sequence 97×
Appears once every 776 timeslots of 8
That will happen. In addition, the long series in normal mode
-Kens has two states: EVEN and ODD.
Therefore, the period is 776 x 2, 1552 time slots.
The system is working. Next, perform individual calculations based on Tables 5 and 6.
Explain the sequence. As mentioned above, easy
The sound generating section 1-5 is activated by pressing a new key.
Now it starts with a long sequence.
From the initial mode long sequence
Explanation will be provided for each time slot. Addition section (13)PDD＋PED→PDR (15) O →TR1 (16) O →TR2 (17) O →ZR1 (18) O →ZR2 Time slot (13) means PDD
The contents of the register called PED are
Add the contents and store it in a register called PDR
That's what it means. Time slots (15) to (18) are
Write O to registers TR1, TR2, ZR1, and ZR2.
It means getting into it. Data bank reading section (12) WTD→HAD→HAD (14) HAD→CONT→CONT, DIF1 (16)〜(17)HAD→STE→EAR1 What these mean is that the data on the far left
(For example, if it is time slot (14), the device called HAD is
data) from data bank 1-6 as the address
Read the data CONT written in the center,
Stored in the registers CONT and DIF1 with the names on the far right.
It means paying. Initial mode sequence Addition section (1) PDR＋JD L.B.；O→ER2/1 (3) CRG+OCT+1→WE2→ΔWAR (4) D.B.＋EAR1→EAR2 (6) O →WR1 (8) O →ER1 (9) O →WE2 (10) O →WE1,WR2 O→ER2/1 in time slot (1) is a
ER2, 2 at the first time of the start sequence, that is, ODD.
At the time of EVEN, set O to the register ER1.
means to write. Also, L.B. means PDR
+JD operation result is stored in the L buffer without storing it in the register.
It is sent to the multiplier (described later) via the
means. In time slot (3),
After storing the calculation result in a register called WE2,
This means to decode and store it in ΔWAR.
D.B. in time slot (4) is the data described below.
The value obtained by the data bank readout section is stored in the register.
The data is sent to the adder via the D bus (described later) without going through the data processor, etc.
It means to put out. Multiplication section (4)～(6) C.B.×CN1→FR The above C.B. registers the result obtained in the addition section.
This means inputting directly to the multiplication section without going through the data.
In this case, the value obtained at time slot (1) is
It means the calculation result of PDR + JD. Data bank reading section (1) HAD→ΔSTE→A.B. (3)～(4) EAR1/2→E1/2→ΔT1/2, ΔE1/
2, ΔZ1/2 (6)〜(7) HAD→STW／ΔSTW→STW／WAR Here, A.B. of time slot (1) is the data base
The value obtained by reading the link is stored in a register, etc.
It is meant to be input directly to the A input of the adder without going through the
Taste. Also, time slots (6) to (7) STW/ΔSTW→STW/WAR is
- During the first test, that is, ODD, there is a date called STW.
Read the data and store it in a register called STW,
At the second time, that is, EVEN, the data ΔSTW is
Read and store in a register called WAR
means. Next, the normal mode will be explained. Normal mode shot sequence In Table 6, the places marked with * are no
The first shoot after a toklock occurs
The calculation is performed only by the
The flags that control the operation are the calculation request flag CLRQ and
I'll call you. Addition section (1) WE2+WE1 →L.B. (2) STW+WAR →D.B., B.B. (3) ZR1＋ΔZ1 →ZR1 (4) DIF1＋C.B.→D.B. (5) ER1＋ΔE1＋Ci →ER1 (6) ZR2＋ΔZ2 →ZR2 (7) WAR＋ΔWAR →WAR＊ (8) ER2＋ΔE2＋Ci →ER2 (9) FR＋CDR →CDR＊ Here, L.B. of time slot (1) is the calculation result
is input directly to the multiplier without going through a register.
means. D.B. and B.B. of time slot (2) are the same.
The calculation results are directly transferred to the data bank reading section and
This means inputting to the B input of the adder. Thailand
C.B. in Muslot (4) is the calculation result of the addition section
This means inputting directly without going through a register.
In this case, STW at time slot (2)
The calculation result of +WAR is input. Also, D.B.
The calculation result is directly input to the data bank reading section.
It means to force. Time slots (5) and (8)
Ci at time slots (3) and (6), respectively.
It means to add the carry of the operation
It's the taste. Multiplication section (1)～(3) WR2＋ER2→WE2＊ (4)～(6) C.B.×CN→(DAC) (7)～(9) WR1×ER1→WE1＊ Here, the C.B. of time slots (4) to (6) are additions.
Input the output of the section directly to the multiplier section without going through a register etc.
It means to do. In this case, the time slot
This corresponds to the calculation result of WE2+WE1 in (1). Also
(DAC) means that the calculation result is DAC (DA
Indicates input to a converter (described later). Data bank reading section (4)～(5) C.B.→W1→WR1＊ (7)～(8) C.B.→W1→WR2＊ Here, C.B. of time slots (4) to (5) is the addition section.
Input the calculation results directly to the data bank reading section.
and set it as the address of data bank 1-6.
In this case, the time slot in the adder is
This corresponds to the calculation result of STW + WAR in (2). Ta
Time slots (7) to (8) C.B. are also time slots.
Corresponds to the calculation result of DIF1 + (STW + WAR) in (4)
do. long sequence Addition section (13) ΔT1/2 + TR1/2 →TR1/2 (14) PDR＋JD →L.B. (15) ΔEAR1/2+EAR1/2+Ci →EAR1/2 (16) PDD+PED →PDR Here, L.B. of time slot (14) is
The calculation result, that is, the value of PDR + JD, is sent through the register.
This means that it is directly input to the multiplication section. time
Ci of slot (15) is the calculation of time slot (13).
It means the uphill climb (carry) that occurs as a result of going.
Ru. Multiplication section (16)〜(18) CN＋C.B.→FR Here, C.B. registers the operation result in the addition section.
This means inputting directly to the multiplication section without going through the star.
However, in this case, in the adder time slot (14)
The calculation result of PDR + JD is input. Data bank reading section (14)～(15) EAR2/1→E2/1→ΔT2/1,
ΔE2/1, ΔZ2/1 Here, 2/1 means the odd number of times, i.e.
2 for ODD (e.g. E2 for E2/1), even number of times
In other words, it becomes 1 (E1) at EVEN.
Taste, read different data with EVEN, ODD,
It means storing to another register. Figure 2 shows the musical tone generator 1-5 in Figure 1A.
FIG. First, use this diagram to create each block.
To explain the outline of the function, 2-1 is the master clock.
Here, we use f=8.00096MHz.
I am using it. 2-2 is a sequencer (hereinafter referred to as SEQ)
), and the clock is clocked by master clock 2-1.
The frequency of the tsuku signal is divided, and the entire musical tone generating section 1-5
sequence signal (hereinafter referred to as SQ signal) and each
Generates seed control signals. 2-3 is microcomputer interface
-FACE Department (hereinafter referred to as UCIF), and the
Microcontrollers 1-4 can easily process the various data shown in the table.
The sound is transmitted asynchronously with the sound generator 1-5, but this
SQ generated by SEQ
This is a circuit that synchronizes with the signal. Further flag Kon
Initial mode, normal mode
Generates a flag INI that instructs mode switching. 2
-4 is the comparison register section (hereinafter referred to as CDR).
register CDR8 shown in the above calculation sequence.
Obtained by sequentially dividing the channel and master clock.
8 channels are compared with the 10-bit frequency divided signal.
Issues minute note clock and calculation request flag CLRQ.
live. 2-5 is a random access memory section (hereinafter referred to as
(referred to as lower memory) and is performed in the musical tone generator 1-5.
The results of various calculations are stored. 2-6 is flua
This is the FA section (hereinafter referred to as FA), which stores various data.
Built-in 16-bit full adder for addition.
Ru. 2-7 is a multiplication unit (hereinafter referred to as MPLY).
the law of nature, (2's complement 12 bits) x (absolute value 10 bits) It has a multiplier that performs calculations. 2-8 is digital
A digital analog converter (hereinafter referred to as DAC)
Yes, the digital output from MPLY2-7
Convert musical sound data to analog musical sound data.
2-9 is an analog buffer memory section (hereinafter referred to as ABM).
), the machine cycle frequency is calculated from DAC2-8.
The musical sound data generated in the period is processed by CDR2-4.
Changes to pitch synchronization due to generated note clocks
exchange. The functions and configuration of ABM2-9 are published in Japanese Patent Publication No.
Analog buffer shown in Publication No. 59-214091
It is similar to Amemory. 2-10 is input/output
It is a circuit section (hereinafter referred to as I/O) and is a data bank.
Sends an address signal to blocks 1-6, and
Waveform data and envelope data corresponding to the signal
Read the read data as necessary.
data conversion. 2-11 is the matrix
The switch section (hereinafter referred to as MSW) is the UCIF
Connected to 2-3, CDR2-4, memory 2-5
horizontal bus lines (HA, HB, HC, HD,
HE, HL buses), FA2-6, MPLY2-
7. Vertical bar connected to I/O2-10
line (A, B, C, D, L buses) and
This is a circuit that connects according to the SQ signal. these
The calculation sequence shown in Tables 5 and 6 depending on the circuit.
It is the one that executes the steps. Next, each block will be explained. Figure 4 is a detailed diagram of SEQ2-2 in Figure 2.
It is. 4-1 is a counter and a master clock
The various timing signals shown in Figure 1C are
generate a number. TS is the time in Figure 1 C
This is a signal representing the lot, and CHC is the channel control signal.
channel number in Figure 1 C.
This is a signal representing EV is in the calculation sequence.
This is a signal representing ODD and EVEN, and EV=0 is
ODD, EV=1 means EVEN. 4-2 is
It is SQROM (sequence ROM). SQROM4
-2 address input has a signal representing the time slot.
No. TS and flag INI are input, and these
each time slot based on the input.
Generating seed control commands. 4-3 is a logic gate
The output from SQROM4-2 is converted into various flags.
And further control with calculation request flag CLRQ etc.
SQ signal (performance information, effect switches 1-3, etc.)
As shown, each functional block is assigned to each time slot.
A signal that instructs how to operate in each case;
Inside, abbreviated as SQ) is generated. FIG. 5 is a detailed diagram of UCIF2-3. Figure 5
5-1 is a latch, and in Fig. 1, 5-1 is a latch.
A/D0-7 given by microcomputer 1-4
Latch by ALE. A/D0~7 and ALE
Since the relationship is as shown in Figure 1B, the latch
5-1 contains the addresses shown in Table 1.
be touched. 5-2 is a latch, and microcomputer 1-
A/D0~7 given by 4 is made easier.
Chi. The relationship with A/D0 to 7 is shown in Figure 1B.
As shown in Table 1 for latch 5-2.
The data shown is latched. 5-3 is la
latch 5-1, controlled by latch 5-1
Latch the output of Enter the address in two stages like this
The reason why ALE latches is periodic regardless of
This is because the address becomes “1” in this way.
By latching in two steps, a new
Latch 5-3 until data is written.
Address and data are stored in each chip 5-2.
will be done. 5-4 is 8 bits per word.
RAM, A is address input, OE is output control
control terminal, and data terminal D is connected to the HE bus.
It is. Here, when OE=1, given by A input,
Outputs the data of the received address from the D terminal.
Ru. Also, WE is a write control terminal, and when WE=1
At the same time, the data given to the D terminal is given to the A input.
Write to the given address. OE, WE are SQ credit
It is controlled by the number. RAM5-4 has the first
Various data shown in the table (NOD, PDD, RLD,
VOL.DMP/SOL, TAB/PE, VLD) and CO
control data CONT (written from data bank)
It's crowded. (details will be described later), pitch data register data
Each data PDR is stored for 8 channels.
There is. 5-5 is a selector, and microcomputer 1-4
and the address specified by the SQ signal.
selectively outputs the response using another SQ signal, and
This is given to the A input of 5-4. 5-6 is faith
It is a signal processor, connected to the HE bus, and
It takes in data and generates various flag signals. Ma
Release date sent from microcontroller 1-4
16 types of release errors depending on the data RLD4 bits.
Generates envelope data and sends it to the HE bus
Ru. 5-7 is a gate, which responds to the SQ signal.
The output of Tsuchi 5-2, that is, the output from microcomputer 1-4.
Send data onto the HE bus. Next, the operation of UCIF2-3 will be explained. The data shown in Table 1 is the type shown in Figure 1 B.
Assuming that it is given from microcontrollers 1-4 at the timing,
If the address is 05₁₆, the data is 89₁₆In other words, Chiyanne
If you instruct key 5 to press key F#1, first
The address is locked in latch 5-1 by the ALE signal.
The latch 5-2 is then connected to the latch 5-2 by a signal.
At the same time as the data is latched, the latch 5-3 is connected.
The dress is latched. Then at a predetermined timing
selector 5-5 selects the output of latch 5-3.
At the same time, gate 5-7 opens and RAM 5-4
A write signal is given to the WE of. this write
The HE bus is latched to latch 5-2 by the signal.
The data that was written, that is, the data that microcontrollers 1-4 try to write
data i.e. 89₁₆is given, RAM5-4
The A input is 05, which is the output of latch 5-3.₁₆gave
Therefore, address 05 of RAM5-4₁₆to the address
89₁₆The data will be written. Do it like this
The various data shown in Table 1 are written to RAM5-4.
It gets sucked in. As shown in Table 1, RAM5-4
Flags such as VOL flag and PE flag are written in
These flags are included in the HE bus.
It is sent to the signal processor 5-6 via the
I've been using it since I got it. FIG. 6 is a detailed diagram of CDR2-4. 6-1
is a 10-bit frequency divider that uses the master clock as input.
It is. 6-2 is RAM with comparator (hereinafter referred to as CDRAM)
It is called. ), 8 words with 13 bits per word
has. The top 10 bits of each word are compared.
A frequency divider 6 is provided with a frequency divider and is input from terminal T.
A comparison is made with the frequency division data by -1, and the 10-bit
When all matches, a match pulse is output from terminal C.
Powered. The functions of OE, WE, A, and D are as described above.
It is the same as RAM5-4. 6-3 is a decoder
Yes, the relationship between A input, EN input and D output is shown in Table 8.
As shown below. 6-4 to 6-11 are RS La
When a positive pulse is applied to the S input, the Q output
When the force becomes “1” and a positive pulse is applied to the R input, Q
Output becomes “0”. RS latch 6-4 is a change
channel 0, RS latch 6-5 is channel 1,...
A coincidence pulse of is applied to S. 6-12 is sele
It is a controller, and the channels are
One of them is transmitted by the channel code CHC3 bit.
Select the number and output from D. 6-13 is latch
According to the SQ signal, the output of selector 6-12 is
Latch power. 6-14 is an AND gate. Next, regarding the operation of CDR2-4 shown in Figure 6.
explain. Frequency divider 6-1 divides the master clock
and sends the 10-bit frequency divided output to T of CDRAM6-2.
give to input. Each word of CDRAM6-2 has
Contains arbitrary values, but the top 10 bits of these values
When the output value matches the output value of the frequency divider 6-1,
Output the matching pulse from the C terminal. CDRAM6-
The A input of 2 is a signal representing CHC, that is, a channel.
has been entered, so each word has its own channel.
Since it is compatible with all channels, it is possible to
generates a pulse. This coincidence pulse is
is input to RS latches 6-4 to 6-11.
Therefore, the channel corresponding to the coincident pulse is
The Q output of the RS latch is set to "1".
One of the Q outputs of RS latches 6-4 to 6-11
Selector 6 according to channel code CHC
-12 are sequentially selected and locked in latch 6-13.
be touched. The output of latch 6-13 is an AND gate
6-14, so currently selector 6
The Q output of the RS latch selected by -12 is “1”
Then, the SQ signal applied to AND gate 6-14
Depending on the number, the corresponding channel of the D output of the decoder 6-3
When the channel becomes “1”, the Q output of the above RS latch becomes
Reset to “0”. FIG. 7 is a detailed diagram of the memory 2-5. Figure 7
In, 7-1 to 7-4 are RAM, OE,
Each function of WE, A, and D is the same as RAM5-4 mentioned above.
It is the same. Here, RAM7-1 has WAR,
EAR1, ΔZ1, ΔE1, WE1, EAR2, ΔZ2, ΔE2
Each register is in RAM7-2, WR2, ZR1,
ΔT1, FR, ΔWAR, ZR2, ΔT2 registers
However, RAM7-3 has ER1, TR1, DIF1, DW1,
ER2, TR2, STW, TAB′, HAD registers
However, RAM7-4 has NOD', WE2, and VLD' records.
Each register is stored for 8 channels.
Ru. Note that NOD′, TAB′, and VLD′ are the RAMs mentioned above.
NOD, TAB, VLD data in 5-4
This is what I wrote. 7-5 is 1 word 10 bits
It is a ROM of 13 words and is shown in Tables 5 and 6.
The note coefficient CN in the calculated operation sequence is recorded.
It is remembered. Here, Q is the output and A is the address input.
power, OE is the output control terminal, and when OE = 1, it is connected to Q.
The contents of the ROM are output, and when OE = 0, Q = high.
It is impedance. The value of note coefficient CN is
As shown in Table 7. In addition, ROM7-5
10-bit output connects to lower 10 bits of HD bus
has been done. 7-6 is a signal processor, RAM
ND (note data) from NOD′ stored in 7-4.
read out data) and OCT (octave data).
Based on the data and PE flag
The circuit that generates the Yune data PED and the register
A decoder that reads and decodes the data of star WE2.
A code circuit is provided. FIG. 8 is a detailed diagram of FA2-6. In Figure 8
, 8-1 to 8-8 are latches, and SEQ
It operates using the φ1 and φ3 signals generated by 2-2.
8-9 is an adder, and the value given to the A input and
The value given to the B input (both 16 bits) and the
-Adds the value given to input Ci, and calculates C and
Take out from Co. Co is the carry resulting from the operation
This is the output. 8-10, 8-11 are bit processing times
output by latch 8-1 and latch 8-2.
This is a circuit that performs power bit manipulation. 8-12 is an argument.
control gate, and latches 8-6 according to the SQ signal.
force the output to “1” or “0”. Some
Otherwise, if you output it as is, it will perform the same operation. 8-
13 is RAM, its size is 1 word, 9 bits.
It is 12 words long. A.D, WE, OE
Each function is the same as the RAM 5-4 described above. D out
The 9 bits of power are connected to the lower 9 bits of the C bus.
There is. RAM8-13 is for phase matching (described later)
Individual waveform data readings for 12 notes can be performed in registers.
Performs phase management of the protruding address (WAR). Figure 9A is a detailed diagram of MPLY2-7. No.
In Fig. 9, 9-1 to 9-9 are latches. child
Here, latch 9-3 contains bits 0 to 3 of the L bus.
9, but latch 9-5 has bits 9 to 9 of the L bus.
port 12 is connected. 9-10 is encoder
It is. The input/output relationship is as shown in Table 9.
Ru. 9-11 is a shifter, input from I
The 16-bit signal follows the control signal input to C.
Shift and output from O. The contents of the shift are the 10th
As shown in the table. 9-12 are bit processing times
The latch 9-3 outputs in response to the SQ signal.
Performs bit processing of the signal. 9-13 is a decoder
Assuming input A and output D, the relationship is shown in Table 11.
It is a cage. 9-14 is a selector and enters C.
If C=1, then A, depending on the input SQ signal.
If C=0, select the 16 signals input to B.
Select and output from Y. Note that the lower 11 bits of A input
is connected to GND (ground potential) (i.e.
“0” is given). 9-15 is shifter I
The 14-bit signal input from C is input to C.
It is shifted according to the control signal and output from O. Schiff
The contents of the list are shown in Table 12. 9-16
is a multiplier, and the A input is 12 according to this complement representation.
Bit, B input is 10 bits of absolute value and output is 2 bits.
It is 14 bits with complement representation. Normally 12 bits
Performing a 10-bit operation yields a 22-bit result.
However, the 14-bit output of multiplier 9-16 is of course 22-bit.
These are the top 14 bits of the total. Therefore, the multiplier
The input/output relationship in 9-16 is as follows:
become. C=A×B/256 In addition, multiplier 9-16 in MPLY2-7
uses the following technique to further simplify the circuit.
I'm there. Normally, when configuring a multiplier, a 2's complement value of 12 bits is used.
A multiplier with bits x absolute value of 10 bits has 116 adder sets.
22-bit accurate arithmetic results can be obtained.
However, in this system, the 22-bit
Only the top 14 bits of the bits are used. That is,
In this example, the output of the lower 8 bits is not used.
The calculation error due to the omission of the adder cell is in the upper 14 bits.
Addition for lower 7-bit operations that does not affect the LSB of
All cell cells are omitted. Therefore, this multiplier 9
-16 has 28 adder cells for lower bit operations.
The configuration is as shown in Figure 9 (b), with the main part omitted.
Ru. In Figure 9B, similar cells are omitted within the broken line.
I wrote it down. Also, each block is a full adder.
input is A, B, Ci (carry input), output is sum
S and Cary Co. FIG. 10 is a detailed diagram of I/O2-10. No.
In Figure 10, 10-1 to 10-8 are latches.
Ru. Here, the latch 10-3 is a latch with a set
The latch input is connected to bits 7 to 9 of the D bus.
It is connected. 10-9 is the shifter selector,
Switching between A input and B input using C input, and switching between A input and
Performs a 1-bit shift. 10-10 is bit processing
This is a circuit that strengthens the lower 3 bits according to the SQ signal.
This is a circuit that legally sets it to "1" or "0". 1
0-11 is a decoder, and the relationship between input I and output D is
The personnel in charge are as shown in Table 13. Decoder 10-
The A input of latch 11 has the bit of the output of latch 10-7.
Bits 12 to 15 are given. 10-12 is set
which is given to A or B depending on the C input.
Select one of the signals and output it from Y.
Ru. 10-13 is a shifter, which is connected to the input of control terminal C.
Shift the input from I according to the force and output from O
do. 10-14 is a noise circuit,
Add noise to input data according to lag NA
Ru. FIG. 11A is a detailed diagram of MSW2-11.
The part surrounded by a circle is the switch, and specifically the part
As shown in Figure 11B, it is composed of Nch MOSFETs.
When the SQ signal becomes “1”, the MOSFET is
When turned on, the vertical line and horizontal line become conductive.
data is transferred. In this MSW2-11
In order to speed up the data transfer,
φ1 signal for each time slot on all bus lines
Data transfer is performed after precharging.
It's summery. This switch is an Nch MOSFET.
Since it is configured, “1” of the transferred data
level drops by the threshold voltage of the MOSFET
This is to prevent this from happening. Figure 11 C~Figure 11
This is the switch used in MSW2-11.
This is an example of a pattern, and the points of intersection surrounded by circles are
It is connected through it. For convenience in this example
The case where each bus is 8 bits will be explained below. No.
Figure 11C shows bn and an (n=0~
7) is connected. Figure 11 D is b0
~ Change the four values of b3 and “0” vertically using the switch.
It is designed to write to the direction bus. No.
In Figure 11 E, b0 to b3 to a0 to a3, c4 to c
7 is written to a4 to a7.
This causes the two sets of buses to appear separately.
Data can be mixed and transferred to other buses
It was designed so that Figure 11 is the bit position.
The location was converted and transferred from bus to bus.
By arranging the switch like this,
Position the upper and lower 4 bits of the horizontal bus data.
Change and transfer to vertical bus. Figure 11
Figure 11 is an example of a circuit for setting constants on the bus.
, and in Figure 11, all “0” is set on the bus.
The circuit shown in Figure 11 is connected to the bus 10101010, i.e.
A.A.₁₆This is a circuit to set. This is a switch
The parts without , a7, a5, a3, a1 are like this
By precharging just before the switch opens
Anything with “1” written is retained as is.
It depends. Figure 11 is determined by the flag TO.
It is designed to change the value of a number, and if TO=0
ba00₁₆is written to the bus and if TO=1 then EB₁₆
is written to the bus. Figure 11 C - Figure 11 Li
Install the switch shown in MSW2-11 according to the application.
By placing and selectively opening and closing, any bus
Bits that require data transfer from to any other bus
This makes it possible to include For example, HA bus?
to A bus, from HB bus to B bus, from C bus
SW when you want to transfer data to the HC bus at the same time
1, SW7, and SW13 should be turned on at the same time.
Also, data on the C bus is transferred to the L bus and D bus.
When necessary, turn on SW28, SW29, and SW30.
If so, C bus → HL bus → L bus and D bus
Data is transferred over the road. In addition, in MSW2-11, data transfer
is carried out at the timing shown in FIG.
In other words, in the section of φ1=1, the vertical and horizontal bass lines are
After pre-charging the in, from the falling edge of φ1.
Data is transferred in the section up to the falling edge of φ3,
It latches at the falling edge of φ3. Here, the standing position of φ3
The section from the descent to the rise of φ1 is a latch operation.
This is the margin for stable operation. Next, data banks 1-6 will be explained. de
Data banks 1-6 store four types of data.
ing. They are (1) header address data, (2) header address data,
Tsuda data, (3) waveform data, (4) envelope data
It is ta. Here, the header address data is
Indicates at which address the data is stored
The data is 8 bits, and the header data is the waveform data.
address where the data and envelope data are stored.
8 bytes of data representing the resources and their attributes
It is. Next, we will explain the above four types of data in more detail.
I will clarify. (1) Header address data (HAD) This data is stored in each tablet, each octave, each
Address the note data assigned to each 3 keys.
Data that indicates the address of the header data as a
be. Table 14 shows the storage location of header address data.
As shown in
Set data TAB, bit 4 to bit 2
Turb data OCT, bit 1 to bit 0 are no.
The upper 2 bits of the data ND, the remaining bits are
All contain "1". TAB here,
The 10 bits consisting of OCT and ND are called WTD.
Each of them is shown in Table 1.
Not even. Header by header address data
The data address is shown in Table 15 and the bit
Header address data is entered in bits 10 to 3.
The upper bits are all "1". Also, below
Enter data from 000 to 111 in the 3rd place bit. (2) Header data (HD) Header data is stored at the addresses shown in Table 15.
One word is 8 bits stored, so 8 words of data are stored.
The contents of each of the 8 words are shown in Table 16.
It is. In Table 16, CONT is the control
This is the header data and is indicated by this header data.
Displays the attributes of waveform data and envelope data.
vinegar. E1′ is one of the two types of envelope data.
On the other hand. The other envelope data E2′
The start address is given by STE+ΔSTE.
W1 and W2 are two types of waveform data, and W1's
The start address is given by STW + ΔSTW.
Ru. Note that CONT is configured as shown in Table 17.
The meaning is as follows.
Ru. P/O: The musical tone based on this header data is a piano.
with type envelope or organ type envelope
This is a flag indicating whether the P/O=
If it is 1, it means that it is a piano type. ORG: Indicates which range the musical sound data originally belongs to.
This is 3-bit information that indicates whether the
The correspondence between ORG and range is shown in Table 18.
Ru. Therefore, the waveform data actually exists as one period.
information indicating how many samples to
There is also. W8: Is the waveform data 12-bit precision or 8-bit precision?
Indicates whether the test is accurate or not. If W8=1, 8 bits
accuracy. When W8=1, waveform data
4-bit “0” is added to the lower part of the waveform.
The amplitude level is maintained. PCM: Rise of waveform data W1 when PCM=1
Indicates that the part is PCM. NA: When superimposing a noise signal on a musical tone signal.
This is a 2-bit signal used. (3) Waveform data (W1, W2) As mentioned above, the musical tone generator 1-5 generates waves.
12-bit and 8-bit format data
Two types are used. sold here
When you think about ROMs, most of them are 1 word.
8 bits or less, 1 word
12 bits are rare. Therefore, the present invention
The waveform is stored in ROM as shown below. Immediately
Chi, In the case of 8 bits, it depends on STW and ΔSTW.
Store one word at a time sequentially from the address determined by
However, in the case of waveform data of 1 word and 12 bits,
As shown in Figure 12, the upper 8 bits are STW+
Store sequentially from the address indicated by ΔSTW
However, the lower 4 bits are the value of STW + ΔSTW
Add by shifting 1 bit to the right and putting 1 in the MSB.
2 words in the lower 4 bits and upper 4 bits from the address
They are stored sequentially. For example, if the address
0444₁₆The lower 4 of the upper 8 bits of the waveform data in
Bit location is address 1222₁₆top 4 bits of
So, address 0445₁₆About a
dress 1222₁₆This means that the lower 4 bits of (4) Envelope data (E1′, E2′) Envelope data consists of 1 word with 16 bits.
The data format is shown in Table 19.
It is a cage. ΔT is envelope address update
This is the data that determines the interval. S is for envelope
This is a flag indicating the slope (increase or decrease). Z
is a flag indicating the magnitude of the slope of the envelope.
and DATA is its size. Shown in Table 19
The data is determined by STE and ΔSTE shown in Table 16.
stored in the data bank according to the specified address.
ing. The data bank is structured as described above.
gives a change in tone for every three keys next to each other.
On the other hand, within the same octave,
If you have the same header address data
Waveform data, envelope data, header data
You can obtain musical tones with the same timbre without increasing the timbre. Ma
In addition, arbitrary waveform data in each header data,
Envelope data can be specified, so fewer waves can be created.
Even if it is shape data and envelope data,
It is also possible to generate various musical tones by combining them.
It is. Next, the initial sound when the key is pressed in the musical tone generator 1-5 is
dial processing, note clock generation method, envelope
Waveform generation method We will now explain how to generate waveforms. (1) Initial processing During initial processing, musical tones are generated by pressing keys.
Initial settings of various registers are performed when generated.
Ru. The calculation sequence starts from the initial mode by pressing the key.
It starts with a long sequence of codes, so
In the accounting department, PDR first appeared in time slot 13.
period is set. To explain this operation in more detail,
Figure 5: PDD is read from RAM5-4 and HE
Data gets on the bus. At the same time, Fig. 7 signal processor 7
-6, the PED is given to the HD bus, and the first
In Figure 1 A, SW21 and SW17 are turned on.
PDD takes the A bus and PED takes the B bus. this day
The data is added at FA2-6 as shown in Figure 8.
The calculation results are placed on the C bus. The result of this calculation is
Take the HE bus via SW23 and go to RAM5-4.
Stored in a certain register PDR. Furthermore, this performance
In calculation, transferring PDD and PED to FA2-6 is
Time slot where PDD + PED calculation is actually performed
One time slot before the calculation, the calculation result is
Storing to PDR is one data point where PDD + PED calculation is performed.
This is done after imslot. Regarding the addition operation below,
are all the same. Then the time slot
“0” in TR1, TR2, ZR1, ZR2 in (15) to (18)
is written. This operation requires setting “0” to TR1.
When writing, the time slot
(15) SW in MSW2-11 of Figure 11 A
33 and SW31 are turned on. SW33 is the 11th
The configuration is as shown in the figure, and there is a “0” on the C bus.
is given. SW13 is on at the same time
Then, the data on the C bus is given to the HC bus, and the seventh
In register TR1 in RAM7-3 shown in the figure
“0” is written. On the other hand, in the data bank reading section, the following
It behaves like this. The following explanation focuses on Figure 10.
Ru. By WRD composed of TAB, ND, OCT
The header address data HAD is read out.
Note that the initial mode that performs this initial processing is
In the mode, latch 10-3 is activated by the SQ signal.
It is set to 111. This data is I/O2
Table 15 by shifter 10-13 in -10
The data is converted to the format shown in
RAM7-3 register via bus SW15 and HC bus.
stored in the star HAD. At the same time as this operation,
Header address data read from data bank
Data HAD is latch 10-8, latch 10-6.
They are latched one after another and the shifter selector 10-9
The data is formatted as shown in Table 15.
is switched and latched in latch 10-4. Latsuchi
10-4, first the bit processing circuit 10
-10 gives 000 to the lower 3 bits.
Control data CONT is data bank 1-
6 and latched via latch 10-8.
It is latched to the upper 8 bits of 10-7. Conte
Roll data CONT is selected by selector 10-12,
Lid 10-13, noise circuit 10-14, latch
The register of RAM5-4 is accessed from the D bus via 10-2.
Stored in star CONT. On the other hand, latch 10-
The upper 4 bits of 7 are connected to decoders 10-11.
16 bits according to the truth table shown in Table 14.
You can obtain the following data. However, at this time, decoding
The C input of the data card 10-11 is "1". Se
Rectors 10-12 select this decoder output
Then, shifters 10-13 shift 6 bits to the right and output
Strengthen. Here, the output of this shifter 10-13 is
Considering this, decoder 1 from latch 10-7
The data input to 0-11 is P/O and
ORG3 bits. Now decoder 10-11 C
Since the input is “1”, the decoder 10-11
Output is determined by ORG3 bit only. Therefore de
The output of coder 10-11 is transferred to 6 by shifter 10-13.
The values shifted to the right by bits are the values shown in Table 18.
Ru. This value is the noise circuit 10-14, latch 10
-2 to the D bus, MSW2-11
In the RAM7-3 register via SW15
data is stored in data DIF1. Next, bit processing is performed on the output of latch 10-4.
Circuit 10-10 sets 001 to the lower 3 bits, then
Give 010 to the upper and lower STE of the header data.
8 bits of each position are read out. This STE value is
Rector 10-12, shifter 10-13, noise times
route 10-14, to D bus via latch 10-2
given, through SW5 in MSW2-11
and stored in register EAR1 of RAM7-1. Next, enter the shot sequence. Shyoto Sea
The kens are executed twice. in time slot (1)
PDR and JD are added, where JD is a constant
Turn on SW32 in MSW2-11
It is obtained by SW32 is shown in Figure 11
It has a eel configuration, JD = 45B₁₆Tonatsutei
Ru. Multiply this addition result by the note coefficient CN.
Combine them to get FR. Explain this series of yen calculations in detail.
Then, PDR + JD is calculated at time slot (1).
The result is placed in time slot (2) as described above.
and is given to the C bus. Now to MSW2-11
SW28 and SW29 turn on, and C bus → HL
Data is transferred in the order of bus → L bus, and
MPLY2-7 latch 9-1
be touched. In the next time slot (3), the 7th
According to the note data ND from ROM7-5 in the figure
The value of CN is read and applied to the HD bus.
This value is passed through SW19 in MSW2-11.
Latch 9 of MPLY2-7
-3 is latched. The output of latch 9-1 is shifted
to latch 9-2 via data 9-11 to latch 9-2.
The output of 3 is passed through the bit processing circuit to the latch 9-4.
sent to and latched. Therefore, Latch 9-2
The value of PDR + JD is the value of CN in latch 9-4.
is latched. Then multiplier 9-16
Calculate the product of (PDR + JD) and CN, and shifter 9-1
5 to latch 9-8 and latched.
Ru. In addition, in these series of operations, the shifter 9
-11, bit processing circuit 9-12, shifter 9-1
5 operates to pass data. That is,
“1” is given to the C input of encoder 9-10.
It is. The value of latch 9-8 is MSW from L bus.
RAM7-2 register via SW9 of 2-11
stored in the data FR. Therefore, in time slot (2)
Then, ORG+OCT+1 is calculated. This performance
In the calculation, the +1 operation is shown in FA2-6 in Figure 8.
This is done by logic gates 8-12. That is,
Logic gate 8-12 is strong in the corresponding time slot.
If a “1” is outputted, the latch 8-5 becomes “1”.
latches and gives “1” to the Ci input of the adder.
It is. The meaning of this operation is as follows.
It is. In other words, ORG is
Value indicating whether it belongs to the range (temporarily assume this is N)
is the inverse logic of octave data OCT.
It shows. OCT, ORG, and waveform samples
The numerical relationships are shown in Tables 18 and 22. Therefore ORG+
1 would represent -N. In other words, ORG+OCT+1=OCT-N...(1-1) That is, this is currently trying to occur.
The range of the musical tone signal (that is, the range to which the pitch data belongs)
octave value) and what you are actually trying to use.
The original range of the waveform data (that is, the range to which the waveform data belongs)
octave shift)
This is a value indicating the amount of In other words, how many octaves is the original waveform?
Indicates whether the tone will be read as a high pitched sound. this
The value is temporarily stored in register WE2 of RAM7-4.
The signal is then decoded by the signal processor 7-6.
It is stored in the register ΔWAR of RAM7-2.
The value of ΔWAR for the value of ORG + OCT + 1 is the 20th
As shown in the table. In other words, the pitch data belongs to
Octave value and octave to which the waveform data belongs
The difference between the values (ORG + OCT + 1) is a power of 2
ΔWAR is obtained as follows. number
Expressed as a formula, it is as shown in formula (1-2). ΔWAR=2(ORG+OCT+1)
...(1-2) Below, time slot (4) is EAR2, time slot (6), (8),
(9), (10) WR1, ER1, WE2, WE1, WR2
The initial settings for each register are performed. On the other hand, in the data bank reading section,
The header stored in RAM7-3 with the long sequence
Read the Tsuda address data HAD, D bus →
Through latch 10-1 → shifter selector 10-9
bit processing circuit 1.
Enter 001 in the lower 3 bits of 0-10 to enter the data.
Read the ΔSTE of header data from the bank. child
The value is latch 10-7 → selector 10-12 → switch.
Lid 10-13 → Noise circuit 10-14 → Latch
10-2 to the D bus, MSW2-
A bus via SW26 and SW30 at 11
is input to FA2-6 and added to EAR1.
Ru. Then store in register EAR1 of RAM7-1
STE (envelope data E1′ star)
address) is read out, and the D bus → latch 10
-1→Latch 1 via shifter selector 10-9
Latched at 0-4. The output of latch 10-4 is
“0” is set to LSB by bit processing circuit 10-10.
Then “1” is entered and shown in Table 19.
Read the 2-byte envelope data exactly as shown.
put out. This value of 16 bits latches to latch 10-7.
be done. According to the output of latch 10-7, the first
ΔT1, ΔE1, ΔZ1, second time in shot sequence
The values of ΔT2, ΔE2, ΔZ2 in the shot sequence of
occurs. First, the decoder 10-11 has a
The upper 4 bits of 10-7 are input, but
The upper 4 bits of latch 10-7 are shown in Table 19.
However, the value of ΔT is included. Therefore decoder 1
0-11 decode ΔT according to Table 13 and set
output to the director 10-12. Selector 10-1
2, at this time C=1 and B input is selected.
The selected signal is output to the shifter 10-13. this selector
10-12 output is shifter 10-13, noise circuit
No bit manipulation is performed in 10-14.
is applied to the D bus through latch 10-2 without
Then, in MSW2-11, switch SW10 and HB bus.
stored in register ΔT1 of RAM7-2 via
Ru. ΔE1, ΔZ1, ΔE2, ΔZ2 are shown in Table 19.
shifter 10 according to Z, S, DATA where
Bit operations are performed at -13 and stored in each register.
will be paid. What bit operations are performed
The details are as shown in FIG. In Table 19
The data format differs depending on the Z value in
It shows what will happen. Next, read ΔSTE from data bank 1-6.
As in the case of register HAD from RAM7-3.
Read the value, latch it to latch 10-4, and set the bit.
The header address data is processed by the address processing circuit 10-10.
The first initial mode for the lower 3 bits of HAD.
100, then 101, second initial mode
In the code, set the data by giving 110 and then 111.
Read STW and ΔSTW from tabank 1-6,
STW is the register STW of RAM7-3, ΔSTW is
Store in register WAR of RAM7-1. The above completes the initial settings for all registers.
Complete. (2) How to generate a note clock First, note clock used in musical tone generator 1-5.
The principle of the Tsuk generation method will be explained with reference to Figure 3.
Ru. In Figure 3, 3-1 is a frequency divider and a terminal
Divide the master clock input to CK,
A 10-bit frequency divided output is output from Q. 3-2 is
The comparator compares the A input and B input, and A=
When it becomes B, Q outputs "1". 3-3
is a flip-flop, and at the rising edge of the CK input
It takes in the signal given to the D input and outputs it from the Q.
Ru. 3-4 is an adder, which calculates the sum of A input and B input.
is output from C. 3-5 is the B input of adder 3-4.
This is a constant circuit that inputs a constant M for force. 3
-6 is an RS latch, and a positive pulse is applied to the S input.
When it enters, Q=1 and a positive pulse enters the R input.
and Q=0. 3-7 is a delay circuit,
Delays the input signal and outputs it. 3-8 is AND
It is a gate. Next, the operation shown in FIG. 3 will be explained. First, RS Ratu
Assuming that the Q output of Q3-6 is "0",
The output of AND gate 3-8 is always “0”.
The Q output of flip-flop 3-3 is constant.
Ru. On the other hand, the frequency divider uses the frequency division of the master clock.
000₁₆from 3FF₁₆Outputs a 10-bit Q that repeats
Ru. Suppose that the output of flip-flop 3-3 is N.
Of course, if it is 000₁₆≦N≦3FF₁₆Because it is
There will always be a moment when the Q output of frequency divider 3-1 becomes N.
exists, and in this case, the Q output of comparator 3-2 is
A matching pulse is output. Then this matching pulse
RS is connected to the S input of RS latch 3-6.
The Q output of latch 3-6 becomes “1” and the write pulse
signal is output from AND gate 3-8. pretend
The D input of the pop-flop 3-3 is connected to the adder 3-4.
Since C output is given, the value of N+M is written.
be caught. At the same time, the write pulse is delayed
Q output of RS latch 3-6 after being delayed by circuit 3-7.
Set the force to “0”. For this reason, the flip-flop again
The Q output of 3-3 is constant, but the value varies from N to
It has changed to N+M. Therefore, next is the frequency divider 3-1.
Generates a match pulse when the Q output becomes N+M.
That will happen. By repeating this, the comparison
The output value of the frequency divider 3-1 is N, N+M,
A pulse is generated when N+2M... Two
Therefore, the frequency divider 3-1 counts the master clock M times.
A match pulse will be generated each time the signal is hit.
Also, N+nM＞3FF₁₆In this case, the adder
The output of 3-4 is N+nM- after overflow.
3FF₁₆To achieve this, the master clock must be turned M times.
A coincidence pulse is generated when counting
Needless to say. In other words, one of the comparator 3-2
The target pulse is used as a note clock, and the constant M is changed.
Note clocks with various periods can be obtained by
and its frequency is (master clock frequency
number) ÷M. Also, the Q output of SR latch 3-6
corresponds to the calculation request flag CLRQ. The above is the notebook clock generation method according to the present invention.
It is the principle. Next, in the musical tone generating section 1-5 shown in FIG.
Details of the calculation sequence for generating a note clock
explain about. A key is pressed on the keyboard 1-1, and the microcomputer 1-4
instructs the musical tone generator 1-5 to generate a musical tone.
, the operation sequence is initialized as described above.
Start with mode long sequence. Thailand first
In Muslot (13), PDD+PED→PDR……(2-1) Next, enter the shoot sequence and time slot.
Tsuto(1)……(6) PDR＋JD→L.B.……(2-2) C.B.×CN→FR……(2-3) calculations are performed. Then switch to normal mode
and in the time slot (9) of the short sequence. FR+CDR→FR (2-4) Long sequence time slots (14) to (18)
in PDR＋JD→L.B.……(2-5) C.B.×CN→FR……(2-6) PDD+PED→PDR……(2-7) calculations are performed. Here, PDD is shown in Table 1.
PDD, that is, pitch detune data,
PED is the aforementioned pitch extend data.
JD is a constant and 1115_Ten(45B in hexadecimal)
The value has been set. Note coefficient CN is assigned
It is a value determined by the pitch name, and the value is determined by the pitch name and CN.
The relationships are shown in Table 7. Theory of Tables 5 and 6
As mentioned above, operations (2-2), (2-3)
And calculations (2-5) and (2-6) are as shown below.
Can be expressed. (PDR+JD)×CN→FR……(2-8) Here, PDR is PDD + PED, so it is calculated
(2-8) is (PDD+PED+JD)×CN→FR
...(2-9) becomes. The value of this FR is shown by calculation (2-4).
Accumulate in CDR. As mentioned above, this accumulation is
Occurs once every time a note clock occurs.
Therefore, if the initial value of CDR is N, the value of CDR is N,
It changes as N+FR+N+2×FR,... this
The upper 10 bits of CDR and the master clock are
Compare the 10-bit frequency-divided signal obtained by the next frequency division,
Since we are trying to generate a matching pulse, the actual
for, Comparison with N/8, N+FR/8, N+2×FR/8,... The top 10 bits of the CDR are the third
Corresponds to flip-flop 3-3 in the figure, FR/8
corresponds to the value M of constant circuit 3-5 in FIG. late
If you perform the calculations (2-1) to (2-7) above on
A fixed-period notebook clock is obtained, and its frequency is (Master clock frequency)÷FR/8. (3) Waveform generation method Figure 1 Waveform generation in musical tone generator 1-5
The method can be roughly divided into the following five steps. Immediately
Chi: Address generation Read waveform data from data bank 1-6
generate the actual address. Waveform readout Data the waveform data specified by the address above.
Control data is read from data banks 1-6.
Performs bit processing according to the data CONT. envelope multiplication 2 wave mixing CN multiplication Each step will be explained in detail below. Address generation Header data is initialized by pressing a key.
STW (start address of W2), ΔSTW (W1
number of words), DIF1 (number of samples included in one waveform)
number) is stored in registers STW, WAR, DIF1,
Further, the register ΔWAR is determined by the calculation. child
The address is set in normal mode based on these data.
In the following process,
When the waveform data has a PCM part (PCM=1)
If not (PCM=0), the address generation will be different.
Therefore, it is divided into cases with a PCM part and cases without a PCM part.
I will explain. If there is no PCM section As shown in Table 6, at time slot (2),
Find the sum of STW and WAR, and use this sum to
Read waveform 1 from data bank 1-6 and
Add DIF1 to the above sum at imslot (4)
data bank with the value of SW + WAR + DIF1.
Waveform 2 is being read out from block 1-6. child
Here, STW is the start address of waveform 2, and
The register WAR has an initial value of ΔSTW, that is, waveform 1.
Contains the negative number of words contained in the time
Accumulate ΔWAR in slot (7). Therefore
The value of STW + WAR is the start address of waveform 1.
The value increases sequentially for each value of ΔWAR. Ma
In addition, the value of ST + WAR + DIF1 is calculated by adding DIF1 to this value.
Therefore, from the start address of waveform 2,
It is a value that increases every ΔWAR. here,
ΔWAR is a value representing the reading skip of the waveform
Therefore, as described above, for waveform 1 and waveform 2,
address can be generated. In addition, in the main musical tone generating section 1-5, the PCM
section is absent, solo flag SOL = 0, and
Phase alignment when no quarter shift is performed
conduct. The phase matching method is based on the calculation sequence
When changing from normal mode to normal mode
RAM as the calculation result in the first time slot (7)
Data whose address is the homophone name in 8-13
Store 9 bits in register WAR. RAM8
-13 output is 9 bits, but the C bus is
Since it is charged, the aforementioned 9 bits of the total 16 bits are
“1” is entered in the upper 7 bits. 2nd time
The calculation results for subsequent time slots (7) are shown in Table 6.
As shown, it is stored in the register WAR and
Use the homophone name in RAM8-13 as the address
Updated in register (phase register). This way
By setting the
Even if a musical tone has already been generated, the chi
The value of register WAR in Yannel is RAM8
I am trying to generate a musical tone through -13.
To be given to the register WAR of the channel
In order to match the phase between these two channels,
becomes possible. Here, the time slot (7) calculation WAR+
Let's talk about ΔWAR. When WAR＋ΔWAR≧0, it has nothing to do with the range.
As a result of the operation, -512 is sent to the C bus._Ten(FFOO₁₆)but
Given. If there is no octave shift
Since ΔWAR=1, the value of register WAR is
It will repeat with a period of 512. Multiple channels that generate the same note due to the above
The register WAR for each file is always the same.
The same note occurring in different channels
The phases of the waveforms match perfectly, and the phase
alignment is achieved. Next, the calculation STW + in time slot (2)
Let's explain WAR in more detail. Data is read from register STW of RAM7-3.
The HC bar as shown in MSW2-11
by clock φ3 via bus, SW11, and A bus.
It is latched by latch 8-1 of FA2-6. simultaneous
The value of register WAR in RAM7-1 is set to HA bus,
FA2- by clock φ3 via SW2 and B bus.
It is latched to the latch 8-2 of 6. latch 8-1
The output is determined by the bit processing circuit 8-10.
Latch 8- by clock φ1 without receiving
It is latched at 3. On the other hand, the output of latch 8-2
inputs ORG in the bit processing circuit 8-11.
Bit processing is performed as shown in Table 21.
After that, it is latched to latch 8-4 by clock φ1.
Ru. Adder 8-9 is latch 8-3, latch 8-4
Add the outputs of latch 8-7 and latch 8-8.
to the C bus. Bit processing circuit 8-
In step 11, perform the bit processing as described above.
As a result, the register WAR changes with a period of 512
However, depending on each octave
It will change periodically. For example, ORG
= 5, OCT = 2, there is no octave shift.
As mentioned in the initial processing section, ΔWAR=
It is 1. Also, from Table 21, the register WAR bit
Since slots 7 and 8 are always 1, the time slot
Assuming STW′=0, the calculation result of (2) is −10, −9, ...−1, −128, −127, ... -1, -128... Thus, it repeats in 128 cycles. Also,
2 octave shift when ORG=4 and OCT=5
Therefore, ΔWAR=4. Also, according to Table 21
Bits 6, 7, and 8 of register WAR are always 1.
Similarly, -40,...-8,-4,-64,-60,-56... -4, -64,... Thus, it repeats in 16 cycles. When OCT=2, the repetition period is 128, The repetition period is 16 when OCT=5.
The desired waveform points are obtained from Table 22.
It is shown that. Also, when ORG=4, OCT=5, the register
Table 18 shows that WAR increases by 4.
4 samples of data with 64 waveform samples as shown
The original waveform data can be obtained by acquiring one point at a time for each waveform.
Being able to raise the octave by two octaves
It shows. If there is a PCM section If there is a PCM section, address generation is done by the PCM section.
performance in time slot (2) compared to the case without
The calculation is different, but the other things are the same. In time slot (2), the performance of STR + WAR is
calculation is performed. Namely: Data is read from register STW of RAM7-3.
Extracted, via HC bus, SW11, A bus
The clock φ3 locks the latch 8-1 of FA2-6.
be hit. At the same time, the RAM7-1 register
The value of WAR is transmitted via the HA bus, SW2, and B bus.
It is latched by latch 8-2 of FA2-6. here
The output of the latch 8-1 is sent to the bit processing circuit 8-1.
0, the output of latch 8-2 is sent to bit processing circuit 8-1.
1, but both outputs undergo bit processing.
sent to latch 8-3 and latch 8-4 without being
and are added by an adder 8-9. Now, consider the value of register WAR
If there is no PCM section, register WAR will contain the first
The negative number of samples included in one period of the waveform as a period value.
number is written, but if there is a PCM part,
Used as the PCM part as the initial value of register WAR
The negative number of samples for all waveforms will be written.
Ru. Therefore, the calculation result of time slot (2) is data
PCM part start address of waveform 1 in banks 1-6
The value increases sequentially by ΔWAR from the response.
The end of the PCM section is detected at the time slot (7).
Check that WAR+ΔWAR≧0 in the calculation.
The address is generated after the PCM section is completed.
It is exactly the same as without the PCM section, and the bit processing
Bit processing is performed by the logic circuit 8-11. In addition, the address calculation in the musical tone generator 1-5
is 16 bits, but the address signal is 16 bits.
Of course, there may be cases where this is not sufficient. So, the book
In the musical sound generation section 1-5, the tablet data
The address space is expanded using the upper 3 bits of TAB.
It is now possible to stretch. to I/O2-10
The latch 10-3 is the latch for address space expansion.
and the tablet data is stored in latch 10-3.
The upper 3 bits of TAB are latched. Namely: When you enter the initial mode by pressing a key, the RAM
The tablet data stored in 5-4 is MSW2
-11 to register TAB' of RAM7-3.
Stored. Then when you enter normal mode,
The value of register TAB' of RAM7-3 is read,
In I/O2-10 via MSW2-11
It is latched by latch 10-3. In this way
Although the internal calculation is 16 bits, the address is 19 bits.
access space. Waveform readout Waveform readout is performed at time slots (2) and (4).
This is done based on the address given. time slot
The calculation result from step (2) is sent to the C bus, SW28, and HL bus.
I/O2-10 via bus, SW30, and D bus.
It is latched by latch 10-1. First, latch 1
0-1 output is shifter selector 10-9, latch
10-4, the bit processing circuit 10-10
Latched by 10-5 and then latched by 10-3
Read data banks 1-6 along with the data
Then, the output of data bank 1-6 is latched 10-8.
is latched to. Then, the output of latch 10-1
is shifted to the right by 1 bit using shifter selector 10-9.
is added, “1” is added to the MSB, and the latch 10-
It is latched at 4. The output of latch 10-4 is bit
to latch 10-5 via gate processing circuit 10-10.
latched, and with the data by latch 10-3.
Read data banks 1-6 to
The output of 1-6 is latched into latch 10-7.
At this time, the upper 8 bits of latch 10-7 are
Since the output of 10-8 is given, the previous data
It is latched with the values in data banks 1-6. child
Now, the lower 8 bits of latch 10-7 are latched.
The data is as described in the data bank section.
Equivalent to 2 words of the lower 4 bits of a 12-bit waveform.
Ru. The output of latch 10-7 is output to selector 10-12.
is applied to shifters 10-13 via
The latch is shifted 4 bits to the right and the latch 10-1
If the LSB of the output is 0, the lower 8 bits are also 4 bits.
If LSB = 1, the lower 4 bits are shifted to the right.
is output from shifter 10-13 without being shifted.
Ru. Here, in the control data CONT
When W8=1, that is, 8-bit waveform is specified,
In this case, shifters 10-13 set the lower 4 bits to “0”.
and output it. The output of shifters 10-13 is noise
D bus via circuit 10-14, latch 10-2
RAM7- through MSW2-11
3 is stored in register WR1. This value is the waveform
1 waveform data. to the address obtained by time slot (4)
The same process will be performed in any case. However, control
If NA=00 in role data CONT
The noise signal is added in the noise circuit 10-14.
available. When AN=01, bit 9, NA=
When NA=10, bit 10, when NA=11, bit
9 and 10 are replaced with noise signals. child
The noise signal can be superimposed without using an adder as in
It's folded. This is the waveform data of waveform 2
It is stored in register WR2 of RAM7-2. envelope multiplication Create two types of waves, waveform 1 and waveform 2, as described above.
The waveform data was obtained, but for this waveform data
Perform envelope multiplication. En for waveform 1
The envelope is stored in register ER1 of RAM7-3 as a waveform.
The envelope for 2 is in the register of RAM7-3.
It is included in TAER2. Now, let's talk about the envelope.
In other words, the envelope is a 4-bit exponent part.
13-bit floating point display with 9-bit fraction
There is. Envelope multiplication is performed twice for each channel.
However, each operation is similar, so the time
Regarding the calculation of WR1×ER1 in slots (7) to (9)
I will explain. The data in register ER1 of RAM7-3 is MSW
Latch 9-3 of MPLY2-7 via 2-11
and is latched by latch 9-5. Here, Ratsu
The lower 10 bits of register ER1 are stored in chip 9-3.
Bits 9-12 of register ER1 are set to bits 9-5.
Latched. Next, register of RAM7-3
WR1 data is MPLY via MSW2-11
It is latched by latch 9-1 of 2-7. Latch 9
The output of -3 is sent to the bit processing circuit 9-12.
The MSB of is set to “1” and latched to latch 9-4.
be done. That is, the latch 9-4 has the envelope
Hypothesis is latched. The output of latch 9-1 is
It is latched to latch 9-2 via lid 9-11.
Ru. At this time, SQ is input to the C input of encoder 9-10.
1 is given by the signal, and the shifter 9-1
00001 is given to the C input of 1. Therefore shifter
9-11 is the lower 12 bits of latch 9-1, that is, data.
Waveform data of waveform 1 read from data bank 1-6
12 bits are sent to latch 9-2. Multiplier 9
-16 is the data of latch 9-2 and latch 9-4
The 14-bit product is held in latch 9-7.
is selected and sent to shifter 9-15. On the other hand, latch 9-5 contains the exponent part of the envelope.
is latched, and dego is connected via latch 9-6.
The selector 9-1 decodes the
4 to the shifter 9-15 as a control signal.
It will be done. Therefore, the output of latch 9-7 is the envelope
shifted by the exponent of the
It will be latched. In this way, fixed-point
Multiplication of waveform data and floating point envelope
It will be done. The output of latch 9-8 is from the L bus.
RAM7-1 register via MSW2-11
Stored in WE1. Waveform data of waveform 2 and encoder
Multiplication of the envelope is done in the same way, RAM7-4
is stored in register WE2. 2 wave mixing As described above, the waveforms are applied to registers WE1 and WE2.
The shape is stored. In this step, WE1 and WE2
Find the sum of The calculation in time slot (1) is
This corresponds to this. CN multiplication Two-wave mixing is performed in time slot (1), but the main musical tone
In the generation part 1-5, ABM2-9 and fiber
Depending on the characteristics of routers 1-7, it may occur depending on the note name.
The sound pressure level generated may differ. for this
CN multiplication performs the correction. Here, the correction
Using the note coefficient CN as it is as a coefficient for
There is. WE2+WE1 at time slot (1)
The calculation result is sent from C bus to SW28, HL bus, SW
29. Latch 9 of MPLY2-7 via L bus
-1. On the other hand, ROM of memory 2-5
Note coefficient according to note data ND from 7-5
CN is read and HD bus, SW24, L bus
Latch to latch 9-3 of MPLY2-7 through
It will be done. Here, WE1+WE2 is 16-bit data.
However, the A input of multiplier 9-16 is 12 bits.
In MPLY2-7, the following processing is performed.
Ru. That is, the upper 5 bits of latch 9-1 are encoded.
input to the encoder 9-10, and the encoder 9-10
Data as shown in Table 9 is input from both terminals A and B.
Output. In other words, the data at latch 9-1
Find the actual number of bits, and depending on this result,
12 bits from latch 9-1 by shifter 9-11.
Take out the tube. For example, if the value of latch 9-1 is
3A26₁₆, this data is effectively 15 bits
Since it is data, shifter 9-11 is latch 9-1.
Take out the 12 bits below bit 14 and use shifter 9.
-11 output is 744₁₆becomes. In this way
Multiplying the real part of WE2 + WE1 by the note coefficient
and return to the original number of bits using shifter 9-15.
Return and latch with latch 9-9. As described above, a multiplier with a small number of bits can be used.
When performing multiplication on data with a large number of bits.
Ru. The value obtained in this way is sent to DAC2-8.
Output and corrected to the specified cycle by ABM2-9
Output as a musical tone signal. By the way, in the main musical tone generating section 1-5,
As mentioned in Table 1, the instructions from the microcomputer
Switch CN multiplication to VLD multiplication by lag VOL
can be done. That is, in a long sequence
Therefore, the register VLD8 bit of RAM5-6 is
RAM7-4 registers via MSW2-11
Sent to LVD′. MSW2-11 when sending
Bit shift is performed at 8-bit data.
Shifted to the left by 2 bits and further set “0” to the lower 2 bits.
is added and converted to 10-bit data. this
Therefore, the number of bits in VLD is the same as the number of bits in CN.
Become one. Add the value of ROM7-5 to the value of WE2+WE1
Multiply or multiply by the value of register VLD′
is determined by the flag VOL in Table 1, and VOL=
If 0, ROM7-5 sends data to HD bus
However, if VOL=1, RAM7-4 is connected to the HD bus.
Send data. By configuring as above, microcontroller 1
-4, the musical tone generator 1-5 outputs the musical tone signal.
It is now possible to change the level of the issue, and as shown in Table 1.
Amplitude modulation is achieved by sequentially changing the value of VLD.
It becomes possible to At least one of the speed and pressure with which you press the keys.
If you create a VLD based on the touch response device
Noh is realized. The touch response function increases the speed and strength of keyboard operations.
The volume, tone, etc. change depending on the pitch.
Ru. For example, on a piano, the harder you press the keys, the louder the volume.
Not only will the sound be brighter, but the tone will also be brighter, making it easier to hit weakly.
When I key the key, not only is the volume low, but the tone is also muffled.
Become something. The volume and tone change automatically depending on the strength of the keystrokes.
However, in the case of a piano, the keyboard changes after the key is pressed.
Even if you change the force with which you press the button, the sound quality is decreasing
cannot make any changes. Pi like this
In that case, only the strength of the keystrokes is the touch response function.
This feature is especially useful at the initial stage.
It's called Tutsi control. Generally, percussion instruments fall into this category.
belong to On the other hand, the trumpet is sustained depending on the strength of the breath.
This sound quality can also be changed.
When playing by imitating the keyboard of an electronic musical instrument
Also, when a key is pressed while a trumpet sound is being generated,
Change the volume and tone by increasing or decreasing the strength
This is necessary. This feature is especially useful after-sales service.
-It's called touch control. Generally, stringed instruments
Wind instruments belong to this category. In the embodiment of the present invention, as described above, the VOL file
By performing VLD multiplication by the lag, each channel
The volume can be controlled independently for each channel. As an application example, measuring the strength of keystrokes and
Create VLD values accordingly and transfer them from the microcontroller.
Different VLDs transferred for each keystroke
The volume of each sound will change accordingly. When the microcontroller transfers VLD, it responds to the value of VLD.
If you change the tablet data and transfer it, the book
The musical tone generator of the embodiment changes the volume according to the value of VLD.
As mentioned earlier, you can also change the tone.
This is clear from the functional description. Regarding this tone switching, VLD is 8-bit
Let's explain with an example. Table 23 shows the range of VLD values and their corresponding
An example of the strength and weakness name and tablet name is shown below. Every time VLD decreases by 1 bit, the volume decreases by 1/2.
It is 6 dB lower, which is the name of the musical term for dynamics.
assigned to each. Also, the strength is gorgeous
Since we need a tone, we need to tap waveform data rich in harmonics.
Assign this to bullet 0, and at a volume lower than MP.
Waveform data close to a sine wave is required because a mellow tone is required.
to assign multiple types of waves to Tablet 3.
Prepare shape data in a data bank. By doing this, the VLD will change depending on the strength of the keystroke.
At the same time, the tone is switched in four ways within the numerical range of
256 different volumes can be specified depending on the 8-bit VLD.
Wear. The above was the initial touch control.
However, similarly, depending on the amount of pressure on the key after the key is pressed,
and VLD that changes from moment to moment according to the value of VLD.
The microcontroller sends the tablet data to be converted into
The musical tone generator of this embodiment changes the key press pressure after the key is pressed.
The tone and volume can be changed moment by moment according to the
I can do it. The above is aftertouch control. (4) Envelope generation method Envelope generation in musical tone generator 1-5
The method can be divided into the following three steps. That is, Address generation Reading envelope data envelope calculation Each step will be explained in detail below. Address generation Header data is set by initial setting by pressing the key.
STE (start address of envelope data E1′)
), ΔSTE (word of envelope data E1′)
registers EAR1, EAR2, TR1,
TR2, ΔT1, and ΔT2 are initially set. this
Address calculations are performed based on these data.
Address calculations do not need to be performed frequently, so
This is done in a long sequence of calculation sequences.
Ru. Furthermore, the embedding is performed at the odd numbered times of the long sequence.
Perform address calculation of rope data E1′ on even numbered times.
Perform address calculation on envelope data E2′
There is. In the odd numbered long sequence, the time
in slot (13) ΔT1＋TR1→TR1……(4-1) in time slot (15) ΔEAR1+EAR1+Ci→EAR1...(4-2) The calculation is performed and the data bank is created using the value of EAR1.
1-6 is read. Time slot (15)
Ci is the accumulation of ΔT1 performed in time slot (13)
This corresponds to the overflow caused by. play here
Calculation (4-1) will be explained in detail. First, the value of register ΔT1 of RAM7-2 is HB
bus, FA2-6 via MSW2-11
It is latched to the lock 8-1. At the same time, RAM7-3
The value of register TR1 is HC bus, MSW2-11
is latched to latch 8-2 of FA2-6 via
Ru. The output of latch 8-1 is sent to bit processing circuit 8-1.
0 forces bit 3 to “0” (bit
The reason why bit 3 is set to "0" will be explained later. ), Ratu
It is latched at 8-3. The output of latch 8-2 is
latch 8-4 via bit processing circuit 8-11.
Latched. Here, the bit processing circuit 8-11
In this case, processing such as bit conversion is not performed. La
The outputs of the latch 8-3 and the latch 8-4 are sent to the adder 8-
9 and added through latch 8-7 and latch 8-8.
and give it to the C bus via MSW2-11.
Store the addition result in register TR1 of RAM7-3.
Ru. If an overflow occurs in the addition result,
If so, “1” is output from Co of adder 8-9.
Ru. This output is latched with latch 8-6 and tied.
Used when calculating Muslot (15). However, this
This applies when there is no PCM part in the waveform data.
Yes, if there is a PCM part in the waveform data (flag
PCM = 1), there is no register until the PCM part is read.
“0” is forcibly set as the calculation result for data TR1.
is input. Therefore, the overflow due to the accumulation of ΔT1
Since no low occurs, it is necessary to read the PCM until
In this case, the value of EAR1 will not be updated. ΔT1 is
As mentioned in the initial processing section, in Table 13
This is the value of D output when C=0, and register TR1
is a 16-bit register, so for example ΔT1
=4000₁₆Then operation (4-1) is performed 4 times
and register TR1 overflows, and the operation (4
-2) Ci=1 and the address can be updated.
Here, operations (4-1) and (4-2) are long seams.
It is held once every two Kens. As shown in Figure 1 C
and the long sequence of the same channel is 388
The period of the time slot, that is, one time slot is
Since it is 250ns, it appears in a period of 97μs. Therefore performance
Calculations (4-1) and (4-2) are performed every 194 μs,
ΔT1=4000₁₆If the address is 776μs,
An update will be made. By the way, envelope data consists of 2 bytes.
Since the address has been updated, please update the address by 2.
Must be updated. Time slot(15)
, update the address as follows:
ing. First, ΔEAR1 is a value determined by ΔT1.
ΔT1≠0008₁₆When ΔEAR1=0000₁₆And
ΔT1=0008₁₆When ΔEAR1=FFEB₁₆=-
twenty one_TenIt is. This operation is in MSW2-11.
It will be held at SW31. SW31 is shown in Figure 11
The value of bit 3 of ΔT1 is
It is controlled by the flag TO shown. Now temporarily
ΔT1≠0008₁₆Then, SW31 connects to the A bus.
0000₁₆However, from register EAR1 of RAM7-1, HA
bus, to B bus via SW2 of MSW2-11
The value of EAR1 is given. These values are FA2−
It is latched by latch 8-1 and latch 8-2 of 6.
Ru. The output of latch 8-1 is sent to bit processing circuit 8-1.
0 to latch 8-3. Here,
Data conversion is performed in the output processing circuit 8-10.
It seems like there is no such thing. At the same time, latch 8-2
The output is given to the bit processing circuit 8-11, and the data
LSB of data is forced to “1” and latch 8-
Sent to 4. That is, in the bit processing circuit 8-11
1 is added in advance. In addition, the latch 8 mentioned earlier
-6 is stored in operation (4-1).
The bar flow is latched in latch 8-5. Therefore
Latch 8-3, latch 8-4 and latch 8-5
When the values are added, the value of latch 8-5 is “1”.
If so, “2” will be added to the value of EAR1.
Ru. On the other hand, if the value of latch 8-5 is "0",
The value of EAR1 remains incremented by 1, but
As mentioned in the section on file processing, I/O2-10
Force the LSB to be “0” or “1”
There will be no inconvenience. By the way, ΔT1=0008₁₆If ΔEAR1 is
FFEB₁₆(-21_Ten). Therefore, from the value of EAR1
twenty one_TenWill be drawn, envelope 10 words ago
data will be read. This results in
Envelope data address loops
It becomes a repeating envelope like a mandolin.
can generate a drop. Calculate first (4-1)
Then, bit 3 is processed by bit processing circuit 8-10.
I mentioned setting it to “0”, but the reason is that bit 3 is
EAR1=FFEB₁₆, and this operation
0008 in register TR1 when doing₁₆do not add
This is for the purpose of ΔT2 at even numbered times of long sequence,
Calculations for TR2, ΔEAR2, and EAR2 are performed in the same way.
It will be done. Note that calculations related to EAR1 and EAR2 are completely independent.
waveform 1 and waveform 2.
can generate envelope signals.
Needless to say. In addition, EAR1 or EAR2
Regarding repetition, the repetition period is also different.
Since it is easy to use, various effects can be obtained.
Wear. Reading envelope data Reading envelope data is a long sequence.
the envelope of waveform 1 on even-numbered times.
the envelope data of waveform 2 at odd-numbered times.
Read data. An error is performed based on the values of registers EAR1 and EAR2.
For instructions on how to read envelope data, please refer to the initial
This is exactly the same as described in the section on processing
Read from data bank 1-6 at I/O2-10
While converting the format of the captured data,
Registers ΔT1, ΔT2, ΔZ1, ΔZ2, ΔE1, ΔE2
I will pay it. envelope calculation By reading the envelope data, ΔZ1,
Data is stored in ΔZ2, ΔE1, ΔE2, and
ER1, ER2, ZR1, ZR2 by initial processing
is given an initial value. depending on these values
Perform envelope calculations. The basis of envelope calculation is the time slot of the addition section.
(3), (5), (6), and (8). Time slot (3),
Calculate the envelope of waveform 1 using (5), and
The envelope of waveform 2 is determined by Muslot (6) and (8).
Calculate. Here, Ci of time slots (5) and (8)
is the overflow caused by the operations using time slots (3) and (6).
Although it is a bar flow, at time slots (3) and (6)
How the resulting overflow is time-stamped
Regarding whether it is added by lot (5) or (8), the address
The time slot for occurrence of
It is similar to ER1 obtained in this way,
The value of ER2 is envelope data. Note that the “envelope” in “(3) Waveform generation method”
As mentioned in the section ``Multiplication'', both ER1 and ER2 are 13
In bit data, the top 4 bits are the exponent part and the bottom 9 bits are the exponent part.
The bit is the mantissa. Therefore, the main musical tone generator
The envelope obtained in step 1-5 is shown below.
It takes shape. Envelope 1 = 1. (lower 9 bits of ER1) x 2
(upper 4 bits of ER1) Envelope 2 = 1. (lower 9 bits of ER2) x 2
(upper 4 bits of ER2) Because it is shown in this way, the level of the envelope
Always has 9-bit resolution regardless of the file size.
It becomes. By the way, envelope calculation can be done in various modes.
It's different. What are the various modes? 1 When the waveform has PCM and when it does not.
(PCM=1/0) 2 Case of piano-type envelope and organ-type envelope
For envelopes. (P/O=1/0) 3 When the damper flag is turned on and when it is turned off.
If. (DMP=1/0) There are three types. Each case will be explained below.
Ru. PCM=0 and P/O=0 The initial setting is “0” for ER1, ER2, ZR1, and ZR2.
, and when the key is pressed, register ΔE1,
The envelope is expressed according to the values of ΔE2, ΔZ1, and ΔZ2.
Do calculations. When the key is released, the time slot (3),
As the values of ΔZ1, ΔE1, ΔZ2, and ΔE2 in (5), (6), and (8),
Released from signal processor 5-6 of UCIF2-3.
data is generated and registers ΔZ1, ΔE1,
Used instead of the values of ΔZ2 and ΔE2. In addition, in this mode, the damper flag
The calculations are not affected in any way by DMP. PCM=0 and P/O=1 The initial setting is “0” for ER1, ER2, ZR1, and ZR2.
, and when the key is pressed, register ΔE1,
The envelope is expressed according to the values of ΔE2, ΔZ1, and ΔZ2.
Do calculations. When the key is released, the damper flag DMP
If = 1, registers ΔE1, ΔE2,
Perform envelope calculation according to the values of ΔZ1 and ΔZ2.
Yes, when damper flag DMP=0, PCM=0 and
This is the same as when P/O=0. PCM=1 and P/O=0 Initial setting is EA1=1FFF₁₆, ER2=0, ZR1
=0, ZR2=0. The key is pressed and the wave
When Type 1 is reading the PCM section, the initial value is retained.
After reading the PCM part, register ΔE1,
The envelope is expressed according to the values of ΔE2, ΔZ1, and ΔZ2.
Do calculations. When the key is released, waveform 1 moves to the PCM section.
UCIF2-3 regardless of whether it is read or not.
Based on release data by signal processor 5-6
calculation is performed. That is, PCM=0 and P/O=
The result is 0. In addition, in this mode, the damper flag
Operations are not affected by DMP. PCM=1 and P/O=1 Initial setting is ER1=1FFF₁₆, ER2=0, ZR1
=0, ZR2=0. Damper flag DMP=0
In this case, once the key is pressed, the key release timing is
The calculation is performed regardless of the program. That is, waveform 1 is
When reading the PCM section, register ER1,
ER2, ZR1, and ZR2 retain their initial values, and the PCM section
After reading registers ΔE1, ΔE2, ΔZ1, ΔZ2
The calculation is started according to the value of . damper flag
When DMP=1, PCM=1 and P/O=0
The case is exactly the same. As mentioned above, you can use it freely depending on the various modes.
can generate an envelope signal. Ma
In addition, ΔE1, ΔZ1 and ΔE2, ΔZ2 can be set completely independently.
The data is clear in the address generation section.
It is updated at the time determined by ΔT1 and ΔT2.
Therefore, in conjunction with the two types of waveform data mentioned above,
Various musical tones can be generated. (Effect of the invention) As described above, the present invention provides waveform data,
start address of the data and the attribute of the waveform data.
first data including an octave value to
and second data containing the address of the data of
It has a data bank that also has at least a timbre
Receive performance information including selection data and pitch data
and the corresponding tone selection data from the above data bank.
Part or all of the pitch data can be used as an address.
a means for reading second data corresponding to the data;
Part or all of the second data from the data bank
Read the first data corresponding to the address
means and the octave value to which the above pitch data belongs.
to which the waveform data in the corresponding first data belongs.
The number obtained by subtracting the octave value is expressed as a power of 2.
a means for creating a value A and a star in the first data;
Add the above value A to the root address in order.
The corresponding wave from the above data bank as the address
By providing a means to read shape data, sound
A desired range of sounds can be created without having to prepare waveform data for each range.
Not only can musical tones be generated, but waveform data can also be generated.
Even if it is a PCM waveform, musical tones can be generated by changing the range.
can be set. Furthermore, each range or part of the range
I heard that you can change the waveform data read out for each range.
Increasing the redundancy of waveform data even in cases where
I can handle it without any problems.

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Claims (1)

[Claims] 1. Data that stores waveform data, first data including a start address of the waveform data, and an octave value to which the waveform data belongs, and second data including the address of the first data. means for receiving performance information including at least timbre selection data and pitch data, and reading out corresponding second data from the data bank based on the performance information; means for reading first data and creating a numerical value A by subtracting the octave value to which the waveform data in the corresponding first data belongs from the octave value to which the pitch data belongs as a power of 2; An electronic musical instrument characterized in that the electronic musical instrument has means for reading out corresponding waveform data from the data bank using an address obtained by sequentially adding the numerical value A to the start address in the data.