JPH0127436B2 - - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a vibrato adding device for an electronic musical instrument, and particularly to a vibrato adding device that has a simple configuration, can change the vibrato frequency while preserving the vibrato waveform, and can select an arbitrary vibrato waveform. Regarding additional equipment. Conventional configuration and its problems Conventionally, vibrato adding devices have been configured to apply analog frequency modulation to the main oscillator, so in order to change the vibrato frequency, it is necessary to change the frequency of the modulation signal. However, the scale of the modulation signal generation circuit becomes large and the output frequency thereof becomes unstable. Furthermore, a method has been proposed in which the vibrato frequency is changed by changing the read address length in a digital vibrato adding device equipped with a vibrato data memory. This method has the advantage of simple configuration, but as the vibrato frequency changes,
This had the disadvantage that the vibrato waveform also changed. Furthermore, since a portion of one vibrato data memory is used, it is not possible to arbitrarily select a vibrato waveform. OBJECTS OF THE INVENTION An object of the present invention is to provide a vibrato adding device that has a simple configuration, can change the vibrato frequency while preserving the vibrato waveform, and can select an arbitrary vibrato waveform. Composition of the Invention The vibrato adding device of the present invention includes a plurality of vibrato data memories that store a plurality of types of frequency modulation data, an address generation unit that generates addresses of the vibrato data memories, and a vibrato data memory that selects one of the vibrato data memories from among the plurality of vibrato data memories. a vibrato data select section for selecting one vibrato data memory; a no-lock generator capable of applying frequency modulation according to the output data of the vibrato data memory; and an address length for controlling the address length of the address generation section. The control section controls the address length generated by the address generation section and selects the vibrato data memory corresponding to the address length by the vibrato data selection section, thereby controlling the address length at any frequency. It has a simple structure and can generate a vibrato waveform of any frequency and any shape. DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an electronic musical instrument employing the vibrato generator of the present invention.
101 is a keyboard section KB; 102 is an operation section TAB consisting of a tone tablet switch, a vibrato effect on/off switch, a glide effect on/off switch, etc.; and 103 is a central processing unit CPU.
104 is a read/write storage device (random access memory called RAM), which is similar to that used in computers, etc.;
106 is a read-only storage device (read-only memory called ROM) that stores programs that determine the operation of the CPU 103, and 106 is a storage device that stores waveform sample data for synthesizing musical tones, control data for waveform interpolation, etc. Memorized ROM
It is. Reference numeral 107 designates a musical tone generator that generates musical tones using waveform sample data and control data stored in the ROM 106, 108 a filter that removes sampling noise, and 109 an electroacoustic transducer. Keyboard section 101, operation section 102, CPU 103,
The RAM 104, ROMs 105 and 106, and musical tone generator 107 are connected by a data bus, an address bus, and a control line. The method of coupling data buses, address buses, and control lines in this manner is a well-known method for configuring minicomputers and microcomputers. Eight to 16 data buses are used, and data is transmitted and received on these bus lines not in one direction but in multiple directions in a time-division manner. Multiple address buses, for example 16, are prepared, and usually the CPU 108
outputs the address code, and other parts receive the address code. Control lines are usually memory request lines and I/O request lines.
IORQ, read wire, write wire, etc. are used. indicates reading and writing memory,
IORQ indicates retrieving the contents of the input/output device I/O, indicates the timing to read data from memory or I/O, and indicates the timing to read data from memory or I/O.
The timing to write data to O is shown. An example of a device using such a control line is the microprocessor _Z80 manufactured by Zilog. Next, the operation of the electronic musical instrument shown in FIG. 1 will be described.
The keyboard section 101 is configured to divide a plurality of key switches into a plurality of groups and to be able to collectively send the on/off states of the key switches in the group to the data bus. For example, in the case of a 61-key keyboard, it is divided into 10 groups of 6 keys (half an octave) and 11 groups of 1 key, and one address code is assigned to each group. An address code indicating one of the above groups arrives on the address line, and the signal and signal
When RD is applied, the keyboard section 101 decodes the address code and outputs 6-bit or 1-bit data indicating on/off of the key switches in the corresponding group to the data bus. These can be constructed using decoders, bus drives and some gate circuits. Of the operation section 102, the tablet switch is connected to the keyboard section 10.
A configuration similar to 1 can be adopted. The CPU 103 reads the instruction code from the address of the ROM 105 that corresponds to the code of the internal program counter, decodes it, performs arithmetic operations, logical operations, reads and writes data,
Performs tasks such as jumping instructions by changing the contents of the program counter. Procedures for these operations are written in the ROM 105. First, CPU1
03 reads a command for importing data from the keyboard section 101 from the ROM 105, and imports codes indicating on/off of each key of the keyboard section 101 for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generating section 107, and musical tone generation data corresponding to the key code is sent out. Next, the CPU 103 sequentially reads a group of instructions from the ROM 105 for importing data from the operation unit 102, decodes them, and generates the address code and control signal corresponding to the operation unit 102.
IORQ and the operation unit 10 to the data bus.
A code expressing the state of the switch 2 is output and read into the CPU 103. Based on the data read into the CPU 103, the ROM 106 selects a tone and generates predetermined effect control data.
timbre selection data and effect control data are sent to the musical tone generator 107. The method of allocating the pressed key code to a finite channel of the tone generating section 107 is known as a generator assigner function. The musical sound generation section 107 generates musical sound synthesis data based on the musical sound generation data supplied from the CPU 103.
Predetermined waveform sample data and control data are taken in from the ROM 106 and subjected to waveform interpolation processing to generate a musical sound waveform, and a musical sound is generated from the electroacoustic transducer 109 via the filter 108. FIG. 2 shows a time chart when data is supplied from the CPU 103 to the tone generator 107.
The I/O port address is supplied to the address bus, and musical tone generation data, effect control data, etc. are supplied to the data bus. and the control signal
At the timing when IORQ changes from a logic low level (hereinafter referred to as "0") to a logic high level (hereinafter referred to as ""), the contents of the data bus are latched to the channel specified by the I/O port address. The various data supplied to the generation unit 107 will be explained.Table 1 shows the I/O port address and the contents of the various data.The I/O port address is expressed in hexadecimal.I/O The data corresponding to port address (00) ₁₆ to (07) ₁₆ is musical tone generation data 8.
It is said that it is possible to generate eight tones for each channel. I/O port address (08) ₁₆ is sustain data that specifies the attenuation characteristics of the envelope signal. I/O port address (09) ₁₆
is damper data that is valid when the envelope characteristic is piano type, and, like sustain data, specifies the attenuation characteristic of the envelope signal.
I/O port address (OA) ₁₆ is pitch control data, which is used to shift the note clock from its normal value. I/O port address (OB) ₁₆ is effect control data, vibrato on/
It consists of off signals and ground on/off signals. The I/O port address (OC) ₁₆ is vibrato select data, which is data for specifying one vibrato data out of a plurality of vibrato data. I/O port address (OD) ₁₆ is vibrato

【table】

【table】

[Table] Speed data that specifies the vibrato frequency. Table 2 shows the composition of the musical tone generation data. Bit positions _D0 to _D3 are note clock designation data that designates the scale frequency. Bit position D ₄ ~
_D6 is waveform sample number designation data that designates the sound generation range. Bit position _D7 is a key on/off signal accompanying the on/off operation of the key switch, and is "0" when off and "1" when on. Table 3 shows waveform sample number specification data SD ₀ to _{SD 2}
This shows the code contents and the number of samples in one cycle of the waveform specified by the code. The waveform sample number specification data SD allows eight types of waveform sample numbers from (000) ₂ to (111) ₂ to be specified, and in this embodiment, 512 samples to 4 samples are specified. Table 4 shows notebook clock specification data ND ₀ ~
This shows the relationship between the contents of the chord represented by ND ₃ and the specified scale specified by that chord. Table 5 shows the composition of the effect control data. B

[Table] Position D ₀ is the vibrato on/off signal VIB,
When the vibrato on/off switch in the operation unit 102 is off, it is "0" and when it is on, it is "1". Bit position _D1 is a delay vibrato on/off signal DVIB, which is a delay vibrato effect control signal, and is "0" when the delay vibrato on/off switch in the operation section 102 is off, and "1" when it is on. Bit position D ₂ is the ground on/off signal GL
When the ground switch in the operation unit 102 is off, it becomes "0", and when it is on, it becomes "1". Bit position _D3 is the organ type/piano type designation signal OPS, which specifies the envelope characteristics, and is “0” for organ type and “1” for piano type.
becomes. Bit position D ₄ is the damper on/off signal DMP
This is valid only when the envelope characteristic is piano type, and is "0" when the damper is off and "1" when it is on. FIG. 3 is a configuration diagram of the musical tone generating section 107.

[Table] In FIG. 3, 301 is a main oscillator, 302 is a sequencer that controls the operation of the musical tone generator 107, 303 is an input register unit that latches various data supplied from the CPU 103, 304 is a timer, and 305 is a A comparison register section 306 is a frequency data processor (hereinafter abbreviated as FDP) that generates frequency data corresponding to the frequency to be generated.
07 is a waveform data processor (hereinafter abbreviated as WDP) that performs waveform interpolation processing, and 308 is musical tone synthesis data.
A data read processor (hereinafter abbreviated as DRP) reads waveform sample data, control data, etc. from the ROM 106; 309 is a read pulse forming unit that generates a pulse signal with a predetermined pulse width;
10 is a calculation request flag generation unit that requests arithmetic processing to the WDP 307, DRP 308, etc.; 311 is a digital/analog converter (hereinafter abbreviated as DAC) that converts a digital signal into an analog signal; 312
consists of two analog switches and one capacitor per channel, an analog buffer memory section for holding analog signals, and 313 an integrator. Here, the waveform interpolation method executed by the WDP 207 will be explained. As a waveform interpolation method, sample wave positions i to i+1 (i=0, 1, 2,
...I-1), one cycle of the musical sound wave repeats M times, and the virtual sample value ^ that exists between the waveform samples (X _i,o and (X _i+1,o ))
This is an attempt to obtain an approximate value by virtually calculating a waveform sample value at a virtual sample point using (X _i,n,o ) using an interpolation operation. The interpolation formula is shown below. (X _i,n,o )={(X _i+1,o )−(X _i,o )} ×N _n+o /MN+(X _i,o ) ……(1) i is divided into I. This is the waveform number at the sample position extracted. (i=0,1,2,...,I-
1) m represents a position in the middle of a transition between waveform numbers i and i+1 repeatedly M times. (m=0, 1, 2, . . . , M-1) n is a sample position obtained by dividing one cycle of the musical sound waveform into N, and is a waveform sample NAND. (n=0,1,2,
..., N-1) The operations around the WDP 207 and DRP 208 are described in detail in Japanese Patent Application No. 57-231482 "Music Sound Generator". In the above configuration, 304, 305, 306,
Reference numeral 310 constitutes a note clock generation section that determines the tone scale, and based on its output signal, the data reading section DRP 308 generates musical tone synthesis data.
Read data from ROM106. Also, input register section 308, comparison register section 305, FDP 306, WDP 307, DRP 30
8. The calculation request flag generation unit 310 is the sequencer 3
02 determines the procedure for processing. When musical tone generation data is supplied from the CPU 103 to a predetermined channel, for example, channel 1, at a predetermined timing determined by the sequencer 302, the data is sent from the input register section 303 to the FDP 306 and WDP 3.
07, musical tone generation data is supplied to the DRP 308. Then, the DRP 308 reads the waveform sample data and control data from the musical tone synthesis data ROM 106. Then, (X _i,o shown in equation (1) is data WDI, and (X _i+1,o ) is supplied as data to the WDP 307.Furthermore, based on the read control data, as shown in equation (1), WDP3 uses the numerator term (N _n+o ) of the interpolation coefficient as data MLP.
Supply on 07. Also, when the final waveform data is reached, the WEF signal that instructs the final waveform data is sent to WDP30.
Supply to 7. The WDP 307 uses the data WD, WD, and MLP supplied from the DRP 308, performs waveform calculation processing according to equation (1), and supplies the processed data to the DAC 311. The DAC 311 converts the digital signal supplied from the WDP 307 into an analog signal and supplies it to the analog buffer memory section 312 as an analog signal, where the capacitor charge corresponding to channel 1 is stored. On the other hand, in the FDP306, the input register section 30
Frequency data is generated based on the musical tone generation data supplied from 3, and is supplied to the register corresponding to channel 1 of the comparison register section 305. Then, the data supplied to the comparison register 305 and the time data supplied from the timer 304 are compared, and if a match is detected, a matching pulse is read out and supplied to the pulse forming section 309 and the calculation request flag generating section 310. . Then, the read pulse forming section 309 generates a read signal with a predetermined pulse width and supplies it to the analog buffer memory section 312. The charge stored in the capacitor corresponding to channel 1 in the analog buffer memory section 312 flows into the integrator 313 in response to the read signal. The calculation request flag generating section 310 generates and holds a calculation request flag for determining the next waveform sample, that is, the virtual sample point ^(X _i,n,o+1 ). Thereafter, when the processing timing becomes channel 1 again, since the calculation request flag has been generated, waveform interpolation processing is performed in the same manner as described above, and charges are stored in the capacitor in the analog buffer memory section 312. Thereafter, waveform interpolation processing is performed in response to the calculation request flag, and a musical tone waveform is generated. The charge stored in the capacitor is ^(X _i,n,o-1 )
This corresponds to the difference between the waveform sample value ^(X _i,n,o ) and the waveform sample value ^(X i,n,o ) obtained this time. Then, the waveform sample value ^(X _i,n,o ) obtained this time is restored by the integrator 313. Regarding the operation around the analog buffer memory section 312 and the integrator 313, please refer to the patent application filed in 1987-
126413 “Waveform reading device”. FIG. 4 is a block diagram of a specific example of the sequencer 302. In the figure, 401 is a two-phase clock generation unit that generates two-phase clock signal φ1 and signal φ2;
402 is a hexadecimal counter that determines the operation sequence per channel; 403 is a counter that generates the channel code currently being processed; 40
4 is a ROM in which operating procedures are stored, and 405 is a decoder. FIG. 5 shows a timing chart of the sequencer 302. A master clock MCK signal is supplied from the main oscillator 301 to the two-phase clock generating section 401. A two-phase clock generating section 401 generates two-phase clock signals φ1 and φ2 as shown in FIG. The signal φ1 is
It is supplied to a hexadecimal counter 402 and a counter 403. The hexadecimal counter 402 has a 4-bit configuration, and the count-up process is performed at the timing when the signal φ1 changes from "0" to "1", the output signal becomes (1111) ₂ , and then the count-up is performed. and (0101) are set to ₂ . As a result, the output signal of the hexadecimal counter 402 becomes 11 states, that is, (0101) ₂ to (1111) ₂ . This is used as a command step signal. The counter 403 has a 3-bit configuration,
Each time the output signal of the 11 counter 402 changes from (1111) ₂ to (0101) ₂ , count-up processing is performed. As a result, the output signal of the counter 403 becomes 8 states, that is, (000) ₂ to (111) ₂ . Use this as the channel code. ROM 404 reads out an instruction code based on the instruction step signal supplied from hexadecimal counter 402 and supplies it to decoder 405 . The decoder 405 decodes the instruction code supplied from the ROM 404 and supplies processing control signals to each section. As a result, the calculation time per channel is 2.75μs.
Therefore, each calculation process is performed in 11 instruction steps. Then, the calculation timing is repeated every 22 μs. FIG. 6 shows a configuration diagram of a specific example of the analog buffer memory section 312. In the figure, 601 is an input terminal;
602 is an output end, 603 to 608 are analog switches, and C ₁ to C ₃ are capacitors. The signals AW ₁ to _{AW 8} supplied to the gate inputs of analog switches 603, 605, and 607 are
It is supplied by WDP307. Furthermore, the signals AR ₁ to AR 8 supplied to the gate inputs of the analog switches 604 , 606 , and ₆₀₈ are supplied from the read pulse forming section 309 . The analog signal converted by the DAC 311 is applied to the input terminal 601 and is applied to the analog switches 603 and 6.
05,607. And channel 1
If the data corresponds to
Only 03 is turned on, and the charge corresponding to the analog signal applied to the input terminal 601 is transferred to the capacitor.
Stored in C ₁ . Then the read pulse corresponding to channel 1
When AR ₁ is supplied from the read pulse generator 309 to the gate input of the analog switch 604, the charge stored in the capacitor C ₁ is transferred to the output terminal 60.
2 to an integrator 313. Analog switches 603, 605, 607
Since it is synchronized with the operation timing of the WDP 307, multiple units are not turned on at the same time. Since the analog switches 604, 606, and 608 are turned on in synchronization with the musical scale frequency, a plurality of them can be turned on at the same time. FIG. 7 is an internal operation timing chart of the musical tone generating section 307. FIG. 7 shows the timing for four channels. Explanation of abbreviations in the figure CRF is a calculation request signal for each channel. Then, the request start point is at the comparison register section 30.
It is synchronized with the coincidence signal supplied from 5. That is, it is synchronized with the scale frequency, and for example, in the C scale, it occurs every 59.74 μs. CLC indicates waveform calculation timing. DAC indicates the timing at which charges are stored in the capacitor in the analog buffer memory 312 via the DAC 311. OTC converts the charge stored in the capacitor in the analog buffer memory 312 into an integrator 313.
It is the timing to supply to the
It is produced in synchronization with the musical scale frequency. The time chart for channel 1 will be explained. The calculation timing corresponding to channel 1 is determined by the channel code generated by the sequencer 302, and as shown in the figure, it is 22μs.
Calculation timing occurs every time. ... Signal CRF1 is generated in the middle of channel code 1. Waveform interpolation processing and frequency data updating are not performed at the generated timing. ...Signal OTC1 is generated at the same time as signal CRF1 is generated.
is generated, and the charge of capacitor C ₁ in analog buffer memory 312 is supplied to integrator 313 . The pulse width of the signal OTC is about 2 μs. ...When the channel code becomes 1 again, reading processing of waveform sample data, waveform interpolation processing, frequency data updating processing, etc. are performed. ...When the calculation process of channel 1 is completed, the signal
DAC1 is generated and charge is stored in capacitor _C1 via DAC311. ...When the calculation process of channel 1 is completed, the signal
Reset CRF1 and cancel the calculation request. ...Similarly to the above, when the signal CRF1 is generated again, the charge stored in the capacitor _C1 at the above timing is transferred to the integrator 313.
is supplied to Thereafter, as described above, each time the signal CRF is generated, one temporary phase waveform sample value calculation process and frequency data update process are performed, and the waveform calculation is performed in synchronization with the generation timing of the signal CRF, that is, the scale period. The result is provided to integrator 313. Regarding the relationship between the calculation cycle and the scale period, it is sufficient that the calculation timing of the same channel can be performed twice within the minimum scale period and that the calculation result can be stored in a capacitor in the analog buffer memory section 312. That is, it is sufficient to provide calculation timing corresponding to 10 channels within the minimum scale period in consideration of vibrato, glide, etc. Explanation on how to generate intervals Regarding notes, a clock signal corresponding to a 12-tone scale is generated. Regarding octave relationships, octave related pitches are generated by changing the number of samples in one cycle of the musical sound waveform stored in the musical tone synthesis data ROM 106. If _C0 note (32.708Hz) is 512 samples, the note clock signal is 32.708Hz x 512 samples ≒
It becomes 16.74KHz. Table 6 shows the note clock frequency, and Table 7 shows the number of waveform samples and octave relationship. Explanation of how the scale period is generated.
05 shows the transition of frequency data supplied to 05. The timer 304 is composed of a 10-bit binary counter, and the output status is expressed in hexadecimal notation as (000) _16.
Count up sequentially from (3FF) to ₁₆ ,
(3FF) ₁₆ becomes (000) ₁₆ again, and from (000) ₁₆ to (3FF) ₁₆ is the signal supplied from the main oscillator 301.
Repeated based on MCK. That is, the repetition frequency T _R of the timer 304 is as shown in the following formula. T _R =2 ¹⁰ ×1/MCK...(2)

【table】

[Table] The transition state of the output data of the timer 304 is shown as timer output data in FIG. As a method of generating the scale period, the timer 304
The output signal of the FDP 306 is compared with the frequency data supplied from the FDP 306, and if a match is detected, a match pulse is sent out from the comparison register section 305.
The generation cycle of the matching pulse becomes the scale cycle of the scale to be sounded. As shown in FIG. 8, a note clock signal can be generated by updating the frequency data.
In other words, the calculation process shown in the formula below is performed using FDP3.
Do it on 06. NFD=MOD(OFD+PD, _TDnax )...(3) NFD is new frequency data. OFD is frequency data before update. PD is scale data determined by the generated scale. TD _nax is the number of output states of the timer 304. In this embodiment, TD _nax is ²¹⁶ , or 1024. Table 8 shows scale data PD corresponding to the 12-tone scale. FIG. 9 is a configuration diagram of a specific example of the FDP 306. In FIG. 9, 901 is a cent scale data generation unit (hereinafter abbreviated as CPD generation unit) that generates scale data (CPD) expressed in cent scale.
It consists of a ROM that stores cent scale data, and is designed to selectively generate CPD based on note clock specification data ND, waveform sample number specification data SD, and organ type/piano type specification signal OPS. . 902 is a pitch control data gate that selects pitch control data; 903 is a vibrato signal generating section that generates a vibrato signal; 904 is a glide signal generating section 905 that generates a glide signal; an exponential converter that converts directly proportional frequency data;

[Table] 906 is an arithmetic unit, 907 is a latch (AL), 908 is a latch (BL), 909 is an adder (FA), 910 is a buffer, and 911 is a gate. 912, 913, 914 are bus lines, 912 is FA bus, 913 is FB bus, 91
4 is the FC bus. Note that pitch control data CPCD, vibrato data CVD, and glide data CGD are also expressed in cent scale. Structure of various data Cent pitch data CPD consists of 11 bits, the upper 4 bits represent 12-tone equal temperament, and the lower 7 bits represent each point of the chromatic scale divided into 128 equal parts. Pitch control data CPCD, vibrato data CVD, and glide data CGD are each composed of 8 bits, using two's complement representation, and have a resolution that divides the chromatic scale into 128 equal parts. It also represents positive and negative pitch control components, vibrato components, and glide components. Description of Vibrato Signal Generating Section 903 FIG. 10 shows a configuration diagram of a specific example of the vibrato signal generating section 903. 1001 in the figure is a vibrato that stores multiple vibrato data CVD.
ROM, 1002 is a vibrato address register that stores address data for reading the vibrato data stored in the vibrato ROM 1001, 1003 is a shifter used for the delay vibrato effect, and 1004 is an output signal of shift 1003 (vibrato data) by the signal RDCVD.
CVD) to the FB bus, 1005 is a signal supplied from the input register section 303
KD, signal VIB, signal DVIB and sequencer 302
1006 is a selector that selects data to be stored in register 1002; 1007 is a gate; 1008 is an AND gate; 1009 is This is a shift detection section that detects shifts in vibrato data CVD. Principle of vibrato signal generation FIG. 11 is a data map diagram showing the contents of the vibrato ROM 1001. One vibrato data memory has a structure of 2048 words with 8 bits per word, and stores data representing a vibrato waveform. Vibrato ROM100 with 16 such vibrato data memories
1 is configured, and one vibrato data memory is selected by the lower 4 bits of the vibrato select data VBD supplied from the input register section 303. Normally, 14-bit vibrato address data is supplied from the FC bus to register 1002 via selector 1006. The lower 11 bits of the 14-bit vibrato address data are used as address data in the vibrato ROM 100.
1, and the upper three bits are supplied to shifter 1003 as shift data. Vibrato ROM 1001 is register 100
Vibrato data is supplied to the FB bus via gate 1004 in accordance with the address supplied from 2. On the other hand, the 14-bit vibrato address data is directly supplied to the FB bus via the gate 1007, is incremented by 1 in the arithmetic unit 906, and is supplied to the FC bus again. Through this repetition, the vibrato address data is incremented by one. Therefore, the vibrato address data supplied from the FC bus is added to the vibrato ROM 1001 as a read address, and is transferred from the FC bus to the FB bus for the purpose of incrementing the vibrato address itself. The selector 1006 is a vibrato ROM 100
1 and the initial value of the vibrato address data added to the shifter 1003. In other words, the selector 1006 normally selects the vibrato address data supplied from the FC bus, and the vibrato address data is incremented one by one by the address increment processing described above. When the address data corresponding to the lower 11 bits of the vibrato address data overflows, a flag is set in the miss detection section 1009, and an initial value selection signal is sent to the selector 1006, and the selector 1006
Initial value supplied from input register section 303
Select VBS (vibrato speed data).
Thereafter, the selector 1006 selects the vibrato address data supplied from the FC bus and performs normal step processing. Therefore, the lower vibrato address data
The 11-bit address data is the initial value VBS.
It will progress between ₁₀ and the final value (2048). The method of setting the vibrato frequency will be explained below. Note that the number of addresses from the initial address value VBS to the final address value (2048) ₁₀ is called the address length. Here, set the initial value of the vibrato address data.
It is called VBS (vibrato speed data) because the above initial value determines the vibrato frequency. In other words, since the time required for one step of vibrato address data is constant, the time required for one cycle of vibrato is determined by the value of the address length. In other words, the vibrato frequency is determined by the address length value. FIG. 12 is an example of one cycle of vibrato data stored in the vibrato ROM 1001. Note that the horizontal axis represents addresses, and the vertical axis represents the size of vibrato data. In this case, by changing the vibrato speed data VBS between (000) ₁₆ = (0) ₁₀ and (2AO) ₁₆ = (672) ₁₀ , the address length changes from 2048 to 1376, resulting in a vibrato of 48.8%. A change in frequency is obtained. However, as the vibrato frequency changes, the vibrato waveform also changes. Also, if the vibrato speed data VBS, that is, the initial value of the address exceeds (2AO) ₁₆ = 672, the data corresponding to the initial value of the address and the data corresponding to the final value will not match, causing discontinuity in the vibrato waveform, so the vibrato speed The maximum value of the data VBS must be kept within a range where discontinuities in the vibrato waveform do not cause any audible problems. A method for selecting vibrato data compatible with vibrato speed data VBS will be described below. FIG. 13 shows an example of vibrato data stored in the vibrato ROM 1001. The data in FIG. 13a is stored in the vibrato memory 1 portion of the vibrato map shown in FIG. It is assumed that the data shown in FIG. 13b is stored in . The horizontal axis shows the address value.
The value is expressed in decimal notation, and the vertical axis represents the size of the vibrato data. In Figure 13, data a is vibrato speed data VBS =
(000) ₁₆ is the vibrato data corresponding to address length = 2048, and the data of b is VBS = (100) ₁₆ =
(256) ₁₀ is vibrato data corresponding to address length = 1792. At this time, the CPU 103 has VBS=
(000) When ₁₆ , vibrato select vibrato
When VBD=(00) ₁₆ , VBS=(100) _16, VBD=
(01) Control is performed so that the number becomes ₁₆ . Then VBS
= (000) VBS = (100) Sine wave vibrato can be added even when _{set to 16 .} Using this method, a constant vibrato waveform can be obtained regardless of the vibrato frequency, and no discontinuity of the vibrato waveform occurs. The relationship between vibrato speed data VBS and vibrato frequency is specifically shown below. If the vibrato data is read out at the calculation timing of channel code 1 and once every four times, the readout cycle will be 88 μs. When VBS = (000) ₁₆ , the address length is 2048, so ₀ = 1/(22μs x 4 x 2048) = 5.55Hz VBS = (100) ₁₆ = (256) When ₁₀ , the address length is
Since it is 1792, ₁ = 1/(22μs x 4 x 1372) = 6.34Hz. In this embodiment, the vibrato frequency is changed by changing the initial value of the vibrato address, but the same effect can be achieved even if the final value of the address or both the initial value and final value are controlled. The effect of this can be obtained. On the other hand, the shifter 1003 controls the amplitude of vibrato data CVD supplied from the vibrato ROM 1003 based on shift data. The relationship between shift data VSFD and output data OSFD of shifter 1003 is as follows. VSFD=(000) ₂ ...OSFD=(00) ₁₆ ,VSFD=
(001) ₂ ...OSFD=(CVD/64), VSFD=(010) ₂
...OSFD=(CVD/32),...,VSFD=(110) ₂
...OSFD=(CVD/2), VSFD=(111) ₂ ...
OSFD=(CVD) The condition setting unit 1005 sets the following operating conditions. Vibrato off This is a case where the vibrato on/off signal VIB is "0", and the output of the selector 1006 is forced to always be (00) ₁₆ . Then, the shift data of shifter 1003 will always be (000) ₂ . As a result, the output data of shifter 1003 becomes (00) ₁₆ . That is, the vibrato data CVD is always (00) ₁₆ . Vibrato on Vibrato on/off signal VIB is “1”
When DVIB is "0", the vibrato is on. Address data stored in register 1002 is supplied to gate 1007 and shifter 1003 via gate 1006. Note that the upper three bits of the address data, that is, the shift data, are forcibly set to (111) ₂ . Then gate 100
The output of the vibrato ROM 1001 (vibrato data CVD) is supplied as is to the input No. 4. Delay vibrato When the vibrato on/off signal VIB and the delay vibrato on/off signal DVIB are "1", a delay vibrato state is entered. When all of the eight channel key-on/off signals KD are turned off and any one of the key-on/off signals KD is turned on, the gate 1006 is controlled to set the address data to (000) ₁₆ . Then, in the shifter 1003, the amplitude control (0,
CVD/64, CVD/32, CVD/16, CVD/8,
CVD/4, CVD/2, CVD) are performed. Then, when the shift data becomes (111) ₂ , the shift vibrato is forcibly set to (111) ₂ , similar to the vibrato on state. The explanations of the symbols listed in Table 9 are as follows. AL sends the data supplied to the FA bus to the signal φ2
Something that latches at the edge of the rising edge. BL latches the vibrato supplied to the FB bus at the rising edge of signal φ2. CRAL is a command to clear latch AL with signal φ2 being “1”. ADD1 is “1” for the carry input of FA909
An instruction to add. TCA uses the results of calculation processing with FA909 as FA
Instructions to feed the bus. RDCPD is a command to supply the center pitch data CPD generated by the CPD generation unit 901 to the FA bus. RDCPCD is pitch control gate 90
A command to open gate 2 and supply pitch control data CPCD to the FB bus. RDCVD is a command to supply vibrato data CVD generated by the vibrato signal generation section 903 to the FB bus. RDCGD is a command for supplying glide data CGD generated by the glide signal generator 904 to the FB bus. RDEXP was converted in the index converter 905
Instruction to supply EXP (CPD) to the FA bus. RDΔEXP is a command to supply ΔEXP (CPD) converted in the index converter 905 to the FB bus. RDFD is a command to read the old frequency data OFD from the comparison register section 305 and supply it to the FB bus. RDVAD is an instruction for supplying the contents of the vibrato address register 1002 in the vibrato signal generating section 903 to the FB bus. RDGAD is a command for supplying glide address data from the glide signal generation unit 904 to the FB bus. WRVAD is an instruction to write the result calculated by the FA 909 to the vibrato address register 1002 in the vibrato signal generating section 903 at the rising edge of the signal φ2. WRGAD is an instruction to write the result calculated by the FA 909 to the glide signal generating section 904 at the rising edge of the signal φ2. WREXP is an instruction to write the result calculated by the FA 909 to the exponent converter 905 at the rising edge of the signal φ2. WRFD is an instruction to write the result calculated by the FA909 into the comparison register section 305 at the rising edge of the signal φ2. Note that 11 in the sequencer 302 shown in FIG.
The state 11 occurring in advance counter 402 corresponds to instruction steps 1-11 shown in Table 9. Vibrato address increment processing Latch the address data stored in the vibrato address register 1002 in instruction step 1.
Write to BL908. Then, in instruction step 2, +1 is added to the vibrato address data VAD, and the addition result is sent back to the vibrato address register 100.

【table】

Store in [Table]. Effects of the Invention As explained above, the vibrato adding device of the present invention changes the vibrato frequency by changing the read address length of the vibrato data memory and selecting the vibrato data memory corresponding to the address length. Therefore, a vibrato waveform of any frequency and any shape can be selected with a simple configuration.

[Brief explanation of drawings]

Figure 1 is a block diagram of an electronic musical instrument that employs the vibrato adding device of the present invention, and Figure 2 is a block diagram of the CPU 103.
3 is a block diagram of the musical tone generating section 107, FIG. 4 is a block diagram of a specific example of the sequencer 302, and FIG. 5 is the operation of the sequencer 302. Time chart diagram; FIG. 6 is a configuration diagram of a specific example of the analog buffer memory unit 312; FIG. 7 is an internal operation time chart diagram of the musical tone generating unit 107; and FIG. 8 is a diagram showing the supply from the FDP 306 to the comparison register unit 305 Frequency data transition diagram, Figure 9 is FDP30
FIG. 10 is a block diagram showing a specific example of the vibrato signal generating section 903; FIG.
The figure is a data map diagram of the vibrato ROM, No. 12.
The figure shows an example of vibrato data, and FIG. 13 shows an example of vibrato data corresponding to vibrato speed. 101...Keyboard section, 602...Operation section, 103
... Central processing unit, 104 ... RAM, 105 ...
...ROM, 106...Musical tone synthesis data ROM, 1
07...Musical tone generator, 301...Main oscillator, 30
2... Sequencer, 303... Input register section,
304...Timer, 305...Comparison register section, 306...Frequency data processor, 307
... Waveform data processor, 308 ... Data read processor, 309 ... Read pulse forming section, 310 ... Calculation request flag generation section, 311 ...
...DAC, 312...Analog buffer memory section,
313... Integrator, 901... CPD generation section, 9
02... Pitch control data gate, 90
3...Vibrato signal generation section, 904...Glide signal generation section, 905...Exponent converter, 906...
...Arithmetic unit, 1001...Vibrato ROM, 10
06...Selector.

Claims (1)

[Claims] 1. A plurality of vibrato data memories that store a plurality of types of frequency modulation data, an address generation section that generates addresses for the vibrato data memories, and a device for selecting one vibrato data memory from the plurality of vibrato data memories. a vibrato data select section, a note clock generator for frequency modulating a musical tone signal using the output data of the vibrato data memory, and an address length control section for controlling the address length of the address generation section; By controlling the generated address length and selecting a vibrato data memory corresponding to the address length using the vibrato data select section, a vibrato waveform of an arbitrary frequency and an arbitrary shape can be generated. A vibrato adding device characterized by: