JPS5865494A - Multi-waveform generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument, and provides a digitized musical tone generation system particularly suitable for large-scale integrated circuits (hereinafter referred to as LSI).

Up to now, many attempts have been made to digitize the sound source circuits of electronic musical instruments, but in all of them, complex waves containing many harmonics are stored in read-only memory (hereinafter referred to as ROM).
After obtaining a musical sound waveform by reading out waveform information from a read/write memory (hereinafter referred to as RAM) at a predetermined clock, a predetermined envelope was added to this using digital or analog means to generate a musical tone signal. .

In this case, there are several problems.

First of all, there is the problem of waveform calculation. To change the timbre, the waveform of the complex wave is changed, but the timbre information is
For example, the drawbars most commonly used in electronic musical instruments have a level of 6 feet (fundamental wave), a level of 4 feet (
2nd harmonic) level, 22/3% foot (3rd harmonic) level, etc. When the proportion of each harmonic is given, from this timbre information, the corresponding composite form is We need to create a waveform of In other words, it is necessary to perform an inverse Fourier calculation. Although microcomputers have recently become available at low cost, this inverse Fourier calculation still requires a time of several hundred milliseconds to about one second. Moreover, each time the performer changes the drawbars or switches the tone tablet, an inverse Fourier calculation is performed, so if the calculation takes time, the tone may not change immediately or there may be no sound for a while. . This is not suitable for playing songs that require frequent tone changes.

The second problem is that the timbre does not change from the time the sound begins until the sound disappears.

In other words, if waveform information is obtained by performing inverse Fourier calculations from the timbre information, it is written into memory, and
Since the waveform information in the memory is read out repeatedly at a predetermined clock, the waveform is always constant. Even if you add a predetermined envelope to this, the tone will not change after all. In order to change the tone from time to time, you can rewrite the waveform in the memory from time to time, but the memory itself is constantly being read, so to rewrite the contents of the memory, aim at the timing of reading ( Writes must be performed in synchronization with read cycles. This readout clock is not always constant because it changes depending on the pitch that is generated.
Rewriting the waveform is also quite troublesome in terms of hardware. Moreover, as mentioned earlier, changing the tone requires inverse Fourier calculations to obtain waveform information from the tone information each time, which means that inverse Fourier calculations are performed at high speed every moment. From this point as well, it can be understood that it is extremely difficult to change the timbre from time to time.

The third problem is the problem of the system clock of the entire hardware. Digital circuits are usually configured to operate based on a fixed clock to facilitate synchronization of the entire system. This clarifies the timing between logic circuits and helps simplify the hardware configuration. On the other hand, in the sound source circuit of an electronic musical instrument, 12 different clocks are provided in order to obtain musical tone signals for each note name of C, C#, D...B.
Changing the read speed. For example, C1, C2,
If you just want to change the octave like C3..., you can change the C note clock to 1/2, 1/4, 1/3... or skip two memory addresses, four memory addresses, etc.
It would be fine to read 8 increments, but the clock of C♯ note is 21/21 compared to the clock of C note.
The clock must be slightly faster than 12 times.

Similarly, in the case of a D note, 21/1 of the clock of the C note
2x, 21/12x for D# notes... These 21/12, 22/12, 23/12...
are all irrational numbers, so in order to generate these 12 clocks using hardware, it is necessary to use independent clocks.
Two clock generators will be provided. The problem here is that the speeds of the 12 clocks are completely independent, so they cannot be synchronized and it is impossible to share hardware. A conversion circuit (hereinafter referred to as a D/A conversion circuit) is required, and the hardware becomes excessively large-scale and the system configuration becomes complicated.

The fourth problem is that it is difficult to generate a waveform with an arbitrary frequency. That is, as devices for generating a sine wave or the like at an arbitrary frequency, JP-A-47-9167 "Frequency Synthesizer", JP-A-48-52454 "Digital Frequency Synthesizer", JP-A-50-140243 ``Frequency synthesizer'' and Japanese Patent Publication No. 52-31731 ``Tonic sound waveform generator'' are known, but both require a large amount of memory to generate an arbitrary frequency, or are truly arbitrary. It was difficult to generate this frequency.

The present invention solves the above-mentioned problems and provides a digital waveform generator that can be easily integrated into an LSI as a sound source circuit for an electronic musical instrument.

First, the present invention will be explained in detail. FIG. 1 is a waveform diagram when the present invention is applied to generating a sine waveform.

In FIG. 1, the solid line indicates an ideal sine wave. One period of this sine wave is divided into N parts. Here N is a positive integer L
and M. Next, the point where one period is divided into L is x0,
Let x1, x2..., xi,...xL-1. There are M points in each L-divided section. Counting those division points from xi, 0, 1, ..., j, ..., (M-1)
It is numbered and expressed as xij. In this way,
All N points within one period can be expressed as xij. Here, i=0, 1, 2,..., L-1 and j=0, 1, 2,..., M-1. Therefore, the above xi is expressed as xi0.

Also, since one period is 2π, the phase of point xij is θ=i
j=2π/N×(Mi+j) (1).

When expressed as a sine wave f(xij), f(xij
)=A sin {2π/N(Mi+j)} (2). Here, A represents the amplitude of the sine wave.

In the present invention, to represent f(xij), all of xij,
In other words, it does not have N sample values, but has L sample values xi0, and the remaining (NL) xij (j≠
Regarding point 0), an attempt is made to find an approximate value by interpolation.

When linear interpolation is performed as an interpolation calculation, f(xi+1
,0) and f(xi,0), f∧(xij)={f(xi+1,0)−f(xi,0
)}j/M+f(xi, 0), the interpolated value f∧(xij)
fxij) can be approximated by

f∧(xij)=A{sin2π/L(i+1)−si
n2π/Li}j/M+A sin2π/Li (3) In the case of a sine wave, it can be expressed as.

In the following explanation, L=2048 and M=128 will be described. Therefore, N=262144.

Further, i can be expressed with 11 bits and j with 7 bits (ij) can be expressed with an 18-pit binary number.

FIG. 2 is a block diagram of one embodiment of the present invention.

In Figure 2, 1 is the waveform address register (AREG)
2 is a differential address register (JREG). The waveform address register 1 and the differential address register 2 each have 72 read/write memories each having 18 bits per word. 3 is a 72-decimal slot counter, and the above 72
One of the sets can be selected. Clock φ0
As a result, the slot counter 3 increments and sequentially selects the 72 sets of registers, and the selection is repeated.

The clock φ1 is a read signal RD, and the contents are read from a set of registers selected by the slot counter 3 and output. φ2 is a write signal WR, and A of the set of registers selected by the slot counter 3
Write a new address value to REG. The full adder 4 inputs the outputs of the waveform address register 1 and the differential address register 2, adds the two, and outputs the sum to the waveform address register 1. The above is the address calculation section.

From the above explanation, the address calculation unit calculates the difference address Dp(nT) to the waveform address WAp(nT) at time nT.
It can be seen that WAp(nT+T) is calculated by adding . That is, WAp(nT+T)=WAp(nT)+Dp(nT)...
Perform the calculation in (4). Here, T is the sampling period, and n is the accumulation of 72 registers during the sampling period T. p represents the number of 72 sets of registers from 0 to 71. Therefore, the sampling period T is 72 times the period TC of the clock φ1. In other words, when clock φ1 is applied 72 times, the calculation of formula 4 is executed 72 times from p=O to 71,
Dp(
nT) has been added and renewed.

One set of clocks φ0, φ1, and φ2 constitutes one time slot. There will now be 72 time slots. Any timeslot can be denoted by p.

The 18-bit output of the waveform address register is supplied to a waveform memory and a waveform calculation circuit. The waveform memories include a first waveform memory (ROM1) 5 and a second waveform memory (ROM1).
2) 6.

ROM2 is f (xi, 0) = Asin (2π/N x Mi) = Asi
n(2π/Ni)...(5) (i=0, 1, 2,..., i,...L-1) is stored. i is expressed as an 11-bit binary number, and 2048 sample values are stored. ROM1 is f(xi+1,0)-f(xi,0) =A{sin-2π/L(i+1)-sin2π/Li
}...(6) (i=0, 1, 2,..., i, L-1) is stored. ROM2 also stores 2048 sample values.

The output of ROM1 is supplied to one input of multiplier (MPY) 7. A partial address j of the waveform address is supplied to the other input. The output of multiplier 7 is divided by divider 8
is divided by a constant number M. therefore,
The output of the divider 8 is {f(xi+1,0)−f(xi,
0)}j/M=A{sin2π/L(i+1)−sin
2π/Li}j/M (7) is output. This output is added to the output of ROM2 by the full adder 9, and f∧(xij)=A{sin2π/L(i+1)−si
n2π/Li}j/M+A sin2π/Li (8) is obtained. This value approximates the sine wave in FIG. 1 with a broken line.

From the above explanation, it has become clear that an arbitrary waveform f(xij), for example a sine wave, can be generated by linear interpolation. In interpolation, the values of L and M can be any value, and therefore the value of N can also be any value, but in reality, since circuits based on base numbers are often used, it is preferable to use this exponent. is preferred. As an example, set L to 2048
, M is 128. At this time, i is expressed as an 11-bit binary number, j is expressed as a 7-bit binary number, and (i
j), that is, (Mi+j), is expressed as an 18-bit binary number. The lower 7 pits of (Mi+j) directly represent j, and the upper 11 pits represent i. Therefore, among the waveform addresses, waveform memory ROM1
and waveform memory address i which is the address of ROM2,
This means that the partial address j corresponding to the interpolation position is naturally separated. This is very advantageous in that a complicated device for separating waveform memory addresses and partial addresses from waveform addresses is not required. Furthermore, the divider 8 only needs to shift 7 bits, which is advantageous in this respect as well.

FIG. 3 is a block diagram of the main parts of another embodiment of the present invention in which the multiplier and divider, which are part of the waveform calculation device, are replaced with a readout memory (ROM 3) 10.

The ROM1 stores the difference between the original waveforms, but if L is set sufficiently large, the difference becomes small. Naturally, the value of M also becomes smaller. For example, if the waveform sample in ROM2 is expressed in 12 bits, A can be 2047. At this time, the difference is {(xi+1,0)-f(xi,0)
} can be represented by 4 bits including the sign. On the other hand, j is 7 bits. Therefore, the number of combinations of inputs may be (4+7) bits=2048. R.O.
If the output of M3, {f(xi+1,0)-f(xi,0)}j/M, is expressed with 4-bit precision, a ROM of 2048×4=8192 bits is sufficient. A ROM of this level can be realized more easily than when both a multiplier and a divider are provided.

FIG. 4 shows that the waveform address (Mi+j) is divided into a waveform memory address and a partial address, and each ROM1, 2, 3
This is an example of the bit length at each stage when the input address becomes the input address of the full adder 9 and finally becomes the two inputs of the full adder 9.

Figure 5 shows a total of four data latches (D-La +
It has a so-called pipeline configuration in which channels 1 to 4 are provided and data is sequentially shifted using a clock φ0. In the configurations shown in FIGS. 2 and 3, there is only a period of time TC from when the waveform address is generated until the waveform sample f∧(xij) is obtained. therefore,
The operation delay time of each ROM 5, 6, multiplier 7, divider 8, and full adder 9 is strictly limited. On the other hand, in the embodiment shown in FIG. 6, each of ROMs 1 and 2, ROM 3, and full adder 9 only needs to operate within the period TC.
There is no need for high-speed logic circuits, which is advantageous.

This concludes the explanation of the configuration for generating the arbitrary waveform f(xij), and next, the setting of the frequency of the waveform generated by the above configuration will be explained.

In FIG. 2, it has been stated that the waveform address follows equation (4). In equation (4), when Dp(nT)=1, the waveform address WAp(nT) increases by 1. Therefore, in the case of the sine wave shown in FIG. 1, one waveform is generated in N sample periods.

When Dp(nT)=2, two waves are generated at N sample periods. Generally, when Dp(nT)=1, one wave is generated every N sample period. Therefore, the frequency F(J) of the generated sine wave is F(J)=J/N
It is represented by T. T is sample synchronization. N=218T
= 28 μS, F(J) = 0.1362392J (Hz). The possible range of J is 0 to 218-1. J=0
Then you will get the same sample value.

This is, in other words, direct current. If J=216,
Four samples can be read out in one waveform, and the frequency at that time is 8928 Hz. If J=217,
It becomes 17.857kHz. In this case, this is the limit of Nyquist's definition.

In the above explanation, the differential address Dp(nT) is a constant value D
The explanation has been made assuming that Dp is stored in the differential address register 2 in advance.

Next, a method for rewriting Dp will be explained.

In FIG. 2, 100 is a memory that prepares and stores new data when updating the contents of the waveform address register 1 and the differential address register 2. Update data is written into the read/write memory 100 by the microcomputer 200 asynchronously, that is, at relatively free timing without being constrained by the timing of waveform generation.

Then, in a predetermined time slot p of the 72 time slots, the update data is transferred to the waveform address register 1 and the difference address register 2. An example of a portion related to this transfer is shown in FIG.

In FIG. 6, 1 is a waveform address register, 2 is a differential address register, and 3 is a slot counter. These are similar to those described in FIG. Note that the output of the full adder 4 is supplied to the DI terminal of the waveform address register 1. Reference numeral 22 denotes an address buffer register for temporarily storing new updated differential addresses, and is provided with 72 sets corresponding to the number of time slots p. The selector 20 receives an address signal output from the slot counter 3 and a clock φ1 (read signal RD1) in response to an update signal RNW, which will be described later.
and the address signal and write signal WR2 output by the microcomputer 200 are selected and supplied to the address buffer register 22. When the update signal RNW is "0", the set on the microcomputer side is selected.

The clock φ0 counts up the slot counter 3, supplies a new time slot address to the waveform address register and the differential address register 2, and designates a predetermined time slot. Next, clock φ1 is generated, and 2
Data is read from the two address registers 1 and 2 and supplied to the full adder 4. Next, clock φ2 is generated,
At the same time slot address, write the output of full adder 4 to the waveform address register. At this time, since the update signal RNW is "0", WR1 is blocked by the AND gate 25, and the differential address Dp=J maintains the same value. In this state, a sine wave determined by Dp=J continues to be generated.

The microcomputer 200 controls the buffer register 21
and 22 predetermined time slots, and at the same time, the update differential addresses Dp(oT) are sequentially outputted and written by the write signal WR2. When changing to a new frequency for all time slots, Dp(oT) is applied to all addresses of the buffer register 22.
Write (p=0, 1, 2, ..., 71). After that, the microcomputer 200 outputs a SET signal to the update control circuit 24. A SLOT0 signal which becomes "1" when slot p=0 is added from the slot counter 3. After the SET signal is output, the update signal RN is generated at the same time as the clock φ0 indicating the first time slot p=0.
W becomes “1” for 72 time slots, and becomes “0” at the same time as clock φ0 indicating the next time slot p=0.
” Return to

When the update signal RNW becomes “1”, the buffer register 2
2 is accessed by slot counter 3 and R
The update waveform address Dp(oT) of the buffer register 22, which is brought into the read state by D1, is written into the memory 72 of the differential address register 2 one after another. Then, the writing is completed and the update signal RNW becomes "0". Thereafter, a new Dp(oT) is read from the differential address register 2 by φ1, and new data begins to be supplied to the full adder 4. Then, the frequency is changed to the new frequency from the next sample.

A time chart showing the operation of FIG. 6 is shown in FIG. 7, and a specific configuration of the update control circuit shown in FIG. 6 and its time chart are shown in FIGS. 8a and 8b.

In the embodiment of FIG. 6, since the waveform address WAp(nT) is not updated, the phase of the waveform of the new frequency is determined by the instantaneous phase of the waveform of the previous frequency.

Furthermore, even when changing to a new frequency, a new waveform is generated smoothly by connecting to the previous waveform, which is convenient when applying modulation such as vibrato or portamento.

If you want to start from a predetermined phase when changing the frequency,
synchronously when a given time slot p is selected,
All you have to do is set the contents of the waveform address register to that phase value.

FIG. 9 is a block diagram of an embodiment showing another method of updating WAp(nT) and Dp(nT). The different parts from FIG. 6 will be explained. 30 is a slot latch that specifies a time slot; 32 is a waveform address latch; 34
are differential address latches, each of which has a data input terminal connected to a data bus of the microcomputer 200, and a write terminal to which a write signal WR is applied. Address signal AD of microcomputer 200 is decoded via address decoders 31, 32, and 33, and selects slot latch 30, waveform address latch 33, and differential address latch 34. In this state, slot data p and waveform address data WAp(oT) are transferred from the data bus to differential address data Dp.
By supplying (oT) and applying a write signal WR, each data can be written to the latch.

A comparator 36 outputs a match signal "1" when the outputs of the slot counter 3 and the slot latch 30 match. 37 is an update control circuit that outputs an update signal RNW based on the coincidence signal and the SET signal output from the microcomputer 200;

A data selector 38 selects either the output of the full adder 4 or the output of the waveform address latch 32 and supplies it to the waveform address register. Update signal RNW is “1”
”, the output of the waveform address latch 32 is selected.

When the SET signal is "0", the update signal RNW is "0", and normal waveform generation is performed.

This is similar to what was explained in FIG. As mentioned above, the microcomputer 200 stores the slot data p,
When the SET signal is output after latching the waveform address data WAp(oT) and the differential address data Dp(oT), as shown in the time chart of FIG.
When the first match signal is output after the T signal is output, the update signal RNW becomes "1". At this time, instead of the output of the full adder 4, new waveform address data WAp(oT
) is written, and new differential address data Dp(oT) is written to the pth memory of the differential address register 2. Writing is completed and the slot counter is
When the value changes from p to p+1, the update control circuit 37 outputs an END signal, and the update signal RNW returns to "0". Therefore, the waveform generator generates a waveform for the next slot. Then, at the next slot p, waveform generation of a new differential address, that is, frequency, starts from a new waveform address.

The method shown in FIG. 9 has the advantage that when changing to a new frequency, it can start from a new waveform address, so the phase of the waveform can be set freely. However, when rewriting a certain slot p, at least the clock period TC is required.
Since it takes several times more time, all slots p = 0 ~
It takes 1 to 2 mS to change the frequency of 71.

FIG. 10 shows an example of the update control circuit 37 shown in FIG. Further, a time chart of each part in FIGS. 9 and 10 is shown in FIG. 11. Figure 9, Figure 10, Figure 11
The END signal shown in the figure is used as an interrupt signal to notify the microcomputer 200 that writing has ended.

When the microcomputer 200 receives the END signal,
After that, the microcomputer 200 may write the next data into the slot latch 30, waveform address latch 32, and differential address latch 34.

In addition, in the embodiments shown in FIGS. 5 and 9, each clock period T
Although it is difficult to change the differential address for each C, the updating circuit portion may be changed to update the differential address at high speed.

Furthermore, if the ROM1 and ROM2 in FIG. 2 are replaced by read/write memories and the contents thereof can be rewritten, it becomes possible to generate not only a sine wave but also a plurality of waveforms. In Figure 3, ROM1, ROM2, ROM
3 can be replaced with read/write memory.

In the above explanation, the slot counter 3 is set to 72.
Since it is a sine wave having 72 independent frequencies and phases, it is possible to generate sine waves with 72 independent frequencies and phases by time division multiplexing, but it goes without saying that more than 72 sine waves may be generated.

Next, a method for reducing the memory capacity of sine waves will be explained.

FIG. 12 is an example of waveforms of sine wave samples for i=0 to L/4. ROM2 has Asin2π/NMi i=0, 1, 2, ..., L/4 as indicated by the black circle.
ROM1 has A{sin2π/N(Mi+M)-sin2π/NMi as shown in the white circle.
}i=0, 1, 2, ..., L/4 is stored. FIG. 13 shows a waveform address calculation circuit that reads a complete sine wave from such ROM1 and ROM2. In FIG. 13, 4 is the waveform address WAp (
This is a full adder that adds the differential address Dp(nT) and the differential address Dp(nT). Its output represents WAp(nT+T) and the second
Return to the core deformation address register shown in the figure. D0~D
Of the 17 18-bit outputs, 7 bits D0 to D6 are partial addresses, and 11 bits D7 to D17 are waveform memory addresses, of which D17 represents the positive and negative sides of a sine wave. D16 is the odd quadrant and even quadrant of the sine wave, in other words, the phases 0~π/2, π~3π/2 and π/2~
π, represents the distinction between 3π/2 and 2π. D7 to D16 are i
It becomes a 9-bit code representing =1 to (L/4-1). D0 to D15 are added to the selector 41 and complementer 4
It is converted into a two's complement number by 0 and is added to the selector 41. The selector 41 selects (DO to D15) when D16 is "0", that is, in an odd quadrant. When D16 is "1", that is, in an even quadrant, the outputs of complementers 40 and 42 are selected. Therefore, the selector 41 generates the value of i in a reciprocating manner from 0 to L/4 to 0 in FIG. 12. D1
6 is also applied to the MSB of ROM1 and ROM2, i=L
Used when reading /4.

Since D17 corresponds to the sign of the sine wave, it is used as it is as a sign bit.

By doing the above, the difference values stored in the ROM 1 will be only positive values, so the sign bit will not be necessary. Further, since only positive values are input to the full adder 47, an adder may be used instead of an adder/subtractor. Furthermore, since the number of waveform addresses is reduced from N to about 1/4, the memory capacity is also reduced to about 1/4.

In the above description, an example of linear interpolation calculation has been described, but it goes without saying that interpolation using a quadratic curve or interpolation calculation using other functions may also be performed.

Also, in the above explanation, the focus was on sine waves.

It is also possible to store and generate any waveform other than a sine wave in the ROMs 1, 2, and 3.

As described above, the present invention includes a waveform memory, a waveform calculation circuit, and a waveform address calculation circuit, and the waveform address calculation circuit uses a waveform memory address indicating the address of the waveform memory and a virtual address other than the address of the waveform memory. The address is time-division multiplexed, the waveform memory is time-division multiplexed and read out using the waveform memory address, the output is added to the waveform calculation circuit along with the virtual address, and the waveform output is time-division multiplexed and calculated. Therefore, it is possible to generate waveforms with high frequency variable accuracy using a small-scale waveform memory, similar to when a waveform memory having large-scale addresses is used.

In addition to the waveform memory, waveform calculation circuit, and waveform address calculation circuit, multiple waveform address registers and differential address registers that support time division multiplexing are provided. The waveform addresses are sequentially computed by accumulating the difference addresses, which are stored in the waveform address register, and the waveform memory is accessed using the waveform memory address included in the waveform address to read out the waveform sample. The waveform calculation circuit performs interpolation calculations between the waveform samples based on the partial addressed waveform samples included in the waveform address, so by providing 72 or more sets of waveform address registers and differential address registers, a large number of sine waves can be generated by time division multiplexing, and the efficiency of using the waveform memory and waveform calculation circuit can be increased. Moreover, the frequency can be selected arbitrarily, and its change over time is also possible.

Therefore, if 72 sets are used for one musical tone, up to 72 harmonics can be produced, and if used for a compound instrument, for example, 8 tones with harmonics up to the 9th order can be created at the same time.
An extremely flexible waveform generator can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the waveform generation principle of the waveform generator of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram of main parts of another embodiment of the present invention, and FIG.
6 is a block diagram showing the relationship between digital codes of the present invention, FIG. 6 is a block diagram of the third embodiment of the present invention, FIG. 6 is a block diagram showing the main parts of the embodiment of FIG. 4 of the present invention, FIG. 7 is a time chart of the embodiment shown in FIG. 6, and FIGS. 8(a) and (b)
9 is a block diagram showing a main part of the sixth embodiment of the present invention, and FIG. 10 is a diagram showing an embodiment of the update control circuit. , FIG. 11 is a time chart thereof, FIG. 12 is a diagram showing sine wave samples in the waveform memory, and FIG. 13 is a diagram of another embodiment of the waveform address calculation circuit. 1...Waveform address register, 2...Difference address register, 3...Slot counter, 4...Full adder, 5...Memory (for difference value) 5...Memory (for waveform),
7... Multiplier, 8... Divider, 9... Full adder. Name of agent: Patent attorney Toshio Nakao and 1 other person ms@Ki'7! It IEf, ←−−−−−−−− 5ttfro uuuuuuuuuuuuuuuuuuuuuuu
"-1--------]----itm-one-one

Claims (8)

[Claims] (1) A waveform memory, a waveform calculation circuit, and a waveform address calculation circuit are provided, and the waveform address calculation circuit calculates a waveform memory address indicating the address of the waveform memory and a virtual address other than the address of the waveform memory. The waveform memory is time-division multiplexed and read out using the waveform memo address, the output thereof is added to the waveform calculation circuit together with the virtual address, and the waveform output is time-division multiplexed and calculated. A multiplex waveform generator characterized by: (2) A waveform memory, a waveform arithmetic circuit, a waveform address calculation circuit, and a plurality of waveform address registers and difference address registers compatible with time division multiplexing are provided, and the waveform address stored in the waveform address register is updated by the difference address. The difference addresses stored in the address register are accumulated to sequentially calculate the waveform address, the calculation result is stored in the waveform address register, and the waveform memory is accessed using the waveform memory address included in the waveform address. A multiplexed waveform generating device, wherein the waveform sample is read out, and the waveform arithmetic circuit performs an interpolation operation between the upper waveform samples based on the partial address included in the waveform address and the waveform sample. (3) The multiple waveform generation device as set forth in claim 2, characterized in that the waveform calculation circuit performs a linear interpolation calculation between the waveform samples stored in the waveform memory. (4) In the description of claim 2, the waveform memory is composed of a first waveform memory and a second waveform memory,
A multiple waveform generation device characterized in that a second waveform memory stores sample values of a waveform to be generated, and a first waveform memory stores a difference value between the waveform sample values. (5) In the statement of claim 2, the difference value in the first waveform memory is multiplied by a coefficient corresponding to the partial address, and the product is added to the waveform sample value in the second waveform memory to perform interpolation. A multiplex waveform generator characterized in that it performs a performance. (6) In the description of claim 5, a circuit that multiplies the difference value of the first waveform memory by a coefficient corresponding to a partial address receives the difference value and the partial address as input, and inputs the difference value and the partial address. A multiplex waveform generator characterized by using a storage device that outputs multiplied products. (7) In the statement of claim 4 or 5, the first memory stores the difference value of the positive strong wave sample, and the second waveform memory stores the sample value of the sine wave. A multiplex waveform generator characterized by: (8) The multiplex waveform generator as set forth in claim 4, wherein the first and second waveform memories are read/write memories and are configured to generate waveforms other than sine waves.