JPH0225515B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sine wave generator that generates a sine wave.

Conventional sine wave generators that generate sine waves are
It is used in various technical fields; for example, in the field of electronic musical instruments, there is a sine wave synthesis method. For example, in such an electronic musical instrument using a sine wave synthesis method, amplitude value data of one cycle of sine waves is
It is stored in ROM (read-only memory) in advance, and when creating a musical tone, the ROM is addressed according to the frequency information (scale information) input from the keyboard etc., and thereby the sine wave and harmonic of the corresponding frequency are stored. A sine wave is read from the ROM, and a musical tone is created and emitted.

By the way, in conventional sine wave generators of this type, in order to generate good sine waves, the ROM is required.
As a result, it is necessary to store amplitude value data for many sample points, which increases the storage capacity of the ROM and increases costs.
If the storage capacity of the ROM is made small, there is a problem that good sine waves cannot be generated.

This invention was made against the background of the above-mentioned circumstances, and its purpose is to collect 1/4 period sine wave data, specifically, the amplitude value data of each sample point and the difference value between each sample point. data is stored in a waveform memory, and read out by addressing this waveform memory. From the 1/4 cycle sine wave data,
It is an object of the present invention to provide a sine wave generating device which also performs interpolation processing to create a sine wave for one cycle, thereby solving the problems of the conventional art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to an electronic musical instrument that reads sine waves according to scale frequencies and generates musical tones will be described below with reference to the drawings. FIG. 1 is a diagram showing the main circuit configuration of this embodiment.
is a keyboard with multiple performance keys. The keyboard 1 generates key codes corresponding to the operated performance keys. For example, this key code is a code indicating the octave and note (scale) of the performance key.

And this key code is frequency information conversion
Supplied to ROM2. This frequency information conversion
The ROM2 stores frequency information (that is, information indicating the phase angle) corresponding to the key code.
This frequency information is stored in the accumulator 3 with an accumulation command of 0.
(Clock 0 will be explained later).

For example, 12-bit data is supplied from the accumulator 3 to the A input terminals A ₀ -A ₁₁ of the adder 4. Note that the most significant bit of the above 12-bit data is a sign bit, and the exclusive OR gate 6 ₁₂
The signal is input to the A input terminal _A11 of the adder 4 via the adder 4.

On the other hand, 12-bit data from the envelope information generating circuit 5 is supplied to the B input terminals B ₀ -B ₁₁ of the adder 4 via exclusive OR gates 6 ₀ -6 ₁₁ . Also, the carry input terminal cin of this adder 4
is supplied with clock 0.

The envelope information generating circuit 5 is supplied with envelope control commands, such as on/off information of performance keys on the keyboard 1, or ADSR (Attack Decay Sustain Release) information set in advance by a switch, etc. According to the information, 12-bit data for envelope control is given to the exclusive OR gates ₆₀ to ₆₁₁ . Furthermore, this exclusive or gate 6 ₀ ~
A clock 0 is applied to one end of each of the exclusive OR gate ₆₁₁ and the exclusive OR gate ₆₁₂ .

Therefore, when this clock 0 is at the "0" level, the adder 4 adds the 12-bit data given from the A input terminal and the B input terminal, and adds the 12-bit data from the S output terminals _S0 to _S11 . Output the resulting data as data. On the other hand, when the clock 0 is at the "1" level, the adder 4 receives 12-bit data provided from the A input terminal by inverting only the level of the sign bit, and 12-bit data provided from the B input terminal. Inverts the level of each bit of the 12-bit data and adds "+1" to that value, that is, data obtained by inverting the sign of the data given from the B input terminal (two's complement representation). , S output terminals output the resulting data as 12-bit data.

The above 12-bit data output from the adder 4 is given to the sine wave section 7, which converts the peak value (amplitude value) of the sine wave into 11-bit data.
Output as D ₀ to D ₁₀ . The specific configuration of this sine wave section 7 is shown in FIGS. 2 to 5.
This will be described later with reference to the drawings.

The 11-bit data output from the sine wave section 7 is supplied to the A input terminals _A0 to _A10 of the accumulator 8, and the most significant bit (sign bit) is also supplied to the carry input terminal Cin for accumulation. calculated. Incidentally, the accumulator 8 is reset at the timing of the rising edge of the signal obtained by inverting the clock 0 by the inverter 9, that is, the clock 0. From this accumulator 8, 12-bit data is sent to output terminals _SS0 to _S11.
is output from. That is, of this 12-bit data, the most significant bit _S11 is the sign bit, the second bit _S10 is the ^20th place bit, and the third to lowest bits _S4 to _S11 are the data below the decimal point. This is the bit shown.

The 12-bit data output from the accumulator 8 is read into the latch 10 at the rising edge of clock 0, and the output data is applied to the D/A converter, where it is converted into an analog signal and converted into an audio signal. The sound will be emitted via a conversion circuit.

Next, the specific configuration of the sine wave section 7 will be explained with reference to FIGS. 2 to 5. FIG. 2 is a detailed circuit diagram of this sine wave section 7. In the figure, 15 is
The ROM 15 stores the peak value (amplitude value) of a 1/4 period sine wave as shown in Figure 3 ^.
It is divided into (=64) sample points and stored.
That is, the 6-bit data output from the output terminals _{S4 to S9} of the adder 4 is input to the A input terminals A0 to _A5 of the ROM 15 via exclusive OR gates ₁₆₀ to ₁₆₅ , and the address It is specified. Furthermore, the output data from the S output terminal _S10 of the adder 4 is applied to the other ends of the exclusive OR gates ₁₆₀ to ₁₆₅ , respectively. Then, 4-bit difference value data (described later) and 10-bit peak value (amplitude value) data are sent from the ROM 15 to its D output terminals D ₀ to _{D 3} ,
This is what is read from _D4 to _D13 .

On the other hand, the 4-bit data from the S output terminals S ₀ to S ₃ of the adder 4 are sent to the exclusive OR gates 17 ₀ to 17 ₃
are supplied to the B input terminals B ₀ to _{B 3} of the multiplier 18 via. Then, the C input terminal of the multiplier 18
_C0 to _C3 are the D output terminals _D0 to _D3 of the ROM15.
The difference value data read from is supplied,
Thus, this multiplier 18 has respective input terminals B ₀ to _{B 3} ,
Multiply each 4-bit data from C ₀ to _{C 3} and send the upper 4-bit data to the E output terminal.
Output from E ₀ to E ₃ and F input terminal F ₀ of adder 19
~F is giving to ₃ . Note that the output data from the S output terminal _S10 of the adder 4 is applied to the other ends of the exclusive OR gates ₁₇₀ to ₁₇₃ .

Here, as shown in FIG. 3, the multiplier 18 is configured so that the data of the peak value of the sine wave for 1/4 period is stored in the ROM 15 at the above-mentioned 64 sample points. , as shown in Figure 4, n
This is a circuit for interpolating peak value data between the th sample point and the (n+1)th sample point using a linear interpolation method. That is, the C input terminal of the multiplier 18
C ₀ to _{C 3} contain the difference value data between the current n-th sample point's peak value data and the next n+1-th sample point's peak value data from the D output terminals D ₀ to _{D 3} of the ROM 15. It is output and supplied,
Therefore, the multiplier 18 uses this difference value data as the maximum interpolation value and outputs the maximum interpolation value to the B input terminals B ₀ -
With the address data from the S output terminals S ₀ to _{S 3} supplied to B ₃ , interpolated data of 16 sample points between the nth and n+1th sample points is obtained, and the upper 4 bits of the data are added. F of vessel 19
This is applied to input terminals F ₀ to F ₃ , respectively.

On the other hand, the G input terminals G ₀ to _{G 9} of the adder 19 have
Peak value data (data for the nth sample point) from the D output terminals D ₄ to _{D 13} of the ROM 15 is input, and as a result, the adder 19
Adding the interpolation value data supplied from the multiplier 18 to the peak value data of the th sample point, outputting the resulting data from the H output terminals _H0 to _H9 ,
The signals are output from D output terminals D ₀ to D ₉ via exclusive OR gates 20 ₀ to 20 ₉ .

Sign bit data output from the S output terminal _S11 of the adder 4 is input to the other ends of the exclusive OR gates ₂₀₀ to ₂₀₉ . Further, this sign bit data is output as it is from the D output terminal _D11 as sign bit data.

With the above configuration of the sine wave section 7, the sine wave can be
During the readout, the address data changes from "000000" to "1111111" to the A input terminals _A5 to _A0 of the ROM15.
"111111" → "000000", "000000" → "111111",
It is input by changing from "111111" to "000000". However, in the case of this embodiment, each sample point is not addressed consecutively, but intermittently,
To specify an address, dots such as "000000" or "111111" are not necessarily taken. In other words, from the minimum address "000000" to the maximum address "111111" will be input for two round trips, and as a result,
From the 1/4 period sine wave stored in the ROM 15 as shown in Fig. 3, the sine wave as shown in Fig. 5 is generated.
A sine wave for one period can be obtained, and, moreover,
This one-cycle sine wave is sent to the multiplier 18 described above.
By using an interpolation circuit using , the sine wave is even better than the 1/4 cycle sine wave shown in FIG. In addition, 2 shown in the sine wave in Figure 5
The bit data “00”, “01”, “10”, and “11” indicate the correspondence between the output contents of the S output terminals S ₁₁ and S ₁₀ of the adder 4 and each part of the obtained sign number. , when the data of the S output terminal _S11 that outputs the sign bit is "0", it indicates a positive peak value (0 to 1.0),
Moreover, when it is "1", it indicates a negative peak value (0 to -1.0). Furthermore, when the output of the S output terminal _S10 is "0", the address data "000000" → "111111" is input to the A input terminals _A5 to _A0 of the ROM15, and on the other hand, the output of "1" is input to the A input terminals A5 to A0 of the ROM15. Sometimes, the address data "111111" → "000000" is input. Furthermore, as shown in Figure 3, the ROM15
For the sine wave stored in , the peak value data for the maximum address data "111111" is not all "1" (D output terminals D ₄ to D ₁₃ of ROM 15), but rather than all "1". The data is considered to be somewhat small.

This is because the interpolated value data (data from output terminals D ₀ to _{D 5} ) is prevented from exceeding "1111". In other words, the sine wave is the address (input terminal
Given from _A5 to _A0 . ) changes from all 0 to "000001", the difference value is the largest, and this difference value data can be expressed as 4-bit data.

Next, the operation of this embodiment will be explained. First of all,
The above-mentioned clock 0 and its inverted clock 0 (accumulation command 0) will be explained with reference to FIG. These clocks 0 and 0 are clocks that alternately invert the "0" level and the "1" level as shown in FIGS. 6a and 6b. For convenience of explanation, the timing when the clock 0 is at the "0" level will be referred to as timing _t0 , and the time when the clock 0 is at the "1" level will be referred to as the timing _t1 .

Therefore, as shown in FIG. 6c, the circuit shown in FIG. 1 operates in a time-sharing manner at two timings. That is, the accumulator 3 is
Every time the accumulation command 0 becomes "1", frequency information corresponding to the performance key being operated is added, and the accumulation result data is applied to the adder 4.

In the adder 4, the data from the envelope information generation circuit 5 is directly supplied from the B input terminal at timing _t0 , and therefore, the data from the A input terminal and
Addition is performed. Furthermore, at timing _t1 , as described above, the data from the envelope information generating circuit 5 is supplied to the B input terminal with its sign inverted, and therefore, the adder 4 inputs this data and the A input terminal. The data from is added. This addition result data is then applied to the sine wave section 7.

Therefore, the sine wave section 7 is generally addressed differently at each of the two timings, timing t ₀ and timing t ₁ , so that at each timing, the data exposed from this sine wave section 7 is accumulated. It is accumulated by the unit 8.

The cumulative result is latched in latch 10 at the rising edge of clock 0.

Next, the operation of the sine wave section 7 will be explained. Address data is applied to this sine wave section 7 from the S output terminal of the adder 4. If the upper 2 bits S ₁₁ and S ₁₀ of that data are “0, 0”, then
The data output from the output terminals S ₉ to _{S 4} of the adder 4 is directly supplied to _the A input terminals A ₅ to _{A 0} of the ROM 15, and the difference value data (i.e., Sample points addressed by the contents of input terminals A ₀ to _{A 5} and +1 to the above contents.
The value of the difference between the peak value and the sample point addressed by the value obtained is output and sent to the multiplier 18, and the peak value of that sample point is output from the output terminals _D4 to _D13. It is output and sent to the adder 19. Furthermore, the data output from the output terminals S ₀ to _{S 3} of the adder 4 is directly applied to the multiplier 18 . Therefore, the adder 19 combines the peak value data supplied from the input terminals _G0 to _G9 with the actual difference value data (interpolated value data) supplied from the multiplier 18 to the input terminals _F3 to _F0 . are added and output as amplitude value data from output terminals _H0 to _H9 . The data is then directly applied to the input terminals A ₀ to _{A 10} of the accumulator 8. In this way, the phase angle is 0~
The sine wave unit 7 generates peak value data between π/2.

Next, a case where the upper two bits S ₁₁ and S ₁₀ of the address data given from the adder 4 are "0, 1" will be explained. In that case, the address data supplied from the output terminals S ₉ to _{S 0} to the sine wave section 7 is transmitted through the exclusive OR gates 16 ₅ to 16 ₀ , 17 ₃ to 1
The logic level is inverted at 7 ₀ , and each ROM1
5, will be supplied to the multiplier 18. As a result, the contents of the output terminals S ₉ to _{S 0} of the adder 4 are all 0.
While the actual address data changes from all 1s to all 0s, the phase angle changes from π/2 to π.
The adder 19 outputs the peak value of the sine wave of the part. The output thereof is then directly applied to the input terminals A ₀ to _{A 10} of the accumulator 8.

Furthermore, when the upper two bits S ₁₁ and S ₁₀ of the address data given from the adder 4 are "1, 0", the output terminals S ₀ to _{S 9} of the adder 4 are supplied to the sine wave section 7. Amplitude value data based on the address data is output from the adder 19,
The outputs H ₀ to H ₉ of the adder 19 are inverted in logic level by the exclusive OR gates 20 ₀ to 20 ₉ and sent to the accumulator 8. and,
At that time, the carry input terminal Cin of the accumulator 8 is
A “1” signal is given. In other words, exactly 0~
This means that the sine wave of the π/2 portion is output with its sign inverted, and the peak value of the sine wave with a phase angle of π to 3π/2 is obtained.

Similarly, when the upper two bits S ₁₁ and S ₁₀ of the address data given from the adder 4 are "1, 1", the sine wave section 7 is output from the output terminals S ₉ to _{S 0} of the adder 4.
The data fed into the exclusive or gate 16 ₅
~16 ₀ and 17 ₃ ~17 ₀ , the logic level is inverted and supplied to the ROM 15 and the multiplier 18. Therefore, the output terminal H ₉ of the adder 19 ~
The peak value data output from H ₀ has a phase angle of π/2π
It corresponds to the sine wave of the part. Then, the logic level of the data is inverted by the exclusive OR gates 20 ₉ to 20 ₀ and supplied to the accumulator 8.
Since a "1" signal is applied to the carry input terminal C _IN of the accumulator 8, it is converted into a negative value. Therefore,
This means that the peak value of the sine wave in the portion where the phase angle is 3π/2 to 2π has been obtained.

As mentioned above, this sine wave section 7
is operated in a time-division manner at timings t ₀ and t ₁ , and generally different addressing is performed at these timings t ₀ and t ₁ .

Now, if we express this using a mathematical formula, it becomes as follows. Now, let "a" be the data output from the accumulator 3, and "E" be the output data from the envelope information generation circuit 5. Then, at timing t ₀ , each data “a” and “E” are directly given to the input terminals A ₀ to A ₁₁ and B ₀ to B ₁₁ of the direct adder 4, so the output of the adder 4 is a+E and
Since the data is supplied to the sine wave section 7, the data input to the accumulator 8 and accumulated is sin2πa+E/2 ¹² = sin(a+E)π/2048...Equation
(1) becomes.

Furthermore, at timing _t1 , the most significant bit (sign bit) given from the accumulator 3 is inverted at the exclusive OR gate ₆₁₂ , and furthermore, the data E given from the envelope information generation circuit 15 is inverted at the exclusive OR gate 612. ₀ to 6 Inverted at ₁₁ and adder 4
In order to give a "1" signal to the carry input terminal cin of the adder 4, the data addressed and outputted by the output of the adder 4 and accumulated by the accumulator 8 is -sin2πa-E/2 ¹² =- sin(a-E)π/2048...
Equation (2) is obtained.

Therefore, the output of accumulator 8 is sin(a+E)π/2048−sin(a−E)π/2048 =2COSaπ／2048sinEπ／2048...Equation (3) becomes.

Therefore, the electronic musical instrument of this embodiment is generated by the output data E of the envelope information generating circuit 5 (that is, the data applied to the B input terminal of the adder 4 via the exclusive OR gates ₆₀ to ₆₁₁ ). Now, it turns out that envelope control can be performed. That is,
The envelope control value in that case is 2sinEπ/2048...Equation (4).

Next, envelope control will be specifically explained with reference to FIGS. 7 and 8. First, when the key is on and no waveform is being output, the envelope information generating circuit 5 outputs data "0". Therefore, at each timing _t0 , the peak value read out from the sine wave section 7 is sinaπ/2048 from equation (1). On the other hand, at each timing _t1 , the peak value read from the sine wave section 7 becomes -sinaπ/2048 from equation (2).

FIG. 7 explains the above state. FIG. 1 shows the peak value read out from the sine wave section 7 at timing _t0 , and FIG. 2 shows the peak value read out from the sine wave section ₇ at timing t1.
The peak values read from the respective peaks are shown. In this way, since the phases 1 and 2 in FIG. 7 are the same and the signs of the peak values are opposite, the resultant data after adding the two, that is, the output data of the latch 10, is as shown in FIG. 3, No waveform will be output. From this state, the envelope information generation circuit 5
converts the output data E to "1024" (=010000000000)
As _the phase shift increases gradually _toward The wave height values read from the wave section 7 are data of the same phase, as shown in FIGS. 8 1 and 2, respectively, and the output waveform is at the maximum level (double) as shown in FIG. 8 3. becomes. This means that COSaπ/2048 is read out from equation (1) at t ₀ , COSaπ/2048 is read out from equation (2) at t ₁ , and by adding the two, the waveform of 2COSaπ/2048 is obtained. , which can also be understood from the output.

Therefore, when the performance key is turned on,
In order to rapidly increase the output level from the 0 level to the maximum level, the output data E of the envelope information generating circuit 5 needs to be rapidly increased from "0" to "1024". To shift from the attack state to the decay state, the data E is sequentially decreased from "1024" to a predetermined value. In order to shift to the sustain state, the data E is held at a predetermined value. As a result,
The output level remains constant. Then, if the data E is gradually decreased to "0" from the time when the key-off of the performance key is detected, the release state will be reached. Then, when the data E becomes "0", the output level will be 0.
As a result, no musical sound is output.

The above has explained the case where ADSR has each envelope state, but the same applies to cases where there are three envelope states such as attack, sustain, and release, such as an organ sound, or cases where there are other envelope states. Envelope control is possible.

In the above embodiment, only one sine wave section 7 is provided, and by time-sharing processing using two timings, t ₀ and t ₁ , the equations (1) and (2) that lead to the above equation (3) are obtained.
However, two sine wave sections are provided and, for example, the sum of the output data of the accumulator 3 and the envelope information generation circuit 5 is applied to one of them. , the difference value is applied to the other sine wave section, and as a result, the data output from both sine wave sections are added together and outputted by an adder. It is possible to read out two sinusoidal waveforms.

In addition, in the above embodiment, a 1/4 period sine wave is divided into 2 ⁶ = 64 sample points and stored in the ROM, and interpolation is performed using 4 bits.
We made it possible to read one waveform from the 1/4 waveform, and ended up dividing one period into 4096 sample points, but in general, when reading a sine wave by dividing it into 2 ⁿ sample points, the ROM The first and second waveforms read from are sin2πa+E/2 ⁿ ...Equation (5) -sin2πa-E/2 ⁿ ...Equation (6), and the combined waveform is 2COSaπ/2 ^n-1 sinEπ /2 ^n-1 ...Equation (7) is obtained.

Furthermore, the above data a and data E are added to A of the adder 4.
When inputting to the input terminal and the B input terminal, the circuit of this embodiment operates as shown in the following equation, except for the exclusive OR gate ₆₁₂ .

sin2πa+E/2 ¹² +sin2πa−E/2 ¹² =2sinaπ/2 ¹¹ COSEπ/2 ¹¹ ...Equation (8) In this case, the envelope control value is 2COSEπ/2 ¹¹ ...Equation (9).

Moreover, if another gate circuit is added to the circuit of this embodiment, −sin2πa+E/2 ¹² +sin2πa−E/2 ¹² =−2COSaπ/2 ¹¹ sinEπ/2 ¹¹ ...Equation (10) can be obtained, In that case, the envelope control value is −2sinEπ/2 ¹¹ . . . Equation (11).

It is obvious that the calculation method can be changed in various other ways.

Furthermore, in the above embodiment, a sine wave of the relevant scale frequency, that is, a fundamental wave, is obtained in response to the operation of a performance key. By performing processing, it is possible to obtain high-order harmonic waves together with the fundamental wave, thereby making it possible to obtain a desired waveform including harmonic components.

Furthermore, the present invention is applicable not only to electronic musical instruments but also to all devices that utilize sine waves.

As explained above, this invention stores a 1/4 cycle worth of sine waves in a waveform memory, and reads out and processes the 1/4 cycle worth of sine waves from this waveform memory. Since a sine wave generator capable of generating a sine wave for one period has been provided, the capacity of the waveform memory is significantly smaller than that of the conventional device, which has the advantage of reducing costs. In addition, when reading a 1/4 period sine wave from the waveform memory, an interpolation circuit that interpolates the peak value between each sample point makes it possible to obtain an extremely good sine wave. There are great advantages in this respect as well. In addition, the present invention provides a first circuit that accumulates frequency information to generate an address signal, and controls the inversion of the lower bit of the address signal using the lower bit of the two most significant bits of the address signal. By providing this means, it is possible to obtain an address signal that repeats up and down every 1/4 period from this first circuit means, and also to obtain an address signal that repeats up and down every 1/4 period, and also to follow at least the upper bit of the two most significant bits of the address signal. By providing a second circuit means for inverting the sign of the waveform output, it is possible to obtain waveforms in quadrants with different polarities.Although the configuration is simple, it is possible to perform interpolation processing on all cycles of sine waves of arbitrary frequencies. This has the advantage that it can be generated as an appropriate waveform.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of the main part of an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the sine wave section 7, and FIG.
The figure shows a 1/4 period sine wave stored in the ROM 15, and Figure 4 shows the ROM 1 in the sine wave section 7.
5 is a diagram illustrating the relationship between the peak value and the difference value output from the sine wave section 7. FIG. 5 is a diagram showing one cycle of the sine wave output from the sine wave section 7. FIG. Figures 7 and 8, which show clock pulses and their time-division states, show two waveforms read out in a time-division manner from the sine wave section 7, and envelope control performed by combining the waveforms. FIG. 1... Keyboard, 2... Frequency information conversion
ROM, 3...Accumulator, 4...Adder, 5...Envelope information generation circuit, ₆₀ to ₆₁₂ ...Exclusive OR gate, 7...Sine wave section, 8...Accumulator,
15...ROM, ₁₆₀ to ₁₆₅ ...Exclusive OR gate, ₁₇₀ to ₁₇₃ ...Exclusive OR gate, 18
... Multiplier, 19 ... Adder, 20 ₀ to 20 ₉ ...
Exclusive or gate.

Claims (1)

[Claims] 1. Frequency information generating means for generating frequency information corresponding to a frequency to be generated; and a frequency information generating means that accumulates the frequency information generated by the frequency information generating means at predetermined timings to generate a sine for all cycles. address signal supply means for supplying an address signal for generating wave data, and each bit _S9 to _S0 except the most significant two bits _S11 and _S10 of the address signal outputted from this address signal supply means. a first circuit means that supplies the signal directly or inverted according to the level of the lower bit _S10 of the two most significant bits, and the amplitude value of each sample point corresponding to a 1/4 period sine wave; In addition to storing data, difference value data between each sample point is also stored, and amplitude value data and difference value data of each of the above sample points are generated by the upper bit signal of the output of the first circuit means. A waveform memory means generates interpolated value data for the amplitude value data using the difference value data generated from the waveform memory means and the lower bit signal of the output of the first circuit means, and generates interpolated value data for the amplitude value data. and the amplitude value data to output waveform data; and a code of the waveform data outputted from the interpolation calculation means is determined by the sign of the most significant address signal generated by the address signal supply means. The second bit is converted according to at least the upper bit _S11 of the two bits.
and 1/4 of the waveform stored in the waveform memory means.
A sine wave generator characterized in that it is possible to obtain waveform data of a sine wave subjected to interpolation processing for a full period from amplitude value data and difference value data corresponding to a sine wave for a period.