JPS6320358B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic musical instrument that generates musical tones based on digitally generated musical sound waveforms.

For example, music synthesizers generate musical tones by reading musical waveforms such as sine waves, rectangular waves, sawtooth waves, etc. from a waveform memory. Also, one way to change the timbre of the generated musical sound is to add noise to the musical waveform from the waveform memory, but in this case, if the musical waveform and noise are input to an adder and simply added, The number of bits representing the composite amplitude value may be larger than the number of bits representing the maximum amplitude value of the musical sound waveform, and therefore the capacity of the digital/analog conversion circuit connected to the output side of the musical tone generation circuit may be reduced. There is a risk that inconveniences such as exceeding the limit may occur. On the other hand, in order to eliminate such drawbacks, it is possible to keep the maximum amplitude value of the musical sound waveform small in advance, but if this is done, the musical sound level when no noise is added becomes small, and the S/N
There are drawbacks that are not a good idea when considering ratios.

This invention was made against the background of the above-mentioned circumstances, and its purpose is to change the polarity of the predetermined musical sound waveform when adding a noise waveform to the musical sound waveform to change the timbre of the generated musical sound. To provide an electronic musical instrument which performs the addition or subtraction of a noise waveform to the predetermined musical sound waveform by determining the polarity and switching between adding and subtracting the noise waveform to the predetermined musical sound waveform, thereby generating musical tones.

Various embodiments of the present invention will be described below with reference to the drawings. 1 to 7 show a first embodiment in which the present invention is applied to a music synthesizer. In FIG. 1, a keyboard 1 of a musical synthesizer is provided with a plurality of keys arranged in musical scale order. In addition, the switch part 2 has a square wave, PWM
A switch for selecting various sound source waveforms (BASIC WAVE) such as waves (asymmetric square waves) and sawtooth waves, a switch for varying the amount of noise generated by a noise control section 6 to be described later, and a digital filter 7. , the envelope generator 8, etc., are provided. And the keyboard 1 and switch part 2 are
It is periodically scanned by a CPU (central processing unit) 3, and each key switch output of the keyboard 1 and each switch output of the switch section 2 is supplied to the CPU 3.

The CPU 3 is a device that controls all operations of this music synthesizer, and is composed of a microprocessor, etc., but its details will be omitted.

A ROM (read only memory) 4 is a memory that stores the scale frequency code β. Address data for reading the scale frequency code β corresponding to the pitch of the operation keys on the keyboard 1 is then supplied from the CPU 3, and the scale frequency code β that is read as a result is supplied.
is supplied to the wave generator 5.

The wave generator 5 receives the above-mentioned scale frequency code β and data α, which will be described later, supplied from the CPU 3.
This circuit creates the above-mentioned sound source waveform (that is, musical sound waveform) by digital calculation based on γ and K, and the created waveform data is supplied to the digital filter 7 via the noise control section 6. When changing the tone, the noise control section 6 adds or subtracts noise to the waveform data while determining the polarity of the waveform data from the wave generator 5, that is, whether the amplitude value is positive or negative. As a result, a musical tone whose timbre has changed from the original musical tone is generated.

Based on the control signal from the CPU 3, the digital filter 7 removes a predetermined overtone component from the waveform data passed through the noise control section 6, and supplies the output to the envelope generator 8. The envelope generator 8 applies an envelope to the output of the digital filter 7 based on the control signal from the CPU 3 to obtain a musical tone signal, and supplies the musical tone signal to the digital/analog converter 9. As a result, a musical tone signal converted into an analog quantity is output from the digital/analog converter 9, and the musical tone is transmitted to the amplifier 1.
0, the sound is emitted through the speaker 11. The digital filter 7 may be applied to Japanese Patent Application No. 55-53179 ``Digital Filter Device'', and the envelope generator 8 may be applied to Japanese Patent Application No. 56-74244 ``Envelope Control System for Electronic Musical Instruments''.

Next, referring to FIG. 2, the wave generator 5
The configuration will be specifically explained. Full Adder 15 A
The 16-bit data output from the shift register 17 is circulated and applied to input terminals _A15 to _A0 . Further, 16-bit data α (α ₁₅ to α ₀ ) output from the CPU 3 is applied to the B input terminals B ₁₅ to B ₀ of the full adder 15 . Note that this data α is a constant value. Furthermore, a high level signal "H" is always applied to the carry input terminal Cin of the full adder 15. Therefore, the full adder 15 subtracts the input data α to the B input terminal from the input data at the A input terminal, and outputs the resultant data from the S output terminals _S15 to _S0 , which are connected to the output side of the full adder 15. full adder 16 a
Apply to input terminals _A15 to _A0 . This full adder 16
The B input terminals B ₁₅ to _{B 0} of the game circuit G ₁ output the scale frequency code β (in the case of creating a rectangular wave) or the gate circuit G ₂ output the data β ± (β−
K) γ (in the case of PWA wave generation) are preset via AND gates 18 ₁₅ to 18 ₀ , respectively. In addition,
A carry output output from the terminal Cout of the full adder 15 is applied to each control input terminal of the AND gates 18 ₁₅ to _{18 0} via the inverter 19 .

The result data of full adder 16 is S output terminal S ₁₅ ~
It is output from _S0 and applied to the shift register 17 connected to the output side of the full adder 16. For example, if this music synthesizer is an 8-tone polyphonic synthesizer, the shift register 17 is composed of 8 stages of 16-bit capacity shift registers connected in cascade. The circuit shown in FIG. 2 executes time-division processing operations for eight channels under the control of the CPU 3.

The lower 9 of the output data of the shift register 17
Bit data is exclusive or gate 20 ₈ ~ 20 ₀
is applied to Further, each of the 10 to 15 bits of the output data is applied to each control input terminal of AND gates 22-1 to 22-6 via inverters 21-1 to 21-6, respectively. Furthermore, the data of the most significant bit of the above output data is sent to the inverter 21-7.
is applied to the other input terminal of the AND gate 22-6. AND gates 22-1 to 22-6 are connected in series as shown, and therefore the output of AND gate 22-6 is applied to the other input terminal of AND gate 25-5. The outputs -5 to 22-2 are applied to the other input terminals of the AND gates 22-4 to 22-1 at the subsequent stage. The output of AND gate 22-1 is then applied to exclusive OR gates 20 ₈ to 20 ₀ .

The output of exclusive OR gates 20 ₈ to 20 ₀ is ROM
(Read-only memory) 23 is applied to A input terminals A ₈ to A ₀ as address data. The ROM 23 stores 1/4 waveform sine wave data shown in FIG. This waveform data is used to interpolate points where the amplitude level of the rectangular wave etc. generated by the wave generator 5 changes suddenly.
The 7-bit amplitude value data read from output terminals 0 ₆ -0 ₀ of the ROM 23 is input to OR gates 24 ₆ -24 ₀ .

On the other hand, the output of the AND gate 22-2 is also applied to the OR gates 24 ₆ to 24 ₀ via the inverter 25. The outputs of the OR gates 24 ₆ to 24 ₀ are then supplied to the noise control section 6.

A scale frequency code β and data K (constant value) are applied to the subtraction circuit 41, respectively. The result data β-K output from the subtraction circuit 41 is applied to the multiplication circuit 42. Data γ (this data γ is data that determines the duty ratio of the generated waveform and takes a value of 0γ1) is also applied to this multiplier circuit 42, and the resulting data (β−
K) γ is input to the addition/subtraction circuit 43. A scale frequency code β is applied to the other end of the addition/subtraction circuit 43, and an output of a polarity inversion circuit 32, which will be described later, is applied to the control input terminal ±. The result data β±(β-K)γ of the addition/subtraction circuit 43 is a gate circuit.
Applied to G ₂ . Note that the scale frequency code β is input to the gate circuit _G1 , and its opening/closing is controlled by a control signal outputted by the CPU 3 in response to the operation of a switch specifying rectangular wave generation. Also gate circuit
_G2 is controlled to open and close by a control signal output by the CPU 3 in response to the operation of a switch specifying PWM wave generation.

The polarity inversion circuit 32 includes a shift register 48 and an exclusive OR gate 49 connected to the output side of the shift register 48. And at the other end of exclusive or gate 49, full adder 15
A signal from the output terminal C' of is inputted via the inverter 50. The output of the exclusive OR gate 49 is fed back to the input side of the shift register 48 as a polarity inversion signal, and is also input to the noise control section 6, and is further applied to the control input terminal ± of the addition/subtraction circuit 43 as an addition/subtraction command. . In the case of the above-mentioned 8-note polyphonic synthesizer, the shift register 48 is made up of 8 stages of 1-bit capacity shift registers connected in cascade. Also full adder 1
5 outputs an "H" level signal (carry) when the result data of the full adder 15 reaches "512".

Next, the configuration of the noise control section 6 will be specifically explained with reference to FIG. The outputs of exclusive OR gates 6-2 ₆ to 6-2 ₀ are applied to input terminals A ₆ to A ₀ of the lower seven bits of the A input terminal of full adder 6-1. In addition, the input terminal _A7 of the most significant bit of the A input terminal of the full adder 6-1 and the input terminal of the B input terminal
The above polarity inversion signal is applied to the other input terminals B ₇ , B ₆ , B ₄ to _{B 0} except for B 5 via the inverter 6-3 or the inverter _6-4 . Furthermore, an OR gate 6 is connected to the input terminal _B5 of the sixth bit of the B input terminal.
-5 output is applied. Also full adder 6
The above polarity inversion signal is directly applied to the carry input terminal Cin of -1. Thus, data 0 6 to 0 0 via the OR gates 24 ₆ to 24 ₀ are respectively input to one end of the exclusive OR gates 6-2 ₆ to 6-2 ₀ , and data 0 ₆ to 0 ₀ are inputted to each other terminal. In both cases, polarity inversion signals are input. The polarity inversion signal is input to the OR gate 6-5 via the inverter 6-4 and the transfer gate 6-6, and a noise signal is input via the AND gate 6-7. The transfer gate 6-6 gates the control signal outputted by the CPU 3 according to the operation state of the noise switch on the switch section 2, which is operated when changing the tone, by the signal via the inverter 6-8. controlled. Further, the AND gates 6-7 are directly gate-controlled by the above control signal. Further, the noise signal is a signal whose level randomly changes to "H" or "L" when the noise switch is turned on. and full adder 6
The result data output from the -1 S output terminals S ₇ to _{S 0} is sent to the digital filter 7.

Next, the operation of the above embodiment will be explained with reference to FIGS. 5 to 7. First, the operation when generating a rectangular wave will be explained with reference to the time chart in FIG. Now, it is assumed that noise is not added to change the timbre of the generated musical tone. In this case, first, turn on the switch for specifying the rectangular wave on the switch section 2, turn off the noise switch, and operate other necessary switches. Therefore, by turning on the square wave designation switch, the CPU 3 sets the gate circuits G ₁ and G ₂ of the wave generator 5 to "H" (that is, "1").
A level or "L" (ie, "0") level signal is output. Therefore, from then on, gate circuit G ₁ is opened and gate circuit G ₂ is closed. Also CPU
3 outputs a "0" level control signal to the noise control section 6, and therefore the AND gate 6 in FIG.
-7 is closed, and on the other hand, transfer gate 6-
6 is opened by the output "1" of the inverter 6-8.

The case where, for example, one key on the keyboard 1 is turned on in the above state will be described below. In this case, when the above one key is turned on, CPU3
Predetermined address data for reading out the scale frequency code β corresponding to the operation key from the ROM 4 is output to the ROM 4. As a result, the scale frequency code β is read from the ROM 4 and supplied to the wave generator 5. This scale frequency code β is applied to the AND gates 18 ₁₅ to 18 ₀ via the gate circuit G ₁ which is being opened. Now, the output of the output terminal Cout of the full adder 15 is “0”
Therefore, the output of the inverter 19 is “1”
Accordingly, the AND gates 18 ₁₅ to _{18 0} are currently being opened. Therefore, the above scale frequency code β is converted to full adder 16 through AND gates 18 ₁₅ to 18 ₀ .
is applied to the B input terminals B ₁₅ to B ₀ of . On the other hand, at this time, 16-bit all "0" data is applied from the S output terminals S ₁₅ to _{S 0} of the full adder 15 to the A input terminals A ₁₅ to _{A 0} of the full adder 16. Therefore, the result data of the full adder 16 at that time will be data with the same value as the set scale frequency code β, and S
When output from the output terminals S ₁₅ to _{S 0} , the signals are input to the shift register 17 . After this data is shifted, it is output from the shift register 17 and is input cyclically to the A input terminals A ₁₅ to A ₀ of the full adder 15, and is also input to the inverters 21 ₇ to 21 ₁ of the exclusive OR gates 20 ₈ to 20 ₀ . .

In the case of this embodiment, all values of the scale frequency code β of each scale are output as values larger than "1024". That is, any one of the upper 11 to 16 bits of the 16-bit data always contains "1" data. Therefore, when the scale frequency code β is set when one key is turned on, and the shift register 17 outputs data of the same value, the output of the AND gate 22-2 is always "" as shown in FIG. 5e. 0” level. Therefore, the output of the AND gate 22-1 is also at the "0" level while the output of the AND gate 22-2 is "0" as shown in FIG. 5B. Furthermore, at this time, the output of inverter ₅₅₀ is
As shown in Figure c, the output of the polarity inversion circuit 32 (polarity inversion signal) is at "1" level, and therefore the output of the polarity inversion circuit 32 is at the "1" level as shown in Figure 5D.
As shown in the figure, it is at the "0" level. As a result, the "0" level signal of the AND gate 22-1 is supplied to the exclusive OR gates ₂₀₈ to ₂₀₀ , and the data of the lower 9 bits of the output of the shift register 17 is directly transferred to the A input terminals _A8 to A of the ROM 23. Applied to ₀ .
Further, a "1" level signal obtained by inverting the "0" level signal of the AND gate 22-2 by the inverter 25 is applied to the OR gates 24 ₆ to 24 ₀ , and therefore, the OR gates 24 ₆ to 24 ₀ each output a "1" level signal. Level signals 0 ₆ to 0 ₀ are output and applied to one end of each of exclusive OR gates 6-2 ₆ to 6-2 ₀ in the noise control section 6 . Therefore, exclusive or gate 6-2 ₆ ~
A "0" level polarity inversion signal is applied to each other end of _6-20 . Therefore, the noise control section 6
All "1" level signals are input to the input terminals _A6 to _A0 of the lower 7 bits of the A input terminals of the full adder 6-1. The output "1" of the inverter 6-3 is also input to the input terminal _A7 of the most significant bit. On the other hand, at the B input terminals B ₇ to _{B 0} of the full adder 6-1,
The “0” level polarity inversion signal is transferred to the inverter 6-4.
The inverted signal (“1”) is input. That is,
Since the transfer gate 6-6 is open and the output of the AND gate 6-7 is "0", the inverter 6 is also connected to the input terminal _B5 of the B input terminal.
A polarity inversion signal inverted by -4 is applied via the transfer gate 6-6 and the OR gate 6-5. Furthermore, carry input terminal of full adder 6-1
A “0” level polarity inversion signal is also applied to Cin. As a result, at this time, full adder 6-1
The result data outputted from the S output terminals S ₇ to _{S 0} becomes “11111110” and is sent to the digital filter 7. The waveform diagram in FIG. 5a shows a rectangular wave sent to this digital filter 7. Therefore, the digital filter 7 removes the specified overtone component under the control of the CPU 3, and the envelope generator 8 applies an envelope to its output, and starts generating and emitting musical tones of the scale of the operation keys. .

When data with the same value as the set scale frequency code β is input cyclically to the A input terminals ₁₅ to _A0 of the full adder 15, the constant value data α output from the CPU 3 is input to the B input terminals _B15 to _B0 . It is input as 16-bit data. In addition, since the carry input terminal Cin is always set to the "H" level, the full adder 15 performs the first subtraction operation of β - α at this time, outputs the resulting data from the S output terminal, and outputs the resultant data from the S output terminal to the full adder 16. Apply to the A input terminal. Note that "-α" in the above formula "β-α" corresponds to the value obtained by subtracting "-1" from the values of α ₀ , α ₁ , . . . α ₁₅ in FIG. When this subtraction operation is executed, the output of the carry output terminal Cout of the full adder 15 becomes "1" level, so the output of the inverter 19 becomes "0", and the AND gates 18 ₁₅ to 18 ₀ are closed. Therefore, the scale frequency code β to the B input terminal of the full adder 16 is
input is blocked. Therefore, the result data of the full adder 16 at this time is the same as the result data of the first time of the full adder 15, and is applied to the shift register 17. Then, when this first result data is output from the shift register 17, it is inputted cyclically to the A input terminal of the full adder 15, while exclusive OR gates 20 ₈ to 20 ₀ and inverters 21 to -7 to
21-1. After this first calculation, the data input states to the A input terminal, B input terminal, and carry input terminal Cin of the full adder 6-1 are unchanged from the previous time, so the above data "11111110" is input to the digital filter 7. ” is sent.

Full Adder 15, And Gate 18 ₁₅ ~ 18 ₀ ,
In the full adder 16 and shift register 17,
The cumulative subtraction operation, which is exactly the same as the first subtraction operation described above, results in data, that is, shift register 1.
The process is repeated until the output of 7 becomes "1024" (see FIG. 5f). During this time, the data input states to the A input terminal, the B input terminal, and the carry input terminal Cin of the full adder 6-1 do not change, and therefore, the data "11111110" is continuously sent to the digital filter 7 during this time. Then, when the output of the shift register 17 becomes smaller than "1024" by the next subtraction operation, the data in the upper 11th to 16th bits of the output of the shift register 17 are all "0", and so Gattete and Gate 22-2
The output of is inverted to "1" level as shown in FIG. 5e. Therefore, from now on, the output of the inverter 25 becomes "0" level and is input to the OR gates 24 ₆ to 24 ₀ .

On the other hand, during the cumulative subtraction operation in which the output of the shift register 17 is from "1024" to "512", the 10th bit data of the output of the shift register 17 holds "1", and therefore, during this period, the As shown in FIG. 5b, the output of the AND gate 22-1 is still "0", and the exclusive OR gates 20 ₈ to 20 ₀
supplied to Therefore, the above "1024" to "512"
During this period, the lower 9-bit data of the output of the shift register 17 continues to be applied to the A input terminal of the ROM 23 as it is. During the above period, the output of the polarity inversion circuit 32 continues to be at the "0" level as shown in FIG. 5d.

Therefore, assuming that the output of the shift register 17 becomes "1024" or less, for example "1023", then the lower 9 bits of the output of the shift register 17 are all "1", It is applied to the A input terminal of the ROM23. Therefore, the ROM 23 is addressed by this 9-bit all "1" address data, and the 7-bit all "1" data is read out and sent to the noise control section 6 as shown in FIG. On the other hand, in the noise control section 6, since the polarity inversion signal is still at the "0" level, all "1" data is input to the A input terminal of the full adder 6-1, and all "1" data is also input to the B input terminal. is input, and furthermore, the carry input terminal
Data “0” is input to Cin. Therefore, the resulting data is "11111110", which is the same as last time.
The signal is sent to the digital filter 7.

Next, when the output of the shift register 17 becomes a value smaller than "1023" by data α due to the next cumulative subtraction operation, the ROM 23 is stored at an address smaller by α than the above-mentioned 9-bit all "1" data (i.e., "511"). Addressed by data. Therefore, as can be seen from Figure 4, the ROM
From the full adder 6-23, data smaller by a predetermined value than the 7-bit all "1" data mentioned above, that is, data with an amplitude value slightly smaller than the previous one, is read out.
It is applied as is to the A input terminal of 1. The S output terminal of the full adder 6-1 outputs result data that is smaller by "1" than the input data to the A input terminal, and is sent to the digital filter 7.

Thereafter, in the same way, the output of the shift register 17 decreases by α by each cumulative subtraction operation,
Until the value reaches "512", the address data in the ROM 23 is sequentially addressed in the direction of decreasing by α, and accordingly, each time, amplitude value data with a smaller value than the previous one is read out. Ru. During this time, the input states of data to the A input terminal, the B input terminal, and the carry input terminal Cin of the full adder 6-1 are the same as described above, and accordingly, the data is input to the digital filter 7 with the above-mentioned sequentially decreasing amplitude. Data smaller by "1" than the value data is sent. and shift register 17
When the output is "512", the ROM 23 is addressed by address data of 9 bits all "0".

Next, the result data of cumulative subtraction operation is full adder 1
5, when the value changes from "512" to "511" or less, "1" is output from the output terminal C' of the full adder 15.
The signal is output, and in response, one pulse signal is output from the inverter 50 as shown in FIG. 5c. As a result, as shown in FIG. 5d, the output of the polarity inversion circuit 32, that is, the polarity inversion signal is inverted to the "1" level, and the exclusive OR gate 6-2 ₆
~6-2 ₀ , are applied to the carry input terminals Cin of the inverters 6-3, 6-4, and the full adder 6-1, respectively.

Therefore, when data below "511" is output from the shift register 17 as shown in Figure 5f, the upper 10 to 16 bits of the output are all "0".
Therefore, the output of the AND gate 22-1 changes to the "1" level as shown in FIG. 5B, and is applied to the exclusive OR gates 20 ₈ to 20 ₀ . On the other hand, 9-bit all "1" data is again applied to the other ends of the exclusive OR gates ₂₀₈ to ₂₀₀ , and the output thereof is inverted to 9-bit all "0" and applied to the A input terminal of the ROM 23. . Therefore, the result data of cumulative subtraction is "511" to "0".
While the address data sequentially decreases by α, the ROM 23 is sequentially addressed in the direction in which the address data increases from all "0" to all "1". Further, _the amplitude value data read out as a result becomes larger sequentially as shown in FIG _.
All bits are inverted through A of full adder 6-1.
Input terminals A ₆ to _{A 0} are input, “0” signal is input to A input terminal A ₇ , all “0” data is input to B input terminals B ₇ to B ₀ , and a carry input is input. Since the “1” signal is input to the terminal Cin, the data output from the full adder 6-1 during this period is transferred to the ROM2.
By adding "1" to the polarity-inverted version of the amplitude value data read from 3, it becomes equal to the data, and the data is sent to the digital filter 7.

As shown in FIG. 5 f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave in FIG. interpolated accordingly.

When the cumulative subtraction result becomes "0" or less as described above, a "0" signal is output from the carry output terminal Cout of the full adder 15 during the next subtraction operation, and as a result, the AND gates 18 ₁₅ to 18 ₀ are temporarily opened. The scale frequency code β is applied to the B input terminals B ₁₅ to _{B 0} of the full adder 16. and full adder 16
When the data given to the A input terminal of 1 and this scale frequency code β are added, and the resulting data is output from the shift register 17, the above data, that is, the scale frequency code β is greater than "1024" as described above. Therefore, for the reasons mentioned above, from this point on, as shown in Figure 5 b and e,
Each output of AND gates 22-1 and 22-2 is inverted to "0" level.

After the scale frequency code β is set again as described above,
The cumulative subtraction operation by α is executed, and the output of the shift register 17 decreases from β by α, and becomes “1024”.
decreases to During this period, the A input terminals A ₇ to A 0 and the B input terminals B ₇ to _{A 0} of the full adder 6-1
Since 8-bit all "0" data is input to both _B0 and a "1" signal is input to the carry input terminal Cin, data "00000001" is sent to the digital filter 7 during this time.

While the cumulative subtraction result becomes "1024" or less and further decreases to "512", the AND gate 22-2 is always activated from the point at which it becomes less than "1024" shown in FIG. 5 f, that is, "1023" or less. The output of is inverted to "1" level. Therefore, between "1023" and "512", the output of the full adder 6-1 stores the ROM 23 at its maximum address (9 bits all "1" data).
It is equal to the data obtained by adding "1" to the inverted polarity of the amplitude value data sequentially addressed and read from the address to the minimum address (9-bit oak "0" data).

Furthermore, when the cumulative subtraction result becomes "512", "1" is output from the output terminal C' of the full adder 15 as described above.
A signal is output, and in response to this, the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 5d. Next, when the cumulative subtraction result becomes "511" or less, the output of the AND gate 22-1 is inverted to the "1" level. As a result, as mentioned above, when the cumulative subtraction result is between "511" and "0", the output of the full adder 6-1 is read by sequentially addressing and reading the ROM 23 from the minimum address to the maximum address. "1" from the amplitude value data
The resulting data is the result of subtracting .

As shown in FIG. 5f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave shown in FIG. 5a is interpolated by the waveform data from the ROM 23. When the cumulative subtraction result becomes "0" or less, a "0" signal is output from the carry output terminal Cout of the full adder 15 during the next calculation, the scale frequency code β is set based on the full adder 16, and the next period The calculation process of the square wave starts.

With the above, the arithmetic processing operation for generating a rectangular wave for one cycle is completed. As shown in FIG. 5, for example, the calculation period in which the output of the shift register 17 changes from "0" to "0" (that is, the period during which each of the previous and current scale frequency codes β is set, respectively) is
When T' and the sampling period are Ts, the calculation period T' is expressed by the following equation (1).

T'=Ts・β/α...(1) Also, the frequency of the rectangular wave generated as described above
₀ is the following formula (2) when the sampling frequency is s
It is represented by

o=1/2T'=s/2·α/β (2) Next, in the case of the above-mentioned rectangular wave generation, the operation when adding noise to change the timbre of the generated musical sound will be explained. For this purpose, the noise switch is turned on in advance along with the switch for specifying the rectangular wave on the switch section 2. Therefore, the CPU
3 outputs a "1" level control signal, and as a result, the AND gate 6-7 is opened, the transfer gate 6-6 is closed, and the full adder 6 is opened.
A noise signal that randomly changes to the "0" level or the "1" level is applied to the input _B5 of the -1 B input terminal.

First, as mentioned above, from the time the scale frequency code β is set at the B input terminal of the full adder 16 until the data as a result of cumulative subtraction becomes "1024", the noise signal is at the "0" level or "1".
The operation of the noise control section 6 will be explained for each level. During this period, full adder 6-1 A
8-bit all "1" data is input to the input terminal, and a "0" signal is input to the carry input terminal Cin. Furthermore, when the noise signal is "0", data "11011111" is input to the B input terminal,
On the other hand, when the noise signal is "1", 8-bit all "1" data is input. Therefore, when the noise signal is "0", the result data from the full adder 6-1 supplied to the digital filter 7 is "11011110", which is only "00100001" from the data 0 ₆ to 0 ₀ applied to the A input terminal. Small data (amplitude value data) will be supplied. Also, when the noise signal is "1", the digital filter 7
The result data supplied to is "11111110",
That is, the data (amplitude value data) is smaller by "1" than the data 0 ₆ to _{0 0} applied to the A input terminal.
In the left half of the waveform in Fig. 6, that is, the waveform with an amplitude of positive polarity based on the amplitude value data "10000000", the waveform shown by the solid line is when the noise signal is "1", and the waveform shown by the broken line is “0”. Therefore, the generated waveform is represented by either one of two types of amplitude value data shown by a solid line or a broken line depending on whether the noise signal is "0" or "1".

While the result data of the above cumulative subtraction changes from "1024" to "512", the amplitude value data read from the ROM 23 is directly input to the input terminals _A6 to _A0 of the A input terminal of the full adder 6-1. 0 ₆ to _{0 0} , a "1" signal is input to the input terminal _A7 , and a "0" signal is input to the carry input terminal Cin. When the noise signal is "0", data "11011111" is input to the B input terminal,
On the other hand, when the noise signal is "1", 8-bit all "1" data is input. Therefore, this period is exactly the same as the previous periods, and when the noise signal is "0", data smaller by "00100001" than the data input to the A input terminal of the full adder 6-1 is sent to the digital filter 7. Also, when the noise signal is "1", data smaller by "1" is sent out. That is, the waveform shown in FIG. 6 is obtained.

The result data of the above cumulative subtraction is "0" from "512"
During this period, the inverted data of the amplitude value data 0 ₆ to 0 ₀ from the ROM 23 is input to the input terminals A ₆ to A ₀ of the A input terminal of the full adder 6-1, and the input terminal A ₇
A “0” signal is input to the terminal, and the carry input terminal
A “1” signal is input to Cin. When the noise signal is "0", 8-bit all "0" data is input to the B input terminal, and when the noise signal is "1", data "00100000" is input.
Therefore, the data supplied to the digital filter 7 during this period is "1" larger than the data applied to the A input terminal when the noise signal is "0", and when the noise signal is "1" Sometimes the data is larger by "00100001" than the data applied to the A input terminal. That is, the right half of the waveform shown in FIG. 6, that is, the solid line waveform with negative polarity amplitude (noise signal is
) or the broken line waveform (when the noise signal is “1”)
).

Next, as shown in FIG. 5f, the shift register 17
During the period when the output of is between "0" and "1024", that is, when the scale frequency code β is set again at the B input terminal of the full adder 16 and then until the resultant data of the cumulative subtraction reaches "1024", 8-bit all “0” data is input to the A input terminal of the full adder 6-1, and the carry input terminal
A “1” signal is input to Cin, and all 8 bits are “0” at the B input terminal when the noise signal is “0”.
Data is input, and on the other hand, when the noise signal is "1", data "00100000" is input. Therefore, the data supplied to the digital filter 7 during this period is data "00000001" when the noise signal is "0", that is, data larger by "1" than the data applied to the A input terminal, and When the noise signal is "1", the data is "00100001", that is, the data is larger by "00100001" than the data applied to the A input terminal. That is, the waveform shown in FIG. 6 is obtained.

While the result data of the above cumulative subtraction changes from "1024" to "512", the A of full adder 6-1
Inverted data of data 0 ₆ to _{0 0} from the ROM 23 is input to input terminals A ₆ to A ₀ of the input terminals, and input terminal A ₇
A “0” signal is input to the terminal, and the carry input terminal
When a “1” signal is input to Cin and the noise signal is “0” to the B input terminal, all 8 bits are “0”.
Data is input, and on the other hand, when the noise signal is "1", data "00100000" is input. Therefore, the data supplied to the digital filter 7 during this period is "1" larger than the data applied to the A input terminal when the noise signal is "0", and when the noise signal is "1" The data is larger by "00100001" than the data applied to the input terminal.

Furthermore, while the result data of the above cumulative subtraction changes from "512" to "0", the data 0 ₆ to 0 ₀ from the ROM 23 are input to the input terminals A ₆ to A ₀ of the A input terminal of the full adder 6-1. Input it as is, and also input a “1” signal to input terminal A ₇ , and then input it to the carry input terminal.
A “0” signal is input to Cin. When the noise signal is “0”, data “11011111” is input to the B input terminal, and on the other hand, the data “11011111” is input to the B input terminal.
At this time, 8-bit all "1" data is input. Therefore, during this period, the digital filter 7
When the noise signal is "0", the data supplied to the A input terminal is "00100001" smaller than the data applied to the A input terminal, and when the noise signal is "1", the data supplied to the A input terminal is "00100001" smaller than the data applied to the A input terminal. The data will be smaller by 1.

As explained above, when adding noise to change the timbre of a generated musical sound, when the polarity of the amplitude of the generated rectangular wave is on the positive side, the noise is added in the direction where the amplitude decreases, and if the polarity is When is on the negative side, noise is added in the direction where the amplitude increases. Therefore, the inconvenience that the amplitude of the generated musical tone exceeds the capability of the D/A converter 9 does not occur.

Next, the operation in the case of generating a PWM wave will be explained with reference to FIG. Note that it is assumed that no noise is added. In this case, the PWM on switch section 2
Turn on the wave designation switch and turn off the noise switch. As a result, gate circuit _G1 is turned off and gate circuit _G2 is turned on. In this state, when one key on the keyboard 1 is turned on, the calculation and generation process of the PWM wave is started.

The explanation will now start from the timing when the shift register output shown in FIG. 7F is "0"("0" at the left end of the figure). That is, at this point, the output (polarity inversion signal) of the polarity inversion circuit 32 is at the "1" level as shown in FIG. A "1" signal is applied to the exclusive OR gates 6-2 ₆ to 6-2 ₀ in the section 6, the inverters 6-3 and 6-4, and the carry input terminal Cin of the full adder 6-1, respectively.

On the other hand, the subtraction circuit 41 outputs the result data β-K and gives it to the multiplication circuit 42, and the multiplication circuit 42 outputs the result data (β-K)γ to the addition and subtraction circuit 43.
is giving to Furthermore, the addition/subtraction circuit 43 outputs result data β+(β-K)γ, which is applied to the gate circuit _G2 . For example, the data K is "1024", and the data γ that determines the duty ratio is
It takes a value of 0γ1.

Therefore, when the above-mentioned one key is turned on, data β+(β-K)γ is set in the full adder 16 at the start of arithmetic processing in accordance with the same operation as described during the rectangular wave generation operation. . Then, a cumulative subtraction operation is performed to subtract data α (a constant value) from this setting data β+(β−K)γ. Until the resulting data, that is, the output of the shift register 17, decreases by α to "1024", the AND gate 2
2-1, the inverter 50, the polarity inverting circuit 32, and the AND gate 22-2 output "0", "1", respectively.
Therefore, during this period, the read waveform from the ROM 23 is invalidated, and the data output from the full adder 6-1 and sent to the digital filter 7 is "00000001". Become.

When the cumulative subtraction result data, that is, the shift register output, becomes less than "1024", the AND gate 22-
The output of 2 is inverted to "1" level. Therefore, while the above result data changes from "1024" to "512", the polarity of the amplitude value data 0 ₆ to _{0 0} read out by sequentially addressing the ROM 23 from the maximum address to the minimum address is reversed. +1 to
The resulting data is output from the full adder 6-1 and sent to the digital filter.

When the resultant data becomes "512", the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 7d, and a subtraction command is given to the addition/subtraction circuit 43.
Further, a "0" signal is applied to the carry input terminal Cin of the exclusive OR gates 6-2 ₆ to 6-2 ₀ inverters 6-3, 6-4 and the full adder 6-1. Moreover, when the above result data becomes "511" or less, the output of the AND gate 22-1 becomes "1" as shown in FIG. 7b.
Flip to level. Therefore, the result data is "511"
Until the change from 0 to 0, the output of the full adder 6-1 is data obtained by subtracting 1 from the amplitude value data read by addressing the ROM 23 from the minimum address to the maximum address. is output and sent to the digital filter 7.

When the resultant data becomes "0" or less as shown in FIG. 7f, data .beta.-(.beta.-K).gamma. is set in the full adder 16 during the next subtraction operation. As shown in FIGS. 7b and 7e, when the resultant data becomes "0" or less, each output of the AND gates 22-1 and 22-2 is inverted to the "0" level. When the data β-(β-K)γ is set in the full adder 16, the subtraction operation of α is started again. As a result, the output of the full adder 6-1 holds the data "11111110" until the data decreases to "1024".

When the resultant data becomes smaller than "1024", the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 7e. Therefore, while the result data decreases to "512", the full adder 6-1
The output is data smaller by "1" than the amplitude value data 0 ₆ to _{0 0} read out by addressing the ROM 23 from the maximum address to the minimum address,
The signal is sent to the digital filter 7.

Next, while the result data becomes smaller than "512" and further decreases to "0", the AND gate 22-
1. Each output of the polarity inversion circuit 32 is both inverted and held at the "1" level. Therefore, the output of the full adder 6-1 during this period is data obtained by adding "1" to the polarity-inverted data of the amplitude value data 0 ₆ to 0 ₁ read out by addressing the ROM 23 from the minimum address to the maximum address. and is sent to the digital filter 7.

This completes the arithmetic processing operation for one cycle of the PWM wave, and the following is a repetition of what has been described above. And its frequency o is the same as in the case of a square wave, and the formula
Expressed by (2). Further, since the operation when adding noise to change the timbre of the generated musical sound is the same as in the case of the rectangular wave described above, the explanation of the operation will be omitted.

Next, the case of a sawtooth wave will be explained with reference to FIGS. 8 to 11. First, FIG. 8 shows a circuit in which a part of the circuit is added to the circuit of the wave generator 5 shown in FIG. 2, thereby making it possible to generate sawtooth waves in addition to rectangular waves and PWM waves. Therefore, in the circuit of FIG. 8, the same reference numerals are given to the same components as those of the circuit of FIG. 2, and the explanation thereof will be omitted, and the configuration of the circuit added to FIG. .

That is, in FIG. 8, the OR gates 24 ₆ to 2
4 ₀ is amplitude value data 0 read from ROM23
In addition to signals ₆ to 0 ₀ , the output of AND gate 22 - 2 is applied via inverter 25 and transfer gate 26 . And or gate 24 ₆ ~
The output of 24 ₀ is applied to one end of each of exclusive OR gates 27 ₆ -27 ₀ . exclusive or gate 27 ₆ ~
₂₇₀ , the output of the AND gate 22-1 is connected to the inverter 28 and the transfer gate 2.
9. The outputs of the exclusive OR gates 27 ₆ to 27 ₀ are applied to the A input terminals A ₆ to A ₀ of the full adder 30 forming a polarity inversion circuit. Further, the output of the AND gate 22-1 is connected to the A input terminal _A7 of the full adder 30, and the inverter 28,
It is applied via the transfer gate 29 and the inverter 31. Further, the output of the AND gate 22-1 is similarly connected to the carry input terminal Cin of the full adder 30, and the inverter 28 and the transfer gate 29.
In addition to the polarity inversion circuit 3 described later,
2 outputs are applied via transfer gate 33. And the S output terminal of the full adder 30 S ₇ ~ _{S 0}
The data output from the transfer gate 34
₇ to 34 ₀ and is sent to the digital filter 7 via the noise control section 60.

The transfer gate 26 is controlled to open or close by applying a control signal output from the CPU 3 to the gate when a switch is operated to designate a rectangular wave or a PWM wave, respectively. The transfer gates 29 and 35 are each directly applied with a control signal output by the CPU 3 when a switch for specifying a sawtooth wave is operated, and the transfer gate 33 is controlled to open and close by receiving the control signal via an inverter 36. Further, transfer gates 34 ₇ to 34 ₀ connect the output of the AND gate 22-2 to the inverter 2.
5, transfer gate 35, inverter 37
The voltages are applied to the gates through the gates to control opening and closing.

Output data M and data K of the shift register 17 are input to the subtraction circuit 45 . The resulting data M-K is then applied to the input terminal A of the division circuit 44. On the other hand, the result data β-K of the subtraction circuit 41 is applied to the input terminal B of the division circuit 44. Then, the result data of the division circuit 44 (M-
K)/(β-K) is the transfer gate46 ₇
~ ₄₆₀ The signal is sent to the digital filter 7 as sawtooth wave data via the noise control section 60.
Further, the output of the AND gate 22-2 is connected to each of the transfer gates ₄₆₇ to ₄₆₀ to the inverter 25, transfer gate 35, and inverter 3.
7 and 47, respectively, and the opening/closing is controlled.
The opening and closing of the gate circuit _G1 is controlled by a control signal outputted by the CPU 3 when a switch for specifying a sawtooth wave is operated in addition to a switch for specifying a rectangular wave.

FIG. 9 shows a specific configuration of the noise control section 60. The output data S ₇ -S ₀ from the full adder 30 or the division circuit 44 are sent to the A input terminals A ₇ -A 0 of the full adder 60-1, and are transferred to the A input terminals A 7 -A ₀ of the full adder _60-1 .
4 ₀ or transfer gates 46 ₇ to 46 ₀ . Also, among the B input terminals, input terminal B ₅
The signal S ₇ (sign bit data) among the data S ₇ to _{S 0} is directly applied to each input terminal except the input terminals. Furthermore, the input terminal B ₅ of the above-mentioned 6th bit of the B input terminal
is applied with the output of the OR gate 60-3. Furthermore, the signal _S7 is applied to the carry input terminal Cin via the inverter 60-2. Further, the OR gate 60-3 receives the signal _S7 via the transfer gate 60-4, and also receives a noise signal via the AND gate 60-5.
The transfer gate 60-4 gates the control signal output by the CPU 3 according to the operation state of the noise switch on the switch section 2, which is operated when changing the tone, by the signal via the inverter 60-6. controlled. Also and gate 60
-5 is directly gated by the above control signal. The result data from the full adder 60-1 is output from the C output terminals _C7 to _C0 and sent to the digital filter 7.

Next, referring to FIG. 10, a description will be given of a sawtooth wave generation scheme when no noise is added. First, turn on the switch on the switch section 2. As a result, gate circuit G ₁ , transfer gates 29, 35
is opened, and gate circuit G ₂ and transfer gates 26 and 33 are closed. In this state, when one key on the keyboard 1 is turned on, arithmetic processing for generating a sawtooth wave starts.

The explanation will now start from the timing when the shift register 17 output is "0"("0" at the left end in the figure) shown in FIG. 10d. At this point, the scale frequency code β is set in the full adder 16. Therefore, when this scale frequency code β is subsequently output from the shift register 17, since the code β is data larger than "1024", the AND gates 22-1 and 22 are output as shown in FIGS. 10b and 10c, respectively. -2 outputs are both inverted to "0" level. Since the output of the AND gate 22-2 becomes "0", the output of the inverter 37 becomes "0", and the output of the inverter 47 becomes "0".
The output becomes "1", and accordingly, the transfer gates 34 ₇ to 34 ₀ are closed and the transfer gates 46 ₇ to 46 ₀ are opened. Also, in the full adders 15 and 16, the shift register 17, and the AND gates 18 ₆ to 18 ₀ , the above scale frequency code β
The cumulative subtraction operation for subtracting data α (constant value) starts. Since the output state of the AND gate 22-2 does not change until the data as a result of the cumulative subtraction operation decreases to the value "1024",
The output of the division circuit 44 to the digital filter 7 is sent through the open transfer gates 46 ₇ to 46 ₀ and the noise control unit 60, respectively. Therefore, the subtraction circuit 45 is connected to the input terminal A of the division circuit 44.
The output data M-K of the subtraction circuit 41 is input to the input terminal B, and the output data β-K of the subtraction circuit 41 is applied to the input terminal B, respectively. Therefore, the output data of the divider circuit
H′ is expressed by the following equation (3).

H'=M-K/β-K×H...(3) where M is the output of the shift register 17, K is a constant value, "1024" in this example, and H is the maximum amplitude value. , is "254" in this example.
Therefore, equation (3) can be rewritten as the following equation (4).

H'=M-1024/β-1024×245...(4) Then, until the data as a result of the above cumulative subtraction becomes "1024", the data M gradually becomes smaller, so the above equation (4 ), the values of data S ₇ to _{S 0} also change accordingly. In this case, data _S7 to _S0 is 8 bits all “1” data to data “10000000”
During the period when the noise control unit 60 reduces the data to the A input terminal of the full adder 60-1,
S ₇ to _{S 0} are input, data “11111111” is input to the B input terminal, and the carry input terminal
A “0” signal is input to Cin. Therefore, during this period, the data output from the C output terminal of the full adder 60-1 and supplied to the digital filter 7 is the data obtained by subtracting "1" from the data applied to the A input terminal of the full adder 60-1. Also the above data
While S ₇ to _{S 0} are decreasing from data “10000000” to 8-bit all “0” data, data S 7 to _{S 0} are input to the A input terminal of the full adder 60-1, and data S ₇ to S 0 are input to the B input terminal. 8-bit all "0" data is input, and a "1" signal is also input to the carry input terminal Cin. Therefore, the data supplied to the digital filter 7 during this period is the data obtained by adding "1" to the data applied to the A input terminal.

Next, when the output M of the shift register 17, that is, the resultant data of the cumulative subtraction becomes "1024", the data _S7 to _S0 applied to the full adder 60-1 becomes "0". When the resultant data becomes "1024" or less, the output of the AND gate 22-2 is inverted to the "1" level. Therefore, transfer gate 34 ₇
~34 ₀ is opened and transfer gate 4
6 ₇ to 46 ₀ are closed. And until the above result data decreases to "512", the AND gate 22-
Since the output of the inverter 28 is held at the "0" level, the output "1" of the inverter 28 is passed through the open transfer gate 29 to the exclusive OR gates ₂₇₆ to 27.
₀ is applied to the carry input terminal Cin of the inverter 31 and full adder 30, respectively. That is, when the result data is between "1023" and "512", data S is data obtained by inverting the polarity of the amplitude value data 0 ₆ to _{0 0} that are sequentially addressed and read from the ROM 23 from the highest address to the lowest address. ₇ ~ Output from full adder 30 as S ₀ and transfer gate 34 ₇
~34 ₀ through full adder 6 of noise control unit 60
Applied to the A input terminal of 0-1. During this time, the data _S7 to _S0 gradually increase from 8-bit all "0" data to data "10000000". Meanwhile, during this time, 8-bit all "0" data is applied to the B input terminal of the full adder 60-1.
Further, a "1" signal is input to the carry input terminal Cin. Therefore, the above result data is "1024" ~
While changing to "512", the data supplied to the digital filter 7 becomes data obtained by adding "1" to the data S ₇ to _{S 0} applied to the A input terminal of the full adder 60-1.

When the resultant data becomes smaller than "512", the output of the AND gate 22-1 also becomes "1" level, as shown in FIG. 10b. Therefore, “1”
After the signal is applied to the exclusive OR gates 20 ₈ to 20 ₀ , the ROM 23 is addressed from the lowest address to the highest address, while the output “0” of the inverter 28 is applied to the exclusive OR gates 27 ₆ to 20 0 .
₂₇₀ is applied to the carry input terminal Cin of the inverter 31 and full adder 30, respectively. Therefore, between "511" and "0", the A of full adder 60-1 is
Data S ₇ to _{S 0} varying from data “10000000” to 8 bits all “1” are applied to the input terminal,
Further, data "11111111" is applied to the B input terminal, and a "0" signal is applied to the carry input terminal Cin. Therefore, during this period, data obtained by subtracting "1" from the data applied to the A input terminal is supplied to the digital filter 7. Then, the scale frequency code β is set in the full adder 16 again.

This concludes the explanation of one cycle of sawtooth wave generation when no noise is added. and its frequency
o is expressed by the following equation (5).

o=s・α/β (5) Next, the operation in the case of generating a sawtooth wave with added noise will be explained with reference to FIG. In this case, the noise switch is turned on together with the switch for specifying the sawtooth wave on the switch section 2. Therefore, a "1" level control signal is output from the CPU 3 to the noise control unit 60, and as a result, the AND gate 60-
5 is opened and the transfer gate 60-
4 is closed, and a noise signal that irregularly changes between "0" and "1" is applied to the input terminal _B5 of the B input terminal of the full adder 60-1. Then, when the scale frequency code β is set in the full adder 16 and the noise signal is "0" until the cumulative subtraction result data becomes "1024", the B input terminal of the noise control section 60 has the data "11011111". is applied, and a "0" signal is applied to the carry input terminal Cin. Therefore, the data supplied to the digital filter 7 is A of the full adder 60-1.
This data is smaller by data "00100001" than data S ₇ to _{S 0} applied to the input terminal. On the other hand, when the noise signal is "1", the above B input terminal has 8
Since bit all "1" data is applied and a "0" signal is applied to the carry input terminal Cin, the data supplied to the digital filter 7 is data smaller by "1" than the data applied to the A input terminal. becomes.

Next, while the above data _S7 to _S0 sequentially decrease from data "10000000" to 8-bit all "0" data, when the noise signal is "0",
8-bit all “0” data is input to the B input terminal of the full adder 60-1, and the carry input terminal
A “1” signal is input to Cin. Therefore, data larger by "1" than the above data S ₇ to S ₀ is sent to the digital filter 7. On the other hand, when the noise signal is "1", data "00100000" is applied to the B input terminal, and the carry input terminal
A “1” signal is input to Cin. Therefore, the digital filter 7 is supplied with data obtained by adding the data "00100001" to the data S ₇ to S ₀ .

Next, the result data of cumulative subtraction is "1024" to "512"
During this period, when the noise signal is "0", 8-bit all "0" data is applied to the B input terminal of the full adder 60-1, and a "1" signal is applied to the carry input terminal Cin. is applied. Therefore, data obtained by adding "1" to the data S ₇ to _{S 0} is sent to the digital filter 7. On the other hand, when the noise signal is "1", the data "00100000" is applied to the B input terminal, and the "1" signal is applied to the carry input terminal Cin, so at this time, from the above data S ₇ to _{S 0} Data larger by data "00100001" is sent to the digital filter.

Next, the cumulative subtraction result data is “512” to “0”
When the noise signal is "0", data "11011111" is applied to the B input terminal of the full adder 60-1, and "0" is applied to the carry input terminal Cin. A signal is applied. Therefore, data smaller than the data S ₇ to _{S 0} by data "00100001" is supplied to the digital filter at this time. On the other hand, when the noise signal is "1", 8-bit all "1" data is applied to the B input terminal, and a "0" signal is applied to the carry input terminal. Therefore, at this time, data smaller by "1" than the data S ₇ to _{S 0} is supplied to the digital filter 7.

In the waveform diagram of FIG. 11, the amplitude level larger than the reference level of data "10000000",
That is, at the amplitude level of the positive polarity, the solid line indicates when the noise signal is "1", and the broken line indicates when the noise signal is "0". At an amplitude level smaller than the above reference level, that is, an amplitude level with negative polarity, the solid line indicates when the noise signal is "0", and the broken line indicates when the noise signal is "1".
It shows when. In the case of this sawtooth wave as well, when noise is added, the above-mentioned rectangular wave,
Similarly to the case of PWM waves, when the polarity of the generated sawtooth wave is on the positive side, noise is added in the direction of decreasing its amplitude, and when the polarity is on the negative side, noise is added in the direction of increasing its amplitude. will be added. Therefore, the inconvenience that the amplitude of the generated musical tone exceeds the capability of the D/A converter 9 does not occur.

The operations of the wave generator 5 shown in FIG. 8 when generating rectangular waves and PWM waves are almost the same as those of the wave generator 5 shown in FIG. Omitted.

Next, with reference to FIGS. 12 and 13, the configuration of a noise control section that can vary the amount of added noise signal will be described. FIG. 12 shows a modification of the noise control section 6 shown in FIG. In addition, the third
Components common to those in the figures are given the same reference numerals and their explanations will be omitted. As is clear from the figure, in this case, the noise signal is input as 8-bit data _N7 to _N0 . For this reason, in addition to the noise switch, the switch section 2 is provided with, for example, a slide switch that increases or decreases the amount of noise. Each bit data of the noise waveform signals N ₇ to _{N 0} is passed through the corresponding AND gates 6-7 ₇ to 6-7 ₀ and the OR gate 6-
B input terminal of full adder 6-1 via 5 ₇ ~ 6-5 ₀
Applied to _B7 to _B0 . The opening and closing of the AND gates _6-87 to _6-80 are respectively controlled by corresponding bit data of the 8-bit control signal. Further, each bit data of the control signal is further applied to each of the corresponding transfer gates _6-67 to _6-60 via the corresponding inverter _6-87 to _6-80 . 6 ₇ ~6-
Controls opening and closing of ₆₀ . In addition, a polarity inversion signal is input to the transfer gates 6-6 ₇ to 6-6 ₀ via the inverter 6-4, and the output of each transfer gate 6-6 ₇ to 6-6 ₀ is input to the corresponding OR gate. 6-5 ₇ to 6-5 ₀ to input terminals B ₇ to B ₀ .

When noise is to be added using the noise control section 6 having the above configuration, the noise switch is turned on and the slide switch for increasing or decreasing the amount of noise is set to a desired position. Therefore, and gate 6-
Among 7 ₇ to 6-7 ₀ , the AND gate specified by the slide switch is opened, and the inverter 6
The inverter output corresponding to the AND gate opened above among the outputs from −8 ₇ to 6-8 ₀ is “0”
Further, the corresponding transfer gates 6-6 ₇ to 6-6 ₀ are closed. As a result, noise signals N ₇ to _{N 0} of a desired level are output and applied to the B input terminals B ₇ to B ₀ of the full adder 6-1 via the AND gate and OR gate that are being opened. Therefore, the values of the noise signals N ₇ to N ₀ range from the minimum value of the 8-bit all “0” data to the 8-bit all “1” value.
It changes digitally up to the maximum value of , and changes randomly as data within the range according to the setting position of the slide switch, and for the data 0 ₆ to 0 ₀ applied to the A input terminal of the full adder 6-1. It will be added as a variable amount of noise signal. Therefore, musical tones with different tones are generated at any time depending on the amount of the noise signal.

On the other hand, when noise is not to be added, the noise switch is turned off. As a result, a control signal with all bits "0" is output and the AND gate 6-7 ₇
All transfer gates 6-6 7 to 6-6 ₀ are closed, and all transfer gates 6-6 ₇ to 6-6 ₀ are opened.
Therefore, the noise signal N ₇ to _{N 0} is a full adder 6-
The signal is not applied to the B input terminal of No. 1, but a polarity inverted signal is applied instead, and the same operation as described for the noise control section 6 of FIG. 3 is performed.

FIG. 13 shows a modification of the noise control section 60 shown in FIG. 9. Note that the same reference numerals are given to the same components as in FIG. 9, and the explanation thereof will be omitted. In this embodiment as well, the noise signal is 8-bit data N ₇ ~
Output as N ₀ . Therefore, in addition to the noise switch, a slide switch is also provided for adjusting the amount of noise. and the noise signal
Each bit data of _N7 to _N0 is connected to the corresponding AND gate _60-57 to _60-50 and OR gate _60-37.
~ _60-30 to the B input terminals _B7 ~ _B0 of the full adder 60-1. The opening and closing of the AND gates _60-57 to _60-50 are respectively controlled by corresponding bit data of the 8-bit control signal. Further, each bit data of the control signal is further transmitted through corresponding inverters _60-67 to _60-60 to corresponding transfer gates _{60-47 to} 60-60.
_The voltage is applied to each of the transfer gates 60-4 ₇ to 60-4 ₀ to open and close them. Further, the signal _S7 is input to both the transfer gates _60-47 to _60-40 , and the output of each transfer gate _60-47 to _60-40 is connected to the corresponding OR gate _60-37 to 60-40. B input end B ₇ through 3 ₀
Applied to B ₀ .

When adding noise, the noise control section 60 having the above configuration turns on the noise switch and sets the slide switch for varying the amount of noise to a desired position. Therefore, and gate 60
-5 ₇ to 60-5, the AND gate specified by the slide switch is opened, and the inverter output corresponding to the opened AND gate among the outputs of inverters 60-6 ₇ to 60-6 ₀ is opened. becomes the "0" level, and the corresponding transfer gates _60-47 to _60-40 are both closed. In addition, noise signals N ₇ to _{N 0} having a magnitude corresponding to the setting state of the slide switch are output, and are applied to the B input terminals B ₇ to _{B 0} of the full adder 60-1 via the AND gate and OR gate that are being opened. . Therefore, a variable amount of noise signal _N7 to data _S7 to _S0 applied to the A input terminal of the full adder 60-1 is generated.
N ₀ will be added.

On the other hand, when noise is not to be added, at least the noise switch is turned off. As a result, a control signal with all bits at the "0" level is output, AND gates _60-57 to 60-5 are both closed, and transfer gates _60-47 to _60-40 are both opened. As a result, the noise signals N ₇ to _{N 0} are not applied to the B input terminal of the full adder 60-1, and the signal S ₇ is applied instead, which is similar to what was explained regarding the noise control section 60 in FIG. action is performed.

The operations for generating square waves, PWM waves, and sawtooth waves explained above are based on the case where only one key on the keyboard 1 is turned on, but in this example, the music synthesizer is used for eight-note polyphonic. Therefore, even if up to 8 keys are turned on at the same time, the
The circuits shown in Figs. 8, 9, 12, and 13 can simultaneously generate the fundamental wave for each key by time-division processing operation of 8 channels. Omitted.

In addition, in the various embodiments described above, when changing the timbre of a musical sound generated by a fundamental wave such as a rectangular wave, noise is added as another musical sound waveform to the fundamental wave. An arbitrary waveform musical sound waveform may be added. Further, although three types of fundamental waves are used: a rectangular wave, a PWM wave, and a sawtooth wave, other types of fundamental waves such as a triangular wave and a slope wave may be used. Furthermore, in the above embodiment, after setting the initial value β to a full adder, the arithmetic processing was performed to cumulatively subtract a constant value α to obtain the fundamental wave, but after setting the initial value β, the arithmetic processing was performed to cumulatively add a constant value α. In that case, the designs of the circuits shown in FIGS. 2 and 8 may be changed. Furthermore, this invention can be used not only for music synthesizers but also for other electronic musical instruments.

As explained above, when adding a noise waveform to a predetermined musical sound waveform to change the timbre of the generated musical sound, the present invention determines the polarity of the predetermined musical sound waveform and adjusts the tone of the predetermined musical sound according to the polarity. Since an electronic musical instrument is provided in which addition or subtraction of the noise waveform to the waveform is performed by switching between addition and subtraction, the amplitude level of the generated musical tone to which the noise waveform is added exceeds the capability of the digital/analog converter. The occurrence of such inconveniences can be reliably prevented and the desired musical tone can be generated, and when no noise waveform is added, that is, the timbre is not changed, the amplitude level of the generated musical tone is maximized and the S/N ratio is fully considered. There are advantages such as being able to Furthermore, since the amount of noise waveform added can be made variable, there is also the advantage that extremely effective timbre changes can be obtained.

[Brief explanation of the drawing]

1 is a system configuration diagram of an embodiment in which the present invention is applied to a music synthesizer, FIG. 2 is a specific circuit diagram of the wave generator 5, FIG. 3 is a specific circuit diagram of the noise control unit 6, and FIG. 4 is a specific circuit diagram of the wave generator 5. The diagram is ROM
Figure 5 is a time chart explaining the rectangular wave generation operation, Figure 6 is a diagram showing the change in amplitude level when noise is added during square wave generation, and Figure 7 is a diagram of the PWM wave. A time chart explaining the generation operation, FIG. 8 is a specific circuit diagram of the wave generator 5 according to another embodiment, FIG. 9 is a specific circuit diagram of the noise control section 60 of another embodiment, and FIG.
Figure 0 is a time chart explaining the sawtooth wave generation operation, Figure 11 is a diagram showing the change in amplitude level when noise is added to the sawtooth wave, and Figure 12 is a diagram showing the change in amplitude level when noise is added to the sawtooth wave.
A circuit configuration diagram showing a modification of the noise control unit 6 shown in the figure, FIG. 13 is a circuit configuration diagram showing a modification of the noise control unit 6 shown in FIG.
FIG. 3 is a circuit configuration diagram showing a modification example of No. 0; 1...keyboard, 2...switch section, 3...
CPU, 4...ROM, 5...Wave generator, 6...Noise control section, 7...Digital filter, 8...Envelope generator, 9...
Digital/analog converter, 10...amplifier,
15, 16, 30...Full adder, 17...Shift register, 18 ₁₅ to 18 ₀ ...And gate,
20 ₈ to 20 ₀ , 27 ₆ to 27 ₀ ... exclusive OR gate, 21-7 to 21-1 ... inverter, 22-
6-22-1...and gate, 23...
ROM, 24 ₆ ~ 24 ₀ ...Or Gate, 26,2
9,33,34 ₇ ~34 ₀ ,35,46 ₇ ~46 ₀ ...
...transfer gate, 31...inverter,
32... Polarity inversion circuit, 41, 45... Subtraction circuit, 42... Multiplication circuit, 43... Addition/subtraction circuit, 4
4...Division circuit, _G1 , _G2 ...Gate circuit, 6-
1,60-1...Full adder.

Claims (1)

[Scope of Claims] 1. A musical sound waveform generating means for generating a plurality of types of musical sound waveforms; an addition/subtracting means for adding or subtracting a predetermined musical sound waveform and a noise waveform among the musical sound waveforms generated by the musical sound waveform generating means; polarity determining means for determining the polarity of the amplitude value of the predetermined musical sound waveform; while the polarity determining means subtracts the noise waveform from the predetermined musical sound waveform while determining a positive polarity; control means for controlling the operation of the addition/subtraction means so as to add the predetermined musical sound waveform and the noise waveform while determining negative polarity; and musical sound generation means for generating a musical sound based on the output of the addition/subtraction means. An electronic musical instrument characterized by being equipped with. 2. The electronic musical instrument according to claim 1, wherein the musical sound waveform generating means includes variable means for varying the amplitude value of the noise waveform supplied to the addition/subtraction means.