JPH0230033B2 - - Google Patents

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a musical tone signal generating device, and more particularly to a musical tone signal generating device that generates a musical tone signal whose spectral components change over time by sequentially switching and generating a plurality of different musical waveforms. Prior Art Japanese Patent Application Laid-Open No. 58-95790 discloses a musical tone signal generating device that can generate a musical tone signal whose spectral components change over time by sequentially switching and reading out a plurality of different musical waveforms stored in a waveform memory. has been done. In this case, the tone waveform to be read from the waveform memory is switched when the same tone waveform is repeatedly read out for a predetermined number of cycles. Also, when switching musical waveforms, interpolation is performed that changes over time between the same sample points of both waveforms in order to smoothly transition from the preceding musical waveform to the next musical waveform. The interpolation is performed between a predetermined number of cycles in which the same tone waveform is repeatedly read out. In the conventional technology described above, the switching interval of the musical sound waveform is always fixed at a predetermined number of cycles, so the switching interval of the musical sound waveform changes depending on the frequency of the musical sound to be generated, and accordingly The disadvantage is that the time required for interpolation varies. That is, the higher the frequency of a musical tone, the faster the musical sound waveform changes, causing the problem that the time-varying effect of the spectral components becomes non-uniform depending on the pitch. Furthermore, the higher the frequency of a musical tone, the faster interpolation such as waveform switching will be performed, and the effect of smoothly transitioning waveforms will be diminished. Purpose of the invention This invention has been made in view of the above points,
It is an object of the present invention to provide a musical tone signal generating device which controls switching of musical waveforms without being affected by the frequency of musical tones to be generated and eliminates the above-mentioned drawbacks. Summary of the Invention A musical tone signal generating device according to the present invention divides a plurality of different musical sound waveforms sampled discretely between the start and end of a musical tone into a plurality of sample points, and generates a waveform corresponding to each sample point. a waveform storage means that stores data; a readout means that has a plurality of time-sharing processing channels and repeatedly reads out waveform data of a predetermined musical sound waveform from the waveform storage means according to the musical sound frequency to be generated; and the waveform storage means a waveform specifying means for temporally switching and specifying a musical sound waveform to be read from, and a musical sound waveform of the time-division processing channel for two channels corresponding to the preceding musical sound waveform and the next musical sound waveform when switching the musical sound waveform to be read out; interpolation means for weighting, a counting means for generating an independent time function independent of musical tone frequency in order to set the time change of weighting in said interpolation means, and said waveform designation according to the output of said counting means. switching control means for controlling waveform switching in the means, and the interpolation means weights the preceding musical sound waveform with a characteristic of gradually attenuating it in accordance with the count output of the counting means, The waveform is weighted with a characteristic that gradually rises, so that the waveform transitions smoothly. The counting means generates said time function independently of the musical tone frequency to be generated. In the interpolation means, a time change in weighting is set according to this time function.
The switching control means controls waveform switching at a predetermined time point according to the output of the counting means, that is, the time function. The waveform designation means switches the designation of musical waveforms under the control of the switching control means. In this way, the switching and interpolation of musical waveforms is controlled according to a unique time function that is independent of the musical frequency, producing a time-varying effect on spectral components that is independent of changes in pitch, as well as However, smooth interpolation (waveform transition) is guaranteed. However, in setting the above-mentioned time function, this invention
Of course, this does not necessarily preclude some consideration of pitch factors. By the way, the present invention is not limited to a system in which a musical sound waveform to be interpolated is formed by reading out a musical sound waveform from a waveform storage means that stores a plurality of different discretely sampled musical sound waveforms, but the present invention is not limited to a system in which a musical sound waveform to be interpolated is formed. It can also be advantageously applied to systems that form waveforms. An example of a tone waveform forming method using such parameters is a harmonic synthesis method. Conventionally, in order to temporally change the spectrum of a musical tone signal in this harmonic synthesis method, a large number of harmonic coefficient sets that set the relative amplitude of each harmonic are prepared, and these coefficient sets are temporally changed. I switched to , and used it for musical waveform formation calculations. As a result, the capacity of a storage device for storing harmonic coefficients has increased, and it has also become difficult to obtain smooth temporal changes in musical waveforms. Therefore, if a parametric method is applied as the musical sound waveform forming means in this invention, the time change of the musical sound waveform by interpolation according to the present invention will be realized in harmonic synthesis calculation or other parameter method. It has a great effect. That is, according to the present invention, instead of the above-mentioned waveform storage means and reading means, a musical waveform having a shape determined by parameters is formed, and the musical tone is generated in accordance with a phase specified by phase data. musical sound waveform forming means for forming a waveform; and parameter storage means for storing the parameters for determining the shape of each musical sound waveform, with respect to a plurality of different musical sound waveforms sampled discretely from the start to the end of musical tones. and a phase data generating means that generates the phase data that changes according to the frequency of the musical tone to be generated and supplies it to the musical sound waveform forming means. In this case, the above-mentioned waveform designating means temporally switches and designates the musical sound waveform to be formed by the musical sound waveform forming means, reads out the parameters corresponding to the designated musical sound waveform from the parameter storage means, and forms the musical sound waveform by reading out the parameters corresponding to the designated musical sound waveform from the parameter storage means. so as to give it to the forming means. Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. First, the principle of musical tone signal generation employed in the embodiment described below will be explained with reference to FIG. In FIG. 1a, for convenience, a musical sound waveform that should be prepared in advance in the waveform memory is schematically shown using only an amplitude envelope. Since the musical sound waveform of a predetermined period (attack portion) from the start of sound generation changes in a complicated manner, it is difficult to imitate a high-quality attack portion waveform by repeatedly reading out the one-period waveform. Therefore, the musical sound waveform of this attack part is obtained by sampling the continuous multi-cycle waveform as it is and storing it in the waveform memory.For the entire sound generation period after the attack part, there are several different musical sound waveforms (one cycle). are sampled discretely and stored in the waveform memory.Figure 1a
Then, each 1 sampled discretely like that
The periodic waveforms are shown as SEG1 to SEG5, and these will be called segment waveforms for convenience. The basic method of reading out waveforms from the waveform memory in which waveforms are stored as described above is to first read out all the waveforms of the attack section continuously, and then read out the segment waveform SEG1 at a certain timing according to a waveform switching command as described later. ~SEG5 are selected in order, and one cycle of the selected segment waveform is repeatedly read out. For example, after reading out the attack waveform, the first segment waveform SEG1 is repeatedly read out for a certain period of time, then the second segment waveform SEG2 is switched to and read out repeatedly, and thereafter the segment waveforms are sequentially switched. When switching segment waveforms, interpolation techniques are used to provide a smooth transition from a preceding waveform to the next waveform. In that case, in addition to the basic readout method described above, at least the preceding segment waveform and the following segment waveform are read out together in the interval where interpolation is to be performed, and both are weighted respectively according to an appropriate interpolation function. do. As an example, the entire segment waveform switching interval corresponds to the interpolation interval, and the first segment waveform
When reading SEG1, use the second segment waveform
SEG2 is also read out, and at the next switching time, the second and third segment waveforms SEG2,
SEG3 is read out together, and then adjacent segment waveforms are read out together while sequentially switching in the same manner. An example of an interpolation function is shown in FIG. 1b. The solid line indicates the interpolation function IPF1 for the first series,
The broken line indicates the interpolation function IPF2 for the second series. 1st
The series corresponds to one of the two segment waveforms read out for interpolation as described above, and the second series corresponds to the other.
These interpolation functions IPF1 and IPF2 indicate the amount of weighting of the waveform amplitude of each series, and the minimum value is zero (indicating that the waveform is not output). In the attack part that does not perform interpolation, the first series of interpolation functions
Keep IPF1 at maximum value and use the second series interpolation function
Keep IPF2 at minimum value. After the attack portion ends, each of the interpolation functions IPF1 and IPF2 changes over time with predetermined characteristics during a period in which segment waveforms SEG1 to SEG5 are to be interpolated. Both interpolation functions
IPF1 and IPF2 change with opposite characteristics, so that when the weighting of one series gradually decreases, the weighting of the other series gradually increases, thereby achieving a smooth waveform transition. In Figure 1b, the interpolation functions IPF1, IPF
2 shows linear interpolation characteristics, but it is of course not limited to this. t ₁ , t ₂ , t ₃ , and t ₄ each indicate a separate interpolation interval, and the interpolation function of each series is changed each time the interpolation interval is switched.
The slopes of IPF1 and IPF2 are switched alternately. In the interpolation interval _t1 , interpolation is performed to smoothly transition from the segment waveform SEG1 to SEG2. In this case, segment waveform SEG1
is repeatedly read out in the first series, and segment waveform SEG2 is repeatedly read out in the second series. Then, while the first series interpolation function IPF1 gradually decreases from the maximum value, the second series interpolation function IPF
2 gradually increases from the minimum value. The multi-period waveform signal of the segment waveform SEG1 repeatedly read out in the first series is weighted (amplitude controlled) by this interpolation function IPF1, and is repeatedly read out in the second series by the interpolation function IPF2. segment waveform
The multi-period waveform signal of SEG2 is weighted.
By mixing the waveform signals of both series weighted with opposite characteristics in this way, the segment waveform
A musical tone signal whose waveform changes smoothly over time from SEG1 to segment waveform SEG2 is obtained. In the next interpolation section _t2 , interpolation is performed to smoothly transition from the segment waveform SEG2 to SEG3.
In this case, the segment waveform SEG2 is repeatedly read out in the second series following the previous time;
In the first series, segment waveforms SEG1 to SEG3
This is then read out repeatedly. Then, the slopes of the interpolation functions IPF1 and IPF2 are respectively switched to the opposite direction from the previous time. In the other interpolation intervals t ₃ and t ₄ , the segment waveform of one series is switched as well as the interpolation function IPF as described above.
1. The slope of IPF2 switches to the opposite direction. Figure 1b
The numbers of segment waveforms SEG1 to SEG5 used in each series in each interpolation interval _t1 to _t4 are also written. FIG. 2 shows an embodiment of an electronic musical instrument to which the musical tone signal generating device according to the present invention is applied.
In this electronic musical instrument, musical tone signals are generated according to the musical tone signal generation principle as described above with reference to FIG. In FIG. 2, a keyboard 10 includes a number of keys for specifying the pitch of musical tones to be generated. The key assigner 11 detects the press or release of each key,
A process of assigning a pressed key to one of a plurality of musical tone generation channels is performed. As an example, the maximum number of notes that can be produced simultaneously is 12, and the key assigner 11 assigns a pressed key to any of the 12 channels. a key code KC that identifies the key assigned to each channel;
The key-on signal KON, which indicates whether or not the key press continues, and the key-on pulse KONP, which is instantaneously generated when the key press starts, are sent to the key assigner in a time-sharing manner for each channel according to predetermined time-sharing timing. It is output from 11. An example of time division channel timing is shown in FIG. 3. Each channel timing 1~
12 is formed in synchronization with clock pulse _φ2 .
Two subchannel timings ₁ and ₂ are formed by dividing the time slot of each channel timing into two in synchronization with a clock pulse φ1 having twice the frequency of the clock pulse φ2. These subchannel timings 1 and 2 correspond to the first and second sequences in the interpolation described above. That is, in this embodiment, the time slot of one channel is divided into two, and the segment waveforms of the first series (subchannel 1) and the second series (subchannel 2) for interpolation are read out in a time-division manner.
CH1 to CH12 are channel timing signals, which are generated corresponding to channel timings 1 to 12, respectively. Each clock pulse φ ₁ , φ ₂ and signal
CH1 to CH12 are generated from the timing signal generator 12 and supplied to predetermined circuits in the electronic musical instrument shown in FIG. 2, respectively. The phase generator 13 specifies the musical sound waveform to be read out from the waveform memory 14 and reads out this musical sound waveform according to the musical sound frequency to be generated. The signal is generated in a time-division manner in a total of 24 time slots for each subchannel 1 to 12. In terms of correspondence with the configuration of the present invention, there is a reading means for repeatedly reading one cycle of waveform data from the waveform storage means according to the musical tone frequency to be generated, and a musical waveform to be read from the waveform storage means by temporally switching and specifying. This phase generator 13 includes a waveform specifying means for specifying a waveform. The key code is sent to the phase generator 13 from the key assigner 11.
KC, key-on pulse KONP, key-on signal
KON is given, and the musical tone frequency to be generated and the start timing of sound generation are specified by these. The waveform memory 14 stores a plurality of sets of the above-mentioned attack section full waveform and a plurality of segment waveforms corresponding to each timbre. Specifically, as is well known, each waveform is divided into a plurality of sample points, and the waveform data corresponding to each sample point (for example, waveform amplitude data of the sample point) is stored. An example of the memory map in this waveform memory 14 is shown schematically in FIG. Regarding timbre A, waveform data of all waveforms of the attack section are stored in the address range from address A ₀ to A ₁ -1, and from address A ₁
The waveform data for one period of the first segment waveform SEG1 is stored in the address range from A ₂ -1,
Below, each segment waveform in the specified address range
SEG2, SEG3... are stored sequentially. The same applies to the other tones B, C, and so on. A ₀ , A ₁ , A ₂ ..., B ₀ , B ₁ , B ₂ ..., C ₀ ,
C ₁ , C ₂ ... are the start addresses of each address range, A ₀ , B ₀ , C ₀ ... are the start addresses of the attack section, and A ₁ , B ₁ , C ₁ ... are the first segment waveforms. Start address of SEG1, A ₂ , B ₂ ,
C ₂ ... is the start address of the second segment waveform SEG2. As an example, one period waveform is 256
The maximum number of cycles of the entire attack waveform is 256 cycles. still,
As shown in the figure, the number of cycles of the entire attack section waveform differs depending on the tone. It should be noted that each sample point within one period (256 in total) can be expressed by just an 8-bit binary code. Therefore, each sample point within this one cycle is specified by the lowest 8 bits of address data MADR, and each start address A ₁ , A ₂ ..., B ₁ , B ₂ ..., The lowest 8 bits of C ₁ , C ₂ . . . are all "0", and their upper bits have a value valid for specifying each segment waveform. Returning to FIG. 2, the timbre selection circuit 15 outputs timbre selection information TC and supplies it to the phase generator 13, waveform memory 14, crossfade control circuit 16, and envelope generator 17. The crossfade control circuit 16 is for generating an interpolation function for weighting musical waveform signals of two series (subchannels) related to the same sounding channel with opposite characteristics. To show the correspondence with the structure of the present invention, when switching the musical sound waveform to be read, a part of the interpolation means (particularly means for generating the interpolation function); and counting means for generating a time function for setting the time change of weighting in the interpolation means.
The crossfade control circuit 16 includes a switching control means for controlling waveform switching in the waveform specifying means in accordance with the output of the counting means. An attack end signal ATEND indicating that reading of all waveforms of the attack section has been completed and an inverted attack signal indicating that reading of the attack section is not being performed are applied from the phase generator 13 to the crossfade control circuit 16. When the crossfade control circuit 16 confirms that the waveform readout of the attack section is completed based on these signals, it starts generating a predetermined interpolation function. The interpolation function is output from the circuit 16 as crossfade curve data CF, and is applied to a multiplier 18 for weighting calculation. Also, the waveform switching command signal WCHG is applied to circuit 1.
6 and is applied to the phase generator 13. The multiplier 18 for weighting calculations and the adder 20 that adds the output of the multiplier 18 to a signal delayed by one period of the clock pulse φ ₁ in the delay circuit 19 and an undelayed signal form part of the interpolation means. be. Musical waveform data is read out in a time-division manner from the waveform memory 14 in accordance with each sub-channel timing for each channel, and similarly, musical waveform data is read out in a time-division manner in synchronization with each sub-channel timing for each channel from the crossfade control circuit 16. The crossfade curve data CF is read out. Therefore, multiplier 1
In step 8, the musical waveforms read out in a time-division manner corresponding to each subchannel of each channel are respectively weighted according to the corresponding crossfade curve data CF (ie, interpolation function). 1
An adder 20 adds weighted musical waveform data of two subchannels regarding one musical tone generation channel. That is, when the tone waveform signal of the first subchannel is delayed and inputted from the delay circuit 19 to the adder 20, the tone waveform data of the second subchannel of the same channel is inputted to the adder 20.
It is designed to join the other inputs of 0. Thus, the time slot of one channel (time slot corresponding to one period of clock pulse _φ2 )
In the latter half of the process, the two weighted tone waveform data for that channel are mixed. The envelope generator 17 is connected to the key assigner 11
An amplitude envelope waveform signal is generated for each channel in a time-division manner according to the key-on signal KON and the key-on pulse KONP given from the channel. This envelope waveform maintains a constant level while the key is being pressed, and exhibits a decay envelope characteristic in response to the key being released. Since all the waveforms of the attack part stored in the waveform memory 14 have been given attack envelope characteristics in advance, there is no need for the envelope generator 17 to give them attack envelope characteristics. The outputs of the adder 20 and the envelope generator 17 are input to a multiplier 21, and amplitude envelopes corresponding to key presses and key releases are applied to the musical waveform data of each channel in a time-division manner. The output of the multiplier 21 is sent to latch circuits 22-1 to 22- which are provided in parallel corresponding to each channel.
12 data inputs. Each latch circuit 2
The latch control inputs L from 2-1 to 22-12 include
Channel timing signal CH1 corresponding to each
-AND circuits 23-1 to 23 that perform AND logic between CH12 and inverted _{signal 2 of} clock pulse φ2
-12 outputs are given respectively. In this manner, the output of the multiplier 21 is latched into the corresponding latch circuits 22-1 to 22-12 in the latter half of the time-division time slots of each channel. As mentioned above, the adder 20 adds the two weighted tone waveform data for each channel in the latter half time slot of each channel timing 1 to 12 (timing of subchannel 2), so the summation result corresponds to the summation result. The data is latched in each latch circuit 22-1 to 2-12. In this way, the time division of the tone waveform data of each channel is canceled. The outputs of the latch circuits 22-1 to 22-12 are input to the latch circuits 24-1 to 24-12.
Pitch synchronization pulses PSP1 to PSP12 outputted from the phase generator 13 are applied to the latch control inputs L of each of the latch circuits 24-1 to 24-12. The pitch synchronization pulses PSP1 to PSP12 are pulses synchronized with the frequencies of musical tones assigned to each channel, and by latching the musical waveform data accordingly, aharmonic clock components are removed. Each latch circuit 24-1 to 24-
The outputs of 12 are given to an adder 25 and summed, and then converted to an analog signal by a digital/analog converter 26 and sent to a sound system 27. Next, details of each part in FIG. 2 will be explained. FIG. 5 shows an example of the phase generator 13.
A portion indicated by the reference numeral 28 corresponds to a reading means for repeatedly reading one period of waveform data. The key code KC of each channel given in a time-sharing manner from the key assigner 11 is set in the latch circuit 29.
latch circuits 29-1 to 29-12 corresponding to each channel according to channel timing signals CH1 to CH12.
are respectively latched. The variable oscillators 30-1 to 30-12 provided independently for each channel are
Latch circuits 29-1 to 29-1 corresponding to each
Note clock pulses NC1 to NC12 corresponding to the musical tone frequencies of the pressed keys assigned to each channel are generated in accordance with the key code KC given from 2. Note clock pulse NC1~NC12
is applied to a time division control circuit 31, sampled and multiplexed in a time division manner according to channel timing signals CH1 to CH12, and a time division multiplexed output is taken out via a line 32. An example of the time division control circuit 31 is as shown in FIG.
Note clock pulses NC1 to NC12 of each channel are input to set input S 3-12, respectively. The outputs Q of the flip-flops 33-1 to 33-12 and channel timing signals CH1 to CE12 are input to the AND circuits 34-1 to 34-12, respectively, and the outputs are multiplexed by the OR circuit 350 and guided to the line 32. At the same time, they are returned to the reset inputs R of the corresponding flip-flops 33-1 to 33-12. Also, flip-flop 33
-1 to 33-12 output Q is pitch synchronization pulse
It is output as PSP1~PSP2, and as mentioned above, the second
It is applied to latch circuits 24-1 to 24-12 in the figure. Flip-flops 33-1 to 33-12
is set at the rising edge of the signal at the set input S, and reset at the falling edge of the signal at the reset input R. FIG. 7 shows an example of input/output signals of each part in FIG. 6. As is clear from the figure, note clock pulses NC1 to NC2 of the keys assigned to each channel are asynchronous to the channel timing, and these pulses NC1 to NC12 are asynchronous to the channel timing.
At the rising edge of the flip-flop 33-1 to 33-
12, and the corresponding AND circuit 34-1
After that, pulses are output from the AND circuits 34-1 to 34-12 in response to the first channel timing signals CH1 to CH12, and the flip-flops 33-1 to 33 are activated at the falling edge of this output pulse. -12 is reset.
Then, the note clock pulse NC1~NC
Channel timing signal CH at the same frequency as 12
A new note clock pulse synchronized with CH1 to CH12 is obtained from each AND circuit 34-1 to 34-12. In this way, a note clock pulse corresponding to the musical tone frequency of the key assigned to each channel (an integral multiple thereof) is outputted to the line 32 in accordance with the time division timing of the corresponding channel. Returning to FIG. 5, the note clock pulses of each channel applied to the line 32 are input to a counter 38 consisting of an adder 35, a gate 36, and a shift register 37, and the number of pulses is counted in a time-division manner for each channel. Ru. shift register 37
has 24 stages/8 bits, and is shift-controlled by a clock pulse _φ1 synchronized with the subchannel timing. The output of shift register 37 is provided to adder 35 and summed with the note clock pulse on line 32. The addition output is stored in shift register 37 via gate 36. The 24 stages of the shift register 37 correspond to 2 subchannels of each of the 12 channels.
Count values for one channel are stored in two stages (corresponding to two subchannels), respectively. The gate 36 is instantly closed by the key-on pulse KONP just before the start of sound, and the shift register 3
Clear the memory for the corresponding two stages in 7. Since the shift register 37 has a capacity of 8 bits per stage, the counter 38 has a capacity of 8 bits per stage.
56 counts are performed in time division for 24 channels (actually 12 channels). The output of the gate 36 is taken out as the counter output of the counter 38, and is applied to the waveform memory 14 as the lowest 8 bits of the address data MADR. By the count output of the counter 38, each sample point of a one-period waveform consisting of 256 sample points can be sequentially read out. Count is notebook clock pulse NC
1 to NC12, the reading is performed in accordance with the musical tone frequency to be generated. The address data MADR for reading the waveform memory 14 is N+8 bits (N>8),
As described above, the lowest 8 bits sequentially designate sample points within one cycle of the waveform, and the upper N bits designate one cycle of the waveform. The upper N bits of address data for specifying the waveform are given via an adder 41 from a start address generation circuit 40 corresponding to waveform specifying means. The start address generation circuit 40 generates the start addresses A ₀ , B ₀ , C ₀ of all waveforms of the attack section mentioned above.
...and the start address A ₁ of each segment waveform,
A ₂ ... is generated. An attack section period number counter 39 is provided to specify each one-cycle waveform within the entire attack section waveform, and the output of this counter 39 and the attack section start address A ₀ , B ₀ , C ₀ . . . An adder 41 is provided to specify the absolute address of each one-cycle waveform in the entire waveform of the attack section by adding and synthesizing the waveforms. The hardware configuration of the attack section period number counter 39 is the same as that of the counter 38 described above, and the adder 43,
It includes a gate 44 and a shift register 45.
This counter 39 counts the carry-out signal CRY from the most significant bit of the adder 35 in a time-division manner for each channel. This carry-out signal CRY is generated every time a certain channel of the counter 38 counts 256 note clock pulses (that is, every time one cycle of the waveform is read), and by counting this, the number of cycles of the attack section can be counted. can do. The output of the counter 39 is applied to a gate 42, and the gate 42 is opened only during reading of all waveforms in the attack section by an attack signal AT, which will be described later.
1 is given the counter output. The lowest 8 bits of the N-bit start address data generated by the start address generation circuit 40 are input to the other input of the adder 41. Of the N-bit start address data, the 8-bit output data of the adder 41 is located below the most significant N-8 bits of data that were not input to the adder 41, and both data are used to determine the most significant address data MADR. The upper N bits are configured. The count value of the counter 39 indicates the number of cycles counted from the first cycle of the entire waveform of the attack section, and on the other hand, the start address A ₀ ,
B ₀ , C ₀ . . . indicate the first absolute address of the entire attack waveform in the waveform memory 14. Therefore, by adding the two, it is possible to specify the first absolute address for each period of the entire waveform of the attack section (that is, specify each one-period waveform). The attack end detection circuit 46 counts the carryout signal CRY given from the counter 38 and checks whether reading of all waveforms of the attack section has been completed, an example of which is shown in FIG. In FIG. 8, the attack section period number memory 47
The number of cycles of the entire waveform of the attack section is stored for each timbre, and the number of cycles data ATN is read out in accordance with the timbre selection information TC. Subtractor 48, gate 4
9. A counter 52 consisting of a selector 50 and a 24-stage/8-bit shift register 51 counts down the number of cycles each time one cycle of the attack waveform is read out, and performs the down-count in a time-division manner for each channel. . The selector 50 selects the cycle number data ATN read from the memory 47 when the key-on pulse KONP is generated via the B input, and takes it into the shift register 51. At other times, data to be applied to the A input of the selector 50 is selected from the final stage of the shift register 51 via the subtracter 48 and is applied to the shift register 51. A carry-out signal CRY output from adder 35 in FIG. 5 is input to gate 49. Gate 49 is enabled during attack by attack signal AT and carries out signal CRY.
is given to the subtracter 48. The subtracter 48 subtracts 1 from the output data of the shift register 51 when the carry-out signal CRY is applied. In this way, data indicating the number of cycles of the entire attack section waveform is initially entered into the shift register 51, and from then on, the data is subtracted by 1 each time one cycle of the attack section waveform is read, and finally reading of the entire attack section waveform is completed. When the data is all "0". The output of the counter 52 is taken out from the selector 50 and applied to an all "0" detection circuit 520. The all “0” detection circuit 520 is the selector 50
It detects whether the count output data given from is all "0" or not, and outputs a signal "1" when all "0". The output signal of this detection circuit 520 is output as an inverted attack signal, and the signal inverted by the inverter 53 is the attack signal.
Output as AT. Therefore, during the attack, the attack signal AT is "1" and the inverted attack signal is "0", but when the attack is completed, the AT is inverted and becomes "0" and becomes "1". Delay circuit 5
4 sets a signal delay of one cycle of time-division channel timing using a clock pulse _{φ 2 ×} 12 having a period 12 times that of the clock pulse φ 2, and delays the attack signal AT to output the AND circuit 55.
give to An inverted attack signal is given to the other input of the AND circuit 55, and when the signal switches from "0" to "1", it is activated during one time slot (two subchannel time slots) corresponding to that channel. The output of the AND circuit 55 becomes “1”, which is the attack end signal.
Output as ATEND. Furthermore, when the attack is completed, the gate 4 is turned on by the attack signal AT being “0”.
9 is closed and no further down-counting is performed. Therefore, the count value of the counter 52 maintains all "0" except at the time of attack. The operation example in Fig. 8 is shown for one channel.
It will look like Figure 1a. Returning to FIG. 5, start address generation circuit 4
0 selects a set of start addresses in response to tone selection information TC, generates a start address for the attack section in response to key-on pulse KONP, and sequentially switches the start address of each segment waveform in response to waveform switching command signal WCHG. This is something that occurs. An example of this start address generation circuit 40 is shown in FIG. In FIG. 9, the start address memory 56
There are multiple sets of start addresses A ₀ , A ₁ , A 2 ..., B ₀ , _{B 1 ,} B ₂ corresponding to each tone A, B, C...
..., C ₀ , C ₁ , C ₂ ... are stored in advance, respectively, and a set of start addresses (for example, in the case of tone A, A ₀ , A ₁ , A ₂
) is selected. 24 stage shift register 57, selectors 58, 59, 60, adder 61,
A loop including gate 62 constitutes a counter, and the count value taken out from gate 62 in this loop is applied to the address input of start address memory 56. The start address memory 56 sequentially reads out a selected set of start address data (for example, A ₀ , A ₁ , A _{2 .} . . ) according to the count value applied to the address input. That is, when the count value given from the gate 62 is "0", the start address _A0 of the attack section is read out, and when it is "1", the first segment waveform is read out.
Read the start address A ₁ of SEG1 and set it to “2”
Then, read out the start address _A2 of the second segment waveform SEG2. In this way, the start address data read out from the start address memory 56 specifies the waveform to be read out from the waveform memory 14 (FIG. 2). The gate 62 is enabled by the inverted signal of the key-on pulse KONP, and the gate 62 closes in the channel in which the key-on pulse KONP is generated, and the stored contents of the shift register 57 corresponding to the channel are cleared. The output of the final stage of the shift register 57 is applied to the C input of the selector 58, and is also applied to the A input and B input of the selector 58 via delay circuits 63 and 64, respectively. The delay circuit 63 receives a clock pulse φ ₁
A clock pulse φ ₁ with a period equivalent to 23 periods of
The delay is controlled by ×23, and the delay circuit 64 is delayed by the clock pulse _φ1 . The A selection input SA of the selector 58 is supplied with the output of an AND circuit 65 which performs AND logic on the clock pulse φ ₂ and the waveform switching command signal WCHG. The B selection input SB has the inverted signal of clock pulse _φ2 and the signal
The output of an AND circuit 66 which performs the AND logic of WCHG is given. C selection input SC has a signal
A signal obtained by inverting WCHG by an inverter 67 is provided. The output of selector 58 is given to the A input of selector 59. A numerical value "1" is given to the B input of the selector 59, and a numerical value "2" is given to the C input. The A selection input SA of the selector 59 is given a signal obtained by inverting the attack end signal ATEND by an inverter 68, and the B selection input SB is given the output of an AND circuit 69 which performs AND logic on the clock pulse φ ₂ and the signal ATEND. C selection input SC
is the inverted signal of clock pulse _φ2 and the signal
The AND logic of ATEND and the output of the AND circuit 70 are given. The output of selector 59 is given to adder 61. A waveform switching command signal WCHG is given to the other input of the adder 61.
1 is added to the output data of the selector 59 each time becomes "1". The output of the adder 61 is the selector 6
0 to the B input. The output of the sequence return destination memory 71 is applied to the A input of the selector 60. Further, the output of the adder 61 is given to the final segment detection circuit 61A, and the output signal of this detection circuit 61A is input to the A selection input of the selector 60.
SA, and its output signal is sent to the inverter 72.
The inverted signal is applied to the B selection input SB.
The output of selector 60 is applied to shift register 57 via gate 62. Since the shift register 57 has 24 stages and the operating clock pulse is _φ1 , the counting operation is performed in a time-division manner in a total of 24 time slots for each subchannel of each channel 1 to 12.
The counting operation for one channel will be explained below. First, as mentioned above, the key-on pulse
When KONP occurs, gate 62 is closed,
The contents of the two stages of the shift register 57 corresponding to the channel are all cleared to "0". As described later, the waveform switching command signal WCHG is not generated during the attack, so the selector 5
8 always selects C input. Further, during the attack, the attack end signal ATEND is "0", and the selector 59 selects the A input. Further, the output signal of the final segment detection circuit 61A is "0" until the reading of the segment waveform of the final rank is completed, and the selector 60 selects the B input.
Therefore, the contents of the cleared shift register 57 are transferred to the same channel timing via the C input of the selector 58, the A input of 59, the adder 61, the B input of the selector 60, and the gate 62 with a delay of one channel timing cycle. Cycle in sync.
Therefore, starting address memory 5 from gate 62
The counter value given to 6 is maintained at "0", and data indicating the start address (for example, A ₀ ) of the attack section is read out accordingly. When the attack is completed, the attack end signal ATEND is generated from the attack end detection circuit 46 of FIG. 8 only once at the channel timing (time slot for two subchannels) as described above. As a result, the AND circuits 69 and 70 are enabled, and the B input of the selector 59 is selected in the first half time slot (that is, the subchannel 1 timing when clock pulse φ ₂ becomes "1"), and the numerical data "1" is transferred to the shift register. 57. Furthermore, in the second half time slot (that is, subchannel 2 where clock pulse φ ₂ is “0”)
At this timing), the C input of the selector 59 is selected, and numerical data "2" is stored in the shift register 57. In this manner, after the attack is completed, the numerical value "1" is initially set corresponding to subchannel 1, and the numerical value "2" is set corresponding to subchannel 2. As a result, from the start address memory 56, the start address (for example, A ₁ ) of the first segment waveform SEG1 corresponding to subchannel 1 is stored.
Data indicating the start address (for example, A ₂ ) of the second segment waveform SEG2 corresponding to subchannel 2 is read out. This state is maintained until the next waveform switching command signal WCHG is applied. Furthermore, gate 6
An example of a change in the count value for one channel (two subchannels) outputted from No. 2 is shown in FIG. 11b. The waveform switching command signal WCHG is generated by being alternately switched in correspondence to one of two subchannels related to one channel, as will be described later. As shown in FIG. 11b, first, it occurs corresponding to subchannel 1, then it occurs corresponding to subchannel 2, and thereafter, it occurs alternately. Therefore, in the circuit of FIG. 9, the counting operation in response to the waveform switching command signal WCHG is performed for one of the two subchannels. When the switching command signal WCHG is generated corresponding to the first half channel time slot, that is, subchannel 1, the AND circuit 65 is enabled in response to the clock pulse φ ₂ being "1", but the AND circuit 66 is not enabled. . Therefore, in that case,
The output of the delay circuit 63 is selected via the A input of the selector 58, and 1 is added to this data by the adder 61 using the signal WCHG. The delay circuit 63 outputs data 23 time slots ago at subchannel timing, and this is count data of subchannel 2 of the previous cycle regarding the same channel. The value added by 1 to the count value of subchannel 2 becomes the new count value of subchannel 1. In this case, subchannel 2 is greater than the count value of subchannel 1 by 1, and therefore, the count value of subchannel 1 is substantially the same as being added by 2. For example, as mentioned above, when the count value of subchannel 1 is "1" and the count value of subchannel 2 is "2", the first waveform switching command signal
When WCHG is given corresponding to subchannel 1, 1 is added to the count value "2" of subchannel 2 in the previous cycle (that is, the output of delay circuit 63) at the timing of subchannel 1, and
The count value of subchannel 1 changes to "3". In this case, at the timing of subchannel 2, the shift register 5
The output of No. 7 is selected as is, and the count value is not increased. Therefore, the count value of subchannel 2 remains "2". In this way, the read address of subchannel 1 is changed by the first waveform switching command signal WCHG, and the start address of the third segment waveform SEG3 (for example,
A ₃ ) is read from memory 56. On the other hand, the read address of subchannel 2 does not change, and the start address data of the second segment waveform SEG2 is still read. When the waveform switching command signal WCHG is generated corresponding to subchannel 2, contrary to the above, the AND circuit 66 is enabled, the output of the delay circuit 64 is selected via the B input of the selector 58, and this data is 1 is added by the adder 61 according to the signal WCHG. The delay circuit 64 outputs the count value of the subchannel one time slot before, that is, the subchannel 1 of the same channel, and the value added by 1 to this count value becomes the new count value of the subchannel 2. In this case, the count value of subchannel 1 is 1 greater than the count value of subchannel 2, and therefore, the count value of subchannel 2
This is essentially the same as adding 2 to the count value. For example, as described above, when the count value of subchannel 1 is "3" and the count value of subchannel 2 is "2", and the signal WCHG is generated corresponding to subchannel 2, the count value of subchannel 1 is "2". 3" remains as is, and the count value of subchannel 2 changes to "4". As described above, each time the waveform switching command signal WCHG is generated alternately corresponding to one of subchannels 1 and 2, the count value of the corresponding subchannel increases by 2, and correspondingly, each subchannel The order of the segment waveform specified by is "1"
and "2", "3" and "2", "3" and "4", "5" and "4", and so on, and are alternately switched every second.
Through such alternating waveform switching control for every second waveform, allocation of segment waveforms to both streams (subchannels 1 and 2) as shown in FIG. 1B is realized. When a predetermined number of waveform switching command signals WCHG are applied and the output of the adder 61 exceeds a value specifying the final segment waveform, the output signal of the final segment detection circuit 61A becomes "1". Note that this detection circuit 61A stores, for each tone color, a numerical value that designates the last segment waveform among the plurality of segment waveforms stored for each tone color in the waveform memory 14, and uses the tone color selection information TC.
Compares the numerical data read from the memory with the output data of the adder 61 and outputs a "1" signal when "output data value > numerical data value". It consists of a comparator and a comparator. When the output signal of the detection circuit 61 becomes "1", the selector 60 switches to select the A input. As a result, the return destination rank data read from the sequence return destination memory 71 is selected by the selector 60 and stored in the shift register 57. The sequence return destination memory 71 stores return destination ranking data for subchannels 1 and 2 for each timbre, which instructs which ranking segment waveform should be returned to and read after reading the final ranking segment waveform. Then, predetermined return destination order data is read out in accordance with the tone color selection information TC and the clock pulse _φ2 . If the sound continues even after reading out the segment waveform of the final rank, the sequence return destination memory 71 is set so that the reading continues by returning to the segment waveform of the rank corresponding to the return destination rank data. It is provided. In this case, the return destination order data stored in the sequence return destination memory 71 includes the sequence waveform stored in the waveform memory 14.
For tones in which the total number of SEG1, SEG2... is an even number, the numerical value indicating the order of the segment waveform SEG that is actually read back corresponds to subchannel 1, and the number indicating the order of the segment waveform SEG that is actually read back corresponds to subchannel 2. Segment waveform SEG of
A numerical value +1 indicating the rank of +1 is stored respectively. On the other hand, for tones where the total number of sequence waveforms is odd, contrary to the above case, the numerical value corresponds to subchannel 2, and the numerical value corresponds to subchannel 1.
A numerical value +1 is stored corresponding to each. For example, if timbre A is selected and the total number of segment waveforms related to timbre A is "6", and the order of the segment waveform to return to is "3", the count value of subchannel 1 will change from "0" to " 1” →
"3" → "5" → "3" → "5" → "3" → "5"
..., and on the other hand, the count value of subchannel 2 is "0" → "2" → "4" → "6" → "2" →
It changes as "6" → "2" → "6"... As a result, for subchannel 1, segment waveforms SEG1, SEG3, and SEG5 are specified sequentially, and then segment waveforms SEG3 and SEG5 are repeatedly specified, while for subchannel 2, segment waveforms SEG2, SEG4, and SEG6 are specified sequentially, and then segment waveforms SEG3 and SEG5 are specified sequentially. Segment waveforms SEG4 and SEG6 will be repeatedly designated. Next, the crossfade control circuit 16 will be explained with reference to FIG. The counting means 73 is for generating a time function for setting a time change in weighting, and includes a first counter 73A and a second counter 73B. Both counters 73A, 73B include adders 74A, 74B, gates 75A, 75B, and 12-stage shift registers 76A, 76B controlled by clock pulse φ ₂ , respectively, and the outputs of shift registers 76A, 76B are added together. It is possible to perform a counting operation on a time-division basis for each channel by circulating through circuits 74A, 74B and gates 75A, 75B. The first counter 73A is for counting the number of times segment waveforms are switched. The change rate memory 77 stores change rate data corresponding to the number of times of switching in advance for each tone, and contains tone selection information TC.
One set of change rate data is selected according to the change rate data, and one change rate data DT is read out from the selected data according to the number of times of switching counted by the first counter 73A. In addition, gate 75
The output of A is taken out as the count output of the first counter 73A and input to the memory 77. The first counter 73A and the change rate memory 77 correspond to counting rate control means. The second counter 73B counts from a first predetermined value (for example, 0) to a second predetermined value (for example, the maximum value) at a rate according to the change rate data DT read from the memory 77. It is. Change rate data DT is input to adder 74B, and second counter 73B accumulates this data DT at predetermined time intervals. Gate 75B is enabled at non-attack times by the inverted attack signal. Therefore, the count content of the counter 73B is "0" during the attack.
is cleared, and starts counting the data DT when the attack ends. The count output of the second counter 73B is taken out from the gate 75B and input to a function conversion circuit 78 consisting of an exclusive OR circuit. This function conversion circuit 78 converts the lower n bits of the n-bit count output.
-1 bit is input to the exclusive OR circuit separately, the most significant bit MSB is input commonly to each exclusive OR circuit,
When the MSB is "0", the lower n-1 bits are passed through as is, but when it is "1", the lower-1 bits are inverted and output. In this way, the count value that increases from the minimum value 0 to the maximum value ²ⁿ turns around at the 2n ^-1 position, forming a triangular wave-like function that increases from 0 to 2n ^-1 and then decreases from 2n ^-1 to 0. Convert. The output of the function conversion circuit 78 is used as the basic interpolation function IPF2 for the second series (subchannel 2). The inversion circuit 79 inverts each bit of the interpolation function IPF2 to form a function with inverse characteristics, and this function with inverse characteristics is used as the basic interpolation function IPF1 for the first series (subchannel 1). An example of these interpolation functions IPF1 and IPF2 is shown in FIG. 11c. Note that during the attack, the output of the second counter 73B is all bits "0", so the output of the function conversion circuit 78 is all bits "0", and the value of the second series interpolation function IPF2 reaches the minimum value (0). ) is maintained, and the value of the first series interpolation function IPF1 is maintained at its maximum value. The selector 80 is for time-division multiplexing the interpolation functions IPF1 and IPF2 in accordance with the timing of each subchannel 1 and 2, and is connected to the A input.
When IPF2 is added and IPF1 is added to the B input and clock pulse _φ2 is “1” (subchannel 1
When _φ2 is "0" (time slot of subchannel 2), select IPF1 of the A input. The switching control means 81 controls the waveform switching operation in the waveform specifying means, that is, the start address generation circuit 40 in FIG. an all "0" detection circuit 82 for detecting whether or not all bits are "0";
It includes an AND circuit 83 to which the output of this detection circuit 82 and an inverted attack signal are input. The AND circuit 83 is enabled by the signal at times other than attack, and outputs the output signal "1" of the all "0" detection circuit 82 as the waveform switching command signal WCHG. Interpolation function IPF of two subchannels
1. When one of the IPFs 2 that gradually decreases over time with a negative slope becomes all bits "0", the output of the all "0" detection circuit 82 becomes "1" at the timing corresponding to that subchannel, and this A waveform switching command signal WCHG is generated in response to the waveform switching command signal WCHG. Since the slopes of the interpolation functions IPF1 and IPF2 for both subchannels are switched every interpolation interval, the waveform switching command signal WCHG is generated by switching alternately corresponding to one subchannel every time one interpolation is completed. . Figure 11c shows an example of the generation of the waveform switching command signal WCHG corresponding to the interpolation functions IPF1 and IPF2.
Shown in Figure b. The interpolation functions IPF1 and IPF2 outputted from the selector 80 in a time-division manner have temporally linear characteristics, but the crossfade curve memory 84, which corresponds to interpolation function storage means, can change these interpolation functions to arbitrary characteristics. It is provided for the purpose of conversion. For example, various interpolation characteristic curves (weighting curves) as shown by solid lines in FIG. (selection operation using a dedicated switch, etc.), and the selected interpolation characteristic curve is applied to the interpolation functions IPF1 and IPF from the selector 80.
2 is read out as the address.
As mentioned above, the interpolation function IPF1 of both subchannels,
Since IPF2 (so to speak, this is a basic interpolation function) has inverse characteristics, the reading direction of the memory 84 is mutually opposite between both subchannels (when one is in the positive direction, the other is in the opposite direction), and is mutually A curve with an inverse characteristic is read out from the memory 84 in a time-division manner. For example, when an interpolation characteristic curve as shown by a solid line in FIG. 12 a to d is read out corresponding to one subchannel, an interpolation characteristic curve as shown by a broken line in the same figure corresponds to the other subchannel. Read out. The interpolation characteristic curve data corresponding to each subchannel for each channel read out in a time-divisional manner from the memory 84 as described above is given to the multiplier 18 in FIG. 2 as crossfade curve data CF, and its The corresponding segment waveform data is weighted (amplitude control) according to the characteristics. Note that since the functions IPF1 and IPF2 are used as address signals for the memory 84, the counting means 73 and the function conversion circuit 78 correspond to address generation means for the memory 84. By using the memory 84 in this way, the interpolation characteristics can be set to any curve. In addition, since two series of interpolation characteristics are obtained by reading arbitrary interpolation characteristic curves in opposite directions, it is possible to set any interpolation characteristic curve, but as a result (two series of interpolation in synthesis)
Symmetrical interpolation is always performed, and smooth interpolation without bias can be performed. Incidentally, to explain the characteristics shown in Fig. 12, a indicates that the volume level increases at the midpoint of interpolation (the midpoint of musical waveform change), and b indicates that the waveform changes greatly at the beginning, but changes midway through. is gradual, and then changes significantly again at the end. In c, the waveform changes slowly at the beginning and end, and changes greatly in the middle. d has a waveform that changes while fluctuating. Returning to FIG. 10, the all "0" and all "1" detection circuit 85 outputs the switching synchronization signal CHGS in synchronization with the waveform switching timing, and the output of the function conversion circuit 78, that is, the interpolation function
Input IPF2 and detect whether the value is all bits "0" or all bits "1". As is clear from Figure 11c, the interpolation function changes in a triangular waveform.
At the upper peak of IPF2, all bits are "1", and at the lower peak, all bits are "0", which corresponds to the waveform switching timing, that is, the timing of the waveform switching command signal WCHG. Switching synchronization signal CHGS corresponds to when all bits are “0” or when all bits are “1”
becomes “1”. This signal CHGS becomes "1" in the time slots of both subchannels, that is, in the time slots of one channel corresponding to one cycle of clock pulse _φ2 . This signal CHGS is delayed by one cycle of the time division channel timing in accordance with the clock pulse φ ₂ ×12 in the delay circuit 86, and is applied to the adder 74A of the counter 73A via the gate 87. The output of the adder 74A is applied to a 12-stage shift register 76A via a gate 75A, delayed by one cycle of time division channel timing, and returned to the input of the adder 74A. Gate 75A
is controlled by the inverted signal of the attack end signal ATEND.
It is instantaneously closed only when ATEND occurs, and the memory of the shift register 76A regarding the corresponding channel is cleared. The output of the gate 75A is applied to the change rate memory 77 as described above, and also to the all "1" detection signal 88. All “1”
The detection circuit 88 outputs a signal "1" when all bits of the count value of the counter 73A reach "1", that is, the maximum value. This output is inverted by an inverter 89 and is applied to the control input of the gate 87. The count value of the counter 73A maintains the maximum value during the attack, and the gate 87 is closed. When the attack is completed, the attack end signal is sent.
When the count value is cleared by ATEND,
The output of the all "1" detection circuit 88 becomes "0" and the gate 87 is opened. Thereafter, each time the switching synchronization signal CHGS is generated, the count value of the counter 73A increases, and the number of waveform switching is counted. Then, the count value is the maximum value (all “1”)
When this happens, the gate 87 closes and the counting operation stops. Note that the delay circuit 86 is provided to delay the timing at which the signal CHGS is input to the counter 73A by the time delay between the input and output of the shift register 76A. Switching synchronization signal
An example of the number of switching times counted by CHGS and counter 73A is shown in FIG. 11c. As described above, the change rate memory 77 reads out predetermined change rate data DT in accordance with the count value of the counter 73A. This rate of change data
The count value increase rate of the second counter 73B is determined by the value of DT, and the slopes of the interpolation functions IPF1 and IPF2 are determined. , t3, t4...) are determined. In the memory 77, the change rate data DT can be arbitrarily set according to the number of waveform switching (that is, for each interpolation section), so the lengths t1, t2, t3, t4, etc. of each interpolation section are not uniform. It can be set completely arbitrarily. Note that once the first counter 73A reaches the maximum value, it is maintained thereafter, so that the change rate memory 77 continuously reads out the change rate data DT corresponding to the maximum value. Of course, like the other counters, the first counter 73A performs a time-division counting operation for each channel, so the above-mentioned counting of the number of waveform switching and reading of the change rate data DT are performed for each channel in a time-division manner. . Table 1 shows an example of how the change rate data is stored in the change rate memory 77. The numerical values shown in the table are examples of change rate data DT expressed in decimal notation. Table 2 exemplifies the time lengths of each interpolation section t1 to t4 set corresponding to the values in Table 1, where T is a predetermined unit time.

【table】

[Table] As is clear from the above, by using the crossfade curve memory 84, not only can an arbitrary interpolation characteristic curve be obtained;
First counter 73A that counts the number of times of switching
The time length of each interpolation section can also be arbitrarily set by the combination of the change rate memory 77 and the change rate memory 77. The first counter 73A and the change rate memory 77 in FIG. 10, that is, the counting rate control means, can also be changed as shown in FIG. 13.
Change rate initial value memory 90 contains change rate data.
Only the initial value of DT is stored for each timbre, and predetermined change rate initial value data is read out according to the timbre selection information TC. The selector 91 instantaneously selects the initial value data from the memory 90 only at the end of the attack in response to the attack end signal ATEND, and stores it in the shift register 92. shift register 92
has 12 stages and can store data for each channel. The output of the final stage of the shift register 92 is outputted as change rate data DT and is applied to a shift circuit 93 where it is bit shifted in accordance with a control signal from an AND circuit 94 and circulated through the A input of the selector 91. The AND circuit 94 is connected to an inverted signal of the least significant bit LSB of the change rate data DT and a delay circuit 86 (10th
A delayed switching synchronization signal CHGS' is provided in FIG. As an example, the shift circuit 93 shifts each bit of the input data by one bit to the lower order when the signal "1" is applied from the AND circuit 94. When the LSB of the data DT is "0", the AND circuit 94 is enabled, and the initial value data stored in the shift register 92 is sequentially shifted down one bit at a time every time the switching synchronization signal CHGS' is generated. This shift is performed on a time-division basis for each channel. Eventually, when the LSB becomes "1", the AND circuit 94 is disabled and the data DT maintains its current value. An example of the change rate data DT in this case is shown in Table 3.

[Table] In the case of FIG. 13, the change rate data DT changes monotonically compared to FIG. 10, but the configuration is simpler. In the examples shown in FIGS. 10 and 13, the interpolation function folded into a triangular waveform (basic interpolation Since the count value of the counter 73B always starts increasing from all bits "0" and finally reaches all bits "0" due to overflow, it is accurate. required to return to. Therefore, the value of the changed route data DT is required to be a power of 2, such as "1", "2", "4", and "8". On the contrary,
In order to be able to arbitrarily set the value of the change rate data DT, the second counter 73B may be changed as shown in FIG. In counter 72B shown in FIG. 14, a gate 94 is provided between adder 74B and gate 75B. A signal obtained by inverting the carry-out signal from the most significant bit of adder 74B by inverter 95 is applied together with an inverted attack signal to AND circuit 96, and its output is used to invert gate 75B.
is controlled. The most significant bit MSB of the output signal of the adder 74B is input to the gate 75B and is also applied to the rising differential circuit 97, where it is applied to the lower n-1 bits.
The bit is input to gate 94. The rising differential circuit 97 outputs a signal “1” with a width of one period of the clock pulse φ ₂ when the MSB rises to the signal “1”.
This signal "1" is inverted by an inverter 98 and applied to the control input of the gate 94. The output of gate 94 (n-1 bits) and the MSB output of adder 74B are n
It is applied to gate 75B as a bit signal. The output of gate 75B is applied to shift register 76B and is also applied to function conversion circuit 78 in the same manner as described above. During the attack, the AND circuit 96 is disabled by the inverted attack signal "0", and the gate 75B
is closed, and the count values of the counter 73B are maintained at all "0". When the attack is completed, the gate 75B opens, and since the gate 94 is normally open, a counting operation is possible, and the value of the change rate data DT is repeatedly added at predetermined time intervals (one channel timing cycle). In this way, the count value increases at an arbitrary rate depending on the value of the data DT. Most significant bit of addition result
When the MSB changes from "0" to "1", a pulse is output from the rising differential circuit 97 at that channel timing, and the gate 94 is temporarily closed. Since the increase rate of the count value is arbitrary (not limited to a power of 2), when the MSB of the addition result switches from "0" to "1", the lower n-1 bits may not all be "0". do not have. However, as described above, by temporarily closing the gate 94,
The lower n-1 bits of the addition result are forcibly cleared to all bits "0", and the count value given to the shift register 76B via the gate 75B is
The MSB is "1" and its lower n-1 bits are all "0". When the most significant bit MSB of the addition result changes from "1" to "0", that is, when the carry-out signal is output from adder 74B, AND circuit 96 is disabled and gate 75B is closed.
Also at this time, since the increase rate of the count value is arbitrary, the output of the adder 74B does not necessarily have all bits "0". However, by temporarily closing the gate 75B, all bits of the count value output from the gate 75B are forced to be "0". As a result, the output of the function conversion circuit 78 always becomes all bits "0" or all bits "1" at the turning point, and the detection circuits 82 and 85 (Fig. 10)
In this case, all "0" or all "1" can be detected without any problem, and waveform switching control can be performed without any problem. Therefore, according to the configuration shown in FIG. 14, the change rate data DT can be set to any value, not just a power of 2. In this case, in order to cause the waveform to be switched when the segment waveform is read exactly for an integer period, the value of the data DT may be determined in association with the musical tone frequency. In the embodiment described above, the counting rate in the counting means 73 is determined by repeatedly counting data DT of appropriate values at predetermined time intervals.
It is now determined by the value of . However, the counting rate is not limited to this, and the counting rate may be determined by keeping the value of data DT constant and variably controlling the counting time interval (count clock), or by variably controlling both the value of data DT and the counting time interval. You can do it like this. Furthermore, in the example of FIG. 9, in order to increase the count value (segment waveform order data) of a certain subchannel by 2, the start address generation circuit 40 extracts the count value of the other subchannel and increases it by 1. Therefore, the calculation is equivalent to increasing by 2. However, the present invention is not limited to this, and the start address generation circuit 40 may be configured as shown in FIG. 15 to directly add 2 to the count value of the subchannel. In FIG. 15, the same symbols as in FIG. 9 indicate the same circuits, and the circuits corresponding to the symbols 58, 63 to 67 in FIG. 9 are omitted, and the output of the shift register 57 is directly input to the A input of the selector 59. The difference is that Further, a gate 99 is provided, and data of numerical value "2" is provided to the adder 61 via the gate 99 every time the waveform switching command signal WCHG is applied. Therefore,
When the waveform switching command signal WCHG is generated corresponding to one of the subchannels, the numerical value "2" is added to the count value output from the shift register 57 at the timing of that subchannel, and the result is substantially as shown in FIG. Works equally well. In the embodiment described above, as shown in FIG. 1b, the basic interpolation functions IPF1 and IPF2 (address signals of the memory 84) change in a triangular waveform, and the two segment waveforms are always weighted. However, the present invention is not limited to this, and the two waveforms may be weighted only during the transition period of waveform switching. 1st
Figure 6 shows the basic interpolation functions IPF1 and IPF2 in that case.
(memory 84 address signal), for example, segment waveforms SEG1 to SEG2
Both functions IPF in the transition period P ₁ when switching to
1, IPF2 is crossed, and thereafter the interpolation function IPF2 for SEG2 is maintained at the maximum value, and the interpolation function IPF1 for SEG1 is maintained at the minimum value. From SEG2
The same applies to the transition period _P2 when switching to SEG3. In order to perform control as shown in Fig. 16, the first
The detection circuits 82 and 85 in Figure 0 do not simply detect all "0" or all "1", but detect a change from all "0" or all "1" in an increasing direction or a decreasing direction. Waveform switching command signal WCHG or switching synchronization signal based on
All you have to do is generate CHGS. Further, in the above embodiment, two streams (subchannels) for interpolation are time-divisionally processed, but they may be processed in parallel. In addition, in Fig. 2, two series of musical sound waveform signals weighted for interpolation are digitally added in an adder 20 and then D/A converted, but each series is D/A converted independently and then mixed or independent. You may also choose to pronounce it. Further, although the waveform memory 14 shown in FIG. 2 stores the amplitude value data of each sample point of the waveform as is, the present invention is not limited to this, and various storage methods may be employed. For example, the amplitude data of each sample point can be obtained by storing the difference values of the amplitude values between each sample point, reading them out and then accumulating them, or There are various methods, such as storing the data in parts and performing arithmetic processing after reading it out to obtain the real number of the amplitude value of each sample point. Note that in the above example, the segment waveform (SEG
1, SEG2, ...), one cycle of the waveform is stored as is in the waveform memory 14, but the present invention is not limited to this, and only half a cycle of the waveform may be stored.
In this case, positive and negative polarities may be added alternately to the read half-cycle waveform to form a one-cycle waveform. Further, the segment waveform stored in the waveform memory 14 is not limited to one period waveform, but may be a waveform for a plurality of periods (for example, two periods). In the above embodiment, the attack portion of the musical tone signal is generated by storing the continuous multi-cycle waveform as it is in the waveform memory 14 and reading it out as is. Also, according to the present invention, a plurality of segment waveforms are stored in the waveform memory 14, and these are sequentially switched and read out.
Of course, the above-mentioned interpolation process may be performed at the time of waveform switching to generate musical tone signals. In the above embodiment, the musical tone signal generating device according to the present invention is used in a multi-tone electronic musical instrument, but it can of course also be used in a single-tone electronic musical instrument, and furthermore, it can be used not only for electronic musical instruments but also for generating musical tones. Applicable to all devices. In the example shown in FIG. 10, the final interpolation function, that is, the crossfade curve data CF is stored in the memory 84.
However, instead of providing them in the memory 84, IPF1 and IPF2 can be directly given to the multiplier 18 (FIG. 2) as weighting coefficients, or
IPF1 and IPF2 may be modified by appropriate logical operations and then provided to the multiplier 18. In addition, in the above example, each segment waveform
Waveform data of SEG1, SEG2, . but,
The present invention is not limited to this, but each segment waveform can be generated using a musical sound waveform forming means that forms a desired musical sound waveform based on parameters (harmonic relative amplitude coefficients and filter coefficients), such as a harmonic synthesis method or a digital filter method. You can do it like this. An embodiment of the present invention using such a parametric tone waveform forming means will be described below with reference to FIG. In FIG. 17, circuits or devices having the same functions are denoted by the same reference numerals as those shown in FIG. 2, and a description thereof will be omitted. The one-cycle phase data generation circuit 100 is for generating phase data ADR that sequentially specifies each phase (each sample point) within one cycle of a musical sound waveform.
The same configuration as the reading means 28 in FIG. 5 can be used. The tone waveform forming circuit 101 performs a predetermined calculation using parameters to form a tone waveform having a shape determined by the parameters, and also uses phase data given from the phase data generation circuit 100.
This musical sound waveform is formed in accordance with the phase (sample point) specified by ADR.
As this tone waveform forming circuit 101, a circuit which forms a desired tone waveform by, for example, harmonic synthesis calculation can be used. A musical waveform forming circuit using such a harmonic synthesis calculation method was developed in Japanese Patent Publication No. 52-16363.
Since this method is already well known in Japanese Patent Laid-Open No. 1983-90217 (a type in which each harmonic signal is generated in parallel) and Japanese Patent Application Laid-open No. 1988-90217 (a type in which each harmonic signal is generated in a time-sharing manner), the details will be omitted. The outline is shown in FIG. 19. In the case of the harmonic synthesis calculation method, the parameters used for calculation consist of relative amplitude coefficients of each harmonic including the fundamental wave. The harmonic generation circuit 107 in FIG. 19 generates each harmonic signal (including the fundamental wave) according to the phase data ADR, and the multiplier 108 converts the relative amplitude of each harmonic signal into the corresponding relative amplitude coefficient (parameter ), and the addition and synthesis circuit 109 adds and synthesizes them to obtain a musical sound waveform with desired characteristics. The parameter memory 102 stores parameters that determine the characteristics (particularly the shape) of each segment waveform for a plurality of different musical sound waveforms, that is, segment waveforms sampled discretely from the start to the end of musical tones. . In this embodiment, it is assumed that the segment waveform is sampled discretely in the attack part as well, without distinguishing between the attack part and other parts. Each of these segment waveforms has the symbol SEG as before.
shall be distinguished by adding numbers 1, 2, 3, etc. indicating the order of occurrence. In the parameter memory 102, each segment waveform SEG1,
Parameters a1, a2..., b1, b2..., c1, c2... corresponding to ranks 1, 2... of SEG2,... are stored for each tone A, B, C..., and the tone A parameter group corresponding to a predetermined timbre is selected by the selection information TC, and among the selected parameter group, parameters corresponding to the segment ranking data generated from the segment ranking data generation circuit 103 are read out to form a musical sound waveform. The signal is applied to circuit 101.

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Claims (1)

[Scope of Claims] 1. A waveform memory in which a plurality of different musical waveforms sampled discretely between the start and end of a musical tone are divided into a plurality of sample points, and waveform data corresponding to each sample point is stored. reading means having a plurality of time-division processing channels and repeatedly reading out waveform data of a predetermined musical sound waveform from the waveform storage means according to the musical sound frequency to be generated; Waveform specifying means for specifying by temporally switching, and interpolation means for weighting the musical sound waveforms of the time-division processing channels for two channels corresponding to the preceding musical sound waveform and the next musical sound waveform when switching the musical sound waveform to be read. and counting means for generating an independent time function independent of musical tone frequency in order to set the time change of weighting in the interpolation means, and controlling waveform switching in the waveform specifying means in accordance with the output of the counting means. and a switching control means for weighting the preceding tone waveform with a gradually decreasing characteristic and weighting the next tone waveform with a gradually rising characteristic according to the count output of the counting means. A musical tone signal generator that uses weighting to smoothly transition waveforms. 2. The counting means generates the time function by performing a counting operation at a counting rate that does not depend on the musical tone frequency, and the switching control means controls the time function generated from the counting means to a predetermined value. 2. The musical tone signal generating device according to claim 1, wherein the change is detected, and based on this detection, a waveform switching command signal is given to the waveform specifying means. 3. The counting means includes counting rate control means for controlling counting rate switching in synchronization with waveform switching control by the switching control means, and counting operation according to the counting rate controlled by the counting rate control means. 3. The musical tone signal generating device according to claim 1, further comprising a counting circuit for generating the time function according to the counted value. 4. The counting rate control means counts the number of times the musical sound waveform is switched, and specifies a counting rate according to the counted number, and the counting circuit controls the number of times the musical waveform is switched from the first predetermined value to the second predetermined value. 4. The musical tone signal generating device according to claim 3, wherein the counting is performed at the specified counting rate and the time function is outputted in accordance with the counted value. 5. The counting rate control means includes a counter for counting the number of times of switching, and a change rate memory that reads predetermined numerical data according to the number of times of switching counted by this counter,
5. The musical tone signal generating device according to claim 4, wherein the numerical data read from the change rate memory is repeatedly counted at predetermined time intervals in the counting circuit. 6. The counting rate control means includes first means for generating predetermined initial numerical data, and second means for sequentially changing this initial numerical data in synchronization with the waveform switching control, and the counting circuit This second
4. The musical tone signal generating apparatus according to claim 3, wherein the output numerical data of the means is repeatedly counted at predetermined time intervals. 7. A musical sound waveform forming means that forms a musical sound waveform having a shape determined by parameters and also forms the musical sound waveform in accordance with a phase specified by phase data; Regarding multiple different musical sound waveforms sampled discretely between
parameter storage means that stores the parameters that determine the shape of each musical sound waveform; phase data generating means that generates the phase data that changes according to the frequency of the musical sound to be generated and supplies it to the musical sound waveform forming means; waveform designating means for temporally switching and specifying a musical tone waveform to be formed by the musical tone waveform forming means, reading out the parameters corresponding to the specified musical tone waveform from the parameter storage means, and applying the parameters to the musical tone waveform forming means; interpolation means for weighting both tone waveforms so as to smoothly transition from the preceding waveform to the next tone waveform when switching the tone waveform to be played; and a time function for setting a time change in weighting in the interpolation means. and switching control means for controlling waveform switching in the waveform specifying means according to the output of the counting means, and the interpolation means generates the preceding waveform according to the count output of the counting means. A musical tone signal generating device that weights a musical sound waveform with a characteristic that gradually attenuates, and weights the next musical waveform with a characteristic that gradually rises, thereby smoothly transitioning the waveform. 8. The parameters include relative amplitude coefficients of each harmonic including the fundamental wave, and the musical waveform forming means controls and synthesizes each harmonic signal generated according to the phase data with the corresponding relative amplitude coefficient. 8. The musical tone signal generating apparatus according to claim 7, wherein the musical tone signal generating apparatus forms the musical sound waveform by: 9. The parameter comprises a digital filter coefficient, and the musical sound waveform forming means includes means for digitally generating a predetermined sound source waveform signal according to the phase data, and a means for digitally generating a predetermined sound source waveform signal according to the digital filter coefficient given as the parameter. 8. The musical tone signal generating apparatus according to claim 7, further comprising a digital filter circuit having a set filter characteristic and controlling the tone source waveform signal according to the characteristic.