JPH0122631B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION This invention relates to a musical tone signal generating device used in an electronic musical instrument or other device having a musical tone generating function, and particularly to a device capable of generating a musical tone signal containing an aharmonic component.

BACKGROUND OF THE INVENTION Musical tones generated from natural musical instruments, particularly percussion instruments such as pianos and harpsichords, contain components (non-harmonic components) that are not in true harmonic relation to the pitch name. Conventional, well-known musical tone signal generation methods that simply repeatedly read out musical waveforms stored in a waveform memory can only obtain harmonic relationships of integer multiples. was impossible. On the other hand, electronic musical instruments using the harmonic synthesis method, which calculates and synthesizes each harmonic component separately, are capable of synthesizing musical tone signals that include non-harmonic components;
It is disclosed in Publication No. 40527. In other words, by slightly shifting the frequency of each harmonic component to be generated individually relative to an integer multiple of the fundamental frequency as necessary, a partial tone signal of anharmonic component is generated, and by synthesizing these partials. A musical tone signal containing non-harmonic components is obtained.

Problems to be Solved by the Invention However, in the prior art as described above, partial tone signals corresponding to the fundamental wave and each harmonic component are individually generated, and their relative amplitudes are individually controlled. Since this requires a configuration of additive synthesis, there is a problem in that the scale of the hardware becomes large.

This invention was made in view of the above points,
It is an object of the present invention to provide a musical tone signal generating device that can easily generate a musical tone signal containing an inharmonic component with a relatively simple configuration.

Means for Solving Problems The musical tone signal generating device according to the present invention includes a waveform storage means that divides a plurality of musical sound waveforms into a plurality of sample points and stores waveform data corresponding to each sample point; reading means for repeatedly reading waveform data of a predetermined musical sound waveform from the waveform storage means according to the musical sound frequency to be read; a waveform specifying means for temporally switching and specifying the musical sound waveform to be read from the waveform storage means; and interpolation means for weighting both tone waveforms so as to smoothly transition from the preceding tone waveform to the next tone waveform when switching tone waveforms, and each tone waveform stored in the waveform storage means has a basic value. wave and harmonic components, and for all or a predetermined plurality of each musical sound waveform, the switching order sets a predetermined phase difference in at least one of the components between adjacent musical sound waveforms. This is characterized by the fact that the phase difference and the time required for the waveform transition by the interpolation means (interpolation time) realize the anharmonicity.

Effect: Due to the interpolation by the interpolation means, the obtained musical sound signal is not the same as the musical sound wave read out from the waveform storage means, but is one that smoothly transitions from the preceding musical sound wave to the next musical sound wave in the switching order. becomes. This musical waveform transition can be analyzed for each component. That is, regarding the nth component, there is a smooth transition from the nth component of the preceding tone waveform to the nth component of the next tone waveform. Focusing on the initial phase, the initial phase of the musical sound waveform obtained by interpolation gradually increases from the initial phase value of the n-th component of the preceding musical sound waveform to the initial phase value of the n-th component of the following musical sound waveform. Transition. in this case,
For components for which there is no phase difference between adjacent tone waveforms, their initial phases do not change during interpolation. In this way, for the component for which no phase difference is provided, an integral multiple (harmonious) frequency as indicated by its harmonic order is obtained. On the other hand, for components in which there is a phase difference between adjacent tone waveforms, during interpolation, the initial phase thereof gradually shifts from that of the preceding tone waveform to that of the next tone waveform. Due to the transition of the initial phase of a particular component during such an interpolation period, the frequency of the component does not represent the original integral multiple frequency, but rather deviates from it. In this way, a specific component becomes a non-harmonic frequency, and a musical tone signal containing a non-harmonic component is obtained.

The principle of obtaining anharmonic frequency as described above will be explained in more detail with reference to FIG. 1st
In the figure, the second overtone component (indicated by SEG1 ₂ ) contained in the preceding musical sound waveform and the second overtone component (indicated by SEG2 ₂ ) contained in the following musical sound waveform are extracted and shown. As an example, The explanation will be given assuming that a predetermined phase difference is set for the second overtone component. Figure 1 is 3
It is shown in dimensional coordinates, where the X axis is the phase, the Y axis is the amplitude, the Z axis is time, and t _1s is the interpolation start point,
t _1e is the end point of interpolation, and between t _1s and t _1e
It is assumed that linear interpolation is performed from SEG1 ₂ to SEG2 ₂ . In the figure, the phase difference between both second harmonic components is
It is set at 22.5 degrees.

If the fundamental frequency is 440Hz (corresponding to A4 tone), the second overtone is 880Hz (one cycle is 1.136ms). The interpolation period from t _1s to t _1e corresponds to this second harmonic.
Assuming that the time is set to 18.182ms, which corresponds to 16 cycles, if there is no phase difference between the two components SEG1 ₂ and SEG2 ₂ , then exactly 16 cycles worth of second overtones will be generated during this interpolation period and will be synthesized. The frequency of the second overtone component should be exactly twice that of the fundamental wave. However, there is a phase difference of 22.5 between the two components SEG1 ₂ and SEG2 ₂ .
As a result, the initial phase of the second overtone component synthesized by interpolation gradually shifts, and finally the phase at interpolation end time t _1e is 22.5 compared to the phase at interpolation start time t _1s . The degree is off. The direction of this phase shift is determined by the direction of phase shift of SEG2 ₂ with respect to SEG1 ₂ , and in the figure, it is the advancing direction. 22.5 degrees is
This corresponds to a period of 22.5/360=0.0625, which means that a second overtone component with a period of 16.0625 was generated during the interpolation period t _1s to _{t 1e} . The corresponding frequency f ₂ is not exactly the second overtone frequency of 880 Hz, but is f ₂ =16.0625 (period)/18.182 (ms) x 1000 (ms) = 883.44 (Hz). In other words, the second overtone component is synthesized as an anharmonic component shifted by about 3.44 Hz from the integral multiple frequency.

Components of other orders can also be synthesized as anharmonic components using the same principle. For example, under the same conditions as above, if the phase difference of the third harmonic component is 45 degrees, the frequency of the synthesized third harmonic component is
While _{the regular integral multiple frequency is 1320 Hz, f 3 =} 24.125 (period)/18.182 (ms) x 1000 (ms) = 1326.9 (Hz). Note that the period corresponding to a phase difference of 45 degrees is 45/360 = 0.125 (period). Also, under the same conditions as above, if the phase difference of the 4th harmonic component is 90 degrees, then
The frequency f ₄ of the synthesized 4th overtone component is 1760 Hz for the regular integer multiple frequency, whereas f ₄ = 32.25 (period) / 18.182 (ms) × 1000 (ms) = 1773.8 (Hz). . Note that the period corresponding to a phase difference of 90 degrees is 90/360 = 0.25 (period). In addition, not only harmonic components,
A phase difference may be set as described above for the fundamental component, in which case an anharmonic relationship is obtained between the fundamental component that deviates somewhat from the normal frequency and the overtone component that does not deviate. It will be done.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the principle of musical tone signal generation employed in the embodiment described below will be explained with reference to FIG. In FIG. 2a, the outline of the musical sound waveform that should be prepared in advance in the waveform memory is shown only by the amplitude envelope for convenience. Since the musical sound waveform of a predetermined period (attack portion) from the start of sound generation changes in a complicated manner, it is difficult to imitate a high-quality attack portion waveform by repeatedly reading out the one-period waveform. Therefore, it is assumed that the musical sound waveform of this attack section is obtained by directly sampling a continuous multi-cycle waveform and storing it in a waveform memory. Regarding the entire sound generation period after the attack portion, a plurality of tone waveforms are prepared corresponding to discrete time periods, and each is stored in a waveform memory. These plural tone waveforms are used in the interpolation calculation for anharmonic component synthesis according to the present invention. In Figure 2a, each musical sound waveform corresponding to such a discrete time period is
They are shown as SEG1 to SEG5, and for convenience, these will be called segment waveforms.

The basic method of reading out waveforms from the waveform memory that stores waveforms as described above is to first read out all the waveforms of the attack part continuously, and then read out the segment waveform SEG1 at a certain timing according to a waveform switching command as described later. ~SEG5 are selected in order, and one cycle of the selected segment waveform is repeatedly read out. For example, after reading out the attack waveform, the first segment waveform SEG1 is repeatedly read out for a certain period of time, then the second segment waveform SEG2 is switched to and read out repeatedly, and thereafter the segment waveforms are sequentially switched.

When switching segment waveforms, interpolation techniques are used to provide a smooth transition from a preceding waveform to the next waveform. In that case, in addition to the basic reading method described above, at least the preceding segment waveform and the following segment waveform are read out in the interval where interpolation is to be performed, and both are weighted respectively according to an appropriate interpolation function. do. As an example, the entire segment waveform switching interval corresponds to the interpolation interval, and the first segment waveform
When reading SEG1, use the second segment waveform
SEG2 is also read out, and at the next switching time, the second and third segment waveforms SEG2,
SEG3 is read out together, and then adjacent segment waveforms are read out together while sequentially switching in the same manner.

An example of an interpolation function is shown in FIG. 2b. The solid line indicates the interpolation function IPF1 for the first series,
The broken line indicates the interpolation function IPF2 for the second series. 1st
The series corresponds to one of the two segment waveforms read out for interpolation as described above, and the second series corresponds to the other.
These interpolation functions IPF1 and IPF2 indicate the amount of weighting of the waveform amplitude of each series, and the minimum value is zero (indicating that the waveform is not output). In the attack part that does not perform interpolation, the first series of interpolation functions
Keep IPF1 at maximum value and use the second series interpolation function
Keep IPF2 at minimum value. After the attack portion ends, each of the interpolation functions IPF1 and IPF2 changes over time with predetermined characteristics during a period in which segment waveforms SEG1 to SEG5 are to be interpolated. Both interpolation functions
IPF1 and IPF2 change with opposite characteristics, so that when the weighting of one series gradually decreases, the weighting of the other series gradually increases, thereby achieving a smooth waveform transition. In Figure 2b, the interpolation functions IPF1, IPF
2 shows linear interpolation characteristics, but it is of course not limited to this.

t ₁ , t ₂ , t ₃ , and t ₄ each indicate a separate interpolation interval, and the interpolation function of each series is changed each time the interpolation interval is switched.
The slopes of IPF1 and IPF2 are switched alternately. In the interpolation interval _t1 , interpolation is performed to smoothly transition from the segment waveform SEG1 to SEG2. In this case, segment waveform SEG1
is repeatedly read out in the first series, and segment waveform SEG2 is repeatedly read out in the second series. Then, while the first series interpolation function IPF1 gradually decreases from the maximum value, the second series interpolation function IPF
2 gradually increases from the minimum value. The multi-period waveform signal of the segment waveform SEG1 repeatedly read out in the first series is weighted (amplitude controlled) by this interpolation function IPF1, and is repeatedly read out in the second series by the interpolation function IPF2. segment waveform
The multi-period waveform signal of SEG2 is weighted.
By mixing the waveform signals of both series weighted with opposite characteristics in this way, the segment waveform
A musical tone signal whose waveform changes smoothly over time from SEG1 to segment waveform SEG2 is obtained.

In the next interpolation section _t2 , interpolation is performed to smoothly transition from the segment waveform SEG2 to SEG3.
In this case, the segment waveform SEG2 was repeatedly read out in the second read sequence last time, and on the other hand,
In the first series, the segment waveform is from SEG1 to SEG
3 and this is read out repeatedly. Then, the slopes of the interpolation functions IPF1 and IPF2 are respectively switched to the opposite direction from the previous time.

In the other interpolation intervals t ₃ and t ₄ , the segment waveform of one series is switched as well as the interpolation function IPF as described above.
1. The slope of IPF2 switches to the opposite direction. Figure 2b
The numbers of segment waveforms SEG1 to SEG5 used in each series in each interpolation interval _t1 to _t4 are also written.

FIG. 3 shows an embodiment of an electronic musical instrument to which the musical tone signal generating device according to the present invention is applied.
In this electronic musical instrument, musical tone signals are generated according to the musical tone signal generation principle as described above with reference to FIG.

In FIG. 3, a keyboard 10 includes a number of keys for specifying pitches of musical tones to be generated. The key assigner 11 detects the press or release of each key,
A process of assigning a pressed key to one of a plurality of musical tone generation channels is performed. As an example, the maximum number of notes that can be produced simultaneously is 12, and the key assigner 11 assigns a pressed key to any of the 12 channels. a key code KC that identifies the key assigned to each channel;
The key-on signal KON, which indicates whether or not the key press continues, and the key-on pulse KONP, which is instantaneously generated when the key press starts, are sent to the key assigner in a time-sharing manner for each channel according to predetermined time-sharing timing. It is output from 11.

An example of time division channel timing is shown in FIG. 4. Each channel timing 1~
12 is formed in synchronization with clock pulse _φ2 .
Two subchannel timings ₁ and ₂ are formed by dividing the time slot of each channel timing into two in synchronization with a clock pulse φ1 having twice the frequency of the clock pulse φ2. These subchannel timings 1 and 2 correspond to the first and second sequences in the interpolation described above. That is, in this embodiment, the time slot of one channel is divided into two, and the segment waveforms of the first series (subchannel 1) and the second series (subchannel 2) for interpolation are read out in a time-division manner.
CH1 to CH12 are channel timing signals, which are generated corresponding to channel timings 1 to 12, respectively. Each clock pulse φ ₁ , φ ₂ and signal
CH1 to CH12 are generated from the timing signal generator 12 and supplied to predetermined circuits in the electronic musical instrument shown in FIG. 3, respectively.

The phase generator 13 specifies a musical sound waveform to be read out from the waveform memory 14, and reads out this musical sound waveform according to the musical sound frequency to be generated.The phase generator 13 is for specifying a musical sound waveform to be read out from the waveform memory 14, and reads out this musical sound waveform according to the musical sound frequency to be generated. A total of 24 time slots are generated in a time-division manner for each subchannel 1 to 12 of subchannels 1 and 2. In terms of correspondence with the structure of the present invention, there is a reading means for repeatedly reading one cycle of waveform data from the waveform storage means according to the musical tone frequency to be generated, and a musical waveform to be read from the waveform storage means by temporally switching and specifying. This phase generator 13 includes a waveform specifying means for specifying a waveform. The phase generator 13 receives the key code KC from the key assigner 11,
A key-on pulse KONP and a key-on signal KON are provided, and these specify the musical tone frequency to be generated and the start timing of sound generation.

The waveform memory 14 stores a plurality of sets of the above-mentioned attack section full waveform and a plurality of segment waveforms corresponding to each timbre. Specifically, as is well known, each waveform is divided into a plurality of sample points, and the waveform data corresponding to each sample point (for example, waveform amplitude data of the sample point) is stored. The segment waveforms SEG1, SEG2, SEG3, etc. for each timbre are composite waveforms containing fundamental wave and harmonic components, respectively, and the phase of at least one component of each component is shifted by a predetermined amount between adjacent segment waveforms. It is something that exists.

An example of the memory map in this waveform memory 14 is shown schematically in FIG. Regarding timbre A, the waveform data of the entire waveform of the attack part is stored in the address range from address A ₀ to A ₁ -1, and the waveform data for one cycle of the first segment waveform SEG1 is stored in the address range from address A ₁ to A ₂ -1. The waveform data of SEG2, SEG3, . . . are sequentially stored in a predetermined address range. The same applies to the other tones B, C, and so on. A ₀ , A ₁ , A ₂ ..., B ₀ , B ₁ , B ₂ ..., C ₀ ,
C ₁ , C ₂ ... are the start addresses of each address range, A ₀ , B ₀ , C ₀ ... are the start addresses of the attack part, and A ₁ , B ₁ , C ₁ ... are the start addresses of the first segment waveform SEG1. The addresses A ₂ , B ₂ , C ₂ . . . are the start addresses of the second segment waveform SEG2. As an example, one period waveform is sampled at 256 sample points, and the maximum number of periods of the entire attack portion waveform is 256 periods. As shown in the figure, the number of cycles of the entire waveform of the attack section differs depending on the tone. In addition, each sample point within one cycle (total
256) can be expressed using exactly 8-bit binary code.
Therefore, each sample point within this one cycle is specified by the lowest 8 bits of address data MADR, and each start address A ₁ ,
The lowest 8 bits of A ₂ ..., B ₁ , B ₂ ..., C ₁ , C ₂ ... are all "0", and the upper bits have a valid value to specify each segment waveform. .

Returning to FIG. 3, the timbre selection circuit 15 outputs timbre selection information TC and supplies it to the phase generator 13, waveform memory 14, crossfade control circuit 16, and envelope generator 17. The crossfade control circuit 16 is for generating an interpolation function for weighting musical waveform signals of two series (subchannels) related to the same sounding channel with opposite characteristics. To show the correspondence with the structure of the present invention, when switching the musical sound waveform to be read, a part of the interpolation means (particularly means for generating the interpolation function); and counting means for generating a time function for setting the time change of weighting in the interpolation means.
The crossfade control circuit 16 includes a switching control means for controlling waveform switching in the waveform specifying means in accordance with the output of the counting means.

An attack end signal ATEND indicating that reading of all waveforms of the attack section has been completed and an inverted attack signal indicating that reading of the attack section is not being performed are applied from the phase generator 13 to the crossfade control circuit 16. When the crossfade control circuit 16 confirms that the waveform readout of the attack section is completed based on these signals, it starts generating a predetermined interpolation function. The interpolation function is output from the circuit 16 as crossfade curve data CF, and is applied to a multiplier 18 for weighting calculation. Also, the waveform switching command signal WCHG is applied to circuit 1.
6 and is applied to the phase generator 13.

The multiplier 18 for weighting calculations and the adder 20 that adds the output of the multiplier 18 to a signal delayed by one period of the clock pulse φ ₁ in the delay circuit 19 and an undelayed signal form part of the interpolation means. be. Tone waveform data is read out in a time-division manner from the waveform memory 14 in accordance with each sub-channel timing for each channel, and is similarly read out in a time-division manner from the crossfade control circuit 16 in synchronization with each sub-channel timing for each channel. The crossfade curve data CF is read out. Therefore, multiplier 1
In step 8, the musical sound waveforms read out in a time-division manner corresponding to each subchannel of each channel are respectively weighted according to the corresponding crossfade curve data CF (ie, interpolation function). 1
An adder 20 adds weighted musical waveform data of two subchannels regarding one musical tone generation channel. That is, when the tone waveform signal of the first subchannel is delayed and inputted from the delay circuit 19 to the adder 20, the tone waveform data of the second subchannel of the same channel is inputted to the adder 20.
It is designed to join the other inputs of 0. Thus, the time slot of one channel (the time slot corresponding to one period of clock pulse _φ2 )
In the latter half of the process, the two weighted tone waveform data for that channel are mixed.

The envelope generator 17 is a key assigner 11
An amplitude envelope waveform signal is generated for each channel in a time-division manner according to the key-on signal KON and the key-on pulse KONP given from the channel. This envelope waveform maintains a constant level while the key is pressed, and exhibits a decay envelope characteristic in response to the key release. Since all the waveforms of the attack part stored in the waveform memory 14 have been given attack envelope characteristics in advance, there is no need for the envelope generator 17 to give them attack envelope characteristics. The outputs of the adder 20 and the envelope generator 17 are input to a multiplier 21, and amplitude envelopes corresponding to key presses and key releases are applied to the musical sound waveform data of each channel in a time-division manner.

The output of the multiplier 21 is sent to latch circuits 22-1 to 22- which are provided in parallel corresponding to each channel.
12 data inputs. Each latch circuit 2
The latch control inputs L from 2-1 to 22-12 include
Channel timing signal CH1 corresponding to each
-AND circuits 23-1 to 23 that perform AND logic between CH12 and inverted _{signal 2 of} clock pulse φ2
-12 outputs are given respectively. In this way, the output of the multiplier 21 is latched into the corresponding latch circuits 22-1 to 22-12 in the latter half of the time-division time slots of each channel. As mentioned above, the adder 20 adds the two weighted tone waveform data for each channel in the latter half time slot of each channel timing 1 to 12 (timing of subchannel 2), so the addition result corresponds to The data is latched in each latch circuit 22-1 to 22-12. In this way, the time division of the tone waveform data of each channel is canceled.

The outputs of the latch circuits 22-1 to 22-12 are input to the latch circuits 24-1 to 24-12.
Pitch synchronization pulses PSP1 to PSP12 outputted from the phase generator 13 are applied to the latch control inputs L of each of the latch circuits 24-1 to 24-12. The pitch synchronization pulses PSP1 to PSP12 are pulses synchronized with the frequency of musical tones assigned to each channel, and by latching the musical waveform data in accordance with these pulses, aharmonic clock components are removed. Each latch circuit 24-1 to 24-
The outputs of 12 are given to an adder 25 and summed, and then converted to an analog signal by a digital/analog converter 26 and sent to a sound system 27.

Next, details of each part in FIG. 3 will be explained.

FIG. 6 shows an example of the phase generator 13.
A portion indicated by the reference numeral 28 corresponds to a reading means for repeatedly reading one cycle of waveform data. The key code KC of each channel given in a time-sharing manner from the key assigner 11 is set in the latch circuit 29.
latch circuits 29-1 to 29-12 corresponding to each channel according to channel timing signals CH1 to CH12.
are latched respectively. The variable oscillators 30-1 to 30-12 provided independently for each channel are
Latch circuits 29-1 to 29-1 corresponding to each
According to the key code KC given from 2, note clock pulses NC1 to NC12 corresponding to the musical tone frequencies of the pressed keys assigned to each channel are generated. Note clock pulse NC1~NC12
is applied to a time division control circuit 31, sampled and multiplexed in a time division manner according to channel timing signals CH1 to CH12, and a time division multiplexed output is taken out via a line 32.

An example of the time division control circuit 31 is as shown in FIG.
Note clock pulses NC1 to NC12 of each channel are input to set input S 3-12, respectively. The outputs Q of the flip-flops 33-1 to 33-12 and channel timing signals CH1 to CH12 are input to the AND circuits 34-1 to 34-12, respectively, and the outputs are multiplexed by the OR circuit 350 and guided to the line 32. At the same time, they are returned to the reset inputs R of the corresponding flip-flops 33-1 to 33-12. Further, the outputs Q of the flip-flops 33-1 to 33-12 are outputted as pitch synchronizing pulses PSP1 to PSP12, and are applied to the latch circuits 24-1 to 24-12 shown in FIG. 3 as described above. Flip-flops 33-1 to 33
-12 is set at the rising edge of the signal at the set input S, and reset at the falling edge of the signal at the reset input R. FIG. 8 shows an example of input/output signals of each part in FIG. 7. As is clear from the figure, note clock pulses NC1 to NC12 of keys assigned to each channel are asynchronous to the channel timing, and these pulses NC1 to NC12 are asynchronous to the channel timing.
At the rising edge of NC12, flip-flops 33-1 to 33-12 are set to enable the corresponding AND circuits 34-1 to 34-12, and then corresponding to the first channel timing signals CH1 to CH12, the AND circuits 34-1 to 34-12 are enabled. 1 to 34-12, and the flip-flops 33-1 to 33-12 are reset at the falling edge of the output pulses. Then, the notebook clock pulse NC
A new note clock pulse synchronized with the channel timing signals CH1 to CH12 at the same frequency as those of CH1 to NC12 is applied to each AND circuit 34-1 to 34-.
Obtained from 12. In this way, a note clock pulse corresponding to the musical tone frequency of the key assigned to each channel (an integral multiple thereof) is outputted to the line 32 in accordance with the time division timing of the corresponding channel.

Returning to FIG. 6, the note clock pulses of each channel applied to the line 32 are input to a counter 38 consisting of an adder 35, a gate 36, and a shift register 37, and the number of pulses is counted in a time-division manner for each channel. Ru. shift register 37
has 24 stages/8 bits, and is shift-controlled by a clock pulse _φ1 synchronized with the subchannel timing. The output of shift register 37 is provided to adder 35 and summed with the note clock pulse on line 32. The addition output is stored in a shift register 37 via a gate 36. The 24 stages of the shift register 37 correspond to 2 subchannels of each of the 12 channels.
Count values for one channel are stored in two stages (corresponding to two subchannels), respectively. The gate 36 is instantaneously closed by the key-on pulse KONP just before the start of sound generation, and the memory of two corresponding stages in the shift register 37 is cleared.

Since the shift register 37 has a capacity of 8 bits per stage, the counter 38 has a modulus
256 counts are performed in time division for 24 channels (actually 12 channels). The output of the gate 36 is taken out as the count output of the counter 38, and is applied to the waveform memory 14 as the lowest 8 bits of the address data MADR. By the count output of the counter 38, each sample point of a one-period waveform consisting of 256 sample points can be sequentially read out. Count is notebook clock pulse NC
1 to NC12, the reading is performed in accordance with the musical tone frequency to be generated.

The address data MADR for reading the waveform memory 14 is N+8 bits (N>8),
As described above, the lowest 8 bits sequentially designate sample points within one cycle of the waveform, and the upper N bits designate one cycle of the waveform.

The upper N bits of address data for specifying the waveform are given via an adder 41 from a start address generation circuit 40 corresponding to waveform specifying means. The start address generation circuit 40 generates the start addresses A ₀ , B ₀ , C ₀ of all waveforms of the attack section mentioned above.
...and the start address A ₁ of each segment waveform,
A ₂ ...is generated. An attack section period number counter 39 is provided to specify each one-cycle waveform within the entire attack section waveform, and the output of this counter 39 and the attack section start address A ₀ , B ₀ , C ₀ . . . An adder 41 is provided to specify the absolute address of each one-period waveform within the entire waveform of the attack section by addition and synthesis.

The hardware configuration of the attack part period number counter 39 is the same as that of the counter 38 described above, and the adder 43,
It includes a gate 44 and a shift register 45.
This counter 39 counts the carry-out signal CRY from the most significant bit of the adder 35 in a time-division manner for each channel. This carry-out signal CRY is generated every time a certain channel of the counter 38 counts 256 note clock pulses (every time one cycle of the square waveform is read), and by counting this, the number of cycles of the attack section can be determined. can be counted.

The output of the counter 39 is applied to a gate 42, and the gate 42 is opened only during reading of all waveforms in the attack section by an attack signal AT, which will be described later.
1 is given the counter output. The lowest 8 bits of the N-bit start address data generated by the start address generation circuit 40 are input to the other input of the adder 41. Of the N2 bits of start address data, the 8-bit output data of the adder 41 is located below the most significant N-8 bits of data that were not input to the adder 41.
Both data constitute the most significant N bits of address data MADR. The count value of the counter 39 indicates the number of cycles counted from the first cycle of the entire waveform of the attack section, while the start address
A ₀ , B ₀ , C ₀ . . . indicate the first absolute addresses of all waveforms in the attack portion in the waveform memory 14. Therefore, by adding the two, it is possible to specify the first absolute address for each period of the entire waveform of the attack section (that is, specify each one-period waveform).

The attack end detection circuit 46 counts the carryout signal CRY given from the counter 38 and checks whether reading of all waveforms of the attack portion has been completed, an example of which is shown in FIG.

In FIG. 9, the attack part period number memory 47
The number of cycles of the entire waveform of the attack section is stored for each timbre, and the number of cycles data ATN is read out in accordance with the timbre selection information TC. Subtractor 48, gate 4
9. A counter 52 consisting of a selector 50 and a 24-stage/8-bit shift register 51 counts down the number of cycles each time one cycle of the attack waveform is read out, and performs the down-count in a time-division manner for each channel. . The selector 50 selects the cycle number data ATN read from the memory 47 when the key-on pulse KONP is generated via the B input, and takes it into the shift register 51. At other times, data to be applied to the A input of the selector 50 is selected from the final stage of the shift register 51 via the subtracter 48 and is applied to the shift register 51. A carry-out signal CRY output from adder 35 in FIG. 6 is input to gate 49. Gate 49 is enabled during attack by attack signal AT and carries out signal CRY.
is given to the subtracter 48. The subtracter 48 subtracts 1 from the output data of the shift register 51 when the carry-out signal CRY is applied. In this way, data indicating the number of cycles of the entire waveform of the attack section is initially entered into the shift register 51, and from then on, the data is subtracted by 1 each time one cycle of the waveform of the attack section is read, and finally reading of the entire waveform of the attack section is completed. When the data is all "0".

The output of the counter 52 is taken out from the selector 50 and applied to an all "0" detection circuit 520. The all “0” detection circuit 520 is the selector 50
It detects whether the count output data given from is all "0" or not, and outputs a signal "1" when all "0". The output signal of this detection circuit 520 is output as an inverted attack signal, and the signal inverted by the inverter 53 is the attack signal.
Output as AT. Therefore, during the attack, the attack signal AT is "1" and the inverted attack signal is "0", but when the attack is completed, the AT is inverted and becomes "0" and "1". Delay circuit 54
is to set a signal delay of one cycle of the time-division channel timing by a clock pulse _{φ 2 ×} 12 with a period 12 times that of the clock pulse φ 2, and delays the attack signal AT and outputs it to the AND circuit 55.
give to An inverted attack signal is given to the other input of the AND circuit 55, and when the signal switches from "0" to "1", it is activated during one time slot (two time slots of subchannel) corresponding to that channel. The output of the AND circuit 55 becomes “1”, which is the attack end signal.
Output as ATEND. Furthermore, when the attack is completed, the gate 4 is turned on by the attack signal AT being “0”.
9 is closed and no further down-counting is performed. Therefore, the count value of the counter 52 maintains all "0" except at the time of attack. The operation example in Fig. 9 is shown for one channel.
It will look like Figure 2 a.

Returning to FIG. 6, start address generation circuit 4
0 selects a set of start addresses according to the tone selection information TC, generates the start address of the attack section according to the key-on pulse KONP, and sequentially changes the start address of each segment waveform according to the waveform switching command signal WCHG. It is generated by switching. An example of this start address generation circuit 40 is shown in FIG.

In FIG. 10, start address memory 5
6 has multiple sets of start addresses A ₀ , A ₁ , A 2 ..., B ₀ , B ₁ , B ₂ ..., corresponding to each tone color A, B, C _... ,
C ₀ , C ₁ , C ₂ ... are stored in advance, respectively,
A set of start addresses (for example, A ₀ , A ₁ , A ₂ . . . for timbre A) is selected in accordance with the timbre selection information TC. 24 stage shift register 57, selectors 58, 59, 60, adder 61, gate 6
The loop containing 2 constitutes a counter, and the count value taken out from the gate 62 in this loop is applied to the address input of the start address memory 56. The start address memory 56 stores a selected set of start address data (e.g.
A ₀ , A ₁ , A ₂ ...) are read out sequentially according to the count value given to the address input. That is, when the count value given from the gate 62 is "0", the start address _A0 of the attack section is read out,
When it is "1", read the start address A ₁ of the first segment waveform SEG1, and when it is "2", read the start address of the second segment waveform SEG2.
Read A ₂ . In this way, the start address data read from the start address memory 56 specifies the waveform to be read from the waveform memory 14 (FIG. 3).

The gate 62 is enabled by the inverted signal of the key-on pulse KONP, and the gate 62 closes in the channel in which the key-on pulse KONP is generated, and the stored contents of the shift register 57 corresponding to the channel are cleared. The output of the final stage of the shift register 57 is applied to the C input of the selector 58, and is also applied to the A input and B input of the selector 58 via delay circuits 63 and 64, respectively. The delay circuit 63 receives a clock pulse φ ₁
A clock pulse φ ₁ with a period equivalent to 23 periods of
The delay is controlled by ×23, and the delay circuit 64 is delayed by the clock pulse _φ1 . The A selection input SA of the selector 58 is supplied with the output of an AND circuit 65 which performs AND logic on the clock pulse φ ₂ and the waveform switching command signal WCHG. The B selection input SB has the inverted signal of clock pulse _φ2 and the signal
The output of an AND circuit 66 which performs the AND logic of WCHG is given. C selection input SC has a signal
A signal obtained by inverting WCHG by an inverter 67 is provided.

The output of selector 58 is given to the A input of selector 59. A numerical value "1" is given to the B input of the selector 59, and a numerical value "2" is given to the C input. The A selection input SA of the selector 59 is given a signal obtained by inverting the attack end signal ATEND by an inverter 68, and the B selection input SB is given the output of an AND circuit 69 which performs AND logic on the clock pulse φ ₂ and the signal ATEND. C selection input SC
is the inverted signal of clock pulse _φ2 and the signal
The output of an AND circuit 70 which performs the AND logic of ATEND is given.

The output of selector 59 is given to adder 61. A waveform switching command signal WCHG is given to the other input of the adder 61.
1 is added to the output data of the selector 59 each time becomes "1". The output of the adder 61 is the selector 6
0 to the B input. The output of the sequence return destination memory 71 is applied to the A input of the selector 60. Further, the output of the adder 61 is given to the final segment detection circuit 61A, and the output signal of this detection circuit 61A is input to the A selection input of the selector 60.
SA, and its output signal is sent to the inverter 72.
The inverted signal is applied to the B selection input SB.
The output of selector 60 is applied to shift register 57 via gate 62.

Since the shift register 57 has 24 stages and the operating clock pulse is _φ1 , the counting operation is performed in a time-division manner in a total of 24 time slots for each subchannel of each channel 1 to 12.
The counting operation for one channel will be explained below. First, as mentioned above, the key-on pulse
When KONP occurs, gate 62 is closed,
The contents of the two stages of the shift register 57 corresponding to the channel are all cleared to "0". As described later, the waveform switching command signal WCHG is not generated during the attack, so the selector 5
8 always selects C input. Further, during the attack, the attack signal ATEND is "0", and the selector 59 selects the A input. Further, the output signal of the final segment detection circuit 61A is "0" until the reading of the segment waveform of the final rank is completed, and the selector 60 selects the B input.
Therefore, the contents of the cleared shift register 57 are transferred to the same channel timing via the C input of the selector 58, the A input of 59, the adder 61, the B input of the selector 60, and the gate 62 with a delay of one channel timing cycle. Cycle in sync.
Therefore, starting address memory 5 from gate 62
The count value given to 6 is maintained at "0", and data indicating the start address (for example, A ₀ ) of the attack section is read out accordingly.

When the attack is completed, the attack end signal ATEND is generated from the attack end detection circuit 46 of FIG. 9 only once at the channel timing (time slot for two subchannels) as described above. As a result, AND circuits 69 and 70 are enabled, and the B input of selector 59 is selected in the first half time slot (that is, the timing of subchannel 1 when clock pulse φ ₂ becomes "1").
Numerical data “1” is stored in the shift register 57. Further, in the latter time slot (that is, the timing of subchannel 2 when clock pulse φ ₂ becomes "0"), the C input of selector 59 is selected, and numerical data "2" is transferred to shift register 57.
Stored in

In this way, after the attack is completed, the numerical value "1" is initially set corresponding to subchannel 1, and the numerical value "2" is set corresponding to subchannel 2. As a result, from the start address memory 56, the start address (for example, A ₁ ) of the first segment waveform SEG1 corresponding to subchannel 1 is stored.
Data indicating the start address (for example, A ₂ ) of the second segment waveform SEG2 corresponding to subchannel 2 is read out. This state is maintained until the next waveform switching command signal WCHG is applied. Furthermore, gate 6
An example of a change in the count value for one channel (two subchannels) output from the 12th
Shown in Figure b.

The waveform switching command signal WCHG is generated by being alternately switched in correspondence to one of two subchannels related to one channel, as will be described later. As shown in FIG. 12b, the signal first occurs corresponding to sub-channel 1, then it occurs corresponding to sub-channel 2, and thereafter the signal is switched alternately. Therefore, in the circuit of FIG. 10, the counting operation in response to the waveform switching command signal WCHG is performed with respect to one of the two subchannels.

When the switching command signal WCHG is generated corresponding to the first half channel time slot, that is, subchannel 1, the AND circuit 65 is enabled in response to the clock pulse φ ₂ being "1", but the AND circuit 66 is not enabled. . Therefore, in that case,
The output of the delay circuit 63 is selected via the A input of the selector 58, and 1 is added to this data by the adder 61 using the signal WCHG. The delay circuit 63 outputs data 23 time slots ago at subchannel timing, and this is count data of subchannel 2 of the previous cycle regarding the same channel. The value added by 1 to the count value of subchannel 2 becomes the new count value of subchannel 1. In this case, subchannel 2 is larger than the count value of subchannel 1, and therefore, the count value of subchannel 1 is substantially the same as adding two. For example, as mentioned above, when the count value of subchannel 1 is "1" and the count value of subchannel 2 is "2", the first waveform switching command signal
When WCHG is given corresponding to subchannel 1, 1 is added to the count value "2" of subchannel 2 in the previous cycle (that is, the output of delay circuit 63) at the timing of subchannel 1, and
The count value of subchannel 1 changes to "3". In this case, at the timing of subchannel 2, the shift register 5
The output of No. 7 is selected as is, and the count value is not increased. Therefore, the count value of subchannel 2 remains "2". In this way, the read address of subchannel 1 is changed by the first waveform switching command signal WCHG, and the start address of the third segment waveform SEG3 (for example,
A ₃ ) is read from memory 56. On the other hand, the read address of subchannel 2 does not change, and the start address data of SEG2 of the second segment waveform is still read.

When the waveform switching command signal WCHG is generated corresponding to subchannel 2, contrary to the above, the AND circuit 66 is enabled, the output of the delay circuit 64 is selected via the B input of the selector 58, and this data is 1 is added by the adder 61 according to the signal WCHG. The delay circuit 64 outputs the count value of the subchannel one time slot before, that is, the subchannel 1 of the same channel, and the value added by 1 to this count value becomes the new count value of the subchannel 2. In this case, the count value of subchannel 1 is greater than the count value of subchannel 2 by 1, and therefore, the count value of subchannel 2
This is essentially the same as adding 2 to the count value. For example, as mentioned above, when the count value of subchannel 1 is "3" and the count value of subchannel 2 is "2", and the signal WCHG is generated corresponding to subchannel 2, the count value of subchannel 1 is "2". 3" remains as is, and the count value of subchannel 2 changes to "4".

As described above, each time the waveform switching command signal KCHG is generated alternately corresponding to one of subchannels 1 and 2, the count value of the corresponding subchannel increases by 2, and correspondingly, each subchannel The order of the segment waveform specified by is "1"
and "2", "3" and "2", "3" and "4", "5" and "4", and so on, and are alternately switched every second.
Through such alternating waveform switching control for every second waveform, allocation of segment waveforms to both streams (subchannels 1 and 2) as shown in FIG. 2B is realized.

When a predetermined number of waveform switching command signals WCHG are applied and the output of the adder 61 exceeds a value specifying the final segment waveform, the output signal of the final segment detection circuit 61A becomes "1". Note that this detection circuit 61A stores, for each tone color, a numerical value that designates the last segment waveform among the plurality of segment waveforms stored for each tone color in the waveform memory 14, and uses the tone color selection information TC.
Compares the numerical data read from the memory with the output data of the adder 61 and outputs a "1" signal when "output data value > numerical data value". It consists of a comparator and a comparator. When the output signal of the detection circuit 61 becomes "1", the selector 60 switches to select the A input. As a result, the sequence return destination memory 7
The return destination order data read from 1 is selected by the selector 60 and stored in the shift register 57. The sequence return destination memory 71 stores return destination ranking data for subchannels 1 and 2 for each timbre, which instructs which ranking segment waveform should be returned to and read after reading the final ranking segment waveform. Then, predetermined return destination order data is read out in accordance with the tone color selection information TC and the clock pulse _φ2 . If the sound continues even after reading out the segment waveform of the final rank, the sequence return destination memory 71 is set so that the reading continues by returning to the segment waveform of the rank corresponding to the return destination rank data. It is provided. In this case, the return destination order data stored in the sequence return destination memory 71 is as follows:
Sequence waveform stored in waveform memory 14
For tones where the total number of SEG1 and SEG2 is an even number, the number i indicates the order of the segment waveform SEGi that is actually read back corresponding to subchannel 1.
However, a numerical value i+1 indicating the rank of the next segment waveform GEGi+1 of the segment waveform SEGi is stored corresponding to subchannel 2,
Contrary to the above case, for tones with an odd total number of sequence waveforms, a numerical value i is stored corresponding to subchannel 2, and a numerical value i+1 is stored corresponding to subchannel 1, respectively.

For example, if timbre A is selected and the total number of segment waveforms related to timbre A is "6", and the order of the segment waveform to return to is "3", the count value of subchannel 1 will change from "0" to " 1” →
"3" → "5" → "3" → "5" → "3" → "5"
..., while the count value of subchannel 2 is "0" → "2" → "4" → "6" → "2" →
It changes as "6" → "2" → "6"... As a result, for subchannel 1, the segment waveform
After SEG1, SEG3, and SEG5 are specified sequentially, segment waveforms SEG3 and SEG5 are repeatedly specified,
On the other hand, for subchannel 2, the segment waveform
After SEG2, SEG4, and SEG6 are sequentially specified, segment waveforms SEG4 and SEG6 are repeatedly specified.

Next, the crossfade control circuit 16 will be explained with reference to FIG.

The counting means 73 is for generating a time function for setting a time change in weighting, and includes a first counter 73A and a second counter 73B. Both counters 73A, 73B include adders 74A, 74B, gates 75A, 75B, and 12-stage shift registers 76A, 76B controlled by clock pulse φ ₂ , respectively, and the outputs of shift registers 76A, 76B are added together. It is possible to perform a counting operation on a time-division basis for each channel by circulating through circuits 74A, 74B and gates 75A, 75B. The first counter 73A is for counting the number of times segment waveforms are switched. The change rate memory 77 stores change rate data corresponding to the number of times of switching in advance for each tone, and contains tone selection information TC.
One set of change rate data is selected according to the change rate data, and one change rate data DT is read out from the selected data according to the number of times of switching counted by the first counter 73A. In addition, gate 75
The output of A is taken out as the count output of the first counter 73A and input to the memory 77. The first counter 73A and the change rate memory 77 correspond to counting rate control means.

The second counter 73B counts from a first predetermined value (for example, 0) to a second predetermined value (for example, the maximum value) at a rate according to the change rate data DT read from the memory 77. It is. Change rate data DT is input to adder 74B, and second counter 73B accumulates this data DT at predetermined time intervals. Gate 75B is enabled at non-attack times by the inverted attack signal. Therefore, the count content of the counter 73B is "0" during the attack.
is cleared, and starts counting the data DT when the attack ends.

The count output of the second counter 73B is taken out from the gate 75B and input to a function conversion circuit 78 consisting of an exclusive OR circuit. This function conversion circuit 78 converts the lower n bits of the n-bit count output.
-1 bit is input to the exclusive OR circuit separately, the most significant bit MSB is input commonly to each exclusive OR circuit,
When MBS is "0", the lower n-1 bits are passed through as is, but when it is "1", the lower n-1 bits are inverted and output. In this way, the count value increases from the minimum value 0 to the maximum value ²ⁿ , turns around at the 2n ^-1 position, increases from 0 to 2n ^-1 , and then from 2n ^-1 to 0.
Convert to a triangular wave-like function that decreases to .

The output of the function conversion circuit 78 is used as the basic interpolation function IPF2 for the second series (subchannel 2). The inversion circuit 79 inverts each bit of the interpolation function IPF2 to form a function with inverse characteristics, and this function with inverse characteristics is taken as the basic interpolation function IPF1 for the first series (subchannel 1). An example of these interpolation functions IPF1 and IPF2 is shown in Figure 11c.
is shown. Note that during the attack, the output of the second counter 73B is all bits "0", so the output of the function conversion circuit 78 is all bits "0", and the value of the second series interpolation function IPF2 reaches the minimum value (0). ) is maintained, and the value of the first series interpolation function IPF1 is maintained at its maximum value.

The selector 80 is for time-division multiplexing the interpolation functions IPF1 and IPF2 in accordance with the timing of each subchannel 1 and 2, and is connected to the A input.
When IPF2 is added and IPF1 is added to the B input and clock pulse _φ2 is “1” (subchannel 1
When _φ2 is "0" (time slot of subchannel 2), select IPF1 of the A input.

The switching control means 81 controls the waveform switching operation in the waveform specifying means, that is, the start address generation circuit 40 in FIG. All “0” detection circuit 82 detects whether all bits are “0” or not.
and the output of this detection circuit 82 and the inverted attack signal.
It includes an AND circuit 83 inputting AT. The AND circuit 83 is enabled by a signal other than when attacking, and the all "0" detection circuit 82
The output signal “1” is the waveform switching command signal WCHG.
Output as . When one of the two subchannel interpolation functions IPF1 and IPF2 that gradually decreases over time with a negative slope becomes all bits "0", the output of the all "0" detection circuit 82 is output at the timing corresponding to that subchannel. becomes "1", and in response, a waveform switching command signal WCHG is generated. Interpolation function of both subchannels IPF1, IPF
Since the slope of 2 changes every interpolation interval, the waveform switching command signal WCHG is generated by switching alternately corresponding to one subchannel every time one interpolation is completed. Interpolation function IPF1, IPF in Figure 12c
An example of the generation of the waveform switching command signal WCHG corresponding to 2 is shown in FIG. 12b.

The interpolation functions IPF1 and IPF2 outputted from the selector 80 in a time-division manner have temporally linear characteristics, but the crossfade curve memory 84, which corresponds to interpolation function storage means, can change these interpolation functions to arbitrary characteristics. It is provided for the purpose of conversion. For example, various interpolation characteristic curves (weighting curves) as shown by solid lines in FIG. (selection operation using a dedicated switch, etc.), and the selected interpolation characteristic curve is applied to the interpolation functions IPF1 and IPF from the selector 80.
2 is read out as the address.
As mentioned above, the interpolation function IPF1 of both subchannels,
Since IPF2 (so to speak, this is a basic interpolation function) has inverse characteristics, the reading direction of the memory 84 is mutually opposite between both subchannels (when one is in the positive direction, the other is in the opposite direction), and is mutually A curve with an inverse characteristic is read out from the memory 84 in a time-division manner. For example, when an interpolation characteristic curve as shown by a solid line in FIG. 13 a to e is read out corresponding to one subchannel, an interpolation characteristic curve as shown by a broken line in the same figure corresponds to the other subchannel. Read out.

The interpolation characteristic curve data corresponding to each subchannel for each channel read out in a time-divisional manner from the memory 84 as described above is given as crossfade curve data CF to the multiplier 18 in FIG. The corresponding segment waveform data is weighted (amplitude control) according to the characteristics.

Returning to FIG. 11, the all "0" and all "1" detection circuit 85 outputs the switching synchronization signal CHGS in synchronization with the waveform switching timing, and the output of the interval conversion circuit 78, that is, the interpolation function
Input IPF2 and detect whether the value is all bits "0" or all bits "1". As is clear from Figure 12c, the correlation function changes in a triangular waveform.
At the upper peak of IPF2, all bits are "1", and at the lower peak, all bits are "0", which corresponds to the waveform switching timing, that is, the timing of the waveform switching command signal WCHG. Switching synchronization signal CHGS corresponds to when all bits are “0” or when all bits are “1”
becomes “1”. This signal CHGS becomes "1" in the time slots of both subchannels, that is, in the time slots of one channel corresponding to one cycle of clock pulse _φ2 .

This signal CHGS is delayed by one cycle of the time division channel timing in accordance with the clock pulse φ ₂ ×12 in the delay circuit 86, and is applied to the adder 74A of the counter 73A via the gate 87. The output of the adder 74A is applied to a 12-stage shift register 76A via a gate 75A, delayed by one cycle of time division channel timing, and returned to the input of the adder 74A. Gate 75A
is controlled by a signal that is an inversion of the attack end signal ATEND.
It is instantaneously closed only when ATEND occurs, and the memory of the shift register 76A regarding the corresponding channel is cleared. The output of gate 75A is applied to change rate memory 77 and all "1" detection circuit 88 as described above. All “1”
The detection circuit 88 outputs a signal "1" when all bits of the count value of the counter 73A reach "1", that is, the maximum value.
Output. This output is inverted by an inverter 89 and is applied to the control input of the gate 87.

The count value of the counter 73A maintains the maximum value during the attack, and the gate 87 is closed. When the attack is completed, the attack end signal is sent.
When the count value is cleared by ATEND,
The output of the all "1" detection circuit 88 becomes "0" and the gate 87 is opened. Thereafter, each time the switching synchronization signal CHGS is generated, the count value of the counter 73A increases, and the number of waveform switching is counted. Then, the count value is the maximum value (all “1”)
When this happens, the gate 87 closes and the counting operation stops. Note that the delay circuit 86 is provided to delay the timing at which the signal CHGS is input to the counter 73A by the time delay between the input and output of the shift register 76A. Switching synchronization signal
An example of the number of switching times counted by CHGS and counter 73A is shown in FIG. 12c.

As described above, the change rate memory 77 reads out predetermined change rail data DT in response to the count value of the counter 73A. This rate of change data
The value of DT determines the rate of increase in the count value of the second counter 73B, and the slopes of the interpolation functions IPF1 and IPF2 are determined. , t3, t4...) are determined. The memory 77 stores change rate data arbitrarily according to the number of waveform switching (that is, for each interpolation interval).
Since the DT can be set, the lengths t1, t2, t3, t4, etc. of each interpolation section are not uniform and can be set completely arbitrarily. Note that once the first counter 73A reaches the maximum value, it is maintained thereafter, so that the change rate memory 77 continuously reads out the change rate and data DT corresponding to the maximum value.
Of course, like the other counters, the first counter 73A performs a time-division counting operation for each channel, so the above-mentioned counting of the number of waveform switching and reading of the change rate data DT are performed for each channel in a time-division manner. .

Next, a specific example of each segment waveform SEG1 to SEG5 and a specific example of a musical tone signal that is interpolated and synthesized based on the segment waveforms will be described.

Figures 14 to 18 are each segment waveform SEG
This shows an example of segment waveforms SEG1 to SEG5.
SEG5 is made up of a combination of four types of components: a fundamental wave, a second overtone, a third overtone, and a fourth overtone, with the same relative amplitude. In each figure, the initial phase for each component (orders 1, 2, 3, and 4) is written. Further, in FIGS. 14 and 15, exploded views of each component included in the segment waveforms SEG1 and SEG2 are added for reference.

Segment waveforms with adjacent switching orders are SEG
1 and SEG2, SEG2 and SEG3, SEG3 and SEG4,
SEG4 and SEG5.

In this example, segment waveforms SEG1 to SEG5
Regarding all of the above, a predetermined phase difference is set for each overtone component between segment waveforms with adjacent switching orders. Furthermore, the amount of phase difference regarding components of the same order is set to be the same between any adjacent segment waveforms. Further, the amount of the phase difference differs between components of different orders, and the amount of the phase difference increases as the order becomes higher. In other words, each segment waveform SEG1 to SEG
Looking at the initial phase of the second harmonic component of 5, it is 0 degrees, respectively.
They are 22.5 degrees, 45 degrees, 67.5 degrees, and 90 degrees, and the phase difference between any adjacent segment waveforms is set to 22.5 degrees. Similarly, looking at the initial phase of the third overtone component, the phase difference between any adjacent segment waveforms is set to 45 degrees. Furthermore, looking at the initial phase of the fourth overtone component, the phase difference between any adjacent segment waveforms is 90 degrees.

FIG. 19 and FIG. 20 show the segment waveforms SEG1 to SEG5 of FIGS.
This shows an example of a musical tone signal synthesized by interpolation using the device shown in the figure. Fig. 19 shows interpolation sections t ₁ and t ₂ , and Fig. 20 shows the following interpolation sections t ₃ and t ₄ . It is shown. 19 and 20, as an example, the waveform memory 14 is read out according to the fundamental wave frequency of 440 Hz of A4 sound, and the time of each interpolation interval t ₁ to t ₄ is calculated.
An example is shown in which each time is fixed at a time (18.182 ms) corresponding to 8 cycles of A4 sound.

FIG. 21 is a diagram showing the frequency spectrum of the musical tone signal shown in FIGS. 19 and 20. As mentioned above, the fundamental frequency is 440 Hz of A4 tone. FIG. 22 is a spectrum diagram showing the vicinity of the third and fourth overtones in FIG. 21 enlarged in the horizontal axis direction. As is clear from both figures, the frequencies of the second harmonic component, third harmonic component, and fourth harmonic component for which a predetermined phase difference is set between adjacent segment waveforms vary from the normal integral multiple frequency according to the amount of the phase difference. It's deviated. The conditions of the specific example described here are the same as those exemplified to explain the outline of the invention in the first part of the description of this embodiment. Therefore, the specific numerical values of the frequencies of each component can be derived from the numerical values of f ₂ , f ₃ , and f ₄ mentioned above, and the frequency deviation of the second overtone is 3.44.
Hz, the frequency deviation of the third harmonic is 6.9Hz, and the frequency deviation of the fourth harmonic is 13.8Hz. In this way, disharmony is realized. Note that, as in this specific example, the anharmonicity in which the frequency shift increases as the higher-order components increase is close to the anharmonicity of actual piano sounds and harpsichord sounds, and is therefore preferable.

It will be clear from the above that if only a specific component is desired to be anharmonic, it is sufficient to set the phase difference between the segment waveforms for only that component.

In addition, it is not necessary to set a phase difference to a predetermined component in every segment waveform.
A predetermined plurality of segment waveforms within it (e.g.
The phase difference may be set in SEG1, SEG2, SEG3 only). In that case, disharmony is achieved during a specific period of the entire pronunciation period from the start to the end of the pronunciation.

In addition, the amount of phase difference between each segment waveform regarding components of the same order is not kept constant, but is changed over time (i.e., the amount of phase difference in at least one set of adjacent segment waveforms is different from the others). ). In that case, the degree of anharmonicity (frequency shift) can be changed over time (changed in an interpolation section of a segment waveform in which the phase difference is different from the others).

In the examples shown in FIGS. 14 to 22, the relative amplitude of each component in each of the segment waveforms SEG1 to SEG5 is the same, and the timbre does not change even if the segment waveforms are switched. However, the present invention is not limited to this, and each of the segment waveforms SEG1 to SEG5 may differ not only in the initial phase of each component but also in their relative amplitude, and in this case, a temporal change in timbre can also be realized.

Next, a modification of the above-described embodiment will be described.

The first counter 73A and the change rate memory 77 in FIG. 11, that is, the counting rate control means, can also be changed as shown in FIG. 23.
Change rate initial value memory 90 contains change rate data.
Only the initial value of DT is stored for each timbre, and predetermined change rate initial value data is read out according to the timbre selection information TC. The selector 91 instantaneously selects the initial value data from the memory 90 only at the end of the attack in response to the attack end signal ATEND, and stores it in the shift register 92. shift register 9
2 has 12 stages, and data for each channel can be stored. The output of the final stage of the shift register 92 is outputted as change rate data DT and is applied to a shift circuit 93 where it is bit shifted in accordance with a control signal from an AND circuit 94 and circulated through the A input of the selector 91.
The AND circuit 94 is connected to an inverted signal of the least significant bit LSB of the change rate data DT and a delay circuit 86 (the first
A delayed switching synchronization signal CHGS' is provided in FIG. As an example, the shift circuit 93 shifts each bit of the input data by one bit to the lower order when the signal "1" is applied from the AND circuit 94.

When the LSB of the data DT is "0", the AND circuit 94 is enabled, and the initial value data stored in the shift register 92 is sequentially shifted down one bit at a time each time the switching synchronization signal CHGS' is generated. This shift is performed on a time-sharing basis for each channel. When the LSB eventually becomes "1", the AND circuit 94 is disabled and the data DT maintains its current value.

In the examples shown in FIGS. 11 and 23, the interpolation function folded into a triangular waveform (basic interpolation Since the count value of the counter 73B always starts increasing from all bits "0" and finally reaches all bits "0" due to overflow, it is accurate. required to return to. Therefore, the value of the changed route data DT is required to be a power of 2, such as "1", "2", "4", and "8". On the contrary,
In order to be able to arbitrarily set the value of the change rate data DT, the second counter 73B may be changed as shown in FIG.

In counter 72B shown in FIG. 24, a gate 94 is provided between adder 74B and gate 75B. A signal obtained by inverting the carry-out signal from the most significant bit of adder 74B by inverter 95 is applied together with an inverted attack signal to AND circuit 96, and its output is used to invert gate 75B.
is controlled. The most significant bit MSB of the output signal of the adder 74B is input to the gate 75B and is also applied to the rising differential circuit 97, where it is applied to the lower n-1 bits.
The bit is input to gate 94. The rising differential circuit 97 outputs a signal “1” with a width of one period of the clock pulse φ ₂ when the MSB rises to the signal “1”.
This signal "1" is inverted by an inverter 98 and applied to the control input of the gate 94. The output of gate 94 (n-1 bits) and the MSB output of adder 74B are n
It is applied to gate 75B as a bit signal. The output of gate 75B is applied to shift register 76B and is also applied to function conversion circuit 78 in the same manner as described above.

During the attack, the AND circuit 96 is disabled by the inverted attack signal "0", and the gate 75B
is closed, and the count values of the counter 75B are maintained at all "0". When the attack is completed, the gate 75B opens, and since the gate 94 is normally open, a counting operation is possible, and the value of the change rate data DT is repeatedly added at predetermined time intervals (one channel timing cycle). In this way, the count value increases at an arbitrary rate depending on the value of the data DT. Most significant bit of addition result
When the MSB changes from "0" to "1", a pulse is output from the rising differential circuit 97 at that channel timing, and the gate 94 is temporarily closed. Since the increase rate of the count value is arbitrary (not limited to a power of 2), when the MSB of the addition result switches from "0" to "1", the lower n-1 bits may not all be "0". do not have. However, as described above, by temporarily closing the gate 94,
The lower n-1 bits of the addition result are forcibly cleared to all bits "0" and the count value MSB is given to the shift register 76B via the gate 75B.
is “1” and its lower n-1 bits are all “0”
becomes.

When the most significant bit MSB of the addition result changes from "1" to "0", that is, when the carry-out signal is output from adder 74B, AND circuit 96 is disabled and gate 75B is closed.
Also at this time, since the increase rate of the count value is arbitrary, the output of the adder 74B does not necessarily have all bits "0". However, by closing the gate 75B for one hour, all bits of the count value output from the gate 75B are forced to be "0".

As a result, the output of the function conversion circuit 78 always becomes all bits "0" or all bits "1" at the turning point, and the detection circuits 82 and 85 (FIG. 11)
In this case, all "0" or all "1" can be detected without any problem, and waveform switching control can be performed without any problem. Therefore, according to the configuration shown in FIG. 24, the change rate data DT can be set to any value, not just a power of 2. In this case, in order to cause the waveform to be switched when the segment waveform is read exactly for an integral number of cycles, the value of the data DT may be determined in association with the musical tone frequency.

In the embodiment described above, the counting rate in the counting means 73 is determined by repeatedly counting data DT of appropriate values at predetermined time intervals.
It is now determined by the value of . However, the counting rate is not limited to this, and the counting rate may be determined by keeping the value of data DT constant and variably controlling the counting time interval (count clock), or by variably controlling both the value of data DT and the counting time interval. You can do it like this.

Furthermore, in the example of FIG. 10, in order to increase the count value (segment waveform order data) of a certain subchannel by 2, the start address generation circuit 40 extracts the count value of the other subchannel and increases it by 1. Therefore, the calculation is equivalent to increasing by 2. However, the present invention is not limited to these, and the start address generation circuit 40 is
It may be configured as shown in FIG. 5 and directly add 2 to the count value of the subchannel.

In FIG. 25, the same symbols as in FIG. 10 indicate the same circuits, and the circuits corresponding to the symbols 58, 63 to 67 in FIG. 10 are omitted, and the output of the shift register 57 is directly input to the A input of the selector 59. The difference is that Further, a gate 99 is provided, and data of numerical value "2" is provided to the adder 61 via the gate 99 every time the waveform switching command signal WCHG is provided. Therefore, when the waveform switching command signal WCHG is generated corresponding to one subchannel, the numerical value "2" is added to the count value output from the shift register 57 at the timing of that subchannel, and the number "2" is added to the count value output from the shift register 57 at the timing of that subchannel. It operates in the same way as in Figure 9.

In the embodiment described above, the basic interpolation functions IPF1 and IPF2 (address signals of the memory 84) change in a triangular waveform, as shown in FIG. 2b, so that two segment waveforms are always weighted. However, the present invention is not limited to this, and two waveforms may be weighted only during the transition period of waveform switching. Second
Figure 6 shows the basic interpolation functions IPF1 and IPF2 in that case.
(memory 84 address signal), for example, segment waveforms SEG1 to SEG2
In the transition period P ₁ , both functions IPF
1, IPF2 is crossed, and thereafter the interpolation function IPF2 for SEG2 is maintained at the maximum value, and the interpolation function IPF1 for SEG1 is maintained at the minimum value. From SEG2
The same applies to the transition period _P2 when switching to SEG3. In order to perform the control as shown in Fig. 26, the first
The detection circuits 82 and 85 in FIG. 1 do not simply detect all "0" or all "1", but detect a change from all "0" or all "1" in an increasing direction or a decreasing direction. Waveform switching command signal WCHG or switching synchronization signal based on
All you have to do is generate CHGS.

Further, in the above embodiment, two streams (subchannels) for interpolation are time-divisionally processed, but they may be processed in parallel. In addition, in Fig. 3, two series of music waveform signals weighted for interpolation are digitally added in an adder 20 and then subjected to D/A conversion, but each series is independently D/A converted and then mixed or independent. You may also choose to pronounce it.

Further, although the waveform memory 14 shown in FIG. 3 stores the amplitude value data of each sample point of the waveform as is, the present invention is not limited to this, and various storage methods may be employed. For example, the amplitude data of each sample point can be obtained by storing the difference values of the amplitude values between each sample point, reading them out and then accumulating them, or There are various methods, such as storing the data in parts and performing arithmetic processing after reading it out to obtain the real number of the amplitude value of each sample point.

In addition, in the above example, the segment waveform (SEG
1, SEG2, ...), one cycle of the waveform is stored as it is in the waveform memory 14, but the present invention is not limited to this, and it is also possible to store only a half cycle of the waveform, and in this case, the read half cycle Positive for the waveform
Negative polarities may be added alternately to form a one-period waveform. Furthermore, the segment waveforms stored in the waveform memory 14 are not limited to one-cycle waveforms, but are also multiple-cycle waveforms (for example, two-cycle waveforms).
It may also be a waveform with a period of 30 minutes.

In the above embodiment, the attack portion of the musical tone signal is generated by storing the continuous multi-cycle waveform as it is in the waveform memory 14 and reading it out as is. Also, according to the present invention, a plurality of segment waveforms are stored in the waveform memory 14, and these are sequentially switched and read out.
Of course, the above-mentioned interpolation process may be performed at the time of waveform switching to generate musical tone signals. Conversely, the segment waveform interpolation synthesis according to the present invention may be applied only to a part of the period from the start to the end of sound generation.

In the above embodiment, the musical tone signal generating device according to the present invention is used in a multi-tone electronic musical instrument, but it can of course also be used in a single-tone electronic musical instrument. Applicable to all devices. Further, the present invention can be applied not only to the generation of scale sounds but also to the generation of rhythm sounds and the like.

In the example shown in FIG. 11, the final interpolation function, that is, the crossfade curve data CF is stored in the memory 84.
However, without providing the memory 84, IPF1 and IPF2 are directly applied to the multiplier 18 (FIG. 3) as weighting coefficients. or,
IPF1 and IPF2 may be modified by appropriate logical operations and then provided to the multiplier 18.

In addition, in the example shown in Figure 11, switching of segment waveforms is controlled by time (change rate data DT
is set regardless of the pitch of the musical tone to be generated), but the present invention is not limited to this, and the switching may be performed each time the segment waveform is repeatedly read out a predetermined number of cycles. In that case, for example, the counting means 73 shown in FIG. 11 may perform counting in response to the carry signal CRY of the counter 38 shown in FIG. In this case, the number of cycles at which the segment waveform should be switched may be set variably for each interpolation interval t ₁ , t ₂ , t ₃ . . . or for each timbre or each note name, or vice versa. , may be fixed to a constant number of cycles.

As is clear from the above, the amount of anharmonicity obtained by the present invention is determined not only by the phase difference for each component between the two segment waveforms to be interpolated, but also by the time required for interpolation. Ru. Therefore,
Once each segment waveform has been stored in the waveform memory 14 with desired characteristics (desired phase characteristics for each component), the amount of anharmonicity (the amount of frequency deviation with respect to integral multiple frequencies) is controlled by controlling the time required for interpolation. ) can be variably controlled. This interpolation time control (time control for each interpolation interval t ₁ to _{t 4} ) is performed in the 11th
This is realized by variably controlling the change rate data DT in the figure, or by variably controlling the set value of the number of cycles when switching the segment waveform every predetermined number of cycles as described above.

Effects of the Invention As described above, according to the present invention, a plurality of tone waveforms (segment waveforms) including a fundamental wave and harmonic components are stored in the waveform storage means, and these are sequentially switched and read out, and the tone waveforms with adjacent switching order are generate a musical tone signal by temporally interpolating the musical tone signal, and at this time, determine the musical sound waveform to be stored such that a phase difference is established in at least one component between adjacent musical waveforms; Since the components are made to be anharmonic components, an excellent effect is achieved in that anharmonicity can be realized with a relatively simple configuration.

[Brief explanation of drawings]

In order to explain in principle that anharmonic components are generated by interpolation synthesis in this invention, FIG. A waveform diagram showing the waveform (particularly the phase relationship), FIG. 2 is a schematic diagram for explaining the principle of musical tone signal generation by interpolation in an embodiment of the present invention, and FIG. 3 is a diagram to which the musical tone signal generation device according to the present invention is applied. 4 is a timing chart showing an example of clock pulses and channel timing signals and an example of time-division channel timing used in the same embodiment. FIG. 5 is a timing chart showing an example of the time division channel timing used in the same embodiment. 6 is an electrical block diagram showing an example of the phase generator of FIG. 3, and FIG. 7 is an electrical block diagram showing an example of the time division control circuit of FIG. 6. Figure 8 is a timing chart showing an example of each part signal in Figure 7, Figure 9 is an electrical block diagram showing an example of the attack end detection circuit in Figure 6, and Figure 10 is a start address generation circuit in Figure 6. 11 is an electrical block diagram showing an example of the crossfade control circuit of FIG. 3; FIG. 12 is an electrical block diagram showing an example of the crossfade control circuit of FIG.
The figure is a timing chart showing an example of each part signal of FIG. 9, FIG. 10, and FIG. 11, and FIG.
Figures 14 to 18 are diagrams schematically showing the characteristics of various interpolation functions (crossfade curves) prepared in advance in the crossfade curve memory shown in the figure. Figures 14 to 18 are segment waveforms stored in the waveform memory shown in Figure 3. FIG. 14 is a waveform chart showing an example of each case, and FIG. 14 shows the first switching order.
Segment waveform SEG1 in FIG. 15 is the segment waveform SEG2 in the second switching order, and FIG. 16 is the segment waveform SEG3 in the third switching order, SEG17.
The figure shows the segment waveform SEG4 with the fourth switching order.
Figure 18 shows the segment waveform for the fifth switching order.
Figures 19 and 20 showing SEG5, respectively.
The figure is a waveform diagram showing an example of a musical tone signal synthesized in the embodiment of Figure 3 using the segment waveforms of Figures 14 to 18, and Figure 21 is a waveform diagram of the musical tone signal shown in Figures 19 and 20. 22 is a spectrum envelope diagram showing the frequency spectrum of the signal; FIG. 22 is a spectrum envelope diagram showing the vicinity of the third and fourth overtones in FIG. 21 enlarged in the horizontal axis direction; and FIG. 23 is a diagram showing the first counter and FIG. 24 is an electrical block diagram showing a modification of the change rate memory portion, that is, the counting rate control means. FIG. 24 is an electrical block diagram showing a modification of the second counter portion in FIG. An electrical block diagram showing an example of a modification of the start address generation circuit shown in the figure.
FIG. 26 is a diagram showing a different interpolation method from FIG. 2b,
It is. 10...keyboard, 11...key assigner, 13...
... Phase generator, 14 ... Waveform memory, 16 ... Crossfade control circuit, 18, 19, 20 ... Weighting calculation circuit which is part of interpolation means, 28
...Reading means, 40...Start address generation circuit corresponding to waveform specifying means, 46...Attack end detection circuit, 73...Counting means, 73A...
...first counter for counting the number of switching, 73
B...Second counter for time function generation, 77...
...Change rate memory, 81...Switching control circuit, 7
8...Function conversion circuit, 79...Inversion circuit for creating an interpolation function with inverse characteristics, 84...Crossfade curve memory, SEG1 to SEG5...Segment waveform, SEG1 ₂ , SEG2 ₂ ...Segment waveform SEG
1.Second harmonic component of SEG2.

Claims (1)

[Scope of Claims] 1. Waveform storage means that divides a plurality of musical sound waveforms into a plurality of sample points and stores waveform data corresponding to each sample point; reading means for repeatedly reading waveform data of a predetermined musical sound waveform; waveform specifying means for temporally switching and specifying a musical sound waveform to be read from the waveform storage means; and interpolation means for weighting both musical sound waveforms so as to smoothly transition to the next musical waveform, wherein each musical sound waveform stored in the waveform storage means includes a fundamental wave and a harmonic component, respectively. It is something that is
A musical tone signal generating device characterized in that, for all or a predetermined plurality of musical tone waveforms, at least one of the components has a predetermined phase difference between musical waveforms whose switching order is adjacent. 2. The amount of phase difference regarding components of the same order is
2. The musical tone signal generating device according to claim 1, wherein the musical sound waveforms are the same between any adjacent musical sound waveforms. 3. The amount of phase difference regarding components of the same order is
2. The musical tone signal generating device according to claim 1, wherein at least one set of adjacent musical waveforms is different from the others. 4. The musical tone signal generating device according to claim 1, wherein the amount of the phase difference is different between components having different orders. 5. The musical tone signal generating device according to claim 4, wherein the amount of the phase difference increases as the order becomes higher. 6. The waveform storage means further stores a plurality of cycle waveforms of the attack section, and the waveform designation means:
2. The musical tone signal generating device according to claim 1, wherein a plurality of cycle waveforms of the attack section are specified first, and then each of the musical tone waveforms is sequentially switched and specified. 7. The synthesized musical tone signal of the weighted sound waveforms of both musical tones obtained by the interpolation means includes an anharmonic component corresponding to the phase difference, and the amount of anharmonicity is determined by the phase difference and the waveform in the interpolation means. The amount of anharmonicity is determined according to the time required for transition, and the amount of anharmonicity can be controlled by variably controlling the time required for waveform transition in the interpolation means, that is, the interpolation time. The musical tone signal generating device described in .