JPH0263237B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency control device for an electronic musical instrument.

One type of electronic musical instrument is the music synthesizer, but most of this type of electronic musical instrument is based on analog circuits, and there are almost no such electronic musical instruments that have been realized using digital methods.

However, various researches have been conducted on methods for digitally obtaining musical sound waveforms in electronic organs and the like, and some of them appear to have been put to practical use. However, methods for obtaining such musical sound waveforms can be broadly classified into the following three types.

That is, in the first method, the ROM is addressed by the output of an address counter that cumulatively adds a constant value. In this system, when frequency control is performed to impart a vibrato effect or the like to the generated musical tone, this is done by changing the constant value that is cumulatively added. However, in the frequency control in this first readout method, the frequency information, that is, the added data changes exponentially depending on the scale frequency, so if you try to give a vibrato effect of the same depth across the diatonic scale, The data given varies depending on the scale,
The disadvantage is that frequency control becomes extremely complicated.

The second ROM read method is one in which one cycle of ROM read is an integral multiple of the output cycle of the basic clock, and frequency control is performed by controlling the number of clocks to read one cycle of the waveform. It is. However, since the frequency of the generated musical tone is an integral multiple of the output period of the basic clock, it is difficult to control the frequency of a semitone or less evenly across all scales in order to create a vibrato effect. This has the disadvantage that frequency control becomes complicated.

The third ROM read method uses a variable clock to read the ROM, and its frequency control is performed by varying the frequency of the read clock in an analog manner.For this reason, an analog oscillator is used as the oscillator. It will be done. However, since this method uses an analog oscillator, there are still problems with frequency stability, and in particular, this method cannot multiplex the frequency generation section of the waveform synthesizer, making polyphonic There is also the problem that musical tones cannot be obtained from a single waveform synthesizer and the hardware configuration is large.

This invention was made under the various circumstances explained above, and its purpose is to make it possible to easily set pitches by performing digital calculations, and to have the same depth over all pitches. difference,
To provide a frequency control device for an electronic musical instrument, which can obtain a vibrato effect at the same speed and can easily perform tuning.

An embodiment in which the present invention is applied to a music synthesizer will be described below with reference to the drawings. FIG. 1 shows a system configuration diagram of a music synthesizer according to the above embodiment. In the figure, a keyboard 1 is equipped with a plurality of keys, and each key outputs a key operation signal. The switch section 2 includes a switch for selecting various sound source waveforms (fundamental waves) such as a rectangular wave, a PWM wave (asymmetric square wave), and a sawtooth wave, a frequency modulation section 6 to be described later, a digital filter 7,
Various switches are provided, such as switches for controlling the envelope generator 8 and the like. The respective outputs from the keyboard 1 and the switch section 2 are both supplied to a CPU (central processing unit) 3.

The CPU 3 is a device that controls all operations of this music synthesizer, and is composed of a microprocessor, etc., but its details will be omitted.

A ROM (read only memory) 4 is a memory that stores the scale frequency code β. And the scale frequency code β corresponding to the operation key on keyboard 1
The address data to read is output from CPU3,
Supplied to ROM4. Further, the read scale frequency code β is supplied to the wave generator 5.

The wave generator 5 is a circuit that creates the sound source waveform by digital calculation based on the scale frequency code β, data α supplied from the frequency modulation section 6, and data γ.K supplied from the CPU 3. The waveform data is supplied to a digital filter 7. Frequency modulation section 6 is CPU
This circuit outputs the above-mentioned data α that has been frequency modulated based on the control signal from 3. The digital filter 7 removes a part of the harmonic components in the waveform data based on the control signal from the CPU 3 and supplies the output to the envelope generator 8.
Further, the envelope generator 8 controls the digital filter 7 based on the control signal from the CPU 3.
An envelope is applied to the output of the musical tone signal, which is then supplied to the digital/analog modulator 9. The digital/analog modulator 9 is a circuit that converts the input digital musical tone signal into an analog musical tone signal, and this analog musical tone signal is sent to an amplifier 10 connected to the output side of the digital/analog modulator 9. A musical tone is emitted through the speaker 11. Furthermore, this digital filter 7
Patent Application No. 55-53179 for "Digital Filter Device", and Patent Application No. 1983 for Envelope Generator 8
−74244 “Envelope control method for electronic musical instruments”
can be applied.

Next, referring to FIG. 2, the wave generator 5
The specific configuration will be explained. The A input terminals A ₁₅ to _{A 0} of the full adder 15 are applied with 16-bit data outputted from the shift register 17 and circulated. Further, 16-bit data α (α ₁₅ to α ₀ ) from the frequency modulation section 6 is applied to the B input terminals B ₁₅ to B ₀ . and terminal
A high level signal "H" is always applied to Cin. Therefore, the full adder 15 subtracts the input data α to the B input terminal from the input data at the A input terminal, and outputs the resulting data from the S output terminals S ₁₅ ~So, and the full adder 15 is connected to the output side of the full adder 15. 16 A input terminals _A15 to _A0 . The B input terminals B ₁₅ to _{B 0} of this full adder 16 are connected to the scale frequency code β (in the case of creating a rectangular wave or sawtooth wave) output from the gate circuit G ₁ or to the gate circuit
The data β±(β-K)γ (in the case of PWM wave creation) output from G ₂ are outputted from AND gates 18 ₁₅ to 18, respectively.
Preset via ₀ . Note that the carry output output from the terminal Cout of the flarer 15 is applied to each control input terminal of the AND gates 18 ₁₅ to _{18 0} via the inverter 19 .

The result data of full adder 16 is S output terminal S ₁₅ ~
It is output from _S0 and applied to the shift register 17 connected to the output side of the full adder 16. For example, if this music synthesizer is an 8-tone polyphonic synthesizer, the shift register 17 is composed of 8 stages of 16-bit capacity shift registers connected in cascade. The circuit shown in FIG. 2 executes time-sharing processing operations under the control of the CPU 3.

The lower 9 of the output data of the shift register 17
Bit data is exclusive or gate 20 ₈ ~ 20 ₀
is applied to Further, each of the 10 to 15 bits of the output data is applied to each control input terminal of AND gates 22-1 to 22-6 via inverters 21-1 to 21-6, respectively. Furthermore, the most significant bit of the output data is applied to the other input terminal of AND gate 22-6 via inverter 21-7. AND gates 22-1 to 22-6 are connected in series as shown, so the output of AND gate 22-6 is applied to the other input terminal of AND gate 22-5, and the output of AND gate 22-6 is applied to the other input terminal of AND gate 22-5.
The respective outputs of 2-5 to 22-2 are applied to the other input terminal of each of the subsequent AND gates 22-4 to 22-1. The output of AND gate 22-1 is then applied to exclusive OR gates 20 ₈ to 20 ₀ .

The output of exclusive OR gates 20 ₈ to 20 ₀ is ROM
(Read-only memory) 23 is applied to A input terminals A ₈ to A ₀ as address data. The ROM 23 stores 1/4 waveform sine wave data shown in FIG. This waveform data is used to interpolate points where the amplitude level of the rectangular wave generated by the wave generator 5 suddenly changes.
The 7-bit waveform data read from output terminals O ₆ -O ₀ of 3 is applied to OR gates 24 ₆ -24 ₀ .

The output of the AND gate 22-2 is also applied to the OR gates 24 ₆ to 24 ₀ via an inverter 25 and a transfer gate 26. The outputs of the OR gates 24 ₆ -24 ₀ are applied to one end of each of the exclusive OR gates 27 ₆ -27 ₀ . The output of the AND gate 22-1 is applied to the other ends of the exclusive OR gates 27 ₆ to 27 ₀ via an inverter 28 and a transfer gate 29. The outputs of the exclusive OR gates 27 ₆ to 27 ₀ are sent to the A input terminal A ₆ of the full adder 30 configuring the polarity inversion circuit.
~A applied to ₀ . Further, the output of the AND gate 22-1 is applied to the A input terminal _A7 of the full adder 30 via the inverter 28, transfer gate 29, and inverter 31. Furthermore, an AND gate 22- is connected to the input terminal Cin of the full adder 30.
1 is applied via an inverter 28 and a transfer gate 29, and the output of a polarity inversion circuit 32, which will be described later, is applied via a transfer gate 33. And the output end S ₇ of the full adder 30 ~
The data output from S ₀ is transferred to transfer gate 3.
4 ₇ to 34 ₀ to the digital filter 7.

The transfer gate 26 is controlled to open or close by applying a control signal output from the CPU 3 to the gate when a switch is operated to designate a rectangular wave or a PWM wave, respectively. Further, the control signals output from the CPU 3 are directly applied to the transfer gates 29 and 35 when the switch for specifying the sawtooth wave is operated, and the control signals are applied to the transfer gate 33 via the inverter 36 to control opening and closing. Further, transfer gates 34 ₇ to 34 ₀ connect the output of the AND gate 22-2 to the inverter 2.
5. The voltage is applied to the gates via the transfer gate 35 and the inverter 37 to control opening and closing.

A scale frequency code β and data K (constant value) are applied to the subtraction circuit 41, respectively. The resulting data β-K is then applied to a multiplication circuit 42 and a division circuit 44, respectively. The multiplication circuit 42 also receives data γ (this data γ takes a value of 0≦γ≦1,
) is applied to determine the duty ratio, and the resulting data (β-K)γ is added to the adder/subtractor circuit 4.
3 is applied. The scale frequency code β is applied to the other end of the addition/subtraction circuit 43, and the output of the polarity inversion circuit 32 is applied to the control input terminal ±. Then, the result data β±(β
-K) γ is applied to the gate circuit _G2 . In addition,
The gate circuit _G1 is controlled to open and close by a control signal output from the CPU 3 when a switch is operated to specify a rectangular wave and a sawtooth wave.
G ₂ is the CPU when operating the switch that specifies the PWM wave.
The opening/closing is controlled by the control signal output from 3.

Output data M and data K of the shift register 17 are input to the subtraction circuit 45 . The resulting data M-K is then applied to the division circuit 44. Then, the result data of the division circuit 44 (M-K)/(β
-K) is sent to the digital filter 7 as sawtooth wave data via transfer gates 46 ₇ to 46 ₀ . Transfer Gate 46 ₇ ~4
₆₀ , the output of the AND gate 22-2 is connected to the inverter 25, transfer gate 35,
The voltage is applied via the inverters 37 and 47, and the opening and closing are controlled.

The polarity inversion circuit 32 has a shift register 48 and a full adder 1 at the other input terminal of an exclusive OR gate 49 connected to the output side of the shift register 48.
The output from the output terminal C' of 5 is applied via an inverter 50. Further, the output of the exclusive OR gate 49 is fed back to the input side of the shift register 48. In the case of the above-mentioned 8-tone polyphonic synthesizer, the shift register 48 is formed by cascading 8 stages of shift registers each having a capacity of 1 bit. Further, from the output terminal C' of the full adder 15, the full adder 1
When the result data of 5 becomes "512", an "H" level signal (carry) is output.

As shown in the figure, the frequency modulation section 6 includes a low frequency oscillation circuit (LFO) 6-1, a tuning control section 6-2, and a shift register 6-3. And low frequency oscillation circuit 6-1, tuning control section 6-2
Control data D-1 or D-2 is applied to each of them. The low frequency oscillation circuit 6-1 generates a low frequency signal having a waveform of a triangular wave, a sawtooth wave, or a rectangular wave under the control of the input control data D-1, and supplies it to the shift register 6-3. Note that this low frequency oscillation circuit 6-1 will be explained in more detail with reference to FIGS. 7 and 8.

The tuning control section 6-2 performs a tuning control operation under the control of the input control data D-2, and provides the output data to the shift register 6-3. Shift register 6-3 is low frequency oscillation circuit 6
-1 and the data received from the tuning control section 6-2 are supplied to the B input terminal of the full adder 15 as the data α during the vibrato imparting operation or when performing tuning. Further, when neither vibrato application nor tuning is performed, data D-3 is applied from the CPU 3 to the shift register 6-3. The shift register 6-3 then supplies this data to the B input terminal of the full adder 15 as the data α. In the case of the above-mentioned 8-note polyphonic music synthesizer, the shift register 6-3 is formed by cascading eight stages of shift registers each having a capacity of 16 bits.

Next, the configuration of the low frequency oscillation circuit 6-1 will be specifically explained with reference to FIGS. 7 and 8. In FIG. 7, the binary counter 70 is enabled and counts the clock CLK when a control command is applied from the CPU 3 to the input terminal ENABLE (that is, during a vibrato imparting operation). And bit output terminals 1, 2, 4, 8, 16, 3
The count value data outputted from the AND gates 2 and 64 are the corresponding AND gates 71 ₀ and 71 of the AND gate group 71.
₁ , 71 ₂ , 71 ₃ , 71 ₄ , 71 ₅ , and 71 ₆ , respectively. And the above AND gate group 71
is gate-controlled by a signal obtained by inverting a rectangular wave generation command by an inverter 72. Further, each output of the AND gate group 71 is input to a corresponding AND gate of an AND gate group 74 via an inverter group 73, and is also directly input to a corresponding AND gate of an AND gate group 75.

On the other hand, the output of the bit output terminal 128 of the most significant bit of the binary counter 70 is output from the AND gate 7.
6, and also transfer gate group 7
It is input to transfer gate ₇₇₆ in 7. The AND gate 76 is gate-controlled with the rectangular wave generation command and triangular wave generation command by a signal via the OR gate 78, and its output is used as a gate control signal for the AND gate group 74. Gate 76 output,
The signal inverted by the inverter 79 is used as a gate control signal for the AND gate group 75. The respective outputs of the AND gate groups 74 and 75 are both input to a transfer gate group 81 via an OR gate group 80. Further, the transfer gate group 77 is directly gate-controlled by the sawtooth wave generation command, while the transfer gate group 81 is gate-controlled by a signal obtained by inverting the sawtooth wave generation command by an inverter 82. Ru. The output (7-bit data) of the transfer gate group 77 or 81 is
During the counting operation period of each cycle of the binary counter 70, the data provides the amplitude level of each waveform of a triangular wave, a sawtooth wave, and a rectangular wave as shown in FIG. 8b, c, and d, respectively. Generates sawtooth and square wave low frequency signals. A vibrato effect is imparted by these low frequency signals.

Next, the operation of the above embodiment will be explained with reference to FIGS. 4 to 6. First, the operation when a rectangular wave is generated by the wave generator 5 will be explained with reference to the time chart in FIG. In this case, first, turn on the switch for specifying the rectangular wave on the switch section 2, and then operate the other necessary switches. It is assumed that no vibrato or tuning is performed for now. Therefore, by turning on the square wave designation switch, the CPU 3 sets the gate circuits G ₁ and G ₂ of the wave generator 5 to the "H" (that is, "1") level or "L" level, respectively.
(that is, outputs a "0") level signal. Therefore, from then on, gate circuit G ₁ is opened and gate circuit G ₂ is closed. Further, the CPU 3 outputs a "1" level signal to the transfer gate 26, and outputs a "0" level signal to the transfer gates 29 and 35.
Outputs level signal. Therefore, thereafter, the transfer gate 26 is opened and the transfer gates 29 and 35 are closed. Further, as the transfer gates 29 and 35 are closed, the transfer gate 33 and the transfer gates 34 ₇ to 34 ₀ are opened, and the transfer gates 46 ₇ to 46 ₀ are closed.

The case where, for example, one key on the keyboard 1 is turned on in the above state will be described below. In this case, when the above one key is turned on, CPU3
Predetermined address data for reading out the scale frequency code β corresponding to the operation key from the ROM 4 is output to the ROM 4. As a result, the scale frequency code β is read from the ROM 4 and supplied to the wave generator 5. Then, this scale frequency code β is applied to the AND gates 18 ₁₅ to 18 ₀ via the gate circuit G ₁ which is being opened. Now, the output of the output terminal Cout of the full adder 15 is “0”
Therefore, the output of the inverter 19 is “1”
Accordingly, the AND gates 18 ₁₅ to _{18 0} are currently being opened. Therefore, the above scale frequency code β is converted to full adder 16 through AND gates 18 ₁₅ to 18 ₀ .
is applied to the B input terminals B ₁₅ to B ₀ of . On the other hand, at this time, 16-bit all "0" data is applied from the S output terminals S ₁₅ to _{S 0} of the full adder 15 to the A input terminals A ₁₅ to _{A 0} of the full adder 16. Therefore, the result data of the full adder 16 at that time will be data with the same value as the set scale frequency code β, and S
When output from the output terminals S ₁₅ to _{S 0} , the signals are input to the shift register 17 . After being shifted, this data is outputted from the shift register 17 and is input cyclically to the A input terminals A ₁₅ to A ₀ of the full adder 15, as well as to exclusive OR gates 20 ₈ to 20 ₀ and inverters 21 ₇ to 21 _1. .

In the case of this embodiment, all values of the scale frequency code β of each scale are output as values larger than "1024". That is, any one of the upper 11 to 16 bits of the 16-bit data always contains "1" data. Therefore, when the scale frequency code β is set when one key is turned on, and the shift register 17 outputs data of the same value, the output of the AND gate 22-2 is always "" as shown in FIG. 4e. 0” level. Therefore, the output of the AND gate 22-1 is also at the "0" level while the output of the AND gate 22-2 is "0" as shown in FIG. 4B. Furthermore, at this time, the output of the inverter 50 is
The output of the polarity inversion circuit 32 is at the "1" level as shown in FIG. As a result, and gate 2
The "0" level signal of 2-1 is supplied to the exclusive OR gates ₂₀₈ to ₂₀₀ , and the data of the lower 9 bits of the output of the shift register 17 is directly transferred to the ROM 2.
It is applied to the A input terminals A ₈ to A ₀ of No. 3. Further, a "1" level signal obtained by inverting the "0" level signal of the AND gate 22-2 by the inverter 25 is applied to the OR gates 24 ₆ to 24 ₀ , and therefore, the OR gates 24 ₆ to 24 ₀ each output a "1" level signal. A level signal is output and applied to one end of each of exclusive OR gates 27 ₆ -27 ₀ . Therefore, exclusive or gate 27 ₆
“0” of the polarity inverting circuit 32 is at the other end of each of ~27 ₀ .
level output is applied. Therefore, all outputs of the exclusive OR gates 27 ₆ to 27 ₀ become "1" level signals. Also, the inverter 31
The output of is also at the "1" level. As a result, all "1" data is input to the A input terminals _A7 to _A0 of the full adder 30. Further, the output (“0”) of the polarity inversion circuit 32 is connected to the carry input terminal Cin of the full adder 30.
signal) is input. Therefore full adder 3
The resulting data of 0 is output as 8-bit all "1" data from the S output terminals _S7 to _S0 ,
The signal is sent to the digital filter 7 via the transfer gates 34 ₇ to 34 ₀ which are being opened. Figure 4a
The waveform diagram shows a rectangular wave sent to this digital filter 7. Therefore, the digital filter 7 removes the specified overtone component under the control of the CPU 3, and the envelope generator 7 applies an envelope to its output, and starts generating and emitting musical tones of the scale of the operation keys. .

When data with the same value as the set scale frequency code β is inputted cyclically to the A input terminals A ₁₅ to _{A 0} of the full adder 15, the data D-3 input by the CPU 3 is input to the B input terminals B ₁₅ to B ₀ . The data is input via the shift register 6-3 of the frequency modulation section 6 as constant value data α (16-bit data). In addition, since the carry input terminal Cin is always set to the "H" level, the full adder 15 executes the first subtraction operation of β - α at this time, outputs the resulting data from the S output terminal, and the full adder 16 Apply to the A input terminal. Note that "-α" in the above formula "β-α" corresponds to the value obtained by subtracting "-1" from the values of α ₀ , α ₁ , . . . α ₁₅ in FIG. When this subtraction operation is executed, the output of the carry output terminal Cout of the full adder 15 becomes "1" level, so the output of the inverter 19 becomes "0", and the AND gates 18 ₁₅ to 18 ₀ are closed. Therefore, input of the scale frequency code β to the B input terminal of the full adder 16 is blocked. Therefore, the result data of the full adder 16 at this time is the same as the result data of the first time of the full adder 15, and is applied to the shift register 17. And this one
When the result data of the second time is output from the shift register 17, it is input cyclically to the A input terminal of the full adder 15, and is also input to exclusive OR gates ₂₀₈ to ₂₀₀ and inverters 21-7 to 21-1. After this first calculation, the data input states of the A input terminal and the carry input terminal Cin of the full adder 30 are unchanged from the previous time, so the digital filter 7
8-bit all "1" data is sent to.

Full Adder 15, And Gate 18 ₁₅ ~ 18 ₀ ,
In the full adder 16 and shift register 17,
The cumulative subtraction operation, which is exactly the same as the first subtraction operation described above, results in data, that is, shift register 1.
This process is repeated until the output of 7 becomes "1024" (see Figure 4 f). And during this time, Full Adder 30 A
The input state to the input terminal, the carry input terminal Cin, does not change either, so during this period, 8-bit all "1" data is continuously sent to the digital filter 7. Then, when the output of the shift register 17 becomes smaller than "1024" by the next subtraction operation, the data in the upper 11th to 16th bits of the output of the shift register 17 are all "0", and so The output of the AND gate 22-2 is shown in Fig. 4e.
As shown in the figure, it is inverted to the "1" level. Therefore, from now on, the output of the inverter 25 becomes "0" level and is input to the OR gates 24 ₆ to 24 ₀ .

On the other hand, during the cumulative subtraction operation in which the output of the shift register 17 is from "1024" to "512", the 10th bit data of the output of the shift register 17 holds "1", so during this period, Figure 4b
As shown in , the output of the AND gate 22-1 continues to be “0” and the exclusive OR gates ₂₀
0 ₀ is supplied. For this reason, the above "1024" ~
During "512", the lower 9 bit data of the output of the shift register 17 continues to be applied to the A input terminal of the ROM 23 as it is. During the above period, the output of the polarity inversion circuit 32 continues to be at the "0" level as shown in FIG. 4d.

Therefore, assuming that the output of the shift register 17 becomes "1024" or less, for example "1023", then the lower 9 bits of the output of the shift register 17 are all "1", It is applied to the A input terminal of the ROM23. Therefore, the ROM 23 is addressed by this 9-bit all "1" address data, and 7-bit all "1" data is read out as shown in FIG. This 7-bit all "1" data is passed through exclusive OR gates ₂₇₆ to ₂₄₀ through OR gates ₂₄₆ to 240.
27 Enter ₀ . As mentioned above, exclusive or gates 27 ₆ to 27 ₀ and full adder 30
A "0" level signal is still being input to the carry input terminal Cin of the full adder 30, so 8-bit all "1" data is input to the A input terminal of the full adder 30, and as a result, the data is also 8-bit all "1". It is output as data and sent to the digital filter 7.

Next, when the output of the shift register 17 becomes a value smaller than "1023" by data α due to the next cumulative subtraction operation, the ROM 23 is stored at an address smaller by α than the above-mentioned 9-bit all "1" data (i.e., "511"). Addressed by data. Therefore, as can be seen from Figure 3, the ROM
From 23, data smaller by a predetermined value than the above-mentioned 7-bit all "1" data, that is, data with an amplitude value slightly smaller than the previous one, is read out, and the data with that amplitude value is output as is without reversing the polarity by the full adder 30. The signal is sent to the digital filter 7.

Thereafter, in the same way, the output of the shift register 17 decreases by α by each cumulative subtraction operation,
Until the value reaches "512", the address data in the ROM 23 is sequentially addressed in the direction of decreasing by α, and accordingly, each time, amplitude value data with a smaller value than the previous one is read out. Ru. During this time, the input state of data to the A input terminal and the carry input terminal Cin of the full adder 30 is the same as described above, and accordingly, the above-mentioned sequentially decreasing amplitude value data is sent to the digital filter 7. . When the output of the shift register 17 is "515", the ROM 23 is addressed by address data of 9 bits all "0".

Next, the result data of cumulative subtraction operation is full adder 1
5, when the value changes from "512" to "511" or less, "1" is output from the output terminal C' of the full adder 15.
A signal is output, and in response, one pulse signal is output from the inverter 50 as shown in FIG. 4C. As a result, as shown in FIG. 4d, the output of the polarity inversion circuit 32 is subsequently inverted to the "1" level, and the exclusive OR gates 27 ₆ to 27 ₀ , the inverter 31,
The signals are applied to the carry input terminals Cin of the full adder 30, respectively.

Therefore, when data below "511" is output from the shift register 17 as shown in Figure 4f, the upper 10 to 16 bits of the output are all "0".
Therefore, the output of the AND gate 22-1 changes to the "1" level as shown in FIG. 4B, and is applied to the exclusive OR gates 20 ₆ to 20 ₀ . On the other hand, 9-bit all "1" data is again applied to the other terminals of the exclusive OR gates ₂₀₈ to ₂₀₀ , and the output thereof is applied to the A input terminal of the ROM 23, which has been inverted to 9-bit all "0". . Therefore, the result data of cumulative subtraction is "511" to "0".
While the address data sequentially decreases by α, the ROM 23 is sequentially addressed in the direction in which the address data increases from all "0" to all "1". The amplitude value data read out as a result becomes _larger sequentially as _{shown in FIG} . Also, since a "0" signal is input to the A input terminal _A7 and a "1" signal is input to the carry input terminal Cin, the data output from the full adder 30 during this period is the amplitude value data read from the ROM 23. The data is sent to the digital filter 7.

As shown in FIG. 4 f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave in FIG. interpolated accordingly.

When the cumulative subtraction result becomes "0" as described above, a "0" signal is output from the carry output terminal Cout of the full adder 15 for the next subtraction operation, and as a result,
AND gates 18 ₁₅ to 18 ₀ are temporarily opened and the scale frequency code β is input to the B input terminal B ₁₅ of the full adder 16.
~ applied to B ₀ . And full adder 16 A
When the data given to the input terminal and this scale frequency code β are added, and the resulting data is output from the shift register 17, the above data, that is, the scale frequency code β is “1024” as described above.
Since the value is larger, for the reason mentioned above, from this point on, the outputs of the AND gates 22-1 and 22-2 are inverted to the "0" level as shown in FIGS. 4b and 4e.

After the scale frequency code β is set again as described above,
The cumulative subtraction operation by α is executed, and the output of the shift register 17 decreases from β by α, and becomes “1024”.
decreases to During this period, 8-bit all "0" data is input to the A input terminals _A7 to _A0 of the full adder 30, and the carry input terminal
Since a "1" signal is input to Cin, 8-bit all "0" data is sent to the digital filter 7 during this period.

While the cumulative subtraction result becomes "1024" or less and further decreases to "515", the AND gate 22-2 is first applied from the point where it becomes less than "1024", that is, "1023" or less as shown in FIG. The output of is inverted to "1" level. Therefore, between "1023" and "512", the output of the full adder 30 moves the ROM 23 from its maximum address (7 bits all "1" data) to its minimum address (9 bits all "0" data).
It is equal to the inverted polarity of the amplitude value data that is sequentially addressed and read out.

Furthermore, when the cumulative subtraction result becomes "512", "1" is output from the output terminal C' of the full adder 15 as described above.
A signal is output, and in response to this, the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 4d. Next, when the cumulative subtraction result becomes "511" or less, the output of the AND gate 22-1 is inverted to the "1" level. As a result, as mentioned above, when the cumulative subtraction result is between "511" and "0", the output of the full adder 30 is read out by sequentially addressing the ROM 23 from the minimum address to the maximum address. The data matches the amplitude value data and is sent to the digital filter 7.

As shown in FIG. 4f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave shown in FIG. 4a is interpolated by the waveform data from the ROM 23. When the cumulative subtraction result becomes "0" or less, a "0" signal is output from the carry output terminal Cout of the full adder 15 during the next subtraction, and the scale frequency code β is set in the full adder 16 again. Rectangular wave calculation processing is started.

With the above steps, the arithmetic processing operation for generating one period of rectangular waves is completed. For example, the calculation period in which the output of the shift register 17 changes from "0" to "0" (that is, the period during which each of the previous and current scale frequency codes β is set) shown in FIG.
When T' and the sampling period are _Ts , the calculation period T' is expressed by the following equation (1).

T'=Ts・β/α...(1) Also, the frequency _p of the rectangular wave generated as described above
is expressed by the following equation (2) when the sampling frequency is _s .

_p = 1/2T' = s/2・α/β ...(2) Next, we will explain the operation when adding vibrato to the musical tone being emitted using the rectangular wave generated by the above operation. do. In this case, the frequency modulation section 6
The data output from the low frequency oscillation circuit 6-1 in the full data 15 is the low bit information of the data α.
is applied to the B input terminal of. The data α in this case changes at a low frequency according to the operation of the low frequency oscillation circuit 6-1, which will be described below. That is, the seventh
In the figure, the binary counter 70 has an input terminal
A control command from CPU3 is input to ENABLE to perform clock CLK counting operation. The contents of the count value data range from 0 to 0 during one cycle.
Varies up to 256.

Now, if a triangular wave generation command is being outputted ("1") by operating a predetermined switch of the switch section 2, the output of the OR gate 78 becomes "1" and the AND gate 76 is opened. Further, when the other sawtooth wave generation command and square wave generation command are both "0", the inverter 72 output "1" opens the AND gate group 71, and the transfer gate group 71 opens, Furthermore, the transfer gate group 77 is closed, and the transfer gate group 81 is open.

Therefore, during the period when the bit output terminal 128 of the binary counter 70 is "0", that is, the first half of one cycle (count value data between 0 and 128), the output of the AND gate 76 is "0", and Eventually, AND gate group 74 is closed, and AND gate group 75 is opened. Therefore, in the first half of one cycle, the count data (7-bit data) from the bit input terminals 64 to 1 of the binary counter 70 is transmitted through the AND gate groups 71 and 75, the OR gate group 80, and the transfer gate group 81. Output via The output data is the same as the count value data of the binary counter 70, and increases by one.

Next, when the bit output terminal 128 becomes "1", that is, enters the latter half of one cycle (between count data 128 and 256), the output of the AND gate 76 becomes "1" during this period, and the AND gate Group 74 is opened and AND gate group 75 is closed. Therefore, in the latter half of the one cycle, the bit output terminal 64 of the binary counter 70
The output data of ~1 is applied to the inverter group 73 via the AND gate group 71 and all bits are inverted, and the data is further output via the AND gate group 74, the OR gate group 80, and the switch gate group 81.
As a result, the output data decreases by one.

In this way, a triangular wave signal as shown in FIG. 8b is obtained and is used to impart a vibrato effect.

While only the sawtooth wave generation command is being output, the transfer gate group 77 is opened and the transfer gate group 81 is closed. Moreover, the AND gate group 71 is opened, and the AND gate 7
6 is closed, the AND gate group 74 is closed and the AND gate group 75 is opened.

In the first half of one cycle (0 to 128), the count value data of the bit output terminals 128 to 1 of the binary counter 70 is outputted via the AND gate group 71 and the transfer gate group 77. For this reason,
The output data increases by 1 from 0 to 128 with a slope of 1/2 of the triangular wave.

Then, in the latter half of one cycle (128 to 256), the output of the bit output terminal 128 of the binary counter 70 is "1" as the MSB of the output data.
is supplied, the above output data is 128~
Up to 256, it increases by 1 at the same slope as from 0 to 128.

In this way, a sawtooth wave low frequency signal as shown in FIG. 8c is obtained.

When only the square wave generation command is being output, the inverter 72 output “0” causes the AND gate group 7
1 is closed. Also, the AND gate 76 is opened. Therefore, in the first half of one cycle (0 to 128), the bit output terminal 128 is "0",
The AND gate 76 output also becomes "0". As a result, the AND gate group 74 is closed and the AND gate group 75 is opened. However, since the AND gate group 71 is now closed, the AND gate group 75 is closed.
The outputs of the AND gate group 74 are both "0", and the outputs of the AND gate group 74 are also "0". Therefore, in the first half of one cycle, the output data is all "0" data.

On the other hand, in the second half of one cycle (128-256),
The output "1" of the bit output terminal 128 causes the output of the AND gate 76 to become "1", and accordingly, the AND gate group 74 is opened and the AND gate group 75 is closed. Therefore, the output of the AND gate group 71, which is all "0" data, is inverted by the inverter group 73 to become all "1" data, which is output from the AND gate group 74, and furthermore, the OR gate group 80, It is outputted via the switching gate group 81. Therefore, in the latter half of the one cycle, the output data is held at 127 (all "1"). As a result, a rectangular low frequency signal as shown in FIG. 8a is obtained.

If the value of α changes at low frequencies due to the operation of the low frequency oscillation circuit 6-1 as described above, as is obvious from the above equation (2), the frequency _p of the rectangular wave
Since the value also changes according to the change in the data α, a vibrato effect is imparted to the generated musical tone.

Next, an explanation will be given of the operation when performing tuning on the above-mentioned rectangular wave tones. In this case, the data output by the tuning control unit 6-2 in the frequency modulation unit 6 is applied to the B input terminal of the full adder 15 as low bit information of the data α. This data .alpha. is set to a value obtained by adding or subtracting a constant value C from the original value of the data .alpha. by the operation of the tuning control section 6-2. This can be expressed numerically as follows.

That is, if the frequency when no tuning is performed is _p , and the frequency when n cents tuning is performed is _p ', then the frequencies _p and _p ' are expressed by the following equations (3) and (4).
)
are respectively represented by .

_p = a (Hz) ...(3) However, a is a positive number. From the above equations (3), (4) or equation (2), it is the same as the following equations (5) and (6).

_p = fs・α/β ……(5) _p ′=s(α±C)/β ……(6) Therefore, from equations (3) to (6), the value of n is n1200/log2×logα± C/α...(7) That is, by operating predetermined switches in each section, the frequency _p of the generated musical tone changes by n cents according to equation (7), and tuning can be easily performed.

Next, the operation in the case of generating a PWM wave will be explained with reference to FIG. First, PWM on switch section 2
Turn on the wave designation switch. As a result, gate circuit _G1 is closed and gate circuit _G2 is opened.
Also, transfer gates 26, 33, 34 ₇ ~
34 ₀ is opened and transfer gate 29,
35, 46 ₇ to 46 ₀ are closed. In the above state, when one key on the keyboard 1 is turned on, the calculation and generation process of the PWM wave is started.

Now, the explanation will start from the timing when the shift register 17 output shown in FIG. As shown, it is at the "1" level, so an addition command is given to the addition/subtraction circuit 43, and the exclusive OR gates 27 ₆ -
A “1” signal is applied to the carry input terminal Cin of 27 ₀ , the inverter 31, and the full adder 30, respectively.

On the other hand, the subtraction circuit 41 outputs the result data β-K and gives it to the multiplication circuit 42, and the multiplication circuit 42 outputs the result data (β-K)γ to the addition and subtraction circuit 43.
is giving to Furthermore, the addition/subtraction circuit 43 outputs result data β+(β-K)γ, which is applied to the gate circuit _G2 . For example, the data K is "1024", and the data γ that determines the duty ratio is
It takes a value of 0≦γ≦1.

Therefore, when the above-mentioned one key is turned on, data β+(β-K)γ is set in the full adder 16 at the start of arithmetic processing in accordance with an operation similar to that described for the rectangular wave generation operation. Then, a cumulative subtraction operation is performed to subtract data α (a constant value) from this setting data β+(β−K)γ. Until the resulting data, that is, the output of the shift register 17, decreases by α to "1024", the AND gate 2
2-1, the inverter 50, the polarity inversion circuit 32, and the AND gate 22-2 outputs "0" and "0", respectively.
Each level of "1", "1", and "0" is held.
Therefore, during this period, the read waveform from the ROM 23 is invalidated, and the data output from the full adder 30 and sent to the digital filter 6 becomes 8-bit all "0" data.

Cumulative subtraction result data, ie, shift register 1
When the 7 output is less than "1024", AND gate 2
The output of 2-2 is inverted to "1" level. Therefore, while the above result data changes from "1024" to "512", the full adder 30 outputs data with the polarity of the amplitude value data read by sequentially addressing the ROM 23 from the maximum address to the minimum address. The signal is then sent to the digital filter 7.

When the resultant data becomes "512", the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 5d, and a subtraction command is given to the addition/subtraction circuit 43.
Further, a “0” signal is applied to the carry input terminals Cin of the exclusive OR gates 27 ₆ to 27 ₀ , the inverter 31 and the full adder 30 . Further, when the resultant data becomes less than "511", the output of the AND gate 22-1 is inverted to the "1" level, as shown in FIG. 5B. Therefore, until the result data changes from "511" to "0", the output of the full adder 30 is the amplitude value data read out by addressing the ROM 23 from the minimum address to the maximum address. The signal is output and sent to the digital filter 7.

Then, as shown in FIG. 5, when the resultant data becomes "0" or less, data .beta.-(.beta.-K).gamma. is set in the full adder 16 during the next subtraction operation. Note that, as shown in FIGS. 5b and 5e, when the result data is "0", the AND gate 22-
1 and 22-2 are inverted to the "0" level. The above data β(β-K)γ is full adder 16
When set to , the subtraction operation by α is started again. As a result, the output of the full adder 30 is held as 8-bit all "1" data until the data is reduced to "1024".

When the resultant data becomes smaller than "1024" as shown in FIG. 5, the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 5e. Therefore, while the result data decreases to "512", the output of the full adder 30 becomes the same data as the amplitude value data read out by addressing the ROM 23 from the maximum address to the minimum address, and sends it to the digital filter 7. .

Next, while the result data becomes smaller than "512" and further decreases to "0", the AND gate 22-
1. Each output of the polarity inversion circuit 32 is both inverted and held at the "1" level. Therefore, the output of the full adder 30 during this period is data in which the polarity of the amplitude value data read out by addressing the ROM 23 from the minimum address to the maximum address is reversed.
The signal is sent to the digital filter 7.

This completes the arithmetic processing operation for one cycle of the PWM wave, and the following is a repetition of what has been described above. And the frequency _p is the same as in the case of a square wave, and formula (2)
It is represented by Further, the operations regarding vibrato and tuning are the same as those described above.

Next, the case of a sawtooth wave will be explained with reference to FIG. First, the sawtooth wave designation switch on the switch section 2 is turned on. As a result, gate circuit G ₁
is opened, and gate circuit _C2 is closed. Further, transfer gates 29 and 35 are opened, and transfer gates 26 and 33 are closed. In the above state, when one key on the keyboard 1 is turned on, arithmetic processing for generating a sawtooth wave starts.

An explanation will now be given starting from the timing when the output of the shift register 17 is "0"("0" at the left end in the figure) shown in FIG. 6d. At this point, the scale frequency code β
is set in the full adder 16. Therefore, when this scale frequency code β is then output from the shift register 17, since the code β is data larger than "1024", the AND gates 22-1 and 22 are output as shown in FIGS. 6b and 6c, respectively. -2 outputs are both inverted to "0" level. Since the output of the AND gate 22-2 becomes "0", the output of the inverter 37 becomes "0" and the output of the inverter 47 becomes "1", and accordingly, the transfer gates 34 ₇ to 34 ₀ are closed. Then, the transfer gates 46 ₇ to 46 ₀ are opened. Further, in the full adders 15 and 16, the shift register 17, and the AND gates 18 ₁₅ to 18 ₀ , an cumulative subtraction operation for subtracting data α (constant value) from the scale frequency code β starts. Since the output state of the AND gate 22-2 does not change until the data as a result of the cumulative subtraction operation decreases to the value "1024", the output of the divider circuit 44 is sent to the digital filter 7 from the open transformer. It is sent out via argates 46 ₇ to 46 ₀ . The output data M-K of the subtraction circuit 45 is input to the input terminal A of the division circuit 44, and the output data β- of the subtraction circuit 41 is input to the input terminal B.
K is applied to each. Therefore, the output data H' of the division circuit is expressed by the following equation (8).

H'=M-K/β-K×H...(8) where M is the output of the shift register 17, K is a constant value, "1024" in this example, and H is the maximum amplitude value. , is "256" in this example.
Therefore, equation (8) can be rewritten as the following equation (9).

H'=M-1024/β-1024×256...(9) As can be seen from equation (9), shift register 17
When the output M of , that is, the resultant data of cumulative subtraction becomes "1024", the data sent to the digital filter 7 becomes "0". When the resultant data becomes "1024" or less as shown in FIG. 6(d), the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 6(c). Therefore, transfer gates 34 ₇ to 34 ₀ are opened, and transfer gates 46 ₇ to 46 ₀ are closed. Until the above result data decreases to "512", the output of the AND gate 22-1 is held at the "0" level, so the output "1" of the inverter 28 is exclusively transmitted through the open transfer gate 29. It is applied to the carry input terminals Cin of the OR gates 27 ₆ to 27 ₀ , the inverter 31 and the full adder 30, respectively. That is, when the result data is between "1023" and "512", the polarity of the amplitude value inverter that is read out by sequentially addressing the ROM 23 from the highest address to the lowest address is the data that is inverted in the full adder 3.
Output from 0, transfer gate 34 ₇ ~ 3
₄₀ to the digital filter 7.

When the resultant data becomes smaller than "512", the output of the AND gate 22-1 is also inverted to the "1" level, as shown in FIG. 6b. Therefore, “1”
After the signal is applied to the exclusive OR gates 20 ₈ to 20 ₀ , the ROM 23 is addressed from the lowest address to the highest address, while the output “0” of the inverter 28 is applied to the exclusive OR gates 27 _{4 to 27 4} .
27 ₀ is applied to the carry input terminal Cin of the inverter 31 and the full adder 30, respectively. Therefore, between "511" and "0", the amplitude value data read from the ROM 23 is sent to the digital filter 7 as is. And then again full adder 16
A scale frequency code β is set to .

This completes one cycle of sawtooth wave generation. The frequency _p is expressed by the following equation (10).

_p = _s・α/β ...(10) That is, as can be understood from equation (10), in the case of a sawtooth wave, unlike the case of a rectangular wave or PWM wave,
It is necessary to double the scale frequency code β.

Note that the operations regarding vibrato and tuning are similar to those described above.

The operations for generating square waves, PWM waves, and sawtooth waves explained above are based on the case where only one key on the keyboard 1 is turned on, but in this example, the music synthesizer is used for eight-note polyphonic. Therefore, even if up to eight keys are turned on at the same time, each circuit in FIGS. 1 and 2 can simultaneously generate the fundamental wave for each key by time-sharing processing operation of 8 channels. can be done, but detailed explanation thereof will be omitted.

In addition, in the above example, the fundamental wave is a rectangular wave, PWM
Although the three types of fundamental waves are waves and sawtooth waves, other fundamental waves such as triangular waves and slope waves can be used. Furthermore, although the interpolation at the point where the amplitude level of the fundamental wave suddenly changes is performed using a sine wave, other function curves such as a quadratic function, a cubic function, an exponential function, a trigonometric function, etc. may be used. Further, in the above embodiment, a 1/4 period sine wave is stored in the ROM 23, but it may be a 1 period or 1/2 period sine wave. Further, in the above embodiment, after setting the initial value β to the full adder, a cumulative subtraction operation was performed in which a constant value α was sequentially subtracted, but after setting the initial value β, a cumulative addition operation was performed in which a constant value α was sequentially added,
Arithmetic processing for obtaining a fundamental wave similar to the above embodiment may be performed. Furthermore, it goes without saying that the present invention can be used not only for music synthesizers but also for other electronic musical instruments, and can be modified and applied in various ways without departing from the spirit of the present invention.

As explained above, in this invention, after setting the first frequency information, the second frequency information is set from the first frequency information.
The frequency information of the musical tones can be easily determined by repeatedly subtracting the frequency information, and when the resulting data satisfies a predetermined condition, the first frequency information is set again and the subtraction is executed. and,
For example, by periodically changing the second frequency information, it is possible to easily obtain a vibrato effect of the same depth and speed over all pitches;
Since we have provided a frequency control device for electronic musical instruments that can easily perform tuning by changing the frequency information of It also has the advantage of simplifying the hardware configuration and contributing to the miniaturization of electronic musical instruments.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a music synthesizer according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the wave generator 5, and FIG. 3 is a ROM
23 is a memory waveform diagram, Figure 4 is a time chart explaining the rectangular wave generation operation, Figure 5 is a time chart explaining the PWM wave generation operation, and Figure 6 is a sawtooth wave time chart explaining the generation operation. Chaat, 7th
The figure is a detailed circuit diagram of the low frequency oscillation circuit 6-1, and FIG. 8 is a diagram of various waveforms output from the low frequency oscillation circuit 6-1. 1...Keyboard, 2...Switch part, 3...
CPU, 4...ROM, 5...Wave generator, 6...Frequency modulation section, 6-1...Low frequency oscillation circuit, 6-2...Tuning control section, 7...Digital filter, 8...Envelope Generator, 9...Digital/analog converter, 1
5, 16...Full adder, 17...Shift register, 18 ₁₅ to 18 ₀ ...And gate, 20 ₈ to 2
0 ₀ , 27 ₆ ~ 27 ₀ ... Exclusive or gate, 21
-7~21-1...Inverter, 22-6~22
-1...and gate, 23...ROM, 24 ₆ ~
24 ₀ ...Or Gate, 26, 29, 33, 35,
34 ₇ to 34 ₀ , 46 ₇ to 46 ₀ ... Transfer gate, 31 ... Inverter, 32 ... Polarity inversion circuit, 41, 45 ... Subtraction circuit, 42 ... Multiplication circuit, 43 ... Addition and subtraction circuit, 44 ...Division circuit,
_G1 , _G2 ...Gate circuit, 70...Binary counter.

Claims (1)

[Claims] 1. Frequency information output means for outputting first frequency information representing a scale frequency and second frequency information for modulating the scale frequency; Using the frequency information as an initial value, from this initial value the above second
subtracting means for repeatedly subtracting frequency information from the subtracting means; and when the output value of the subtracting means reaches a predetermined value, the first frequency information is supplied from the frequency information outputting means to the subtracting means again to repeatedly subtract. What is claimed is: 1. A frequency control device for an electronic musical instrument, comprising: control means for controlling the frequency so that the subtracting means outputs a predetermined value; 2. Claim 1, wherein the frequency information output means includes means for periodically changing the second frequency information and applying it to the subtraction means, and applies frequency modulation to the output musical tone. A frequency control device for an electronic musical instrument as described in 2. 3. The frequency information output means has means for setting the second frequency information to a value corresponding to tuning and providing it to the subtraction means, and tunes the output musical tone. The frequency control device for an electronic musical instrument according to item 1.