JPS58108586A - Frequency controller for electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a frequency control device IF for an electronic musical instrument.

One type of electronic musical instrument is a music synthesizer.
This woodcutter's electronic musical instrument is mostly based on analog circuits, and 5J! Very little has emerged.

However, in the past, there has been no research into methods for digitally adding musical sound waveforms to electronic organs, etc.11.
, it is thought that some of them have been put into practical use. Methods for obtaining such musical sound waveforms can be roughly divided into three types: first-order.

That is, the first method specifies the ROM@address by the output of an address 0 address counter that performs a constant I[se cumulative addition. In this method, when using frequency control to add a vibrato effect etc. to the generated musical tone, it is necessary to use a constant value that is cumulatively added. This is done by changing. However, in the frequency control in this first readout method, one frequency information, that is, the addition data is modified into the scale frequency and changes exponentially, so it is attempted to give a vibrato effect of the same depth across the diatonic scale. The data given for this purpose varies depending on the scale.

The disadvantage is that frequency control becomes extremely complicated.

In addition, the second ROM successive readout method is such that one cycle of ROM readout is an integer multiple of the basic output cycle of a tsk,
Frequency control is performed by reading out one station period of the waveform and controlling the number of ripple marks.However, as shown above, the frequency of the generated musical tone is basically an integral multiple of the output period of the ripple mark. Therefore, it is difficult to control the frequency mY of a semitone or less evenly over all scales in order to impart a vibrato effect, and therefore there is a drawback that frequency control becomes complicated.

The third ROM successive readout method $-j, R (JM @ is read by a variable clock, and the frequency control of t'' is performed by varying the frequency of the read clock in an analog manner, so the oscillator [H analog oscillator is used. However, since this type of system uses an analog oscillator, there remains a problem with frequency stability, and
In particular, this method cannot multiplex the frequency generation section of the waveform synthesizer, so polyphonic musical tones cannot be obtained from a single waveform synthesizer. There are also points.

This invention has been made under the various circumstances described above, and its purpose is to set an initial value (scale frequency code) corresponding to a scale frequency through arithmetic processing using a digital circuit, and then to set the initial value (scale frequency code). from (t['
Add or subtract from the bite.

As a result, when the data satisfies the predetermined conditions, the above initial value is set again and the same calculation is performed to determine the scale frequency, and the above predetermined value is periodically transformed to simplify everything. It is an object of the present invention to provide a frequency control device for an electronic musical instrument capable of frequency control in which the vibrato effect Y% has the same depth and the same speed over the musical scale, and the frequency can be controlled by changing the above-mentioned predetermined value.

One drawing below? An embodiment applied to the Vt age synthesizer of the present invention will be described with reference to the following. FIG. 1 is a system configuration diagram V of the music synthesizer according to the above embodiment.
Undercover. In the figure, a dP-board 1 is equipped with a plurality of keys, and each key outputs a key operation signal. The switch unit 2 includes a switch for selecting various sound source waveforms (fundamental waves) such as a rectangular wave, a PWM wave (asymmetric square wave), and a sawtooth wave.
Frequency modulation section 6, which will be described later. Digital filter 7゜envelope generator 8 etc. are controlled by switches, etc.
Various switches are provided. The respective outputs from the keyboard 1 and the switch section 2 are both supplied to a CPU'U (Central Processing Unit #) 3.

CPUB1 is a device that performs all operations of the 1s--thick synthesizer, and includes a microprocessor, etc., but the details thereof will be omitted.

A ROM (leat 1 only memory) 4 is a memory that stores the scale frequency code β. Then, the scale frequency code p corresponding to the operation key on the keyboard °1 is read out, and address data is output from Cf'U3.

Supplied to ROM4. The scale frequency code # produced by MarSa is supplied to the unique generator 5.

Uniibu generator 5 Kajijo Ki scale frequency code p,
l! @Supplied from the wave number modulation section 6 1. data1゜CPU
This circuit digitally creates the sound source waveform based on data r and K supplied from B, and the created waveform data is supplied to a digital filter 7. The frequency modulation section 6 is a circuit that outputs the above data having the same wave number fv4 based on a control signal from the CPU 3. The digital filter 7 removes some of the overtone components in the waveform data based on the control signal from the CPU 5, and supplies its output to the envelope generator 8.
An envelope is applied to the output of the digital filter based on the reference number to form a musical tone signal, which is then supplied to the digital/analog converter 9.

The digital/analog converter 9 converts the input digital musical tone No. 1 Y into an analog musical tone signal No. 1 ``f'' is also a circuit, and this analog musical tone signal is sent to the digital 7-to-1 analog converter 9. Connected to the output side - fi3179
Japanese Patent Application No. 1511-74244 entitled "Envelope Control System for Electronic Musical Instruments" can be applied to the envelope generator 8.

Next, referring to FIG. 2, the specific configuration of the ABGE generator 5 will be explained. A input terminal Ats~A of full adder 16
- 16-bit data that is circulated by the shift register 17 is applied. In addition, 16-bit data g (assN
a.) is applied.

A high level signal °H1 is always applied to the terminal Cin K. Therefore, the full adder 15 subtracts the input data α to the B input terminal from the input data to the A input terminal,
As a result, the data 7Si is outputted from the output terminal Slm-8, connected to the output side of the full adder 15) and applied to the A input terminal At5xA@ of the full adder 16. This full adder i6
The B input terminal Bs1NB is the data output from the gate 1 circuit G1, and the data output from the r circuit G1. β thick (#-K) and γ (in the case of PWM wave creation) are respectively ant degree game) 18 easily to taO through the set of 11 sets ζt'L. In addition, each node control input terminal KH of Antogame) 18ts to 1go is connected to the terminal Cou of the flarer 15.
An output of 1m from t is applied via the inverter 19Y.

The result data of the full adder 16 is output from the S output terminal 8 si to S.
The output from full adder 16 is ll1lvcW! Subsequently, this signal is applied to the shift register 17. With a whale
If this music synthesizer is, for example, an 8-tone polyphonic synthesizer, the shift register 17 is a 16-bit capacity shift register 't/8 stages connected in cascade. And the circuit rLCP in Fig. 2
Time-sharing crop rotation is carried out under the control of the US.

Of the output data of the shift register 17, the lower 9 bits of data are subjected to exclusive ORD (20 to 0avc). Furthermore, 10 to 15 bits of the output data are applied to each control input terminal of the Ant 0 gates 2g-1 to 22-6 via respective data frame inverters 21-1 to 21-6, respectively.

Further, the most significant bit of the above output data is applied to the other input terminal of the tend gate 22-6 via the data rush ino <-J21-7. 22-1~22-
6 are connected in series as shown, so that the numbers 1! ! -6 output is applied to the other input terminal of the tend gate 22-5, and hereinafter the same applies to the tend gate 22-5.
~22-3! Each output of each ant 1 game in the subsequent stage) 22-
An application source is applied to each other input terminal of 4 to 22-1. And end day) 22-1 exit cover exclusive or gate 20 Lu ~ 2
Applied to 0.

The outputs of the exclusive OR gates 20s to 20 are applied as address data to the A input terminals of the HROM (read only memory) 23. ROM23 is shown in @3 meat
It stores sine wave data of t/4 wave. This waveform data can be used for interpolation at points where the amplitude level of the rectangular wave etc. generated by the Unibu generator 5 suddenly changes. Waveform data is ORGATE24@N24・
1 is applied to the OR gate 24-~24.
The output of 22-2 is applied via an inverter 25 and a transfer gate 26. and or gate 2
4-~24e outputs are J non-alternative OR gates 278~27
・is applied to one end of each. Exclusive or gate 2 @ ~ 2
7. Each other end KH, Antogame)! S! The output of -1 is signaled through innoc m-28 and transformer 7 agate 29.

And the output of exclusive or gate 2-~27+1.

A input of the full adder 30, which consists of a polarity inversion circuit 1) I
IA@~A is also applied. Further, the output of the AND gate 22-1 at the A input terminal kqVcId of the full adder 30 is connected to the inverter 28. Transfer gate 29° inverter 311? applied via the Furthermore, if the full adder 30 is inputted, the output of the AND gate 22-1 is similarly connected to the inverter 28. In addition to being applied through the transfer gate 29, the output of a polarity inverting circuit 32, which will be described later, is applied through the transfer gate 5syt. The data to be set and output from the output end Sman N8 of the full adder 30 is the transfer gate 34! 〜34・Sent to digital filter 7 via Y.

Note that the upper (transfer gate 26
When the switches specifying the WM waves are operated, a control signal output from the ICCPU 3 is applied to the gate and the opening/closing side a is turned. Also, the transfer gates 29 and 35 are sawtooth wave control signals that are output from the KCPU 3 when the designated switch is operated. Respectively gate K [connection is applied, ty, :) lance 7 agate 33 is applied via inverter 36v, ll'
1rjPI control is possible.

Furthermore, 7 transformers and gates 34 and 34 are the outputs of the above-mentioned ant game) 22-2? Inverter 2B.

Transfer gate 35. The voltages are applied to the L gates of the inverter 37t, respectively, and the S closing control is performed.

The subtraction circuit 41 receives a scale frequency code p and data K (
constant values) are applied respectively. And the resulting data J-
are applied to a multiplication circuit 42 and a division circuit 44, respectively. The multiplier circuit 42 also has data r (this data r is 0≦
Take the value t for r≦1.

) which determines the duty ratio is applied, and the resultant data (β-K)ra is applied to the addition/subtraction circuit 43. The other end of this addition/subtraction circuit 43 has a scale frequency code β.
is applied to the control input terminal ±, and the polarity inverting circuit 3 is applied to the control input terminal ±.
2 outputs are applied.

The result data p±(#-K)r of the addition/subtraction circuit 32 is then applied to the gate circuit G. Note that the gate circuit Gsa
The opening and closing of the gate circuit q is controlled by the control units ' and ' which are output from the CPU 5 when the switches specifying the rectangular wave and the sawtooth wave are operated, respectively. Opening/closing is controlled by

The subtraction circuit 41SK receives the output data M of the shift register 17.
The work data K is input. And the resulting data M-
is applied to the divider circuit 44. The resultant data (M-K)/(It'-K) of the division circuit 44 is sent as sawtooth wave data to the digital filter 7 via transfer gates 46i to 46. Each gate of transfer gates 46T to 46 has a gate 22.
-2 output first inverter 21S,) transfer gate srs.

Inverter 37.47! The opening and closing are controlled.

The polarity inversion circuit 32 includes a shift register 48 and an exclusive OR gate 4 connected to the output side of the shift register 4B.
The output from the output terminal C' of the full adder 15 is applied to the other input terminal of the full adder 9 via an inverter 50V. Further, the output of the exclusive OR gate 49 is fed back to the input side of the shift register 48. In the case of the above-mentioned y:B tone polyphonic synthesizer, the shift register 48 is formed by cascading V8 shift registers each having a capacity of 1 bit. t'r: From the output terminal C' of the full adder 15, the full adder 15
When the resultant data reaches 512J, a signal (carry) at IIHII level is output.

The same wave number modulation unit 6 includes a low frequency oscillation circuit (LFU) as shown in the figure.
) a-t, a chaining control section 6-2 and a shift register 6-3. and low frequency oscillation circuit 6
-1. Each tuning control unit 6-2 has control data D.
-1 or D-2 may also be applied. Low frequency oscillation circuit 6-1
generates low frequency signals of any of four waveforms including triangular waves, sawtooth waves, and rectangular waves under the control of the input control data D-1, and supplies them to the shift register 6-3. The low frequency oscillation circuit 6-IK will be explained in more detail with reference to FIG. 7 and FIG. 8r.

The tuning control unit 6-2 receives input control data D-.
Tuning control operation is performed under the control of S+.

The output data is given to the t shift register 6-3.

The data received from the low frequency oscillation 4gl path 6-1 and the chaining tIt control section 6-2 is sent to the shift register 6-3 as the above-mentioned data α during the vibrato imparting operation or when performing tuning to the B input terminal of the full adder 15. Supply is available.

Furthermore, when vibrato is not applied or tuning is not performed at V#, data D-s is applied from the CPU to the shift register 6-3. The shift register 6-3 supplies this data as the data a to the input terminal of the full adder 150B. In the case of the above-mentioned 8-note polyapolyphonic synthesizer, the shift register 6-3 is composed of an 8-stage cascade V of a 16-bit capacity shift register.

Next, the configuration Y of the low frequency oscillation circuit 6-1 will be specifically explained with reference to FIGS. 7 and 8. In Figure 7,
The binary counter 70 has input terminals BNABLI, cc
A control command was applied from the PUs! (that is, during the vibrato imparting operation), the clock CL is enabled.
Kv meter afru.

Then, bit output size 1, 2, 4, 8, 16°82.
The count value data output from 64 is output from AND gate group 71
The corresponding AND gate 71.

71s, 710, 71m, 71m, 71., 71., respectively. Then, the AND gate group 71 is data-1111rlled by a signal obtained by inverting the rectangular wave generation command by the inverter 72. Also, Ant 1
1417! i's corresponding antenna
It's been a long time since I've been in the middle of a long time since I've been in the middle of a long time.

On the other hand, the output of the bit output terminal 128 of the most significant bit of the binary counter 7o is input to the analog door 6, and the transformer 7 is also input to the analog door 6. ? It's stuck inside the transfer gate 77@. Is the AND gate 76 the rectangular wave generation command and the triangular wave generation command? Gate controlled by a signal via the OR gate 78v,
In addition, its output is used as the gated # signal of the AND gate group 74, and the output of the AND gate 76,
The signal inverted by I/(-# 79 is used as the gate control (IIl signal) of the AND gate group 75.

The respective outputs of the AND gate groups 74 and 75 are connected to the transfer gate group 81 through ORD) 980g.
has been entered. It was. The transformer 7 argate group 77 is directly gate-controlled by the sawtooth wave generation command, while the transfer group 111H is gate-controlled by a signal obtained by inverting the sawtooth wave generation command by one by an inverter 82. Then, the output (7-bit data) of the transfer gate group 77 or H, 81 is obtained during the counting operation period for each period of the binary counter 7001.
As shown in Figure 8-), (c), and (d) T/c, the data gives the amplitude level of each waveform of a triangular wave, a sawtooth wave, and a rectangular wave. A low frequency signal is generated. A vibrato effect is imparted by these low frequency signals.

Next, the operation of the above embodiment will be explained with reference to FIGS. 4 to 6. First, the operation when the rectangular wave is generated by the unique wave generator 5 will be explained with reference to the time chart shown in FIG. In this case, first turn on the switch for specifying the rectangular wave on the switch section 2, and then operate the other necessary switches. It is assumed that nt does not apply vibrato or perform tuning. Therefore, when the rectangular wave designation switch is immediately operated, the gate circuits 11FGt and Gm of the 19 CPUBFX Unibuzi generator 5 are set to the ")I' (i.e. @1°) level or the "2@L" (i.e. '0') level. ) level signal is output.For this reason, from now on,
The gate circuit G1 is opened, and the second gate circuit q is closed. It also outputs a 1111 level signal to the ePUa frame transfer gate 26, and outputs a 10 level signal to the transfer gate "29.85. Therefore, from now on, the transfer gate 26 is opened and the transfer gates 29 and 35 are opened. Also, as a result of the above-mentioned transformer 7-day) 2G and 35 being closed, the transfer gate 33 and the transfer gate 34!
34. is opened, and transfer gate 46! ~
46. is closed. The case where one key on the keyboard @1 is turned on in the above state will be explained below. In the case of JM4, when the above one key is turned on, the CPU5 is R (for JM4,
711: RO
Outputs predetermined address data for reading from M4. As a result, %Rt) M4 to the above universal frequency coat °
β is read out and supplied to the Unibu generator 5.

And gate circuit G is being opened for this scale frequency code I.
(via TV) 18 TIML 8. Now, the output terminal cout of full adder 15
The output of the inverter 19 is 11", so the output of the inverter 19 is 11".
is currently under development. Therefore, the scale frequency code β is applied to the B input terminal Bss-wB of the full adder 16 via the analog signals 18si to 18. At this time, 16 bits all 0. from the 8 output terminal 8ssNs of the full adder 16 to the A input terminal Al5NA
Data is applied. Therefore, the result data of the full adder 16 at that time is the set scale frequency code p.
When data with the same value as 9.8 is output from the output terminal 81iN8@, it is input to the shift register 17. After being shifted, this data is output from the shift register 17, and is circulated to the A input terminals An to A of the full adder 15, as well as to the exclusive OR gates 2o to 206. It is input to inverters 21-211.

By the way, in the case of this embodiment, all gl and digits of the scale frequency code β of each scale are output as large values of "1o24". In other words, the top 11% of 16-bit data16
Any of the bits must contain Jll data. Therefore, when the above-mentioned one key is turned on, the above-mentioned scale frequency code 0β is set (1) Then, when the shift register 17 outputs data of the same value, the completion date)2
The output of 2-2 is always @0 level as shown in FIG. 4(e). Therefore, while the output of the AND gate 22-1 is 100, the output of the AND gate 22-2 is 0°0° level as shown in FIG. As shown in FIG. 4(C), the output of the polarity inverting circuit 32 is at the "0" level, and therefore the output of the polarity inverting circuit 32 is set at the "0" level as shown in FIG. 4(d). , the 1101 level signal of the AND gate 22-1 is supplied to the exclusive OR gates 20s to 2o, and the data of the lower 9 bits of the output of the Iζ shift register 17 is directly applied to the A input terminal A- to As of the ROM 2B. In addition, the IIQII level signal of the AND gate 22-2, which is the @1 level signal inverted by the inverter 25, is applied to the OR gates 246 to 24.
11# level signals are output from 46 to 24@, respectively, and exclusive or day) 2? It is applied to one end of each of @ to 27@.

The output of the polarity inversion circuit 32 at the Om level is not applied to the other ends of the exclusive OR gates 27e to 27-. Therefore, each output of the exclusive OR gates 27.about.27.becomes a signal of 11 level. The output of the inverter 31 is also at the ``L'' level. At this time, the A of the full adder 30 is input mA ~ A @ all @ 111
Data is entered. The output (@0'' signal) of the etrtcrz polarity inversion circuit 32 is input to the middle input terminal of the full adder 30.

Therefore, the result data of Full Adder 30 at this time is 8
S output terminals St to S as bit all @1' data.
Transfer gates 34 to 3 are output from and are being opened.
The signal is sent to the digital filter 7 via 4. The waveform diagram in FIG. 4(a) shows the rectangle [' sent to this digital filter 7.

y:t- is HC, PU with digital filter 7
3 fingers under control? The doubled W component is removed, and the envelope generator 7 applies an envelope 7 to its output vc, and the generation and emission of musical tones of the scale of the operation keys can be enjoyed.

When data with the same value as the set scale frequency code voice is circulated to the A input terminals Au to A of the full adder 15,
The data D-3 inputted to the CPU 3 is input as constant value data (16-bit data) via the shift register 6-3 of the frequency modulation section 6. Since the tr carry input terminal Gin is always set to the "H" level, the full adder 15 at this time
Execute the first subtraction operation of il-g, output the resulting data from the 8 output terminal, and apply it to the A input terminal of the full adder 16. In the table, "-α" in the above formula "β-α" is the second t
1! J's 11+6. gl, "all's f [-6-ra r-
I'm thrilled with the IJLfe stuff. Therefore, when this subtraction operation is executed, the output of the carry output terminal Cout of the full adder 115 becomes @1# level, and therefore the output of the inverter 19 /, % @ Q #, and the AND gate 181i~
18. is closed. Therefore, the input of the scale frequency code °β to the B input terminal of the full adder 16 is blocked ζ7. Therefore, the result data of full adder 16 in this corner is full adder 1! ! The result data is the same as the first result data, and is applied to the shift register 17. When this first result data is output from the shift register 17, it is inputted cyclically to the A input terminal of the full adder 15, while exclusive OR gates 201 to 20e.

The data input to the inverters 21-7 to 21-1 is input to the inverters 21-7 to 21-1, and the data input condition at the A input terminal and middle input terminal (In) of the full adder 30 after this first calculation is unchanged from the previous time. 8-bit all 11m data is sent to the digital filter 7.

Full adder 15. ANDGATE 1811-18・.

Full adder 16. In shift register 17, the following.

As a result of the cumulative subtraction operation that is exactly the same as the first subtraction operation described above, the data, that is, the output of one shift register is
1024'' (see FIG. 4(f)). During this time, the input states to the A input terminal and the carry input terminal C1n of the full adder 30 are also unchanged, so that the 8-bit full@1m data is continuously sent to the digital filter 7 during this period. Then, by the next subtraction operation, the output of the shift register 17 becomes smaller than jl 024J.

Upper output of cough shift register 17! The data of the 1st to 16th bits f+% are all 10''. Therefore, the output of the computer game 22-2 is inverted to the @l'' level as shown in FIG. 4(e). Therefore, from now on, the output of the inverter 25 is input to the m Os level toner OR gates 246-24.

On the other hand, the output of the shift register 17 is [1024
During the cumulative subtraction operation from J to "512J", the lθ-th bit data L "1m?" of the output of the shift register 17 is generated. Hold and therefore during this time.

@Figure 4 (b) As shown in K, continue and gate S!
10# on the output of 2-1, exclusive or gate S! 0
8 to 20. For this reason, the above “1024J~
The darkness of Is 12J is applied to the A input terminal of ROMOR by applying the lower 9 bit data h of the output of one shift register as it is. Further, during the above period rL, as shown in FIG. 4(d)vc, the output of the polarity inversion circuit 32 continues to be at the negative *Os level.

Therefore, the output power of the shift register 17 S j1024
Assuming that the value becomes 10234 or below, the lower 9 bits of the output of the nuclear shift register 17 are all 11, and are applied to the A input terminal of the ROM 28. Therefore, one ROM is 23t! This 9 bits all 111 address 0 address data is specified, and as shown in Fig. 3, 7 bits all 11''
Data 1: Read. This 7-bit all@1m data is input to exclusive OR gates 27--z7. through OR gates 246-24. Therefore, the above-mentioned process
Exclusive ORGATE 27・～27・Okubi Full Adder 30
1J-1 input terminal (5nK is a bottle@Om level signal is being input, and iI- is the A of full adder 30.
8-bit all 11m data is input to the input terminal, and the resulting data is also output as 8-bit all 112 data and sent to the digital filter 7 through the sending system fl.

Next, in the first cumulative subtraction operation, when the output of the Eli shift register 17 becomes a value smaller than j1023J by data a, R, t) The address is specified by the small address data, so as can be seen from Figure 1), the vcRUM23 is empty and the data is smaller than the 7-bit all 111 data by a predetermined value, !l], and the amplitude value is slightly smaller than the previous time. The data of the amplitude value is read out, and the data of the amplitude value is outputted by the full adder 30 without inverting the polarity and sent to the digital filter.

Thereafter, in the same way, the output of the shift register 17 is displayed in small ζ by area a in each cumulative subtraction operation.

Until the value becomes Is 12J, at) M? J!
1, the address data is sequentially specified in the direction of decreasing ζ by a, and correspondingly, the address data is specified by 15 degrees,
Amplitude value data with a smaller value than the previous time is read out. During this period, the input state of the data to the input terminal C1n of the full adder 30 is the same as that described above, and accordingly, the amplitude value of the digital filter command is inputted to the digital filter command as described above. Data is sent out. Then, when the output of the shift register 7 is j512J, the ROM 23 has 9 bits all @On address data and one address is specified.
It becomes t.

Next, the result data of the cumulative subtraction operation is stored in the full adder 15 as [51S! When the value changes from J to (511J or less), a "1" signal is output from the output terminal C' of the full adder 15, and in response, one pulse signal is output from the inverter 50 as shown in Figure (C) of I!4. As a result, after L sea urchin shown in Fig. 4(d).

The output of the polarity inversion circuit 32 is inverted to the 11# level.

Exclusive OR gates 276-27 and inverter 31 are applied to intermediate input terminal C1n of full adder 30, respectively.

Therefore, the data below "511" is shown in Figure 1 (f).
When outputting from the shift register 17 as shown in Ic,
The upper 1ON 16 bits of the output are all "O'f-", so the output of the gate 22-1 becomes @4.
As shown in FIG.
l'llll data is applied, and its output is inverted to all 9 bits "0#" and is applied to the A input terminal of the ROM 23. The result data of this summation cumulative subtraction is [511
R,0M2 while el decreases sequentially from J to rOJ
3 is based on the fact that the addresses are sequentially specified in the direction in which the address data increases from all @0# to all 11#. As a result, the amplitude value data read out gradually increases as shown in Figure @3, but the amplitude value data is passed through the exclusive OR gates 27 to 21 to the A input terminals A to A of the full adder. The signal is input to the A input terminal A, and the 11' signal is input to the carry input terminal Cin K, so the data rLnOM23 output from the MK full adder 30 is read out. amplitude 1
It becomes equal to the polarity χ of the data inverted, and the data is sent to the digital filter 47.

1#4 As shown in Figure 4(f), when the shift register 17 output is between ``to2*J'' and ``0'', the amplitude of the rectangular wave in Figure 4(a) is read from H1ROMz3. You can use F to interpolate string wave waveform data.

As described above, the cumulative subtraction result becomes rOJ.
'*e's carry output terminal Gout of full adder 15
°Om signal is output from , and as a result, Antogame) 1
851w1811 is temporarily opened and the scale frequency code β is applied to the B input terminals B1-B of the full adder 16.

When the data input to the A input terminal of the full adder 16 is added to the scale frequency code β, and the resulting data is output from the shift register 17, the above-mentioned y:
The above data, that is, the scale frequency code Pβn r
Since 1024J is a large value, for the reason mentioned above, from this point on, as shown in Figure 4 Φ), (6), Antogame) 22-1.2S! -2, each output is inverted to the 0'' level.

Set the scale frequency (co)1'#1)1- again as described above, then proceed as described above.

The cumulative subtraction operation of α is executed, and the shift register 17
From the output frame β, decrease ζ by α.j5. (1024J
decreases to And in this darkness, Full Adder 3
8-bit all 10" data is input to the A input terminals A to A of 0, and 11" data is input to the carry input terminal Cin.
Since the signal is being input, 8-bit all II OIT data can be sent to the digital filter 7 during this time.

The cumulative subtraction result is “lo!4J or less, and furthermore, [512
The seki that decreases to J is first shown in Figure 4(f) [10
24J is small, that is, the output of 22-1 is reversed to 1 level from the time when it becomes below [o2sJ].

Therefore, between "1023" and jstzJ, the output of the full adder 30 is.

ROM23χ its ant-sized address (9 bits all @1”
Data) It is equal to the reversed polarity of the amplitude value data that is read out by specifying the next address toward the minimum address (9 bits all 0'' data).

-, when the cumulative subtraction result reaches [512J, as mentioned above, the 11111 signal is output from the output terminal C' of the full adder 115, and in response to this, when the result becomes as shown in Fig. 4(d) K, the Antgame-) 22-1 The output of 61m level is the output H of full adder 30, RUM23V, and the til1 next dress finger from the small address 0 address to the moth large address! The data matches the amplitude value data that can be read out, and is sent to the digital filter 7 at 36°. The amplitude of the rectangular wave in Figure 4 (a) is RO
Interpolation is performed using the waveform data from M23. When the cumulative subtraction result becomes "0" or less, a 10m signal is output from the output terminal eout in the full adder 15 during the next subtraction, and the scale frequency code I is set again in the full adder 18, and one period of the first order The calculation process of the square wave can be started.

With the above, one period of rectangular wave? The liability processing operation for generating is also finished. For example, the calculation period in which the shift register 7 output changes from rOJ to "0" (that is, the period during which the previous and current Gf frequency codes β are respectively set ζ1) shown in FIG. 4 is sampled by T'. Assuming that the period is vT-, the calculation period T' is expressed by the following equation (1).

T'=T-・Koni (1) The frequency fs of the rectangular wave generated as described above is expressed by the following equation (2) when the sampling frequency f f m is used.

f・=□ gT' Next &C% Vibrato for the musical tone being emitted by the rectangular wave generated by the above operation? Explain the operation when adding. In this case, the output f6 data from the low-wave oscillation circuit 6-1 in the 1-frequency modulator 6 is applied to the B input terminal of the full adder 15 as the low-bit information of the above-mentioned Dagu. The data g in this case is generated by the low frequency oscillation circuit 6- described below.
1 changes at low frequency according to rS. That is,
@ In Figure 7, the binary counter 70 is the input Nobuko E
A control command from N A B L B K CPU U a is input, and one counting operation of a clock CLK is performed. And the content of the count value data is θ~ during %1 period
It changes at 256t.

Now, when a triangular wave generation command is being outputted ("1") by operating a predetermined switch of the switch unit 2, the output of the OR gate 7B becomes @11, and the AND gate 76 is opened. Also, when other sawtooth wave generation commands and square wave generation commands are both “O”.

%AND gate group 7 by inverter 72 output @llll
Group 71 was opened and transferred on the day of transfer) Group 71 was opened and transferred. Transfer gate group 77 is closed, and transfer gate group 81 is open.

Therefore, during the period when the bit output terminal 12B of the binary counter 7.0 is "0", that is, the first half of one cycle (count value data 0 to 128), the output cover of the AND gate 76 @
Therefore, the AND gate group γ circuit is opened. Therefore, in the first half of the above-mentioned period, the binary counter 7 is closed.
The count value data (7 bit data) from the 0 bit output terminals 64 to 1 are the 1 AND gate group 71.75 and the OR gate group SO.

It is outputted via the transfer gate group 81. and,
-) is the same as the count value data of the binary counter 70, and increases by 1.

In the next step A, the bit output terminal 128 becomes "1", that is, the latter half of one cycle (count value data 128 to 256
During this period, the output of the AND gate 76 becomes 111, the AND gate group 74 is opened, and the AND gate group 7IS is closed. Therefore, in the latter half of the above-mentioned period.

Output data t from bit output terminals 64 to 1 of binary counter 70, and inverter $73 via AND date group 1v
The data is given and all bits are inverted.

Furthermore, the AND gate group 74. Or game) group 80% switching game output through detailed sty. As a result, the output data is decreased by one.

In this way, a triangular wave signal as shown in Fig. 8(b) is obtained and used for imparting a vibrato effect.
The arcade group 77 is opened and the transfer gate 81 is closed. Furthermore, the AND gate group 74 is closed because the AN)''/'-) group 71 is opened and the ANTO gate flow is closed.

And the AND gate group 75 is opened.

In the first half (0 to 128) of one station period, the count value data of the bar 1 binary counter 700 bit output terminal 12g is output from the AND gate group 71. ) Lance 7 Argate Group 7? Output via lii. For this reason.

The output data is 1/2 # of the triangular wave from %0 to 128.
increases by l.

Then, in the latter half of one cycle (128-256), the output @1m of the binary counter 700-bit output terminal 128 is supplied as M8B of the above output data, so the above output data is It continues to increase by Kl with the same slope.

In this way, a sawtooth wave low frequency signal as shown in FIG. 8(C)K is obtained.

When only the square wave generation command is being output, the inverter 7
The AND gate group γ1 is closed by the second output @0#.

It was. AND gate group Therefore, in the first half of the 1W4 period (O to 12B), the bit output terminal 128 is 10#, and the output of the AND gate 76 is also ``0''. As a result, the AND gate 974 is closed and the AND gate group 75 is opened, but since the AND gate group 11 is now closed, the outputs of the AND gate) $75 are both @Om and AND. -The outputs of the gate group 74 also become *Os. Therefore, in the first half of the above l synchronization, all output data is
01 datatonal.

On the other hand, in the second half of the 1m period (128-256).

Depending on the output @1' of the bit output terminal 12g, the output of the AND gate 76 becomes @1m, and accordingly.

Ding Dating Group 4 has opened, one Ding Dating Group 75
is closed. Therefore, the output of the AND gate group 71,
All 10'' data is inverted by 1 by the inno(-evening group 73) and data that can be called all @1# data is output from the AND gate group 74, and further.

orday) group 80. Output f money via switching date group 81. Therefore, in the latter half of the above-mentioned one cycle, the output data holds 127 (all @ 1 m). As a result, a rectangular low-frequency signal as shown in Fig. 8 (1) K is obtained.

As described above, when the low frequency oscillation circuit s -1h=operation f, the value of 19a changes at low frequency.
As is obvious from the equation, since the frequency f of the rectangular wave also changes according to the change in the data α, a vibrato effect is imparted to the generated musical tone.

Next, an explanation will be given of the operation when tuning the sound collected by the rectangular wave. In this case, the data output by the tuning control section 6-2 in the 1-frequency modulation section 6 is applied to the B input terminal of the full adder 15 as the above data (low bit information). Then, this data arL tuning f[l
Due to the operation of the llIl unit 6-2, the original data 10 ([
A constant wax v is added to K and y: is taken as a subtracted basket. If the equation is used to attenuate, the result will be as follows.

In other words, the frequency vf when tuning is not complete.
The frequency at which the tuning of ttan cents was performed is f・′
Then, one frequency f@, f・′ is the following equation (3), (4)
are respectively represented by .

f・-a (Hz) ...(3)
n (cent) f@' =! a (Hz) e 2
1200 , , (4) where a is a positive number From the above formulas (3) and (4) and from formula (2), the following (5),
This is the same as equation (6).

Therefore, from equations (3) to (6), n [ is i.e., by operating the predetermined switches, the same wave number f@ of the generated musical tone changes by n cents according to equation (7), and chaining is easily possible. It can be done.

Next, the operation in the case of generating PWM waves will be explained with reference to FIG. First, the PWM wave designation switch on the switch unit 2 is turned on. At this point, gate circuit G1 is closed and gate circuit q1 is opened. At t, transformer 7 argate 26% 3B, 34 m~34· is opened, and transformer 7 agate 29° 35.46 V~46· is closed.

In the above state, one key t on the keyboard 1
When turned on, the PWM wave calculation and generation process begins.

Now, the output of the shift register 17 shown in FIG. As shown in FIG.
In addition, exclusive OR gates 27・~27・, inverter 31
．． Full adder 300 console input terminal etn 6' (respectively sl" signal is applied to it. Meanwhile, the subtraction circuit 41 outputs the result data -KV and gives it to the multiplication circuit 42, and the multiplication circuit 42Fx result data (β-K) It outputs rY and gives it to the addition/subtraction circuit 43 -7, -'.Furthermore, the addition/subtraction circuit 43 outputs the result data 11+
CI-K) rw small output, gate circuit GmK is provided.

For a string, the data for the above data is, for example, j1024J, and the data r for determining the weight ratio is t.

Take tV of 0≦r≦l.

Therefore, when one key is turned on, we want to perform the same operation as described above when generating the VC and square waves, and the 71v adder 16 is loaded with data p+(β-K) at the start of the calculation process.
r is set. And this setting data β+(#-K)
The cumulative subtraction operation of subtracting data (constant value) from r is executed until the resulting data, ie, the output of shift register 1, decreases by a to 10244.

5th N(b), (C), (d), (e')rc
As shown, AND gate 22-1. inverter so
, polarity inversion circuit 34 AND gate 22-2 (n each output is husband*, @Om, @1#.

“la and @Qll levels are maintained. Therefore, during this period, the read waveform from HROMzB is invalidated.
The data outputted from the full adder 30 and sent to the digital filter 6 becomes 8-bit all 10# data.

When the result data of the cumulative subtraction, that is, the output of the shift register 17 becomes j1024J, the output of the AND gate 22-2 is inverted to "l level. Therefore, when the result data changes from [o2iJ to j512J,
The full adder 30 outputs data obtained by inverting the polarity of the machine width value data read out by addressing sequentially from the maximum address to the minimum address mIt', and is sent to the digital filter 7.

When the resultant data reaches 5t2J, the output of the polarity inverting circuit 32 is inverted to <10 lv as shown in FIG.

Also exclusive or day) 27@-17・, inverter 31
．． Full adder 30 carry input terminal Gin K@O”
Signals are being applied. In addition, if the above result data becomes 511J or less, as shown in Figure 5 Φ), 1 day) 22-
The output of 1 is inverted to 1111 levels. Therefore, until the result data is converted from "511J" to "O",
The output u of the full adder 30 and the amplitude value data read out from the RUM2sv in the direction from the minimum address to the maximum address are output until that time and sent to the digital filter 7.

Then, as shown in Figure 5(f), the result data is 10''.
If the value is below, the full adder will be 16Kt+ at the next subtraction operation.
L, data β-(β-K)r are set. Table, HS
As shown in Figure-) and (e), the result data is “0”.
When this happens, each output of the AND gates 2z-1 and 22-1 is inverted to the @0# level.

When the data β(β-K)r is set to the full adder 16#c, the subtraction operation starts again.

As a result, the output of the full adder 30 remains 8 bits all 11m data until the data is reduced to [ozaJ].

Then, as shown in Figure 5(f), the result data is “1”.
If it is smaller than “024”, it is ANDGATE S! The output of 2-2 is at the ``l#l# level as shown in 8511M(e)K. Therefore, while the resultant data is decreasing to 512J, the output of the full adder 30 directs the ROM 23v' from the main address to the minimum atrus. The data is the same as the amplitude value data that can be read by addressing the digital filter γ.
Send it to.

Next, the result data is smaller than "512".

While further decreasing to rOJ, the ant° date 22-1
, 11ii outputs of the inversion circuit 32 are both inverted to the 11'' level and held. Therefore, during this period, the outputs of the full adder 30 t!, ROM 2311' are addressed and read from the minimum address to the maximum address, and the 1 amplitude is The data is sent to the 9° digital filter 7 with the keyness of the original data inverted.

Is the calculation processing operation of one cycle of PWM wave YM? .

The following is a repetition of what has been described above. The frequency f@6 (same as in the case of a rectangular wave and expressed by equation 1).The operations regarding vibrato and tuning are the same as described above.

Next 1C Figure 6? The case of a sawtooth wave will now be explained. First, the designated switch t of the sawtooth wave on the switch unit 2 is turned on 'f6°.As a result, the gate (low) path Gx is opened and the gate circuit Gm is closed. In addition, the transformer 7ar gate 29.35 was opened, and the transfer gate t'!
6.33 closes "f". And one key on keyboard 1 in the above state? When turned on, arithmetic processing for sawtooth wave generation begins.

Now, the output of the shift register 17 shown in FIG.
” (“0” at the left end of the figure). At this point, the scale frequency code β is full adder 16.
is set to Therefore, this scale frequency code β is a shift register! 7 then outputs the code I#
Since it is jl (M!4J!9) large data, as shown in Fig. 6 Φ and (C)K, the AND gate 22-1
, 22-2 are both inverted to the "06 level. Then, the output of 22-2 becomes @Om, so the output of the inverter 37 becomes 101. The output of the inverter 47 becomes @1", and this In response to this, the transfer gates 34 to 34 are closed, and the transfer gates 46 to 46 are opened.
6. Shift register 17. Android game) 18tsx
At l8., the cumulative subtraction operation for subtracting data (a constant value) from the acoustic frequency code p starts. Until the data as a result of the cumulative subtraction operation decreases to the value "1024", the AND gate 22-3! Since the output state of 4 does not change, the frame division circuit 4
Transfer gates 46 to 46 whose outputs are open
・I can send it through Nasuke. Therefore, the input terminal A of the division circuit 44
The output data M-K of the subtraction circuit 4s is input to K, and the output data β-K of the subtraction circuit 41 is applied to the input terminal BK. Therefore, the output data H' of the division circuit is given by the following equation (8).

1M on the side is the output of the shift register 17, Kl-j is a constant value, and this 1! In this example, "1024", H is the maximum amplitude value, and in this example, it is "2ssJ. Therefore, equation (8) can be replaced with the following equation (9).

As can be seen from equation (9), IIC, shift register 17
The output M, that is, the result data of cumulative subtraction is I'1Osu
J, the data sent to the digital filter 7 becomes "0". Then, as shown in FIG. 6(d)K, if the result data becomes 10244 or less, the AND gate 22-
2(n output is inverted to the K "l" level shown in Figure 6 (C) K. Therefore, transfer gates 34 to 3
4. is opened and transfer gates 46-46
・Or close. And the Joki result data is j51 S! J
Ant ° day) 22! Since the output of −1 can maintain @0 level, the output of inverter 28 @
12 through the transfer gate 29 which is open, the exclusive OR gates 271-27*, and the inverter 31. The carry input terminals ein and K of the full adder 30 are applied respectively.

That is, the result data is between j, 1023J and s t 2J.

What is the polarity of the third-order data that is sequentially addressed and read from the ROM 23V from the highest 167th address to the lowest address? The inverted data is output from full adder 30 and sent to digital filter 7 via transfer gates 34-34.

When the resultant data becomes smaller than "512", the output direction of the ant degree gate 22-1 is also reversed to the 11 degree level, as shown in FIG. 6 Φ). Therefore, after that "l° signal is applied to exclusive OR gates 2oa~20@, ROM2ft
is addressed from the lowest address to the highest address, while the output ``''Om of the inverter 2B or the exclusive OR gates 21--S!7o.

Inverter 31. Full adder 30 carry input terminal C
are respectively applied to in. Therefore, during the period from j511J to [O], the constant root width data read from the ROM 2B is sent to the digital filter 7 until that time. Then, the scale frequency code β is set in the full adder 16 again.

This concludes the dark period of sawtooth wave generation. Then, the frequency fe is calculated by the following equation (10) K J: f).

f@=f@−□ ... (10) β In other words, as can be understood from equation (10), in the case of a #*-shaped wave, the square wave 14 is different from the case of a PWM wave.

It is necessary to set the scale-wavenumber code β to 2f&.

Note that the operations regarding vibrato and tuning are the same as described above.

In the operation of generating square waves, PWM waves, and sawtooth waves as explained above, only one key on the keyboard is turned on.
As explained in the case of S, in this 11th example, we used a music synthesizer '9t for polyphonic music with 8 notes, so even if up to 8 keys are turned on at the same time, The detailed explanation of whether each circuit in FIG. 2 can simultaneously generate the fundamental wave for each key by time-division processing operation of 8 channels will be omitted.

In addition, in the above embodiment, the three types of fundamental waves, such as a rectangular wave, a PWM wave, and a sawtooth wave, are used, but other fundamental waves such as a triangular wave, a slope wave, etc. can be used. Also, interpolation 1k11 of the place where the vibration level of the fundamental wave suddenly changes: When performing an error on a sinusoidal wave, other functions such as quadratic functions, cubic functions, exponential trigonometric functions, etc.
-May be used. Also, with the above actual mf%l, the frame R (JM2
Although a sine wave Y with 174 cycles is stored in B, a sine wave with 1llf1 period or 1/2 W4 period may be used. Furthermore, in the above embodiment, after setting the initial value βt to full adder, constant @
Either a cumulative subtraction operation is performed to calculate αV, or a cumulative addition operation is performed to sequentially add a constant value gf after setting the initial value p.
It is also possible to perform a weaving process to obtain a fundamental wave similar to the above embodiment.

Furthermore, it goes without saying that this invention can be applied not only to a musical synthesizer but also to other electronic musical instruments, and can be modified and applied in various ways without departing from the spirit of the invention.
Jbo As explained above, this invention sets an initial value (scale frequency code) t' corresponding to a scale frequency by arithmetic processing in a digital circuit, and then repeatedly adds or subtracts a predetermined value to the initial value. .

10) When the result data satisfies the predetermined conditions, the above initial [EY is set again and the same calculation Y:
By periodically changing the frequency, a vibrato effect of the same depth and speed can be easily obtained over all scales. Possible electronic musical instrument frequencies? II control device was provided.

Vibrato can be easily added and tuned using rsWR, which was previously impossible through simple digital calculation processing.
Another advantage is that the hardware configuration can be simplified, contributing to the miniaturization of electronic musical instruments.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a music synthesizer according to an embodiment of the present invention, and FIG. 2 is a system diagram of a music synthesizer according to an embodiment of the present invention.
's aesthetic circuit garden, Figure 3 is the memory waveform diagram of Le υM23, @
Figure 4 is a time chart explaining the square wave generation operation, Figure 5 is a time chart explaining the PWM wave generation operation,
Figure @6 is a time chart explaining the sawtooth wave generation operation, Figure 7 is a detailed circuit diagram of the low frequency oscillation circuit 6-1, and Figure @8 is a diagram of various waveforms output by the low frequency oscillation circuit 6-1. It is. 1...Keyboard, 2...Switch part, 3
...CPU, 4...ROM, 5...unibuzi generator, 6...station wave number modulation section, 6-
DESCRIPTION OF SYMBOLS 1...Low frequency oscillation circuit, 6-2...Chi-engine control section, 7...Digital filter, 8...Envelope a
-Puji generator, 9...Digital/analog converter. 15.16...Full adder, 17...Shift register *18ts arrangement 8...And gate,
20I~20・, 27・~27... Exclusive or gate. 21-7~21-1...Inverter, 22-6~22
-1...AND gate, 23...ROM. 24.5I24...Orgate, S! 6. ++92
9.33,35. B4tW34@, 461-46...transfer gate, 31...inverter,
32... Polarity inversion circuit, 41%45... Subtraction circuit, 42... Ant calculation circuit, 43... Kajo calculation circuit. 44... except 1 [1 circuit s Gs, G 戈... gate circuit. 70...Binary counter. Patent applicant Casio Computer Co., Ltd.

Claims (3)

[Claims] (1) Provide frequency information corresponding to scale frequency @i
means for supplying control information of a predetermined value;
A calculation means for repeatedly adding and subtracting the control information supplied from the second means from this initial value as the frequency lyric IIv initial value supplied from the first means; and control means for controlling the frequency information to be supplied from the first means to the calculation means again, based on the output of the calculation means. Frequency v of output musical tone
A frequency control device for an electronic musical instrument that uses ml II and V% signals. (2) A patent characterized in that the invention further comprises a frequency modulation means for periodically and variablely controlling the control information supplied from the second means to add a frequency quality S++V to the L9 output musical tone. The frequency of the electronic musical instrument according to claim 1 is 1tllll@electrification. (3) The method of @2 above is used to supply knives 6-1. The tuning control means t'[ is provided with a tuning control means t'[ for variably controlling the sound 16Y of the output sound collection by variablely controlling the control information "f".
The frequency control device for an electronic musical instrument according to claim 2, wherein the %/'A is defined as vq9.