JPS6322312B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency control device for an electronic musical instrument.

One type of electronic musical instrument is the music synthesizer, but most of this type of electronic musical instrument is based on analog circuits, and there are almost no such electronic musical instruments that have been realized using digital methods.

However, various researches have been conducted on methods for digitally obtaining musical sound waveforms in electronic organs and the like, and some of them appear to have been put to practical use. One method of obtaining such a musical sound waveform is to provide an address counter that cumulatively adds a constant value, and to specify the address of the ROM using the output of the address counter. When performing frequency modulation on the waveform data read out from the ROM in this way to impart effects such as vibrato, this method uses the waveform data (i.e., frequency data) and vibrato that are vertically symmetrical with respect to the reference level. I try to perform multiplication with the waveform. For this reason, the depth of frequency modulation differs between the plus side and the minus side and is not equal, resulting in an unnatural vibrato. for example,
This method attempts to apply vibrato to the standard frequency of 440Hz using the above-mentioned vertically symmetrical vibrato waveform. Therefore, when the frequency changes by 200 cents to the positive side from 440Hz, the frequency is 493.9Hz (=440 +
53.9) Hz, so if you multiply the vertically symmetrical vibrato waveform by the above 440Hz, the negative side will be (440Hz).
−53.9=)386.1Hz. Therefore, this variation is 226
It becomes a cent.

Furthermore, when frequency data is modulated on the positive side by twice the original frequency data, that is, modulated one octave higher, on the positive side using this method, the negative side is canceled out and the frequency becomes 0. However, this method has the disadvantage that modulation of ±1 octave or more cannot be applied.

Furthermore, this method has the disadvantage that when attempting to apply vibrato of the same depth across the diatonic scale, the data (vibrato waveform) provided for this purpose differs depending on the scale, making frequency control extremely complicated.

In order to solve the above-mentioned drawbacks, there is a method that calculates data in units of cents to obtain desired frequency information, and obtains musical tones based on this frequency information (see Japanese Patent Laid-Open No. 74298/1983). However, in this prior art, based on the note code NC and the octave code OC, a frequency information memory is used to obtain frequency information log ₂ F, and from the changed frequency information log ₂ F′ expressed in cents, the changed frequency expressed as a natural number is obtained. A disadvantage arises in that a ROM or the like is required to obtain the information F', resulting in an increase in circuit scale.

This invention was made under the above-mentioned circumstances, and its purpose is to provide a memory for converting note chords and octave chords into values expressed in cents using logarithms; To provide a frequency control device for an electronic musical instrument that can easily perform frequency modulation without requiring a memory or the like for converting a value expressed in cents into a value expressed in natural numbers.

An embodiment of the present invention applied to a music synthesizer will be described below with reference to the drawings. FIG. 1 shows a system configuration diagram of a music synthesizer according to the above embodiment. In the figure, a keyboard 1 is equipped with a plurality of keys, and each key outputs a key operation signal. The switch section 2 includes a switch for selecting various sound source waveforms (fundamental waves) such as a rectangular wave, a PWM wave (asymmetric square wave), and a sawtooth wave, an equal-tempered frequency calculation section 4, a digital filter 6, and an envelope generator (described later). Various switches are provided, such as switches for controlling 7, etc., respectively. The respective outputs from the keyboard 1 and the switch section 2 are both supplied to a CPU (central processing unit) 3.

The CPU 3 is a device that controls all operations of this music synthesizer, and is composed of a microprocessor, etc., but its details will be omitted.

The equal temperament frequency calculation unit 4 is a circuit that always calculates frequency data β and α according to the equal temperament from the scale frequency code β′ and frequency modulation code α′ given from the CPU 3, regardless of frequency modulation. be.

The wave generator 5 uses the above data β, α
This is a circuit that creates the above-mentioned sound source waveform by digital calculation based on the data γ and K supplied from the CPU 3, and the created waveform data is supplied to the digital filter 6. The digital filter 6 removes a part of the harmonic components in the waveform data based on the control signal from the CPU 3, and supplies the output to the envelope generator 7. Further, the envelope generator 7 applies an envelope to the output of the digital filter 6 based on a control signal from the CPU 3 to generate a musical tone signal, and supplies the signal to the digital/analog converter 8. The digital/analog converter 8 is a circuit that converts the inputted digital musical tone signal into an analog musical tone signal, and this analog musical tone signal is sent to an amplifier 9 connected to the output side of the digital/analog converter 8. A musical tone is emitted through the speaker 10. In addition, this digital filter 6 has a special patent application.
No. 55-53179 ``Digital Filter Device'' and Japanese Patent Application No. 56-74244 ``Envelope Control System for Electronic Musical Instruments'' may be applied to the envelope generator 7.

Next, referring to FIG. 2, the wave generator 5
The specific configuration will be explained. The A input terminals A ₁₅ to _{A 0} of the full adder 15 are applied with 16-bit data outputted from the shift register 17 and circulated. In addition, the B input terminals B ₁₅ to _{B 0} are connected to the 16 from the equal tempered frequency calculation section 4.
Bit data α (α ₁₅ to α ₀ ) is applied. A high level signal "H" is always applied to the terminal Cin. Therefore, the full adder 15 inputs the input data α from the A input terminal to the B input terminal.
is subtracted, and the resulting data is output from the S output terminals S ₁₅ to S ₀ and applied to the A input terminals A ₁₅ to A ₀ of the full adder 16 connected to the output side of the full adder 15.
The B input terminals B ₁₅ to _{B 0} of the full adder 16 are supplied with the scale frequency code β (in the case of creating a rectangular wave or sawtooth wave) output from the gate circuit G ₁ or _the data β ± ( β-K)γ
(in the case of PWM wave creation) are respectively and gate 1
It is preset via ₈₁₅ to ₁₈₀ . Note that the carry output output from the terminal Cout of the full adder 15 is applied to each control input terminal of the AND gates 18 ₁₅ to _{18 0} via the inverter 19.

The result data of full adder 16 is S output terminal S ₁₅ ~
It is output from _S0 and applied to the shift register 17 connected to the output side of the full adder 16. For example, this music synthesizer is 8
Assuming that it is a polyphonic synthesizer, the shift register 17 is composed of eight stages of cascaded shift registers each having a capacity of 16 bits. The circuit shown in FIG. 2 executes time-sharing processing operations under the control of the CPU 3.

The lower 9 of the output data of the shift register 17
Bit data is exclusive or gate 20 ₈ ~ 20 ₀
is applied to Further, each of the 10 to 15 bits of the output data is applied to each control input terminal of AND gates 22-1 to 22-6 via inverters 21-1 to 21-6, respectively. Further, the most significant bit of the output data is applied to the other input terminal of AND gate 22-6 via inverter 21-7. AND gates 22-1 to 22-6 are connected in series as shown, and therefore the output of AND gate 22-6 is applied to the other input terminal of AND gate 22-5.
The respective outputs of 2-5 to 22-2 are applied to the other input terminals of the subsequent AND gates 22-4 to 22-1. The output of AND gate 22-1 is then applied to exclusive OR gates 20 ₈ to 20 ₀ .

The output of exclusive OR gates 20 ₈ to 20 ₀ is ROM
(Read-only memory) 23 is applied to A input terminals A ₈ to A ₀ as address data. The ROM 23 stores 1/4 waveform sine wave data shown in FIG. This waveform data is used to interpolate points where the amplitude level of the rectangular wave etc. generated by the wave generator 5 suddenly changes.
The 7-bit waveform data read from output terminals O ₆ -O ₀ of 3 is applied to OR gates 24 ₆ -24 ₀ .

The output of the AND gate 22-2 is also applied to the OR gates 24 ₆ to 24 ₀ via an inverter 25 and a transfer gate 26. The outputs of the OR gates 24 ₆ -24 ₀ are applied to one end of each of the exclusive OR gates 27 ₆ -27 ₀ . The output of the AND gate 22-1 is applied to the other ends of the exclusive OR gates 27 ₆ to 27 ₀ via an inverter 28 and a transfer gate 29. The outputs of the exclusive OR gates 27 ₆ to 27 ₀ are sent to the A input terminal A ₆ of the full adder 30 configuring the polarity inversion circuit.
~A applied to ₀ . Further, the output of the AND gate 22-1 is applied to the A input terminal _A7 of the full adder 30 via the inverter 28, transfer gate 29, and inverter 31. Furthermore, an AND gate 22- is connected to the input terminal Cin of the full adder 30.
1 is applied via an inverter 28 and a transfer gate 29, and the output of a polarity inversion circuit 32, which will be described later, is applied via a transfer gate 33. And the output end S ₇ of the full adder 30 ~
The data output from S ₀ is transferred to transfer gate 3.
₄₇ to ₃₄₀ to the digital filter 6.

The transfer gate 26 is controlled to open or close by applying a control signal output from the CPU 3 to the gate when a switch is operated to designate a rectangular wave or a PWM wave, respectively. Further, the control signals output from the CPU 3 are directly applied to the transfer gates 29 and 35 when the switch for specifying the sawtooth wave is operated, and the control signals are applied to the transfer gate 33 via the inverter 36 to control opening and closing. Further, transfer gates 34 ₇ to 34 ₀ connect the output of the AND gate 22-2 to the inverter 2.
5. The voltage is applied to the gates via the transfer gate 35 and the inverter 37 to control opening and closing.

A scale frequency code β and data K (constant value) are applied to the subtraction circuit 41, respectively. The resulting data β-K is then applied to a multiplication circuit 42 and a division circuit 44, respectively. The multiplication circuit 42 also receives data γ (this data γ takes a value of 0≦γ≦1,
) is applied to determine the duty ratio, and the resulting data (β-K)γ is added to the adder/subtractor circuit 4.
3 is applied. The scale frequency code β is applied to the other end of the addition/subtraction circuit 43, and the output of the polarity inversion circuit 32 is applied to the control input terminal ±. Then, the result data β±(β
-K) γ is applied to the gate circuit _G2 . In addition,
The gate circuit _G1 is controlled to open and close by a control signal output from the CPU 3 when a switch is operated to specify a rectangular wave and a sawtooth wave.
G ₂ is the CPU when operating the switch that specifies the PWM wave.
The opening/closing is controlled by the control signal output from 3.

Output data M and data K of the shift register 17 are input to the subtraction circuit 45 . The resulting data M-K is then applied to the division circuit 44. Then, the result data of the division circuit 44 (M-K)/(β
-K) is sent to the digital filter 6 as sawtooth wave data via transfer gates 46 ₇ to 46 ₀ . Transfer Gate 46 ₇ ~4
₆₀ , the output of the AND gate 22-2 is connected to the inverter 25, transfer gate 35,
The voltage is applied via the inverters 37 and 47, and the opening and closing are controlled.

The polarity inversion circuit 32 includes a shift register 48 and an exclusive OR gate 49 connected to the output side of the shift register 48. The other input terminal of the exclusive OR gate 49 receives the output from the output terminal C' of the full adder 15.
applied via. Further, the output of the exclusive OR gate 49 is fed back to the input side of the shift register 48. In the case of the above-mentioned 8-tone polyphonic synthesizer, the shift register 48 is formed by cascading 8 stages of shift registers each having a capacity of 1 bit.
Further, the output terminal C' of the full adder 15 outputs an "H" level signal (carry) when the result data of the full adder 15 reaches "512".

Next, various embodiments of the equal tempered frequency calculation section 4 will be described with reference to FIGS. 7 to 13. First, FIG. 7 is a circuit diagram of the first embodiment. In the figure,
Both the scale frequency code β' and the frequency modulation code α' are composed of N bits. The lower n bits specify the pitch (pitch) of a semitone or less, the upper 4 bits specify the note, and the remaining upper (N-n-4) bits specify the octave. . The data specifying the above 4-bit note is expressed in hexadecimal code,
Others are expressed in binary code.

The (N-n-4) bit data specifying each octave of the scale frequency code β' and the frequency modulation code α' are both applied to the binary adder/subtractor 61, and the 4-bit data specifying the notes are both subjected to decimal addition/subtraction. Further, the lower n bits of data specifying a pitch of less than a semitone are applied to a binary adder/subtractor 63. Also, binary adder/subtractor 6
An addition/subtraction command (-) from the CPU 3 is simultaneously applied to the 1 and 12-decimal adder/subtractor 62 and the binary adder/subtractor 63, and in response to this, each adder/subtractor 61-63 performs an addition or subtraction operation on its input data. The carry output of the binary adder/subtractor 63 is the terminal C ₀
It is outputted from and applied to the terminal Cin of the decimal adder/subtractor 62. Further, the carry output of the hexadecimal adder/subtractor 62 is output from the terminal C ₀ and applied to the terminal Cin of the binary adder/subtractor 61 . Therefore, binary adder/subtractor 6
Each result data of the 1 and 12-decimal adder/subtractor 62 is
The result data of the binary adder/subtractor 63 is applied to the ROM 64 as address data.
65 as address data. ROM
A ROM 64 stores a scale frequency code β according to equal temperament, and a ROM 65 stores a frequency modulation code α corresponding to a semitone (100 cents) according to equal temperament as exponential function data. And ROM6
Both the scale frequency code β and the frequency modulation code α read from 4 and 65 are sent to the wave generator 5.

FIG. 8 shows the 4-bit note designation data expressed by the hexadecimal code in the embodiment of FIG. 7 expressed as binary data. Code β', frequency modulation code α', and addition/subtraction commands (-) are applied. The upper N-n bits of the result data of the equal tempered frequency calculation executed by the binary adder/subtractor 66 are stored in the ROM 67.
The lower n bits are respectively applied to the ROM 68 as address data. Therefore, ROM67 has the same function as ROM64, and also has the same function as ROM64.
8 has the same function as the above ROM65, and ROM6
From 4 onwards, the scale frequency code β and ROM68
Frequency modulation codes α are read out from each of them.

In FIG. 9, the ROM 68 is removed from the embodiment of FIG. 8, and a binary adder/subtracter 71 is provided in its place. Therefore, both the scale frequency code β' and the frequency modulation code α' are expressed by binary data, and are input to a binary adder/subtractor 69 having the same function as the binary adder/subtractor 66. Then, the upper N-n bits of the resulting data are input to the ROM 70, which has the same function as the ROM 67, and the scale frequency code β
Read out. On the other hand, the lower n bits of data Y are applied to the binary adder/subtractor 71. Data X, which is equal to the value of the frequency modulation code α when frequency modulation is not performed, is applied to the other end of the binary adder/subtractor 71. The result data X±Y of the binary adder/subtractor 71 is then used as the frequency modulation code α.

Therefore, the value of data X is selected and output by the CPU 3 so as to satisfy the relational expression α=X±Y=X・2 ^100/1200 (1). For example, if we now assume n=6,
Also, if the binary adder/subtractor 71 functions as an adder, and if data Y (data Y takes a value between 0 and 63) is 63, then from equation (1), X+63=X・2 ^100/1200. Eventually, "1059" was selected as X,
Given from CPU3.

In this example, a semitone or less shows a linear change, but there is no problem in practical use.

In FIG. 10, the binary adder/subtractor 71 in FIG. 9 is removed and a decoder 74 is provided in its place, which further simplifies the hardware configuration. Thus, the binary adder/subtractor 72 has the same function as the binary adder/subtracter 69, and the ROM 73 has the same function as the ROM 70. On the other hand, the data of the lower n bits of the result data of the binary adder/subtracter 72 is applied to the decoder 74, and the output data Y and data X of the decoder 74 are output as the frequency modulation code X.

In this case, the lower n bits of data X are all “0”
The data is as follows. Therefore, the following relationship (2) holds true.

X+Y=X・2 ^100/1200 (2) Therefore, data Y is given by the following equation (3).

Y=X(2 ^100/1200 -1)...(3) For example, let n=6, set the lower 6 bits to all "0", and set the value of X to X=1111000000 (="960"). At this time, Y becomes "56" from equation (3). Therefore, the decoder output (data Y) varies from 0 to 56 depending on the output of the lower 6 bits of the binary adder/subtractor 72.
Configure the decoder 74 so that the value of data X
It is sufficient to add it to the lower 6 bits of the frequency modulation code α and send it out as the frequency modulation code α. If you do this, Y will be 0
By changing from ~56, the musical tone changes from 0 to 100 cents, that is, the maximum semitone and pitch.

In addition, as another example X = 1101000000 (= "832") Then, 0≦Y≦48.

FIG. 11 shows an embodiment in which a value obtained by multiplying a vibrato waveform and a vibrato depth designation signal is used as the frequency modulation code α'. In this case, the vibrato waveform signal is output from a predetermined waveform generator (not shown) under the control of the CPU 3, and the vibrato depth designation signal is output by operating a predetermined switch on the switch section 2. Therefore, the vibrato waveform signal and the vibrato depth designation signal are combined into the multiplier 75.
are input together and multiplied. Of the resulting data, the lower bit data corresponding to a semitone is passed through a gate circuit G that is gate-controlled by the control signal a output from the CPU 3, and the upper bit data is directly input to the frequency modulation code α. ' is applied to the equal tempered frequency calculator 76. Further, a scale frequency code β' is applied to the equal-tempered frequency calculator 76. Therefore, the equal tempered frequency calculator 76
For example, the circuit shown in FIG. 8 is used.

In this embodiment, when the control signal a is output as a "0" level and the gate circuit G is closed, the frequency modulation code α' in which the lower bit data corresponding to a semitone is all "0" is equal-tempered. Since it is applied to the frequency calculator 76, the equal-tempered frequency calculator 76
A vibrato waveform that changes chromatically can be obtained by the scale frequency code β' and the frequency modulation code α' outputted by.

FIG. 12 shows an embodiment in which the portamento movement can be performed only during monophonic performance.
That is, the code NEW KEY CODE that is output when a new key is turned on is sent to terminal T of the comparator circuit 77.
is applied. At that time, the code of the key that was previously turned on is on the terminal S of the flip-flop 8.
The output is circulated from 0 and applied. Then, the comparison circuit 77 performs a comparison operation to determine the magnitude relationship between the chords at both terminals T and S, and when the chord at terminal T is smaller than the chord at terminal S, that is, the current pitch is lower than the previous pitch. At times, a "1" level signal is output from the terminal S>T and applied to the control terminal (-) of the binary adder/subtractor 79 to cause the binary adder/subtracter 79 to perform a subtraction operation. On the other hand, when the code at the terminal T is greater than the code at the terminal S, that is, when the current pitch is higher than the previous pitch, a "0" level signal is output from the terminal S>T and the binary adder/subtractor 7
9 and causes the binary adder/subtractor 79 to perform an addition operation. Furthermore, comparison circuit 7
7 outputs a "1" level signal from the terminal S≠T to open the AND gate 78 when the respective codes of both terminals T and S do not match, and on the other hand, outputs a "0" level signal when they match. And gate 78
Close. A periodically output signal EXECUTE is applied to this AND gate 78, and while the AND gate 78 is open, it is sent to the binary adder/subtracter 79 by +1.
signal or -1 signal. The lower m bits of data corresponding to the chromatic scale of the N bits of data latched in the flip-flop 80 are sent to the binary adder/subtractor 79 via the gate circuit G.
Further, the data of the upper Nm bits is directly input in a circular manner. Therefore, the binary adder/subtracter 79 generates a signal for the data given from the flip-flop 80.
A +1 or -1 operation is executed for each input of EXECUTE, and the resulting data is output to flip-flop 80. Of the N-bit data output from the flip-flop 80, the upper N-n bits are applied to the ROM 81 to read out the scale frequency code β from the ROM 81, and the lower n bits are applied to the ROM 82 to read the frequency modulation code α. Read out. Note that the gate circuit G is gate-controlled by a control signal a.

With the above configuration, when the pitch of the newly turned-on key is lower than the pitch of the previous key, the binary adder/subtractor 79 executes a subtraction operation, while the pitch of the newly turned-on key is lower than the pitch of the previous key. When the pitch is higher than the pitch of the previous key, an addition operation is performed by the binary adder/subtractor 79, giving a portamento effect. Furthermore, when the control signal a is outputted at the "0" level, portamento that changes every chromatic scale can be obtained.

FIG. 13 shows an example circuit in which a glide effect can be obtained. When a new key is turned on, the code NEW KEY CODE is directly connected to the terminal T of the comparison circuit 83 and one end of the binary adder/subtractor 84.
It is also applied via the gate circuit _G1 . At the same time, the other end of the binary adder/subtractor 84 has a gate circuit.
Glide width data is applied via _G2 . Furthermore, at the same time, the control terminal (-) of the binary adder/subtractor 84
The signal UP/DOWN is transferred to transfer gate 91.
applied via. At this time, the binary adder/subtractor 84 outputs the code NEW KEY when the signal is an UP command (“1” level).
A glide width subtraction operation is executed for CODE, and on the other hand, when a down command is issued (“0” level), a glide width addition operation is executed for the code NEW KEY CODE. The resulting data is then applied to flip-flop 85. flip flop 8
After the key is turned on, the result data latched at 5 is applied directly to the terminal S of the comparison circuit 83 and to one end of the binary adder/subtractor ₈₄ via the gate circuit G8. At the same time, the upper N-n bits of the effect data are supplied to the ROM 86 to read out the scale frequency code .beta., and the lower n bits are supplied to the ROM 87 to read out the frequency modulation code .alpha.. The binary adder/subtractor 84 further has a control terminal (-) at which the comparator circuit 83 compares the magnitudes of the input data to both terminals S and T, and outputs a signal from the terminal S>T, which controls the transfer gate 92. applied via the Further, a signal EXECUTE is applied to the other end of the binary adder/subtractor 84 via an AND gate 89 and a transfer gate 90. Therefore, after the key is turned on, the binary adder/subtractor 84 performs an addition or subtraction operation on the result data from the flip-flop 85 every time the signal EXECUTE is input.
When the comparison circuit 83 detects a match between the input data at the terminals S and T, the addition or subtraction operation of the binary adder/subtractor 84 is stopped, and the operation of the glide effect is stopped.

That is, the comparator circuit 83 outputs a match signal from the terminal S≠T that is at the "1" level when the two data to the terminals S and T do not match, and is at the "0" level when they match, and is sent to the AND gate 89. Apply. Further, the comparator circuit 83 has a "1" level when the data at the terminal S is larger than the data at the terminal T, and a "0" level when the data is smaller than the data at the terminal T.
A level comparison result signal is output from terminal S>T. Additionally, one signal is output when the key is turned on.NEW
KEY ON is directly applied to gate circuits G ₁ and G ₂ and transfer gate 91, respectively, and both are configured to open when the key is turned on. Further, a signal obtained by inverting the signal NEW KEY ON by an inverter 88 is applied to the gate circuit G ₃ and transfer gates 90 and 92, respectively, and these are both opened after the key is turned on.
Note that the above-mentioned signal UP/down and glide width data are output in response to a switch operation on the switch section 2.

Next, the operation of the above embodiment will be explained with reference to FIGS. 4 to 6. First, the operation when a rectangular wave is generated by the wave generator 5 will be explained with reference to the time chart of FIG. In this case, first, turn on the switch for specifying the rectangular wave on the switch section 2, and operate the other necessary switches. Note that in this case, frequency modulation such as vibrato is not performed. Therefore, by turning on the square wave designation switch, the CPU 3 sets the gate circuits G ₁ and G ₂ of the wave generator 5 to the “H” (i.e., “1”) level or “L” (i.e., “0”) level. ”) outputs a level signal. Therefore, from then on, gate circuit G ₁ is opened and gate circuit G ₂ is closed. Further, the CPU 3 outputs a "1" level signal to the transfer gate 26, and outputs a "0" level signal to the transfer gates 29 and 35. Therefore, thereafter, the transfer gate 26 is opened and the transfer gates 29 and 35 are closed. Further, as a result of the transfer gates 29 and 35 being closed,
Transfer gate 33 and transfer gates 34 ₇ to 34 ₀ are opened, and transfer gates 46 ₇ to 46 ₀ are closed.

The case where, for example, one key on the keyboard 1 is turned on in the above state will be described below. In this case, when one key is turned on, the CPU 3 outputs to the equal-tempered frequency calculation unit 4 a scale frequency code β' corresponding to the operated key and a frequency modulation code α' when frequency modulation is not performed. In response to this, the equal temperament frequency calculation unit 4 outputs the corresponding scale frequency code β and frequency modulation code α by the equal temperament frequency calculation, and supplies them to the wave generator 5. And this scale frequency code β
is the AND gate 1 through the gate circuit G ₁ being opened.
Applied from 8 ₁₅ to 18 ₀ . Now, the output of the output terminal Cout of the full adder 15 is “0”,
Therefore, the AND gates 18 ₁₅ to 18 ₀ are being opened due to the output "1" of the inverter 19.
Therefore, the scale frequency code β is applied to the B input ends B 15 _to B ₀ of the full adder 16 via the AND gates _{18 15} to 18 ₀ . On the other hand, at this time, from the S output terminals _S15 to _S0 of the full adder 15 to the full adder 16
16-bit all "0" data is applied to the A input terminals _A15 to _A0 of. Therefore, the result data of the full adder 16 at that time will be data with the same value as the set scale frequency code β, and the S output terminal
When output from S ₁₅ to S ₀ , it is input to the shift register 17. When this data is shifted and output from the shift register 17, the full adder 15
_It is _circularly inputted to the A input terminals _A15 to _{A0 of} the
~21 Enter ₁ .

In the case of this embodiment, all values of the scale frequency code β of each scale are output as values larger than "1024". That is, any one of the upper 11 to 16 bits of the 16-bit data always contains "1" data. Therefore, when the scale frequency code β is set when one key is turned on, and the shift register 17 outputs data of the same value, the output of the AND gate 22-2 is always "" as shown in FIG. 4e. 0” level. Therefore, the output of the AND gate 22-1 is also at the "0" level while the output of the AND gate 22-2 is "0" as shown in FIG. 4B. Furthermore, at this time, the output of the inverter 50 is
The output of the polarity inversion circuit 32 is at the "1" level as shown in FIG. As a result, and gate 2
The "0" level signal of 2-1 is supplied to the exclusive OR gates ₂₀₈ to ₂₀₀ , and the data of the lower 9 bits of the output of the shift register 17 is directly transferred to the ROM 2.
It is applied to the A input terminals A ₈ to A ₀ of No. 3. Further, a "1" level signal obtained by inverting the "0" level signal of the AND gate 22-2 by the inverter 25 is applied to the OR gates 24 ₆ to 24 ₀ , and therefore, the OR gates 24 ₆ to 24 ₀ each output a "1" level signal. A level signal is output and applied to one end of each of exclusive OR gates 27 ₆ -27 ₀ . Therefore, exclusive or gate 27 ₆
“0” of the polarity inverting circuit 32 is at the other end of each of ~27 ₀ .
level output is applied. Therefore, all outputs of the exclusive OR gates 27 ₆ to 27 ₀ become "1" level signals. Also, the inverter 31
The output of is also at the "1" level. As a result, all "1" data is input to the input terminals _A7 to _A0 of the full adder 30aA. Further, the output (“0” signal) of the polarity inversion circuit 32 is input to the carry input terminal Cin of the full adder 30. Therefore full adder 30
The result data at this time is 8 bits all “1”
It is output as data from the S output terminals S ₇ to _{S 0} and sent to the digital filter 6 via the open transfer gates 34 ₇ to 34 ₀ . The waveform diagram in FIG. 4a shows a rectangular wave sent to this digital filter 6. Therefore, the digital filter 6 removes the specified overtone component under the control of the CPU 3, and the envelope generator 7 applies an envelope to its output, and starts generating and emitting musical tones of the scale of the operation keys. .

When data with the same value as the set scale frequency code β is input in circulation to the A input terminals A ₁₅ to _{A 0} of the full adder 15, the average rate frequency calculation section 4 outputs the data to the B input terminals B ₁₅ to B ₀ . The constant value data (frequency modulation code) α is input as 16-bit data. Also, the carry input terminal Cin is always “H”
Since the full adder 15 is set to the level, the full adder 15 executes the first subtraction operation of β-α at this time, outputs the resulting data from the S output terminal, and applies it to the A input terminal of the full adder 16. In addition, the above formula “β−
``-α'' of ``α'' corresponds to the value obtained by subtracting ``-1'' from the values of α ₀ , α ₁ , . . . α ₁₅ in FIG. Therefore, when executing this subtraction operation, the carry output terminal of the full adder 15
The output of Cout becomes "1" level, and therefore the output of inverter 19 becomes "0", and AND gates 18 ₁₅ to 18 ₀ are closed. Therefore, input of the scale frequency code β to the B input terminal of the full adder 16 is blocked. Therefore, the result data of the full adder 16 at this time is the same as the result data of the first time of the full adder 15, and the result data of the full adder 16 is the same as the result data of the first time of the full adder 15.
Give to 7. When this first result data is output from the shift register 17, the full adder 1
Exclusive OR gates 20 ₈ to 20 ₀ and inverters 21-7 to 21-
Enter 1. After the A input of the full adder 30 after this first calculation, the carry input terminal
The data input state of Cin is unchanged from the previous time, so 8-bit all "1" data is sent to the digital filter 6.

Full Adder 15, And Gate 18 ₁₅ ~ 18 ₀ ,
In the full adder 16 and shift register 17,
The cumulative subtraction operation, which is exactly the same as the first subtraction operation described above, results in data, that is, shift register 1.
This process is repeated until the output of 7 becomes "1024" (see Figure 4 f). And the other day, full adder 30 A
The input state to the input terminal, the carry input terminal Cin, does not change either, so during this period, 8-bit all "1" data is continuously sent to the digital filter 6. Then, when the output of the shift register 17 becomes smaller than "1024" by the next subtraction operation, the data in the upper 11th to 16th bits of the output of the shift register 17 are all "0", and so The output of the AND gate 22-2 is shown in Fig. 4e.
It is inverted to the “1” level as shown in . Therefore, from now on, the output of the inverter 25 becomes "0" level and is input to the OR gates 24 ₆ to 24 ₀ .

On the other hand, during the cumulative subtraction operation in which the output of the shift register 17 is from "1024" to "512", the 10th bit data of the output of the shift register 17 holds "1", so during this period, Figure 4b
As shown in , the output of the AND gate 22-1 continues to be “0” and the exclusive OR gates ₂₀
0 ₀ is supplied. For this reason, the above "1024" ~
During "512", the lower 9 bit data of the output of the shift register 17 continues to be applied to the A input terminal of the ROM 23 as it is. During the above period, the output of the polarity inversion circuit 32 continues to be at the "0" level as shown in FIG. 4d.

Therefore, assuming that the output of the shift register 17 becomes "1024" or less, for example "1023", then the lower 9 bits of the output of the shift register 17 are all "1", It is applied to the A input terminal of the ROM23. Therefore, the ROM 23 is addressed by this 9-bit all "1" address data, and 7-bit all "1" data is read out as shown in FIG. This 7-bit all "1" data is passed through exclusive OR gates ₂₇₆ to ₂₄₀ through OR gates ₂₄₆ to 240.
27 Enter ₀ . As mentioned above, exclusive or gates 27 ₆ to 27 ₀ and full adder 30
A "0" level signal is still being input to the carry input terminal Cin of the full adder 30, so 8-bit all "1" data is input to the A input terminal of the full adder 30, and as a result, the data is also 8-bit all "1". It is output as data and sent to the digital filter 6.

Next, when the output of the shift register 17 becomes a value smaller than "1023" by data α due to the next cumulative subtraction operation, the ROM 23 is stored at an address smaller by α than the above-mentioned 9-bit all "1" data (i.e., "511"). Addressed by data. Therefore, as can be seen from Figure 3, the ROM
23, data smaller by a predetermined value than the above-mentioned 7-bit all "1" data, that is, data with an amplitude value slightly smaller than the previous one, is read out, and the data with the amplitude value is output as is without having its polarity inverted by the full adder 30. The signal is sent to the digital filter 6.

Thereafter, in the same way, the output of the shift register 17 decreases by α by each cumulative subtraction operation,
Until the value reaches "512", the address data in the ROM 23 is sequentially addressed in the direction of decreasing by α, and accordingly, each time, amplitude value data with a smaller value than the previous one is read out. Ru. During this time, the input state of data to the A input terminal and the carry input terminal Cin of the full adder 30 is the same as described above, and accordingly, the above-mentioned sequentially decreasing amplitude value data is sent to the digital filter 6. . When the output of the shift register 17 is "512", the ROM 23 is addressed by address data of 9 bits all "0".

Next, the result data of cumulative subtraction operation is full adder 1
5, when the value changes from "512" to "511" or less, "1" is output from the output terminal C' of the full adder 15.
A signal is output, and in response, one pulse signal is output from the inverter 50 as shown in FIG. 4c. As a result, as shown in FIG. 4d, the output of the polarity inversion circuit 32 is subsequently inverted to the "1" level, and the exclusive OR gates 27 ₆ to 27 ₀ , the inverter 31,
The signals are applied to the carry input terminals Cin of the full adder 30, respectively.

Therefore, when data below "511" is output from the shift register 17 as shown in Figure 4f, the upper 10 to 16 bits of the output are all "0".
Therefore, the output of the AND gate 22-1 changes to the "1" level as shown in FIG. 4B, and is applied to the exclusive OR gates 20 ₈ to 20 ₀ . On the other hand, 9-bit all "1" data is again applied to the other ends of the exclusive OR gates ₂₀₈ to ₂₀₀ , and the output thereof is inverted to 9-bit all "0" and applied to the A input terminal of the ROM 23. . Therefore, the result data of cumulative subtraction is "511" to "0".
While the address data sequentially decreases by α, the ROM 23 is sequentially addressed in the direction in which the address data increases from all "0" to all "1". Further, the amplitude value data that is generated as _a result becomes _larger sequentially as shown _{in FIG} . In addition, since a "0" signal is input to the A input terminal _A7 and a "1" signal is input to the carry input terminal Cin, the data output from the full adder 30 during this period is the amplitude value data successively output from the ROM 23. The data is sent to the digital filter 6.

As shown in FIG. 4 f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave in FIG. interpolated accordingly.

When the cumulative subtraction result becomes "0" as described above, a "0" signal is output from the carry output terminal Cout of the full adder 15 during the next subtraction operation, and as a result,
The AND gates 18 ₁₅ to 18 ₀ are temporarily opened and the scale frequency code β is input to the B input terminal B ₁ ⁵ of the full adder 16.
~ applied to B ₀ . And full adder 16 A
When the data given to the input terminal and this scale frequency code β are added, and the resulting data is output from the shift register 17, the above data, that is, the scale frequency code β is “1024” as described above.
Since the value is larger, for the reason mentioned above, from this point on, the outputs of the AND gates 22-1 and 22-2 are inverted to the "0" level as shown in FIGS. 4b and 4e.

After the scale frequency code β is set again as described above,
The cumulative subtraction operation by α is executed, and the output of the shift register 17 decreases from β by α, and becomes “1024”.
decreases to During this period, 8-bit all "0" data is input to the A input terminals _A7 to _A0 of the full adder 30, and the carry input terminal
Since a "1" signal is input to Cin, 8-bit all "0" data is sent to the digital film 6 during this period.

While the cumulative subtraction result becomes "1024" or less and further decreases to "512", the AND gate 22-2 is first applied from the point when it becomes smaller than "1024", that is, "1023" or less as shown in FIG. The output of is inverted to "1" level. Therefore, between "1023" and "512", the output of the full adder 30 moves the ROM 23 from its maximum address (9 bits all "1" data) to its minimum address (9 bits all "0" data).
It is equal to the inverted polarity of the amplitude value data that is sequentially addressed and read out.

Furthermore, when the cumulative subtraction result becomes "512", "1" is output from the output terminal C' of the full adder 15 as described above.
A signal is output, and in response to this, the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 4d. Next, when the cumulative subtraction result becomes "511" or less, the output of the AND gate 22-1 is inverted to the "1" level. As a result, as mentioned above, when the cumulative subtraction result is between "511" and "0", the output of the full adder 30 is read out by sequentially addressing the ROM 23 from the minimum address to the maximum address. The data matches the amplitude value data and is sent to the digital filter 6.

As shown in FIG. 4f, when the output of the shift register 17 is between "1024" and "0", the amplitude of the rectangular wave shown in FIG. 4a is interpolated by the waveform data from the ROM 23. When the cumulative subtraction result becomes "0" or less, a "0" signal is output from the carry output terminal Cout of the full adder 15 during the next calculation, and the scale frequency code β is set in the full adder 16 again. Rectangular wave calculation processing is started.

With the above, the arithmetic processing operation for generating a rectangular wave for one cycle is completed. For example, the calculation period in which the output of the shift register 17 changes from "0" to "0" (that is, the period during which each scale frequency code β of the previous and current scales is set) shown in FIG.
When T' and the sampling period are T _S , the calculation period T' is expressed by the following equation (4).

T′=T _S・β/α …(4) Also, the frequency of the rectangular wave generated as described above _{is 0}
is expressed by the following equation (5), where _S is the sampling frequency.

₀ =1/2T'= _S /2・α/β (5) Next, the operation in the case of generating a PWM wave will be explained with reference to FIG. First, PWM on switch section 2
Turn on the wave designation switch. As a result, gate circuit _G1 is closed and gate circuit _G2 is opened.
Also, transfer gates 26, 33, 34 ₇ ~
34 ₀ is opened and transfer gate 29,
35, 46 ₇ to 46 ₀ are closed. In the above state, when one key on the keyboard 1 is turned on, the calculation and generation process of the PWM wave is started.

The explanation will now start from the timing when the shift register 17 output is "0"("0" at the left end in the figure) shown in FIG. 5F. That is, at this point, the output of the polarity inversion circuit 32 is "1" as shown in FIG.
Therefore, the addition command is given to the addition/subtraction circuit 43, and the exclusive OR gate 27 ₆
~27 ₀ , a “1” signal is applied to the carry input terminal Cin of the inverter 31 and the full adder 30, respectively.

On the other hand, the subtraction circuit 41 outputs the result data β-K and gives it to the multiplication circuit 42, and the multiplication circuit 42 outputs the result data (β-K)γ to the addition and subtraction circuit 43.
is giving to Furthermore, the addition/subtraction circuit 43 outputs result data β+(β-K)γ, which is applied to the gate circuit _G2 . For example, the data K is "1024", and the data γ that determines the duty ratio is
It takes a value of 0≦γ≦0.

Therefore, when the above-mentioned one key is turned on, data β+(β-K)γ is set in the full adder 16 at the start of arithmetic processing in accordance with an operation similar to that described for the rectangular wave generation operation. Then, a cumulative subtraction operation is performed to subtract data α (a constant value) from this setting data β+(β−K)γ. Until the resulting data, that is, the output of the shift register 17, decreases by α to "1024", the AND gate 2
2-1, the inverter 50, the polarity inversion circuit 32, and the AND gate 22-2 outputs "0" and "0", respectively.
Each level of "1", "1", and "0" is held.
Therefore, during this period, the read waveform from the ROM 23 is invalidated, and the data output from the full adder 30 and sent to the digital filter 6 becomes 8-bit all "0" data.

Cumulative subtraction result data, ie, shift register 1
When the 7 output is less than "1024", AND gate 2
The output of 2-2 is inverted to "1" level. Therefore, while the above result data changes from "1024" to "512", the full adder 30 outputs data with the polarity of the amplitude value data read by sequentially addressing the ROM 23 from the maximum address to the minimum address. The signal is then sent to the digital filter 6.

When the resultant data becomes "512", the output of the polarity inversion circuit 32 is inverted to the "0" level as shown in FIG. 5d, and a subtraction command is given to the addition/subtraction circuit 43.
Further, a “0” signal is applied to the carry input terminals Cin of the exclusive OR gates 27 ₆ to 27 ₀ , the inverter 31 and the full adder 30 . Further, when the resultant data becomes less than "511", the output of the AND gate 22-1 is inverted to the "1" level, as shown in FIG. 5B. Therefore, until the result data changes from "511" to "0", the output of the full adder 30 is the amplitude value data read out by addressing the ROM 23 from the minimum address to the maximum address. The signal is output and sent to the digital filter 6.

Then, as shown in FIG. 5f, when the resultant data becomes "0" or less, data .beta.-(.beta.-K).gamma. is set in the full adder 16 during the next subtraction operation. Note that, as shown in FIGS. 5b and 5e, when the result data is "0", the AND gate 22-
Each output of 1 and 22-2 is inverted to the "0" level. When the data β-(β-K)γ is set to full adder, the subtraction operation by α is started again. As a result, the output of the full adder 30 is held as 8-bit all "1" data until the data is reduced to "1024".

When the resultant data becomes smaller than "1024" as shown in FIG. 5f, the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 5e. Therefore, while the result data decreases to "512", the output of the full adder 30 becomes the same data as the amplitude value data read out by addressing the ROM 23 from the maximum address to the minimum address, and sends it to the digital filter 6. .

Next, while the result data becomes smaller than "512" and further decreases to "0", the AND gate 22-
1. Each output of the polarity inversion circuit 32 is both inverted and held at the "1" level. Therefore, the output of the full adder 30 during this period is data in which the polarity of the amplitude value data read out by addressing the ROM 23 from the minimum address to the maximum address is reversed.
The signal is sent to the digital filter 6.

This completes the arithmetic processing operation for one cycle of the PWM wave, and the following is a repetition of what has been described above. And its frequency ₀ is the same as in the case of a square wave, and formula (5)
It is represented by

Next, the case of a sawtooth wave will be explained with reference to FIG. First, the sawtooth wave designation switch on the switch section 2 is turned on. As a result, gate circuit G ₁
is opened, and gate circuit _G2 is closed. Further, transfer gates 29 and 35 are opened, and transfer gates 26 and 33 are closed. In the above state, when one key on the keyboard 1 is turned on, arithmetic processing for generating a sawtooth wave starts.

An explanation will now be given starting from the timing when the output of the shift register 17 is "0"("0" at the left end in the figure) shown in FIG. 6d. At this point, the scale frequency code β
is set in the full adder 16. Therefore, when this scale frequency code β is then output from the shift register 17, since the code β is data larger than "1024", the AND gates 22-1 and 22 are output as shown in FIGS. 6b and 6c, respectively. -2 outputs are both inverted to "0" level. Since the output of the AND gate 22-2 becomes "0", the output of the inverter 37 becomes "0" and the output of the inverter 47 becomes "1", and accordingly, the transfer gates 34 ₇ to 34 ₀ are closed. Then, the transfer gates 46 ₇ to 46 ₀ are opened. Further, in the full adders 15 and 16, the shift register 17, and the AND gates 18 ₁₅ to 18 ₀ , an cumulative subtraction operation for subtracting data α (constant value) from the scale frequency code β starts. Since the output state of the AND gate 22-2 does not change until the data as a result of the cumulative subtraction operation decreases to the value "1024", the output of the divider circuit 44 is sent to the digital filter 6 from the open transformer. It is sent out via argates 46 ₇ to 46 ₀ . The output data M-K of the subtraction circuit 45 is input to the input terminal A of the division circuit 44, and the output data β- of the subtraction circuit 41 is input to the input terminal B.
K is applied to each. Therefore, the output data H' of the division circuit is expressed by the following equation (6).

H'=M-K/β-K×H...(6) where M is the output of the shift register 17, K is a constant value, in this example "1024", H is the maximum amplitude value, In this example, it is "256".
Therefore, equation (6) can be rewritten as the following equation (7).

H'=M-1024/β-1024×256...(7) As can be seen from equation (7), shift register 17
When the output M of , that is, the data as a result of cumulative subtraction becomes "1024", the data sent to the digital filter 6 becomes "0". When the resultant data becomes "1024" or less as shown in FIG. 6(d), the output of the AND gate 22-2 is inverted to the "1" level as shown in FIG. 6(c). Therefore, transfer gates 34 ₇ to 37 ₀ are opened, and transfer gates 46 ₇ to 46 ₀ are closed. Until the above result data decreases to "512", the output of the AND gate 22-1 is held at the "0" level, so the output "1" of the inverter 28 is excluded via the open transfer gate 29. The signals are applied to the carry input terminals Cin of the target OR gates 27 ₆ to 27 ₀ , the inverter 31 and the full adder 30, respectively. In other words, when the result data is between "1023" and "512", the full adder 30 outputs data in which the polarity of the amplitude value data read out by addressing the ROM 23 sequentially from the highest address to the lowest address is output, and the transfer data is outputted from the full adder 30. The signal is sent to the digital filter 6 via the argates ₃₄₇ to ₃₄₀ .

When the resultant data becomes smaller than "512", the output of the AND gate 22-1 is also inverted to the "1" level, as shown in FIG. 6b. Therefore, “1”
After the signal is applied to the exclusive OR gates 20 ₈ to 20 ₀ , the ROM 23 is addressed from the lowest address to the highest address, while the output “0” of the inverter 28 is applied to the exclusive OR gates 27 _{6 to 27 6} .
27 ₀ is applied to the carry input terminal Cin of the inverter 31 and the full adder 30, respectively. Therefore, between "511" and "0", the data is not sent to digital filter 6.
The amplitude value data read from the ROM 23 is sent out as is. Then, the scale frequency code β is set in the full adder 16 again.

This completes one cycle of sawtooth wave generation. The frequency ₀ is expressed by the following equation (8).

₀ = _S・α/β …(8) In other words, as understood from equation (8), in the case of a sawtooth wave, unlike the case of a rectangular wave or PWM wave,
It is necessary to double the scale frequency code β.

Next, an explanation will be given of the operation when performing frequency modulation on the musical tone generated by the above-described operation and adding vibrato and the like. In this case, the equal-tempered frequency calculation unit 4 of the various embodiments shown in FIGS. 7 to 13 performs an operation different from that when no frequency modulation is performed, and the scale frequency code β is not a constant value but constantly changes. data α, that is, frequency modulation code α
is output and supplied to the wave generator 5.

First, in the case of the embodiment shown in FIG. 7, the data of the lower n bits of each of the scale frequency code β' and the frequency modulation code α', both of which are output from the CPU 3 as N-bit data, are applied to the binary adder/subtractor 63, and Each data of the upper 4 bits of the hexadecimal code is applied to the hexadecimal adder/subtractor 62, and furthermore, the data of the upper N-n-4 bits are applied to the binary adder/subtractor 61, respectively. Each of the adders/subtractors 61 to 63 similarly performs an addition operation or a subtraction operation in response to an addition command or a subtraction command from the CPU 3.
In that case, the carry output of the binary adder/subtractor 63 is applied to the terminal Cin of the binary adder/subtractor 62,
Further, the carry output of the binary adder/subtractor 62 is applied to the terminal Cin of the binary adder/subtractor 61. And each result data of binary adder/subtractor 61, 62 is
It is applied to the ROM 64 and the scale frequency code β corresponding to the scale of the operation key is read out. On the other hand, the result data of the binary adder/subtractor 63 is applied to the ROM 65, and a frequency modulation code α for changing the frequency of the generated musical tone up to a semitone according to equal temperament is read out. That is, as is obvious from equation (5) or equation (8), if the frequency modulation code α changes, the frequency ₀ of the generated musical tone also changes, and frequency modulation such as vibrato is performed.

In the case of the embodiment shown in FIG. 8, the scale frequency code β′,
Since both frequency modulation codes α' are expressed and applied as binary data, the binary adder/subtractor 6
6 adds or subtracts both codes β' and α', and supplies the upper N-n bits of the resulting data to the ROM 67, and supplies the lower n bits to the ROM 68.
Therefore, the scale frequency code β corresponding to the musical scale is read from the ROM 67, and the varying frequency modulation code α is read from the ROM 68.

In the case of the embodiment of FIG. 9, the binary adder/subtractor 69
is the top N of the resulting data by adding or subtracting the scale frequency code β' and the frequency modulation code α'
-n bits are applied to the ROM 70, and lower n bits of data Y are applied to the binary adder/subtracter 71. Therefore, the scale frequency code β corresponding to the scale is read out from the ROM 70. On the other hand, data X having the same value as the frequency modulation code α (constant value) when no frequency modulation is applied is output from the CPU 3 and applied to the other end of the binary adder/subtractor 71.
This data X is calculated according to the above equation (1). Therefore, the frequency modulation code α by the binary adder/subtractor result data X+Y or X−Y
outputs.

In the case of the embodiment of FIG. 10, the binary adder/subtractor 7
Similar to the binary adder/subtractor 69 in FIG. 9, the scale frequency code β', the frequency modulation code α', and an addition command or a subtraction command based on binary data are applied to the adder/subtractor 2, respectively. Then, the upper N-n bits of the resulting data are applied to the ROM 73, and the lower n
Bit data is applied to decoder 74. Therefore, the scale frequency code β corresponding to the scale is read out from the ROM 73. On the other hand, the decoder 74
outputs data Y calculated by the above equation (3) with respect to data X having a value when the data of the lower n bits are all "0". Then, data obtained by adding data Y to the lower bits of data X is output as a frequency modulation code α. Therefore, frequency modulation is performed using a frequency modulation code α that changes according to changes in data Y.

In the case of the embodiment shown in FIG. 11, the vibrato depth is designated by operating a switch on the switch section 2. Furthermore, when chromatic vibrato is not to be applied, the other switches are operated in the same way, and the signal a is output as "1" to open the gate circuit G.
As a result, after the key is turned on, the scale frequency code β' of that key is output and applied to the average rate frequency calculator 76. In addition, the vibrato waveform and each signal specifying the vibrato depth are multiplied in the multiplier 75, and as a result, the upper bits of the data are directly sent, and the lower bits corresponding to semitones are sent to the equal tempered frequency calculator 76 via the gate circuit G. It is applied as a frequency modulation code α'. Therefore, the equal temperament frequency calculator 76 executes the equal temperament frequency calculation according to the operation of the embodiment circuit shown in FIG. 8, and outputs a scale frequency code β and a frequency modulation code α. This vibrato changes at the same depth and speed across the whole tone scale.

On the other hand, when applying a chromatic vibrato, a predetermined switch is operated in that manner, and a signal a of "0" is output to close the gate circuit G. Therefore, the lower bit data corresponding to a semitone of the result data output from the multiplier 75 is applied to the equal tempered frequency calculator 76 as all "0". Therefore, the frequency modulation code α output from the equal-tempered frequency calculator 76 is output as a value indicating a change that imparts a chromatic vibrato.

In the case of the embodiment shown in FIG. 12, this embodiment circuit operates when obtaining a portamento effect during monophonic performance. In other words, when the current key is turned on after the previous key was turned off, the code for that key is NEW.
KEY CODE is output and applied to terminal T of comparison circuit 77. At this time, the code of the previous operation key is applied to the terminal S of the comparison circuit 77, so the comparison circuit 77 compares the magnitude relationship between the two codes. When the pitch of the current key is lower than the pitch of the previous key, the comparator circuit 77 outputs a "1" level signal from the terminal S>T and applies it to the control terminal (-) of the binary adder/subtractor 79. , gives a subtraction command. Furthermore, the comparator circuit 77 now outputs a “1” level signal from the terminal S≠T, and the AND gate 78
to open. Therefore, the binary adder/subtractor 79 performs a -1 operation each time the signal EXECUTE is input through the AND gate 78, and the code of the previous key is decreased by one. Also, it is assumed that the signal a is currently being output as "1". Therefore, the upper N-n bits of the result data from the above subtraction operation are applied to the ROM 81, and the lower n bits are applied to the ROM 82, so that the scale frequency code .beta. and the frequency modulation code .alpha. are read out, respectively. In this case, the frequency modulation code α exhibits a change in which the frequency decreases in accordance with the average rate. On the other hand, if the signal a is outputted as "0", the frequency modulation code α shows a change in which the frequency decreases chromatically. When the comparison circuit 77 detects a match between the respective codes of both terminals S and T, it outputs a "0" level signal from the terminal S≠T and closes the AND gate 78.
The subtraction operation of the binary adder/subtractor 79 stops. That is, the above operation completes the portamento operation from the treble side to the bass side.

On the other hand, when the pitch of the current key is higher than the pitch of the previous key, the comparison circuit 77 outputs a "0" level signal from the terminal S>T to give an addition command to the binary adder/subtractor 79. Therefore, the binary adder/subtractor 79 executes a +1 operation until the comparator circuit 77 matches the data at both terminals S and T, and in response, the ROM 81 outputs the scale frequency code β for the scale of the operation key. , a frequency modulation code α is output from the ROM 82, and shows a change in which the frequency increases sequentially in accordance with the average rate. Furthermore, if the signal a is set to the "0" level, the change in the frequency modulation code α will show a change in which the frequency increases chromatically. The speed at which this scale changes is uniform throughout the entire range.

In the case of the embodiment shown in FIG. 13, when obtaining the UP glide effect, the switch of the switch section 2 is operated in this manner. In addition, the size of the glide width is specified by the switch. Then, when you turn on the key, a one-shot signal NEW KEY ON occurs when the key is turned on.
(“1”) is output, and gate circuits G ₁ , G ₂ and transfer gate 91 are both opened. Therefore, the binary adder/subtractor 84 functions as a subtracter when NEW KEY is ON. Also, the code from the above key on
NEW KEY CODE is applied to one end of the binary adder/subtractor 84 via gate circuit _G1 . Furthermore, the glide width is applied to the other end of the binary adder/subtractor ₈₄ via the gate circuit G2, so that when the key is turned on, the binary adder/subtractor 84 receives the code NEW KEY.
The glide width is subtracted from CODE and the resulting data is applied to flip-flop 85.

After the one-shot signal NEW KEY ON is output, the output of the inverter 88 is inverted to the "1" level, and the transfer gates 90, 92 and gate circuit _G3 are opened. Therefore, the result data is applied to the terminal S of the comparator circuit 83 as well as to one end of the binary adder/subtractor 84 via the gate circuit _G3 .
Thereafter, the comparison circuit 83 compares each data of the terminals S and T, outputs a "0" level signal from the terminal S>T, and outputs a "0" level signal from the terminal S>T, and outputs a "0" level signal from the control terminal (-) of the binary adder/subtractor 84.
is given through the transfer gate 92 as an addition instruction. Furthermore, the comparator circuit 83 outputs a “1” level signal from the terminal S≠T, and the AND gate 89
The AND gate 8 is opened and the signal EXECUTE is
9, applied to the other end of the binary adder/subtractor 84 via the transfer gate 90. Therefore, the binary adder/subtractor 84 performs a +1 operation on the result data each time the signal EXECUTE is input. The upper N-n bits of each result data are stored in the ROM 86.
The lower n bits are provided to the ROM 87. Therefore, the scale frequency code β is read out from the ROM 86. Further, a frequency modulation code α is read out from the ROM 87, and the frequency modulation code α exhibits a change in which the frequency increases sequentially according to the average rate, and an UP glide effect is obtained. When the comparison circuit 83 detects a match between the data at both terminals S and T, it outputs a "0" level signal from the terminal S≠T, closes the AND gate 89, and stops the UP glide effect generation operation. .

On the other hand, when you want to get the DOWN glide effect, operate the switch like that. Then, when the key is turned on, the binary adder/subtractor 84 outputs the code NEW KEY CODE when the single signal NEW KEY ON is output.
The glide width addition operation is performed on the glide width, and the resulting data is applied to the flip-flop 85. Thereafter, the binary adder/subtractor 84 performs a -1 operation on the result data each time the signal EXECUTE is output, and the value decreases by one. For this reason
The scale frequency code β is read from the ROM 86, while the frequency modulation code α showing a change in which the frequency becomes smaller in accordance with the average rate is read from the ROM 87, thereby obtaining a DOWN glide effect. Therefore, the speed at which the scale changes is constant over the entire range.

The operations for generating square waves, PWM waves, and sawtooth waves explained above are based on the case where only one key on the keyboard 1 is turned on, but in this example, the music synthesizer is used for eight-note polyphonic. Therefore, even if up to eight keys are turned on at the same time, each circuit in FIGS. 1 and 2 can simultaneously generate the fundamental wave for each key by time-sharing processing operation of 8 channels. can be done, but detailed explanation thereof will be omitted.

In addition, in the above example, the fundamental wave is a rectangular wave, PWM
Although the three types of fundamental waves are waves and sawtooth waves, other fundamental waves such as triangular waves and slope waves can be used. Further, although the interpolation at the point where the amplitude level of the fundamental wave suddenly changes is performed using a sine wave, other function curves such as a quadratic function, a cubic function, an exponential function, a trigonometric relationship, etc. may be used. Further, in the above embodiment, a 1/4 period sine wave is stored in the ROM 23, but it may be a 1 period or 1/2 period sine wave. Furthermore, it goes without saying that the present invention can be used not only for music synthesizers but also for other electronic musical instruments, and can be modified and applied in various ways without departing from the spirit of the present invention.

As explained above, this invention creates a new cent unit by adding or subtracting a scale frequency code in cents representing a scale frequency and a frequency modulation code in cents for modulating this scale frequency with an arbitrary cent width. Obtain the scale frequency code of
Converting this new scale frequency code in cents into first frequency information representing a frequency of a semitone or more and second frequency information representing a frequency within a semitone,
Using the first frequency information as an initial value, the subtraction means repeatedly subtracts the second frequency information from this initial value, and when the subtracted value reaches a predetermined value, for example, zero, the first frequency information is subtracted again. After presetting the frequency information, the above-mentioned second frequency information is repeatedly subtracted, and a waveform is created in which one cycle is the period until the output value of the subtraction means reaches a predetermined value. With a simple configuration, it is possible to perform equal frequency modulation on the plus side and minus side, and it is also possible to easily perform frequency modulation of more than a semitone.
Furthermore, since we have provided a frequency control device for electronic musical instruments that allows portamento and glide effects to be easily performed, it is possible to easily perform equal frequency modulation on the plus side and minus side according to equal temperament, making it extremely natural. It has the advantage of not only providing a natural vibrato effect, but also natural portamento and glide effects. Furthermore, since the calculation process is simple, the hardware configuration is also simple, which has the advantage of contributing to miniaturization of electronic musical instruments.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of a music synthesizer according to an embodiment of the present invention, FIG. 2 is a specific circuit diagram of the wave generator 5, and FIG. 3 is a ROM
Figure 4 is a time chart explaining the rectangular wave generation operation, Figure 5 is a time chart explaining the PWM wave generation operation, and Figure 6 is a time chart explaining the sawtooth wave generation operation. Chaat, 7th
1 to 13 are circuit diagrams of various embodiments for performing frequency modulation. 1...Keyboard, 2...Switch part, 3...
CPU, 4... Equal tempered frequency calculation section, 5... Wave generator, 6... Digital filter,
7... Envelope generator, 8... Digital/analog converter, 15, 16, 30... Full adder, 17... Shift register, 18 ₁₅ ~ 1
8 ₀ ...and gate, 20 ₈ ~ 20 ₀ , 27 ₆ ~ 2
7 ₀ ...Exclusive or gate, 21-7~21-1
... Inverter, 22-6 to 22-1 ... AND gate, 23 ... ROM, 24 ₆ to 24 ₀ ... OR gate, 26, 29, 33, 35, _{34 7} to 34
_{0,46 7} ~46 ₀ ...Transfer gate, 3
1... Inverter, 32... Polarity inversion circuit, 4
1, 45... Subtraction circuit, 42... Multiplication circuit, 43
... Addition and subtraction circuit, 44 ... Division circuit, G ₁ , G ₂ ...
...Gate circuit, 61, 63, 66, 69, 71,
72, 79, 84...Binary adder/subtractor, 62...
...Decimal adder/subtractor, 64, 65, 67, 68, 7
0,73,74,81,82,86,87...
ROM, 74...decoder, 75...multiplier, 7
6... Equal tempered frequency calculator, 77, 83... Comparison circuit, 80, 85... Flip-flop, G,
G ₁ ~ G ₃ ... Gate, 88 ... Inverter, 89
...and gate, 90-92...transfer gate.

Claims (1)

[Scope of Claims] 1. A scale frequency code in cents representing the scale frequency to be output, including a chord part in units of semitones and a chord part in units of less than semitones, a chord part in units of semitones, and a chord part in units of less than semitones. code generating means for generating a frequency modulation code in cent units for modulating the scale frequency specified by the scale frequency code with an arbitrary cent width; By adding and subtracting the scale frequency code and the frequency modulation code, a new scale frequency in units of cents is created that changes sequentially according to the frequency modulation code including a code part in units of semitones and a code part in units of less than a semitone. an addition/subtraction means for obtaining a chord; converting and outputting the new scale frequency code in cents output from the addition/subtraction means into first frequency information representing a frequency of a semitone or more and second frequency information representing a frequency within a semitone; a frequency information output means for outputting frequency information, and using the first frequency information from the frequency information output means as an initial value, from this initial value to the second frequency information
subtracting means for repeatedly subtracting frequency information from the subtracting means; and when the output value of the subtracting means reaches a predetermined value, the first frequency information is supplied from the frequency information outputting means to the subtracting means again to repeatedly subtract. What is claimed is: 1. A frequency control device for an electronic musical instrument, comprising: control means for controlling the frequency so that the subtracting means outputs a predetermined value; 2. When frequency modulation is designated by periodically changing the frequency modulation code from the code generation means and giving it to the addition/subtraction means, the frequency information output means receives the new cent unit from the addition/subtraction means. The frequency control device for an electronic musical instrument according to claim 1, wherein the first and second frequency information that changes periodically according to the scale frequency code is supplied to the subtraction means. . 3. When frequency modulation is specified by periodically changing the frequency modulation code in semitone units from the code generating means and giving it to the adding/subtracting means, the frequency information outputting means receives the new frequency modulation code from the adding/subtracting means. 2. The electronic device according to claim 1, wherein only the first frequency information is periodically changed by semitones in accordance with the scale frequency code in units of cents and is provided to the subtracting means. Musical instrument frequency control device. 4. The frequency modulation code from the code generation means is sequentially changed from a value specifying the pitch of the musical tone being generated to a value specifying the pitch of the musical tone to be newly generated, and is applied to the addition/subtraction means. When portamento performance is specified, the frequency information output means outputs the first and second frequencies for the musical tone being sounded, according to the new scale frequency code in cent units that changes sequentially from the addition/subtraction means. The electronic device according to claim 1, wherein the first and second frequency information for the new musical tone to be generated are sequentially changed from the information and supplied to the subtracting means. Musical instrument frequency control device. 5. The frequency modulation code from the code generation means is applied to the addition/subtraction means while changing sequentially in semitone units from a value specifying the pitch of the musical tone currently being generated to a value specifying the pitch of the musical tone to be newly generated. When a portamento performance in semitone units is specified by the above, the frequency information output means outputs the frequency information for the musical tone being sounded in accordance with the new scale frequency code in cent units that changes sequentially from the addition/subtraction means. 1 to the first frequency information for the musical tone to be newly generated, only the first frequency information is sequentially changed every semitone and is supplied to the subtracting means. A frequency control device for an electronic musical instrument according to claim 1. 6. When glide performance is designated by the frequency modulation code being sequentially changed from a value representing a predetermined glide width to zero from the code generating means to the adding/subtracting means, the frequency information outputting means According to the new scale frequency code in units of cents that changes sequentially from the addition/subtraction means, the tone of the musical tone to be produced from the first and second frequency information corresponding to the pitch of the musical tone having the predetermined glide width. 2. The frequency control device for an electronic musical instrument according to claim 1, wherein said first and second frequency information corresponding to a high frequency are sequentially changed and supplied to said subtraction means. 7. When glide performance is designated by the frequency modulation code from the code generating means being sequentially changed in semitone units from a value representing a predetermined glide width to zero and being given to the adding/subtracting means, the frequency information outputting means is the tone of the musical tone to be produced from the first frequency information corresponding to the pitch of the musical tone having the predetermined glide width, according to the new scale frequency code in units of cents that changes sequentially from the addition/subtraction means. Claim 1, characterized in that only the first frequency information is sequentially changed by semitones until the first frequency information corresponding to high is supplied to the subtracting means. Frequency control device for electronic musical instruments.